3 * Intel Management Engine Interface (Intel MEI) Linux driver
4 * Copyright (c) 2003-2012, Intel Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 #include <linux/module.h>
17 #include <linux/moduleparam.h>
18 #include <linux/kernel.h>
19 #include <linux/device.h>
21 #include <linux/errno.h>
22 #include <linux/types.h>
23 #include <linux/fcntl.h>
24 #include <linux/pci.h>
25 #include <linux/poll.h>
26 #include <linux/ioctl.h>
27 #include <linux/cdev.h>
28 #include <linux/sched.h>
29 #include <linux/uuid.h>
30 #include <linux/compat.h>
31 #include <linux/jiffies.h>
32 #include <linux/interrupt.h>
34 #include <linux/pm_domain.h>
35 #include <linux/pm_runtime.h>
37 #include <linux/mei.h>
41 #include "hw-me-regs.h"
44 /* mei_pci_tbl - PCI Device ID Table */
45 static const struct pci_device_id mei_me_pci_tbl[] = {
46 {MEI_PCI_DEVICE(MEI_DEV_ID_82946GZ, MEI_ME_ICH_CFG)},
47 {MEI_PCI_DEVICE(MEI_DEV_ID_82G35, MEI_ME_ICH_CFG)},
48 {MEI_PCI_DEVICE(MEI_DEV_ID_82Q965, MEI_ME_ICH_CFG)},
49 {MEI_PCI_DEVICE(MEI_DEV_ID_82G965, MEI_ME_ICH_CFG)},
50 {MEI_PCI_DEVICE(MEI_DEV_ID_82GM965, MEI_ME_ICH_CFG)},
51 {MEI_PCI_DEVICE(MEI_DEV_ID_82GME965, MEI_ME_ICH_CFG)},
52 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q35, MEI_ME_ICH_CFG)},
53 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82G33, MEI_ME_ICH_CFG)},
54 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82Q33, MEI_ME_ICH_CFG)},
55 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_82X38, MEI_ME_ICH_CFG)},
56 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_3200, MEI_ME_ICH_CFG)},
58 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_6, MEI_ME_ICH_CFG)},
59 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_7, MEI_ME_ICH_CFG)},
60 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_8, MEI_ME_ICH_CFG)},
61 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_9, MEI_ME_ICH_CFG)},
62 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9_10, MEI_ME_ICH_CFG)},
63 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_1, MEI_ME_ICH_CFG)},
64 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_2, MEI_ME_ICH_CFG)},
65 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_3, MEI_ME_ICH_CFG)},
66 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH9M_4, MEI_ME_ICH_CFG)},
68 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_1, MEI_ME_ICH10_CFG)},
69 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_2, MEI_ME_ICH10_CFG)},
70 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_3, MEI_ME_ICH10_CFG)},
71 {MEI_PCI_DEVICE(MEI_DEV_ID_ICH10_4, MEI_ME_ICH10_CFG)},
73 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_1, MEI_ME_PCH_CFG)},
74 {MEI_PCI_DEVICE(MEI_DEV_ID_IBXPK_2, MEI_ME_PCH_CFG)},
75 {MEI_PCI_DEVICE(MEI_DEV_ID_CPT_1, MEI_ME_PCH_CPT_PBG_CFG)},
76 {MEI_PCI_DEVICE(MEI_DEV_ID_PBG_1, MEI_ME_PCH_CPT_PBG_CFG)},
77 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_1, MEI_ME_PCH_CFG)},
78 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_2, MEI_ME_PCH_CFG)},
79 {MEI_PCI_DEVICE(MEI_DEV_ID_PPT_3, MEI_ME_PCH_CFG)},
80 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_H, MEI_ME_PCH8_SPS_CFG)},
81 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_W, MEI_ME_PCH8_SPS_CFG)},
82 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_LP, MEI_ME_PCH8_CFG)},
83 {MEI_PCI_DEVICE(MEI_DEV_ID_LPT_HR, MEI_ME_PCH8_SPS_CFG)},
84 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP, MEI_ME_PCH8_CFG)},
85 {MEI_PCI_DEVICE(MEI_DEV_ID_WPT_LP_2, MEI_ME_PCH8_CFG)},
87 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT, MEI_ME_PCH8_CFG)},
88 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_2, MEI_ME_PCH8_CFG)},
89 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H, MEI_ME_PCH8_SPS_CFG)},
90 {MEI_PCI_DEVICE(MEI_DEV_ID_SPT_H_2, MEI_ME_PCH8_SPS_CFG)},
91 {MEI_PCI_DEVICE(MEI_DEV_ID_LBG, MEI_ME_PCH8_CFG)},
93 {MEI_PCI_DEVICE(MEI_DEV_ID_BXT_M, MEI_ME_PCH8_CFG)},
94 {MEI_PCI_DEVICE(MEI_DEV_ID_APL_I, MEI_ME_PCH8_CFG)},
96 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP, MEI_ME_PCH8_CFG)},
97 {MEI_PCI_DEVICE(MEI_DEV_ID_KBP_2, MEI_ME_PCH8_CFG)},
99 /* required last entry */
103 MODULE_DEVICE_TABLE(pci, mei_me_pci_tbl);
106 static inline void mei_me_set_pm_domain(struct mei_device *dev);
107 static inline void mei_me_unset_pm_domain(struct mei_device *dev);
109 static inline void mei_me_set_pm_domain(struct mei_device *dev) {}
110 static inline void mei_me_unset_pm_domain(struct mei_device *dev) {}
111 #endif /* CONFIG_PM */
114 * mei_me_quirk_probe - probe for devices that doesn't valid ME interface
116 * @pdev: PCI device structure
117 * @cfg: per generation config
119 * Return: true if ME Interface is valid, false otherwise
121 static bool mei_me_quirk_probe(struct pci_dev *pdev,
122 const struct mei_cfg *cfg)
124 if (cfg->quirk_probe && cfg->quirk_probe(pdev)) {
125 dev_info(&pdev->dev, "Device doesn't have valid ME Interface\n");
133 * mei_me_probe - Device Initialization Routine
135 * @pdev: PCI device structure
136 * @ent: entry in kcs_pci_tbl
138 * Return: 0 on success, <0 on failure.
140 static int mei_me_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
142 const struct mei_cfg *cfg;
143 struct mei_device *dev;
144 struct mei_me_hw *hw;
145 unsigned int irqflags;
148 cfg = mei_me_get_cfg(ent->driver_data);
152 if (!mei_me_quirk_probe(pdev, cfg))
156 err = pcim_enable_device(pdev);
158 dev_err(&pdev->dev, "failed to enable pci device.\n");
161 /* set PCI host mastering */
162 pci_set_master(pdev);
163 /* pci request regions and mapping IO device memory for mei driver */
164 err = pcim_iomap_regions(pdev, BIT(0), KBUILD_MODNAME);
166 dev_err(&pdev->dev, "failed to get pci regions.\n");
170 if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) ||
171 dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
173 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
175 err = dma_set_coherent_mask(&pdev->dev,
179 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n");
183 /* allocates and initializes the mei dev structure */
184 dev = mei_me_dev_init(pdev, cfg);
190 hw->mem_addr = pcim_iomap_table(pdev)[0];
192 pci_enable_msi(pdev);
194 /* request and enable interrupt */
195 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
197 err = request_threaded_irq(pdev->irq,
198 mei_me_irq_quick_handler,
199 mei_me_irq_thread_handler,
200 irqflags, KBUILD_MODNAME, dev);
202 dev_err(&pdev->dev, "request_threaded_irq failure. irq = %d\n",
207 if (mei_start(dev)) {
208 dev_err(&pdev->dev, "init hw failure.\n");
213 pm_runtime_set_autosuspend_delay(&pdev->dev, MEI_ME_RPM_TIMEOUT);
214 pm_runtime_use_autosuspend(&pdev->dev);
216 err = mei_register(dev, &pdev->dev);
220 pci_set_drvdata(pdev, dev);
223 * MEI requires to resume from runtime suspend mode
224 * in order to perform link reset flow upon system suspend.
226 pdev->dev_flags |= PCI_DEV_FLAGS_NEEDS_RESUME;
229 * For not wake-able HW runtime pm framework
230 * can't be used on pci device level.
231 * Use domain runtime pm callbacks instead.
233 if (!pci_dev_run_wake(pdev))
234 mei_me_set_pm_domain(dev);
236 if (mei_pg_is_enabled(dev))
237 pm_runtime_put_noidle(&pdev->dev);
239 dev_dbg(&pdev->dev, "initialization successful.\n");
246 mei_cancel_work(dev);
247 mei_disable_interrupts(dev);
248 free_irq(pdev->irq, dev);
250 dev_err(&pdev->dev, "initialization failed.\n");
255 * mei_me_shutdown - Device Removal Routine
257 * @pdev: PCI device structure
259 * mei_me_shutdown is called from the reboot notifier
260 * it's a simplified version of remove so we go down
263 static void mei_me_shutdown(struct pci_dev *pdev)
265 struct mei_device *dev;
267 dev = pci_get_drvdata(pdev);
271 dev_dbg(&pdev->dev, "shutdown\n");
274 if (!pci_dev_run_wake(pdev))
275 mei_me_unset_pm_domain(dev);
277 mei_disable_interrupts(dev);
278 free_irq(pdev->irq, dev);
282 * mei_me_remove - Device Removal Routine
284 * @pdev: PCI device structure
286 * mei_me_remove is called by the PCI subsystem to alert the driver
287 * that it should release a PCI device.
289 static void mei_me_remove(struct pci_dev *pdev)
291 struct mei_device *dev;
293 dev = pci_get_drvdata(pdev);
297 if (mei_pg_is_enabled(dev))
298 pm_runtime_get_noresume(&pdev->dev);
300 dev_dbg(&pdev->dev, "stop\n");
303 if (!pci_dev_run_wake(pdev))
304 mei_me_unset_pm_domain(dev);
306 mei_disable_interrupts(dev);
308 free_irq(pdev->irq, dev);
313 #ifdef CONFIG_PM_SLEEP
314 static int mei_me_pci_suspend(struct device *device)
316 struct pci_dev *pdev = to_pci_dev(device);
317 struct mei_device *dev = pci_get_drvdata(pdev);
322 dev_dbg(&pdev->dev, "suspend\n");
326 mei_disable_interrupts(dev);
328 free_irq(pdev->irq, dev);
329 pci_disable_msi(pdev);
334 static int mei_me_pci_resume(struct device *device)
336 struct pci_dev *pdev = to_pci_dev(device);
337 struct mei_device *dev;
338 unsigned int irqflags;
341 dev = pci_get_drvdata(pdev);
345 pci_enable_msi(pdev);
347 irqflags = pci_dev_msi_enabled(pdev) ? IRQF_ONESHOT : IRQF_SHARED;
349 /* request and enable interrupt */
350 err = request_threaded_irq(pdev->irq,
351 mei_me_irq_quick_handler,
352 mei_me_irq_thread_handler,
353 irqflags, KBUILD_MODNAME, dev);
356 dev_err(&pdev->dev, "request_threaded_irq failed: irq = %d.\n",
361 err = mei_restart(dev);
365 /* Start timer if stopped in suspend */
366 schedule_delayed_work(&dev->timer_work, HZ);
370 #endif /* CONFIG_PM_SLEEP */
373 static int mei_me_pm_runtime_idle(struct device *device)
375 struct pci_dev *pdev = to_pci_dev(device);
376 struct mei_device *dev;
378 dev_dbg(&pdev->dev, "rpm: me: runtime_idle\n");
380 dev = pci_get_drvdata(pdev);
383 if (mei_write_is_idle(dev))
384 pm_runtime_autosuspend(device);
389 static int mei_me_pm_runtime_suspend(struct device *device)
391 struct pci_dev *pdev = to_pci_dev(device);
392 struct mei_device *dev;
395 dev_dbg(&pdev->dev, "rpm: me: runtime suspend\n");
397 dev = pci_get_drvdata(pdev);
401 mutex_lock(&dev->device_lock);
403 if (mei_write_is_idle(dev))
404 ret = mei_me_pg_enter_sync(dev);
408 mutex_unlock(&dev->device_lock);
410 dev_dbg(&pdev->dev, "rpm: me: runtime suspend ret=%d\n", ret);
412 if (ret && ret != -EAGAIN)
413 schedule_work(&dev->reset_work);
418 static int mei_me_pm_runtime_resume(struct device *device)
420 struct pci_dev *pdev = to_pci_dev(device);
421 struct mei_device *dev;
424 dev_dbg(&pdev->dev, "rpm: me: runtime resume\n");
426 dev = pci_get_drvdata(pdev);
430 mutex_lock(&dev->device_lock);
432 ret = mei_me_pg_exit_sync(dev);
434 mutex_unlock(&dev->device_lock);
436 dev_dbg(&pdev->dev, "rpm: me: runtime resume ret = %d\n", ret);
439 schedule_work(&dev->reset_work);
445 * mei_me_set_pm_domain - fill and set pm domain structure for device
449 static inline void mei_me_set_pm_domain(struct mei_device *dev)
451 struct pci_dev *pdev = to_pci_dev(dev->dev);
453 if (pdev->dev.bus && pdev->dev.bus->pm) {
454 dev->pg_domain.ops = *pdev->dev.bus->pm;
456 dev->pg_domain.ops.runtime_suspend = mei_me_pm_runtime_suspend;
457 dev->pg_domain.ops.runtime_resume = mei_me_pm_runtime_resume;
458 dev->pg_domain.ops.runtime_idle = mei_me_pm_runtime_idle;
460 dev_pm_domain_set(&pdev->dev, &dev->pg_domain);
465 * mei_me_unset_pm_domain - clean pm domain structure for device
469 static inline void mei_me_unset_pm_domain(struct mei_device *dev)
471 /* stop using pm callbacks if any */
472 dev_pm_domain_set(dev->dev, NULL);
475 static const struct dev_pm_ops mei_me_pm_ops = {
476 SET_SYSTEM_SLEEP_PM_OPS(mei_me_pci_suspend,
479 mei_me_pm_runtime_suspend,
480 mei_me_pm_runtime_resume,
481 mei_me_pm_runtime_idle)
484 #define MEI_ME_PM_OPS (&mei_me_pm_ops)
486 #define MEI_ME_PM_OPS NULL
487 #endif /* CONFIG_PM */
489 * PCI driver structure
491 static struct pci_driver mei_me_driver = {
492 .name = KBUILD_MODNAME,
493 .id_table = mei_me_pci_tbl,
494 .probe = mei_me_probe,
495 .remove = mei_me_remove,
496 .shutdown = mei_me_shutdown,
497 .driver.pm = MEI_ME_PM_OPS,
498 .driver.probe_type = PROBE_PREFER_ASYNCHRONOUS,
501 module_pci_driver(mei_me_driver);
503 MODULE_AUTHOR("Intel Corporation");
504 MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
505 MODULE_LICENSE("GPL v2");