1 /* SPDX-License-Identifier: GPL-2.0
3 * Copyright 2020-2021 HabanaLabs, Ltd.
11 #include <linux/types.h>
12 #include <linux/if_ether.h>
14 #include "hl_boot_if.h"
16 #define NUM_HBM_PSEUDO_CH 2
17 #define NUM_HBM_CH_PER_DEV 8
18 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_SHIFT 0
19 #define CPUCP_PKT_HBM_ECC_INFO_WR_PAR_MASK 0x00000001
20 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_SHIFT 1
21 #define CPUCP_PKT_HBM_ECC_INFO_RD_PAR_MASK 0x00000002
22 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_SHIFT 2
23 #define CPUCP_PKT_HBM_ECC_INFO_CA_PAR_MASK 0x00000004
24 #define CPUCP_PKT_HBM_ECC_INFO_DERR_SHIFT 3
25 #define CPUCP_PKT_HBM_ECC_INFO_DERR_MASK 0x00000008
26 #define CPUCP_PKT_HBM_ECC_INFO_SERR_SHIFT 4
27 #define CPUCP_PKT_HBM_ECC_INFO_SERR_MASK 0x00000010
28 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_SHIFT 5
29 #define CPUCP_PKT_HBM_ECC_INFO_TYPE_MASK 0x00000020
30 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_SHIFT 6
31 #define CPUCP_PKT_HBM_ECC_INFO_HBM_CH_MASK 0x000007C0
33 #define PLL_MAP_MAX_BITS 128
34 #define PLL_MAP_LEN (PLL_MAP_MAX_BITS / 8)
37 * info of the pkt queue pointers in the first async occurrence
39 struct cpucp_pkt_sync_err {
44 struct hl_eq_hbm_ecc_data {
49 /* Supplemental Information according to the mask bits */
51 /* Address in hbm where the ecc happened */
53 /* SERR continuous address counter */
67 struct hl_eq_ecc_data {
70 __u8 memory_wrapper_idx;
74 enum hl_sm_sei_cause {
76 SM_SEI_LBW_4B_UNALIGNED,
77 SM_SEI_AXI_RESPONSE_ERR
80 struct hl_eq_sm_sei_data {
82 /* enum hl_sm_sei_cause */
87 enum hl_fw_alive_severity {
88 FW_ALIVE_SEVERITY_MINOR,
89 FW_ALIVE_SEVERITY_CRITICAL
92 struct hl_eq_fw_alive {
93 __le64 uptime_seconds;
96 /* enum hl_fw_alive_severity */
101 enum hl_pcie_addr_dec_cause {
102 PCIE_ADDR_DEC_HBW_ERR_RESP,
103 PCIE_ADDR_DEC_LBW_ERR_RESP,
104 PCIE_ADDR_DEC_TLP_BLOCKED_BY_RR
107 struct hl_eq_pcie_addr_dec_data {
108 /* enum hl_pcie_addr_dec_cause */
114 struct hl_eq_header hdr;
116 struct hl_eq_ecc_data ecc_data;
117 struct hl_eq_hbm_ecc_data hbm_ecc_data;
118 struct hl_eq_sm_sei_data sm_sei_data;
119 struct cpucp_pkt_sync_err pkt_sync_err;
120 struct hl_eq_fw_alive fw_alive;
121 struct hl_eq_pcie_addr_dec_data pcie_addr_dec_data;
126 #define HL_EQ_ENTRY_SIZE sizeof(struct hl_eq_entry)
128 #define EQ_CTL_READY_SHIFT 31
129 #define EQ_CTL_READY_MASK 0x80000000
131 #define EQ_CTL_EVENT_TYPE_SHIFT 16
132 #define EQ_CTL_EVENT_TYPE_MASK 0x0FFF0000
134 #define EQ_CTL_INDEX_SHIFT 0
135 #define EQ_CTL_INDEX_MASK 0x0000FFFF
137 enum pq_init_status {
138 PQ_INIT_STATUS_NA = 0,
139 PQ_INIT_STATUS_READY_FOR_CP,
140 PQ_INIT_STATUS_READY_FOR_HOST,
141 PQ_INIT_STATUS_READY_FOR_CP_SINGLE_MSI,
142 PQ_INIT_STATUS_LEN_NOT_POWER_OF_TWO_ERR,
143 PQ_INIT_STATUS_ILLEGAL_Q_ADDR_ERR
147 * CpuCP Primary Queue Packets
149 * During normal operation, the host's kernel driver needs to send various
150 * messages to CpuCP, usually either to SET some value into a H/W periphery or
151 * to GET the current value of some H/W periphery. For example, SET the
152 * frequency of MME/TPC and GET the value of the thermal sensor.
154 * These messages can be initiated either by the User application or by the
155 * host's driver itself, e.g. power management code. In either case, the
156 * communication from the host's driver to CpuCP will *always* be in
157 * synchronous mode, meaning that the host will send a single message and poll
158 * until the message was acknowledged and the results are ready (if results are
161 * This means that only a single message can be sent at a time and the host's
162 * driver must wait for its result before sending the next message. Having said
163 * that, because these are control messages which are sent in a relatively low
164 * frequency, this limitation seems acceptable. It's important to note that
165 * in case of multiple devices, messages to different devices *can* be sent
168 * The message, inputs/outputs (if relevant) and fence object will be located
169 * on the device DDR at an address that will be determined by the host's driver.
170 * During device initialization phase, the host will pass to CpuCP that address.
171 * Most of the message types will contain inputs/outputs inside the message
172 * itself. The common part of each message will contain the opcode of the
173 * message (its type) and a field representing a fence object.
175 * When the host's driver wishes to send a message to CPU CP, it will write the
176 * message contents to the device DDR, clear the fence object and then write to
177 * the PSOC_ARC1_AUX_SW_INTR, to issue interrupt 121 to ARC Management CPU.
179 * Upon receiving the interrupt (#121), CpuCP will read the message from the
180 * DDR. In case the message is a SET operation, CpuCP will first perform the
181 * operation and then write to the fence object on the device DDR. In case the
182 * message is a GET operation, CpuCP will first fill the results section on the
183 * device DDR and then write to the fence object. If an error occurred, CpuCP
184 * will fill the rc field with the right error code.
186 * In the meantime, the host's driver will poll on the fence object. Once the
187 * host sees that the fence object is signaled, it will read the results from
188 * the device DDR (if relevant) and resume the code execution in the host's
191 * To use QMAN packets, the opcode must be the QMAN opcode, shifted by 8
192 * so the value being put by the host's driver matches the value read by CpuCP
194 * Non-QMAN packets should be limited to values 1 through (2^8 - 1)
196 * Detailed description:
198 * CPUCP_PACKET_DISABLE_PCI_ACCESS -
199 * After receiving this packet the embedded CPU must NOT issue PCI
200 * transactions (read/write) towards the Host CPU. This also include
201 * sending MSI-X interrupts.
202 * This packet is usually sent before the device is moved to D3Hot state.
204 * CPUCP_PACKET_ENABLE_PCI_ACCESS -
205 * After receiving this packet the embedded CPU is allowed to issue PCI
206 * transactions towards the Host CPU, including sending MSI-X interrupts.
207 * This packet is usually send after the device is moved to D0 state.
209 * CPUCP_PACKET_TEMPERATURE_GET -
210 * Fetch the current temperature / Max / Max Hyst / Critical /
211 * Critical Hyst of a specified thermal sensor. The packet's
212 * arguments specify the desired sensor and the field to get.
214 * CPUCP_PACKET_VOLTAGE_GET -
215 * Fetch the voltage / Max / Min of a specified sensor. The packet's
216 * arguments specify the sensor and type.
218 * CPUCP_PACKET_CURRENT_GET -
219 * Fetch the current / Max / Min of a specified sensor. The packet's
220 * arguments specify the sensor and type.
222 * CPUCP_PACKET_FAN_SPEED_GET -
223 * Fetch the speed / Max / Min of a specified fan. The packet's
224 * arguments specify the sensor and type.
226 * CPUCP_PACKET_PWM_GET -
227 * Fetch the pwm value / mode of a specified pwm. The packet's
228 * arguments specify the sensor and type.
230 * CPUCP_PACKET_PWM_SET -
231 * Set the pwm value / mode of a specified pwm. The packet's
232 * arguments specify the sensor, type and value.
234 * CPUCP_PACKET_FREQUENCY_SET -
235 * Set the frequency of a specified PLL. The packet's arguments specify
236 * the PLL and the desired frequency. The actual frequency in the device
237 * might differ from the requested frequency.
239 * CPUCP_PACKET_FREQUENCY_GET -
240 * Fetch the frequency of a specified PLL. The packet's arguments specify
243 * CPUCP_PACKET_LED_SET -
244 * Set the state of a specified led. The packet's arguments
245 * specify the led and the desired state.
247 * CPUCP_PACKET_I2C_WR -
248 * Write 32-bit value to I2C device. The packet's arguments specify the
249 * I2C bus, address and value.
251 * CPUCP_PACKET_I2C_RD -
252 * Read 32-bit value from I2C device. The packet's arguments specify the
253 * I2C bus and address.
255 * CPUCP_PACKET_INFO_GET -
256 * Fetch information from the device as specified in the packet's
257 * structure. The host's driver passes the max size it allows the CpuCP to
258 * write to the structure, to prevent data corruption in case of
259 * mismatched driver/FW versions.
261 * CPUCP_PACKET_FLASH_PROGRAM_REMOVED - this packet was removed
263 * CPUCP_PACKET_UNMASK_RAZWI_IRQ -
264 * Unmask the given IRQ. The IRQ number is specified in the value field.
265 * The packet is sent after receiving an interrupt and printing its
266 * relevant information.
268 * CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY -
269 * Unmask the given IRQs. The IRQs numbers are specified in an array right
270 * after the cpucp_packet structure, where its first element is the array
271 * length. The packet is sent after a soft reset was done in order to
272 * handle any interrupts that were sent during the reset process.
274 * CPUCP_PACKET_TEST -
275 * Test packet for CpuCP connectivity. The CPU will put the fence value
276 * in the result field.
278 * CPUCP_PACKET_FREQUENCY_CURR_GET -
279 * Fetch the current frequency of a specified PLL. The packet's arguments
282 * CPUCP_PACKET_MAX_POWER_GET -
283 * Fetch the maximal power of the device.
285 * CPUCP_PACKET_MAX_POWER_SET -
286 * Set the maximal power of the device. The packet's arguments specify
289 * CPUCP_PACKET_EEPROM_DATA_GET -
290 * Get EEPROM data from the CpuCP kernel. The buffer is specified in the
291 * addr field. The CPU will put the returned data size in the result
292 * field. In addition, the host's driver passes the max size it allows the
293 * CpuCP to write to the structure, to prevent data corruption in case of
294 * mismatched driver/FW versions.
296 * CPUCP_PACKET_NIC_INFO_GET -
297 * Fetch information from the device regarding the NIC. the host's driver
298 * passes the max size it allows the CpuCP to write to the structure, to
299 * prevent data corruption in case of mismatched driver/FW versions.
301 * CPUCP_PACKET_TEMPERATURE_SET -
302 * Set the value of the offset property of a specified thermal sensor.
303 * The packet's arguments specify the desired sensor and the field to
306 * CPUCP_PACKET_VOLTAGE_SET -
307 * Trigger the reset_history property of a specified voltage sensor.
308 * The packet's arguments specify the desired sensor and the field to
311 * CPUCP_PACKET_CURRENT_SET -
312 * Trigger the reset_history property of a specified current sensor.
313 * The packet's arguments specify the desired sensor and the field to
316 * CPUCP_PACKET_PCIE_THROUGHPUT_GET -
317 * Get throughput of PCIe.
318 * The packet's arguments specify the transaction direction (TX/RX).
319 * The window measurement is 10[msec], and the return value is in KB/sec.
321 * CPUCP_PACKET_PCIE_REPLAY_CNT_GET
322 * Replay count measures number of "replay" events, which is basicly
323 * number of retries done by PCIe.
325 * CPUCP_PACKET_TOTAL_ENERGY_GET -
326 * Total Energy is measurement of energy from the time FW Linux
327 * is loaded. It is calculated by multiplying the average power
328 * by time (passed from armcp start). The units are in MilliJouls.
330 * CPUCP_PACKET_PLL_INFO_GET -
331 * Fetch frequencies of PLL from the required PLL IP.
332 * The packet's arguments specify the device PLL type
333 * Pll type is the PLL from device pll_index enum.
334 * The result is composed of 4 outputs, each is 16-bit
337 * CPUCP_PACKET_POWER_GET -
338 * Fetch the present power consumption of the device (Current * Voltage).
340 * CPUCP_PACKET_NIC_PFC_SET -
341 * Enable/Disable the NIC PFC feature. The packet's arguments specify the
342 * NIC port, relevant lanes to configure and one bit indication for
345 * CPUCP_PACKET_NIC_FAULT_GET -
346 * Fetch the current indication for local/remote faults from the NIC MAC.
347 * The result is 32-bit value of the relevant register.
349 * CPUCP_PACKET_NIC_LPBK_SET -
350 * Enable/Disable the MAC loopback feature. The packet's arguments specify
351 * the NIC port, relevant lanes to configure and one bit indication for
354 * CPUCP_PACKET_NIC_MAC_INIT -
355 * Configure the NIC MAC channels. The packet's arguments specify the
356 * NIC port and the speed.
358 * CPUCP_PACKET_MSI_INFO_SET -
359 * set the index number for each supported msi type going from
362 * CPUCP_PACKET_NIC_XPCS91_REGS_GET -
363 * Fetch the un/correctable counters values from the NIC MAC.
365 * CPUCP_PACKET_NIC_STAT_REGS_GET -
366 * Fetch various NIC MAC counters from the NIC STAT.
368 * CPUCP_PACKET_NIC_STAT_REGS_CLR -
369 * Clear the various NIC MAC counters in the NIC STAT.
371 * CPUCP_PACKET_NIC_STAT_REGS_ALL_GET -
372 * Fetch all NIC MAC counters from the NIC STAT.
374 * CPUCP_PACKET_IS_IDLE_CHECK -
375 * Check if the device is IDLE in regard to the DMA/compute engines
376 * and QMANs. The f/w will return a bitmask where each bit represents
377 * a different engine or QMAN according to enum cpucp_idle_mask.
378 * The bit will be 1 if the engine is NOT idle.
380 * CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET -
381 * Fetch all HBM replaced-rows and prending to be replaced rows data.
383 * CPUCP_PACKET_HBM_PENDING_ROWS_STATUS -
384 * Fetch status of HBM rows pending replacement and need a reboot to
387 * CPUCP_PACKET_POWER_SET -
388 * Resets power history of device to 0
390 * CPUCP_PACKET_ENGINE_CORE_ASID_SET -
391 * Packet to perform engine core ASID configuration
394 enum cpucp_packet_id {
395 CPUCP_PACKET_DISABLE_PCI_ACCESS = 1, /* internal */
396 CPUCP_PACKET_ENABLE_PCI_ACCESS, /* internal */
397 CPUCP_PACKET_TEMPERATURE_GET, /* sysfs */
398 CPUCP_PACKET_VOLTAGE_GET, /* sysfs */
399 CPUCP_PACKET_CURRENT_GET, /* sysfs */
400 CPUCP_PACKET_FAN_SPEED_GET, /* sysfs */
401 CPUCP_PACKET_PWM_GET, /* sysfs */
402 CPUCP_PACKET_PWM_SET, /* sysfs */
403 CPUCP_PACKET_FREQUENCY_SET, /* sysfs */
404 CPUCP_PACKET_FREQUENCY_GET, /* sysfs */
405 CPUCP_PACKET_LED_SET, /* debugfs */
406 CPUCP_PACKET_I2C_WR, /* debugfs */
407 CPUCP_PACKET_I2C_RD, /* debugfs */
408 CPUCP_PACKET_INFO_GET, /* IOCTL */
409 CPUCP_PACKET_FLASH_PROGRAM_REMOVED,
410 CPUCP_PACKET_UNMASK_RAZWI_IRQ, /* internal */
411 CPUCP_PACKET_UNMASK_RAZWI_IRQ_ARRAY, /* internal */
412 CPUCP_PACKET_TEST, /* internal */
413 CPUCP_PACKET_FREQUENCY_CURR_GET, /* sysfs */
414 CPUCP_PACKET_MAX_POWER_GET, /* sysfs */
415 CPUCP_PACKET_MAX_POWER_SET, /* sysfs */
416 CPUCP_PACKET_EEPROM_DATA_GET, /* sysfs */
417 CPUCP_PACKET_NIC_INFO_GET, /* internal */
418 CPUCP_PACKET_TEMPERATURE_SET, /* sysfs */
419 CPUCP_PACKET_VOLTAGE_SET, /* sysfs */
420 CPUCP_PACKET_CURRENT_SET, /* sysfs */
421 CPUCP_PACKET_PCIE_THROUGHPUT_GET, /* internal */
422 CPUCP_PACKET_PCIE_REPLAY_CNT_GET, /* internal */
423 CPUCP_PACKET_TOTAL_ENERGY_GET, /* internal */
424 CPUCP_PACKET_PLL_INFO_GET, /* internal */
425 CPUCP_PACKET_NIC_STATUS, /* internal */
426 CPUCP_PACKET_POWER_GET, /* internal */
427 CPUCP_PACKET_NIC_PFC_SET, /* internal */
428 CPUCP_PACKET_NIC_FAULT_GET, /* internal */
429 CPUCP_PACKET_NIC_LPBK_SET, /* internal */
430 CPUCP_PACKET_NIC_MAC_CFG, /* internal */
431 CPUCP_PACKET_MSI_INFO_SET, /* internal */
432 CPUCP_PACKET_NIC_XPCS91_REGS_GET, /* internal */
433 CPUCP_PACKET_NIC_STAT_REGS_GET, /* internal */
434 CPUCP_PACKET_NIC_STAT_REGS_CLR, /* internal */
435 CPUCP_PACKET_NIC_STAT_REGS_ALL_GET, /* internal */
436 CPUCP_PACKET_IS_IDLE_CHECK, /* internal */
437 CPUCP_PACKET_HBM_REPLACED_ROWS_INFO_GET,/* internal */
438 CPUCP_PACKET_HBM_PENDING_ROWS_STATUS, /* internal */
439 CPUCP_PACKET_POWER_SET, /* internal */
440 CPUCP_PACKET_RESERVED, /* not used */
441 CPUCP_PACKET_ENGINE_CORE_ASID_SET, /* internal */
444 #define CPUCP_PACKET_FENCE_VAL 0xFE8CE7A5
446 #define CPUCP_PKT_CTL_RC_SHIFT 12
447 #define CPUCP_PKT_CTL_RC_MASK 0x0000F000
449 #define CPUCP_PKT_CTL_OPCODE_SHIFT 16
450 #define CPUCP_PKT_CTL_OPCODE_MASK 0x1FFF0000
452 #define CPUCP_PKT_RES_PLL_OUT0_SHIFT 0
453 #define CPUCP_PKT_RES_PLL_OUT0_MASK 0x000000000000FFFFull
454 #define CPUCP_PKT_RES_PLL_OUT1_SHIFT 16
455 #define CPUCP_PKT_RES_PLL_OUT1_MASK 0x00000000FFFF0000ull
456 #define CPUCP_PKT_RES_PLL_OUT2_SHIFT 32
457 #define CPUCP_PKT_RES_PLL_OUT2_MASK 0x0000FFFF00000000ull
458 #define CPUCP_PKT_RES_PLL_OUT3_SHIFT 48
459 #define CPUCP_PKT_RES_PLL_OUT3_MASK 0xFFFF000000000000ull
461 #define CPUCP_PKT_VAL_PFC_IN1_SHIFT 0
462 #define CPUCP_PKT_VAL_PFC_IN1_MASK 0x0000000000000001ull
463 #define CPUCP_PKT_VAL_PFC_IN2_SHIFT 1
464 #define CPUCP_PKT_VAL_PFC_IN2_MASK 0x000000000000001Eull
466 #define CPUCP_PKT_VAL_LPBK_IN1_SHIFT 0
467 #define CPUCP_PKT_VAL_LPBK_IN1_MASK 0x0000000000000001ull
468 #define CPUCP_PKT_VAL_LPBK_IN2_SHIFT 1
469 #define CPUCP_PKT_VAL_LPBK_IN2_MASK 0x000000000000001Eull
471 #define CPUCP_PKT_VAL_MAC_CNT_IN1_SHIFT 0
472 #define CPUCP_PKT_VAL_MAC_CNT_IN1_MASK 0x0000000000000001ull
473 #define CPUCP_PKT_VAL_MAC_CNT_IN2_SHIFT 1
474 #define CPUCP_PKT_VAL_MAC_CNT_IN2_MASK 0x00000000FFFFFFFEull
476 /* heartbeat status bits */
477 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_SHIFT 0
478 #define CPUCP_PKT_HB_STATUS_EQ_FAULT_MASK 0x00000001
480 struct cpucp_packet {
482 __le64 value; /* For SET packets */
483 __le64 result; /* For GET packets */
484 __le64 addr; /* For PQ */
489 __le32 fence; /* Signal to host that message is completed */
492 struct {/* For temperature/current/voltage/fan/pwm get/set */
497 struct { /* For I2C read/write */
502 * In legacy implemetations, i2c_len was not present,
503 * was unused and just added as pad.
504 * So if i2c_len is 0, it is treated as legacy
505 * and r/w 1 Byte, else if i2c_len is specified,
506 * its treated as new multibyte r/w support.
511 struct {/* For PLL info fetch */
513 /* TODO pll_reg is kept temporary before removal */
517 /* For any general request */
520 /* For frequency get/set */
526 /* For get CpuCP info/EEPROM data/NIC info */
527 __le32 data_max_size;
530 * For any general status bitmask. Shall be used whenever the
531 * result cannot be used to hold general purpose data.
536 /* For NIC requests */
540 struct cpucp_unmask_irq_arr_packet {
541 struct cpucp_packet cpucp_pkt;
546 struct cpucp_nic_status_packet {
547 struct cpucp_packet cpucp_pkt;
552 struct cpucp_array_data_packet {
553 struct cpucp_packet cpucp_pkt;
558 enum cpucp_packet_rc {
559 cpucp_packet_success,
560 cpucp_packet_invalid,
565 * cpucp_temp_type should adhere to hwmon_temp_attributes
566 * defined in Linux kernel hwmon.h file
568 enum cpucp_temp_type {
575 cpucp_temp_crit_hyst,
576 cpucp_temp_offset = 19,
577 cpucp_temp_lowest = 21,
578 cpucp_temp_highest = 22,
579 cpucp_temp_reset_history = 23
582 enum cpucp_in_attributes {
587 cpucp_in_highest = 7,
588 cpucp_in_reset_history
591 enum cpucp_curr_attributes {
595 cpucp_curr_lowest = 6,
596 cpucp_curr_highest = 7,
597 cpucp_curr_reset_history
600 enum cpucp_fan_attributes {
606 enum cpucp_pwm_attributes {
611 enum cpucp_pcie_throughput_attributes {
612 cpucp_pcie_throughput_tx,
613 cpucp_pcie_throughput_rx
616 /* TODO temporary kept before removal */
617 enum cpucp_pll_reg_attributes {
621 cpucp_pll_div_factor_reg,
622 cpucp_pll_div_sel_reg
625 /* TODO temporary kept before removal */
626 enum cpucp_pll_type_attributes {
632 * cpucp_power_type aligns with hwmon_power_attributes
633 * defined in Linux kernel hwmon.h file
635 enum cpucp_power_type {
636 CPUCP_POWER_INPUT = 8,
637 CPUCP_POWER_INPUT_HIGHEST = 9,
638 CPUCP_POWER_RESET_INPUT_HISTORY = 11
642 * MSI type enumeration table for all ASICs and future SW versions.
643 * For future ASIC-LKD compatibility, we can only add new enumerations.
644 * at the end of the table (before CPUCP_NUM_OF_MSI_TYPES).
645 * Changing the order of entries or removing entries is not allowed.
647 enum cpucp_msi_type {
648 CPUCP_EVENT_QUEUE_MSI_TYPE,
649 CPUCP_NIC_PORT1_MSI_TYPE,
650 CPUCP_NIC_PORT3_MSI_TYPE,
651 CPUCP_NIC_PORT5_MSI_TYPE,
652 CPUCP_NIC_PORT7_MSI_TYPE,
653 CPUCP_NIC_PORT9_MSI_TYPE,
654 CPUCP_NUM_OF_MSI_TYPES
658 * PLL enumeration table used for all ASICs and future SW versions.
659 * For future ASIC-LKD compatibility, we can only add new enumerations.
660 * at the end of the table.
661 * Changing the order of entries or removing entries is not allowed.
698 /* Event Queue Packets */
700 struct eq_generic_event {
708 #define CARD_NAME_MAX_LEN 16
709 #define CPUCP_MAX_SENSORS 128
710 #define CPUCP_MAX_NICS 128
711 #define CPUCP_LANES_PER_NIC 4
712 #define CPUCP_NIC_QSFP_EEPROM_MAX_LEN 1024
713 #define CPUCP_MAX_NIC_LANES (CPUCP_MAX_NICS * CPUCP_LANES_PER_NIC)
714 #define CPUCP_NIC_MASK_ARR_LEN ((CPUCP_MAX_NICS + 63) / 64)
715 #define CPUCP_NIC_POLARITY_ARR_LEN ((CPUCP_MAX_NIC_LANES + 63) / 64)
716 #define CPUCP_HBM_ROW_REPLACE_MAX 32
718 struct cpucp_sensor {
724 * struct cpucp_card_types - ASIC card type.
725 * @cpucp_card_type_pci: PCI card.
726 * @cpucp_card_type_pmc: PCI Mezzanine Card.
728 enum cpucp_card_types {
733 #define CPUCP_SEC_CONF_ENABLED_SHIFT 0
734 #define CPUCP_SEC_CONF_ENABLED_MASK 0x00000001
736 #define CPUCP_SEC_CONF_FLASH_WP_SHIFT 1
737 #define CPUCP_SEC_CONF_FLASH_WP_MASK 0x00000002
739 #define CPUCP_SEC_CONF_EEPROM_WP_SHIFT 2
740 #define CPUCP_SEC_CONF_EEPROM_WP_MASK 0x00000004
743 * struct cpucp_security_info - Security information.
744 * @config: configuration bit field
745 * @keys_num: number of stored keys
746 * @revoked_keys: revoked keys bit field
747 * @min_svn: minimal security version
749 struct cpucp_security_info {
757 * struct cpucp_info - Info from CpuCP that is necessary to the host's driver
758 * @sensors: available sensors description.
759 * @kernel_version: CpuCP linux kernel version.
760 * @reserved: reserved field.
761 * @card_type: card configuration type.
762 * @card_location: in a server, each card has different connections topology
763 * depending on its location (relevant for PMC card type)
764 * @cpld_version: CPLD programmed F/W version.
765 * @infineon_version: Infineon main DC-DC version.
766 * @fuse_version: silicon production FUSE information.
767 * @thermal_version: thermald S/W version.
768 * @cpucp_version: CpuCP S/W version.
769 * @infineon_second_stage_version: Infineon 2nd stage DC-DC version.
770 * @dram_size: available DRAM size.
771 * @card_name: card name that will be displayed in HWMON subsystem on the host
772 * @sec_info: security information
773 * @pll_map: Bit map of supported PLLs for current ASIC version.
774 * @mme_binning_mask: MME binning mask,
775 * (0 = functional, 1 = binned)
776 * @dram_binning_mask: DRAM binning mask, 1 bit per dram instance
777 * (0 = functional 1 = binned)
778 * @memory_repair_flag: eFuse flag indicating memory repair
779 * @edma_binning_mask: EDMA binning mask, 1 bit per EDMA instance
780 * (0 = functional 1 = binned)
781 * @xbar_binning_mask: Xbar binning mask, 1 bit per Xbar instance
782 * (0 = functional 1 = binned)
783 * @fw_os_version: Firmware OS Version
786 struct cpucp_sensor sensors[CPUCP_MAX_SENSORS];
787 __u8 kernel_version[VERSION_MAX_LEN];
790 __le32 card_location;
792 __le32 infineon_version;
793 __u8 fuse_version[VERSION_MAX_LEN];
794 __u8 thermal_version[VERSION_MAX_LEN];
795 __u8 cpucp_version[VERSION_MAX_LEN];
796 __le32 infineon_second_stage_version;
798 char card_name[CARD_NAME_MAX_LEN];
802 __u8 dram_binning_mask;
803 __u8 memory_repair_flag;
804 __u8 edma_binning_mask;
805 __u8 xbar_binning_mask;
807 struct cpucp_security_info sec_info;
809 __u8 pll_map[PLL_MAP_LEN];
810 __le64 mme_binning_mask;
811 __u8 fw_os_version[VERSION_MAX_LEN];
814 struct cpucp_mac_addr {
815 __u8 mac_addr[ETH_ALEN];
818 enum cpucp_serdes_type {
824 MAX_NUM_SERDES_TYPE = UNKNOWN_SERDES_TYPE
827 struct cpucp_nic_info {
828 struct cpucp_mac_addr mac_addrs[CPUCP_MAX_NICS];
829 __le64 link_mask[CPUCP_NIC_MASK_ARR_LEN];
830 __le64 pol_tx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
831 __le64 pol_rx_mask[CPUCP_NIC_POLARITY_ARR_LEN];
832 __le64 link_ext_mask[CPUCP_NIC_MASK_ARR_LEN];
833 __u8 qsfp_eeprom[CPUCP_NIC_QSFP_EEPROM_MAX_LEN];
834 __le64 auto_neg_mask[CPUCP_NIC_MASK_ARR_LEN];
835 __le16 serdes_type; /* enum cpucp_serdes_type */
840 * struct cpucp_nic_status - describes the status of a NIC port.
841 * @port: NIC port index.
842 * @bad_format_cnt: e.g. CRC.
843 * @responder_out_of_sequence_psn_cnt: e.g NAK.
844 * @high_ber_reinit_cnt: link reinit due to high BER.
845 * @correctable_err_cnt: e.g. bit-flip.
846 * @uncorrectable_err_cnt: e.g. MAC errors.
847 * @retraining_cnt: re-training counter.
849 * @pcs_link: has PCS link.
850 * @phy_ready: is PHY ready.
851 * @auto_neg: is Autoneg enabled.
852 * @timeout_retransmission_cnt: timeout retransmission events
853 * @high_ber_cnt: high ber events
855 struct cpucp_nic_status {
857 __le32 bad_format_cnt;
858 __le32 responder_out_of_sequence_psn_cnt;
859 __le32 high_ber_reinit;
860 __le32 correctable_err_cnt;
861 __le32 uncorrectable_err_cnt;
862 __le32 retraining_cnt;
867 __le32 timeout_retransmission_cnt;
871 enum cpucp_hbm_row_replace_cause {
872 REPLACE_CAUSE_DOUBLE_ECC_ERR,
873 REPLACE_CAUSE_MULTI_SINGLE_ECC_ERR,
876 struct cpucp_hbm_row_info {
882 __u8 replaced_row_cause; /* enum cpucp_hbm_row_replace_cause */
886 struct cpucp_hbm_row_replaced_rows_info {
887 __le16 num_replaced_rows;
889 struct cpucp_hbm_row_info replaced_rows[CPUCP_HBM_ROW_REPLACE_MAX];
892 #endif /* CPUCP_IF_H */