drivers/mfd/db8500-prcmu.c

   1 /*
   2  * Copyright (C) STMicroelectronics 2009
   3  * Copyright (C) ST-Ericsson SA 2010
   4  *
   5  * License Terms: GNU General Public License v2
   6  * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
   7  * Author: Sundar Iyer <sundar.iyer@stericsson.com>
   8  * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
   9  *
  10  * U8500 PRCM Unit interface driver
  11  *
  12  */
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/delay.h>
  16 #include <linux/errno.h>
  17 #include <linux/err.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/io.h>
  20 #include <linux/slab.h>
  21 #include <linux/mutex.h>
  22 #include <linux/completion.h>
  23 #include <linux/irq.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/bitops.h>
  26 #include <linux/fs.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/uaccess.h>
  29 #include <linux/irqchip/arm-gic.h>
  30 #include <linux/mfd/core.h>
  31 #include <linux/mfd/dbx500-prcmu.h>
  32 #include <linux/mfd/abx500/ab8500.h>
  33 #include <linux/regulator/db8500-prcmu.h>
  34 #include <linux/regulator/machine.h>
  35 #include <linux/cpufreq.h>
  36 #include <mach/hardware.h>
  37 #include <mach/irqs.h>
  38 #include <mach/db8500-regs.h>
  39 #include "dbx500-prcmu-regs.h"
  40
  41 /* Index of different voltages to be used when accessing AVSData */
  42 #define PRCM_AVS_BASE           0x2FC
  43 #define PRCM_AVS_VBB_RET        (PRCM_AVS_BASE + 0x0)
  44 #define PRCM_AVS_VBB_MAX_OPP    (PRCM_AVS_BASE + 0x1)
  45 #define PRCM_AVS_VBB_100_OPP    (PRCM_AVS_BASE + 0x2)
  46 #define PRCM_AVS_VBB_50_OPP     (PRCM_AVS_BASE + 0x3)
  47 #define PRCM_AVS_VARM_MAX_OPP   (PRCM_AVS_BASE + 0x4)
  48 #define PRCM_AVS_VARM_100_OPP   (PRCM_AVS_BASE + 0x5)
  49 #define PRCM_AVS_VARM_50_OPP    (PRCM_AVS_BASE + 0x6)
  50 #define PRCM_AVS_VARM_RET       (PRCM_AVS_BASE + 0x7)
  51 #define PRCM_AVS_VAPE_100_OPP   (PRCM_AVS_BASE + 0x8)
  52 #define PRCM_AVS_VAPE_50_OPP    (PRCM_AVS_BASE + 0x9)
  53 #define PRCM_AVS_VMOD_100_OPP   (PRCM_AVS_BASE + 0xA)
  54 #define PRCM_AVS_VMOD_50_OPP    (PRCM_AVS_BASE + 0xB)
  55 #define PRCM_AVS_VSAFE          (PRCM_AVS_BASE + 0xC)
  56
  57 #define PRCM_AVS_VOLTAGE                0
  58 #define PRCM_AVS_VOLTAGE_MASK           0x3f
  59 #define PRCM_AVS_ISSLOWSTARTUP          6
  60 #define PRCM_AVS_ISSLOWSTARTUP_MASK     (1 << PRCM_AVS_ISSLOWSTARTUP)
  61 #define PRCM_AVS_ISMODEENABLE           7
  62 #define PRCM_AVS_ISMODEENABLE_MASK      (1 << PRCM_AVS_ISMODEENABLE)
  63
  64 #define PRCM_BOOT_STATUS        0xFFF
  65 #define PRCM_ROMCODE_A2P        0xFFE
  66 #define PRCM_ROMCODE_P2A        0xFFD
  67 #define PRCM_XP70_CUR_PWR_STATE 0xFFC      /* 4 BYTES */
  68
  69 #define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
  70
  71 #define _PRCM_MBOX_HEADER               0xFE8 /* 16 bytes */
  72 #define PRCM_MBOX_HEADER_REQ_MB0        (_PRCM_MBOX_HEADER + 0x0)
  73 #define PRCM_MBOX_HEADER_REQ_MB1        (_PRCM_MBOX_HEADER + 0x1)
  74 #define PRCM_MBOX_HEADER_REQ_MB2        (_PRCM_MBOX_HEADER + 0x2)
  75 #define PRCM_MBOX_HEADER_REQ_MB3        (_PRCM_MBOX_HEADER + 0x3)
  76 #define PRCM_MBOX_HEADER_REQ_MB4        (_PRCM_MBOX_HEADER + 0x4)
  77 #define PRCM_MBOX_HEADER_REQ_MB5        (_PRCM_MBOX_HEADER + 0x5)
  78 #define PRCM_MBOX_HEADER_ACK_MB0        (_PRCM_MBOX_HEADER + 0x8)
  79
  80 /* Req Mailboxes */
  81 #define PRCM_REQ_MB0 0xFDC /* 12 bytes  */
  82 #define PRCM_REQ_MB1 0xFD0 /* 12 bytes  */
  83 #define PRCM_REQ_MB2 0xFC0 /* 16 bytes  */
  84 #define PRCM_REQ_MB3 0xE4C /* 372 bytes  */
  85 #define PRCM_REQ_MB4 0xE48 /* 4 bytes  */
  86 #define PRCM_REQ_MB5 0xE44 /* 4 bytes  */
  87
  88 /* Ack Mailboxes */
  89 #define PRCM_ACK_MB0 0xE08 /* 52 bytes  */
  90 #define PRCM_ACK_MB1 0xE04 /* 4 bytes */
  91 #define PRCM_ACK_MB2 0xE00 /* 4 bytes */
  92 #define PRCM_ACK_MB3 0xDFC /* 4 bytes */
  93 #define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
  94 #define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
  95
  96 /* Mailbox 0 headers */
  97 #define MB0H_POWER_STATE_TRANS          0
  98 #define MB0H_CONFIG_WAKEUPS_EXE         1
  99 #define MB0H_READ_WAKEUP_ACK            3
 100 #define MB0H_CONFIG_WAKEUPS_SLEEP       4
 101
 102 #define MB0H_WAKEUP_EXE 2
 103 #define MB0H_WAKEUP_SLEEP 5
 104
 105 /* Mailbox 0 REQs */
 106 #define PRCM_REQ_MB0_AP_POWER_STATE     (PRCM_REQ_MB0 + 0x0)
 107 #define PRCM_REQ_MB0_AP_PLL_STATE       (PRCM_REQ_MB0 + 0x1)
 108 #define PRCM_REQ_MB0_ULP_CLOCK_STATE    (PRCM_REQ_MB0 + 0x2)
 109 #define PRCM_REQ_MB0_DO_NOT_WFI         (PRCM_REQ_MB0 + 0x3)
 110 #define PRCM_REQ_MB0_WAKEUP_8500        (PRCM_REQ_MB0 + 0x4)
 111 #define PRCM_REQ_MB0_WAKEUP_4500        (PRCM_REQ_MB0 + 0x8)
 112
 113 /* Mailbox 0 ACKs */
 114 #define PRCM_ACK_MB0_AP_PWRSTTR_STATUS  (PRCM_ACK_MB0 + 0x0)
 115 #define PRCM_ACK_MB0_READ_POINTER       (PRCM_ACK_MB0 + 0x1)
 116 #define PRCM_ACK_MB0_WAKEUP_0_8500      (PRCM_ACK_MB0 + 0x4)
 117 #define PRCM_ACK_MB0_WAKEUP_0_4500      (PRCM_ACK_MB0 + 0x8)
 118 #define PRCM_ACK_MB0_WAKEUP_1_8500      (PRCM_ACK_MB0 + 0x1C)
 119 #define PRCM_ACK_MB0_WAKEUP_1_4500      (PRCM_ACK_MB0 + 0x20)
 120 #define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
 121
 122 /* Mailbox 1 headers */
 123 #define MB1H_ARM_APE_OPP 0x0
 124 #define MB1H_RESET_MODEM 0x2
 125 #define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
 126 #define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
 127 #define MB1H_RELEASE_USB_WAKEUP 0x5
 128 #define MB1H_PLL_ON_OFF 0x6
 129
 130 /* Mailbox 1 Requests */
 131 #define PRCM_REQ_MB1_ARM_OPP                    (PRCM_REQ_MB1 + 0x0)
 132 #define PRCM_REQ_MB1_APE_OPP                    (PRCM_REQ_MB1 + 0x1)
 133 #define PRCM_REQ_MB1_PLL_ON_OFF                 (PRCM_REQ_MB1 + 0x4)
 134 #define PLL_SOC0_OFF    0x1
 135 #define PLL_SOC0_ON     0x2
 136 #define PLL_SOC1_OFF    0x4
 137 #define PLL_SOC1_ON     0x8
 138
 139 /* Mailbox 1 ACKs */
 140 #define PRCM_ACK_MB1_CURRENT_ARM_OPP    (PRCM_ACK_MB1 + 0x0)
 141 #define PRCM_ACK_MB1_CURRENT_APE_OPP    (PRCM_ACK_MB1 + 0x1)
 142 #define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
 143 #define PRCM_ACK_MB1_DVFS_STATUS        (PRCM_ACK_MB1 + 0x3)
 144
 145 /* Mailbox 2 headers */
 146 #define MB2H_DPS        0x0
 147 #define MB2H_AUTO_PWR   0x1
 148
 149 /* Mailbox 2 REQs */
 150 #define PRCM_REQ_MB2_SVA_MMDSP          (PRCM_REQ_MB2 + 0x0)
 151 #define PRCM_REQ_MB2_SVA_PIPE           (PRCM_REQ_MB2 + 0x1)
 152 #define PRCM_REQ_MB2_SIA_MMDSP          (PRCM_REQ_MB2 + 0x2)
 153 #define PRCM_REQ_MB2_SIA_PIPE           (PRCM_REQ_MB2 + 0x3)
 154 #define PRCM_REQ_MB2_SGA                (PRCM_REQ_MB2 + 0x4)
 155 #define PRCM_REQ_MB2_B2R2_MCDE          (PRCM_REQ_MB2 + 0x5)
 156 #define PRCM_REQ_MB2_ESRAM12            (PRCM_REQ_MB2 + 0x6)
 157 #define PRCM_REQ_MB2_ESRAM34            (PRCM_REQ_MB2 + 0x7)
 158 #define PRCM_REQ_MB2_AUTO_PM_SLEEP      (PRCM_REQ_MB2 + 0x8)
 159 #define PRCM_REQ_MB2_AUTO_PM_IDLE       (PRCM_REQ_MB2 + 0xC)
 160
 161 /* Mailbox 2 ACKs */
 162 #define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
 163 #define HWACC_PWR_ST_OK 0xFE
 164
 165 /* Mailbox 3 headers */
 166 #define MB3H_ANC        0x0
 167 #define MB3H_SIDETONE   0x1
 168 #define MB3H_SYSCLK     0xE
 169
 170 /* Mailbox 3 Requests */
 171 #define PRCM_REQ_MB3_ANC_FIR_COEFF      (PRCM_REQ_MB3 + 0x0)
 172 #define PRCM_REQ_MB3_ANC_IIR_COEFF      (PRCM_REQ_MB3 + 0x20)
 173 #define PRCM_REQ_MB3_ANC_SHIFTER        (PRCM_REQ_MB3 + 0x60)
 174 #define PRCM_REQ_MB3_ANC_WARP           (PRCM_REQ_MB3 + 0x64)
 175 #define PRCM_REQ_MB3_SIDETONE_FIR_GAIN  (PRCM_REQ_MB3 + 0x68)
 176 #define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
 177 #define PRCM_REQ_MB3_SYSCLK_MGT         (PRCM_REQ_MB3 + 0x16C)
 178
 179 /* Mailbox 4 headers */
 180 #define MB4H_DDR_INIT   0x0
 181 #define MB4H_MEM_ST     0x1
 182 #define MB4H_HOTDOG     0x12
 183 #define MB4H_HOTMON     0x13
 184 #define MB4H_HOT_PERIOD 0x14
 185 #define MB4H_A9WDOG_CONF 0x16
 186 #define MB4H_A9WDOG_EN   0x17
 187 #define MB4H_A9WDOG_DIS  0x18
 188 #define MB4H_A9WDOG_LOAD 0x19
 189 #define MB4H_A9WDOG_KICK 0x20
 190
 191 /* Mailbox 4 Requests */
 192 #define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE       (PRCM_REQ_MB4 + 0x0)
 193 #define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE        (PRCM_REQ_MB4 + 0x1)
 194 #define PRCM_REQ_MB4_ESRAM0_ST                  (PRCM_REQ_MB4 + 0x3)
 195 #define PRCM_REQ_MB4_HOTDOG_THRESHOLD           (PRCM_REQ_MB4 + 0x0)
 196 #define PRCM_REQ_MB4_HOTMON_LOW                 (PRCM_REQ_MB4 + 0x0)
 197 #define PRCM_REQ_MB4_HOTMON_HIGH                (PRCM_REQ_MB4 + 0x1)
 198 #define PRCM_REQ_MB4_HOTMON_CONFIG              (PRCM_REQ_MB4 + 0x2)
 199 #define PRCM_REQ_MB4_HOT_PERIOD                 (PRCM_REQ_MB4 + 0x0)
 200 #define HOTMON_CONFIG_LOW                       BIT(0)
 201 #define HOTMON_CONFIG_HIGH                      BIT(1)
 202 #define PRCM_REQ_MB4_A9WDOG_0                   (PRCM_REQ_MB4 + 0x0)
 203 #define PRCM_REQ_MB4_A9WDOG_1                   (PRCM_REQ_MB4 + 0x1)
 204 #define PRCM_REQ_MB4_A9WDOG_2                   (PRCM_REQ_MB4 + 0x2)
 205 #define PRCM_REQ_MB4_A9WDOG_3                   (PRCM_REQ_MB4 + 0x3)
 206 #define A9WDOG_AUTO_OFF_EN                      BIT(7)
 207 #define A9WDOG_AUTO_OFF_DIS                     0
 208 #define A9WDOG_ID_MASK                          0xf
 209
 210 /* Mailbox 5 Requests */
 211 #define PRCM_REQ_MB5_I2C_SLAVE_OP       (PRCM_REQ_MB5 + 0x0)
 212 #define PRCM_REQ_MB5_I2C_HW_BITS        (PRCM_REQ_MB5 + 0x1)
 213 #define PRCM_REQ_MB5_I2C_REG            (PRCM_REQ_MB5 + 0x2)
 214 #define PRCM_REQ_MB5_I2C_VAL            (PRCM_REQ_MB5 + 0x3)
 215 #define PRCMU_I2C_WRITE(slave) (((slave) << 1) | BIT(6))
 216 #define PRCMU_I2C_READ(slave) (((slave) << 1) | BIT(0) | BIT(6))
 217 #define PRCMU_I2C_STOP_EN               BIT(3)
 218
 219 /* Mailbox 5 ACKs */
 220 #define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
 221 #define PRCM_ACK_MB5_I2C_VAL    (PRCM_ACK_MB5 + 0x3)
 222 #define I2C_WR_OK 0x1
 223 #define I2C_RD_OK 0x2
 224
 225 #define NUM_MB 8
 226 #define MBOX_BIT BIT
 227 #define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
 228
 229 /*
 230  * Wakeups/IRQs
 231  */
 232
 233 #define WAKEUP_BIT_RTC BIT(0)
 234 #define WAKEUP_BIT_RTT0 BIT(1)
 235 #define WAKEUP_BIT_RTT1 BIT(2)
 236 #define WAKEUP_BIT_HSI0 BIT(3)
 237 #define WAKEUP_BIT_HSI1 BIT(4)
 238 #define WAKEUP_BIT_CA_WAKE BIT(5)
 239 #define WAKEUP_BIT_USB BIT(6)
 240 #define WAKEUP_BIT_ABB BIT(7)
 241 #define WAKEUP_BIT_ABB_FIFO BIT(8)
 242 #define WAKEUP_BIT_SYSCLK_OK BIT(9)
 243 #define WAKEUP_BIT_CA_SLEEP BIT(10)
 244 #define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
 245 #define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
 246 #define WAKEUP_BIT_ANC_OK BIT(13)
 247 #define WAKEUP_BIT_SW_ERROR BIT(14)
 248 #define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
 249 #define WAKEUP_BIT_ARM BIT(17)
 250 #define WAKEUP_BIT_HOTMON_LOW BIT(18)
 251 #define WAKEUP_BIT_HOTMON_HIGH BIT(19)
 252 #define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
 253 #define WAKEUP_BIT_GPIO0 BIT(23)
 254 #define WAKEUP_BIT_GPIO1 BIT(24)
 255 #define WAKEUP_BIT_GPIO2 BIT(25)
 256 #define WAKEUP_BIT_GPIO3 BIT(26)
 257 #define WAKEUP_BIT_GPIO4 BIT(27)
 258 #define WAKEUP_BIT_GPIO5 BIT(28)
 259 #define WAKEUP_BIT_GPIO6 BIT(29)
 260 #define WAKEUP_BIT_GPIO7 BIT(30)
 261 #define WAKEUP_BIT_GPIO8 BIT(31)
 262
 263 static struct {
 264         bool valid;
 265         struct prcmu_fw_version version;
 266 } fw_info;
 267
 268 static struct irq_domain *db8500_irq_domain;
 269
 270 /*
 271  * This vector maps irq numbers to the bits in the bit field used in
 272  * communication with the PRCMU firmware.
 273  *
 274  * The reason for having this is to keep the irq numbers contiguous even though
 275  * the bits in the bit field are not. (The bits also have a tendency to move
 276  * around, to further complicate matters.)
 277  */
 278 #define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
 279 #define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
 280 static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
 281         IRQ_ENTRY(RTC),
 282         IRQ_ENTRY(RTT0),
 283         IRQ_ENTRY(RTT1),
 284         IRQ_ENTRY(HSI0),
 285         IRQ_ENTRY(HSI1),
 286         IRQ_ENTRY(CA_WAKE),
 287         IRQ_ENTRY(USB),
 288         IRQ_ENTRY(ABB),
 289         IRQ_ENTRY(ABB_FIFO),
 290         IRQ_ENTRY(CA_SLEEP),
 291         IRQ_ENTRY(ARM),
 292         IRQ_ENTRY(HOTMON_LOW),
 293         IRQ_ENTRY(HOTMON_HIGH),
 294         IRQ_ENTRY(MODEM_SW_RESET_REQ),
 295         IRQ_ENTRY(GPIO0),
 296         IRQ_ENTRY(GPIO1),
 297         IRQ_ENTRY(GPIO2),
 298         IRQ_ENTRY(GPIO3),
 299         IRQ_ENTRY(GPIO4),
 300         IRQ_ENTRY(GPIO5),
 301         IRQ_ENTRY(GPIO6),
 302         IRQ_ENTRY(GPIO7),
 303         IRQ_ENTRY(GPIO8)
 304 };
 305
 306 #define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
 307 #define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
 308 static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
 309         WAKEUP_ENTRY(RTC),
 310         WAKEUP_ENTRY(RTT0),
 311         WAKEUP_ENTRY(RTT1),
 312         WAKEUP_ENTRY(HSI0),
 313         WAKEUP_ENTRY(HSI1),
 314         WAKEUP_ENTRY(USB),
 315         WAKEUP_ENTRY(ABB),
 316         WAKEUP_ENTRY(ABB_FIFO),
 317         WAKEUP_ENTRY(ARM)
 318 };
 319
 320 /*
 321  * mb0_transfer - state needed for mailbox 0 communication.
 322  * @lock:               The transaction lock.
 323  * @dbb_events_lock:    A lock used to handle concurrent access to (parts of)
 324  *                      the request data.
 325  * @mask_work:          Work structure used for (un)masking wakeup interrupts.
 326  * @req:                Request data that need to persist between requests.
 327  */
 328 static struct {
 329         spinlock_t lock;
 330         spinlock_t dbb_irqs_lock;
 331         struct work_struct mask_work;
 332         struct mutex ac_wake_lock;
 333         struct completion ac_wake_work;
 334         struct {
 335                 u32 dbb_irqs;
 336                 u32 dbb_wakeups;
 337                 u32 abb_events;
 338         } req;
 339 } mb0_transfer;
 340
 341 /*
 342  * mb1_transfer - state needed for mailbox 1 communication.
 343  * @lock:       The transaction lock.
 344  * @work:       The transaction completion structure.
 345  * @ape_opp:    The current APE OPP.
 346  * @ack:        Reply ("acknowledge") data.
 347  */
 348 static struct {
 349         struct mutex lock;
 350         struct completion work;
 351         u8 ape_opp;
 352         struct {
 353                 u8 header;
 354                 u8 arm_opp;
 355                 u8 ape_opp;
 356                 u8 ape_voltage_status;
 357         } ack;
 358 } mb1_transfer;
 359
 360 /*
 361  * mb2_transfer - state needed for mailbox 2 communication.
 362  * @lock:            The transaction lock.
 363  * @work:            The transaction completion structure.
 364  * @auto_pm_lock:    The autonomous power management configuration lock.
 365  * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
 366  * @req:             Request data that need to persist between requests.
 367  * @ack:             Reply ("acknowledge") data.
 368  */
 369 static struct {
 370         struct mutex lock;
 371         struct completion work;
 372         spinlock_t auto_pm_lock;
 373         bool auto_pm_enabled;
 374         struct {
 375                 u8 status;
 376         } ack;
 377 } mb2_transfer;
 378
 379 /*
 380  * mb3_transfer - state needed for mailbox 3 communication.
 381  * @lock:               The request lock.
 382  * @sysclk_lock:        A lock used to handle concurrent sysclk requests.
 383  * @sysclk_work:        Work structure used for sysclk requests.
 384  */
 385 static struct {
 386         spinlock_t lock;
 387         struct mutex sysclk_lock;
 388         struct completion sysclk_work;
 389 } mb3_transfer;
 390
 391 /*
 392  * mb4_transfer - state needed for mailbox 4 communication.
 393  * @lock:       The transaction lock.
 394  * @work:       The transaction completion structure.
 395  */
 396 static struct {
 397         struct mutex lock;
 398         struct completion work;
 399 } mb4_transfer;
 400
 401 /*
 402  * mb5_transfer - state needed for mailbox 5 communication.
 403  * @lock:       The transaction lock.
 404  * @work:       The transaction completion structure.
 405  * @ack:        Reply ("acknowledge") data.
 406  */
 407 static struct {
 408         struct mutex lock;
 409         struct completion work;
 410         struct {
 411                 u8 status;
 412                 u8 value;
 413         } ack;
 414 } mb5_transfer;
 415
 416 static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
 417
 418 /* Spinlocks */
 419 static DEFINE_SPINLOCK(prcmu_lock);
 420 static DEFINE_SPINLOCK(clkout_lock);
 421
 422 /* Global var to runtime determine TCDM base for v2 or v1 */
 423 static __iomem void *tcdm_base;
 424
 425 struct clk_mgt {
 426         void __iomem *reg;
 427         u32 pllsw;
 428         int branch;
 429         bool clk38div;
 430 };
 431
 432 enum {
 433         PLL_RAW,
 434         PLL_FIX,
 435         PLL_DIV
 436 };
 437
 438 static DEFINE_SPINLOCK(clk_mgt_lock);
 439
 440 #define CLK_MGT_ENTRY(_name, _branch, _clk38div)[PRCMU_##_name] = \
 441         { (PRCM_##_name##_MGT), 0 , _branch, _clk38div}
 442 struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
 443         CLK_MGT_ENTRY(SGACLK, PLL_DIV, false),
 444         CLK_MGT_ENTRY(UARTCLK, PLL_FIX, true),
 445         CLK_MGT_ENTRY(MSP02CLK, PLL_FIX, true),
 446         CLK_MGT_ENTRY(MSP1CLK, PLL_FIX, true),
 447         CLK_MGT_ENTRY(I2CCLK, PLL_FIX, true),
 448         CLK_MGT_ENTRY(SDMMCCLK, PLL_DIV, true),
 449         CLK_MGT_ENTRY(SLIMCLK, PLL_FIX, true),
 450         CLK_MGT_ENTRY(PER1CLK, PLL_DIV, true),
 451         CLK_MGT_ENTRY(PER2CLK, PLL_DIV, true),
 452         CLK_MGT_ENTRY(PER3CLK, PLL_DIV, true),
 453         CLK_MGT_ENTRY(PER5CLK, PLL_DIV, true),
 454         CLK_MGT_ENTRY(PER6CLK, PLL_DIV, true),
 455         CLK_MGT_ENTRY(PER7CLK, PLL_DIV, true),
 456         CLK_MGT_ENTRY(LCDCLK, PLL_FIX, true),
 457         CLK_MGT_ENTRY(BMLCLK, PLL_DIV, true),
 458         CLK_MGT_ENTRY(HSITXCLK, PLL_DIV, true),
 459         CLK_MGT_ENTRY(HSIRXCLK, PLL_DIV, true),
 460         CLK_MGT_ENTRY(HDMICLK, PLL_FIX, false),
 461         CLK_MGT_ENTRY(APEATCLK, PLL_DIV, true),
 462         CLK_MGT_ENTRY(APETRACECLK, PLL_DIV, true),
 463         CLK_MGT_ENTRY(MCDECLK, PLL_DIV, true),
 464         CLK_MGT_ENTRY(IPI2CCLK, PLL_FIX, true),
 465         CLK_MGT_ENTRY(DSIALTCLK, PLL_FIX, false),
 466         CLK_MGT_ENTRY(DMACLK, PLL_DIV, true),
 467         CLK_MGT_ENTRY(B2R2CLK, PLL_DIV, true),
 468         CLK_MGT_ENTRY(TVCLK, PLL_FIX, true),
 469         CLK_MGT_ENTRY(SSPCLK, PLL_FIX, true),
 470         CLK_MGT_ENTRY(RNGCLK, PLL_FIX, true),
 471         CLK_MGT_ENTRY(UICCCLK, PLL_FIX, false),
 472 };
 473
 474 struct dsiclk {
 475         u32 divsel_mask;
 476         u32 divsel_shift;
 477         u32 divsel;
 478 };
 479
 480 static struct dsiclk dsiclk[2] = {
 481         {
 482                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_MASK,
 483                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI0_PLLOUT_DIVSEL_SHIFT,
 484                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 485         },
 486         {
 487                 .divsel_mask = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_MASK,
 488                 .divsel_shift = PRCM_DSI_PLLOUT_SEL_DSI1_PLLOUT_DIVSEL_SHIFT,
 489                 .divsel = PRCM_DSI_PLLOUT_SEL_PHI,
 490         }
 491 };
 492
 493 struct dsiescclk {
 494         u32 en;
 495         u32 div_mask;
 496         u32 div_shift;
 497 };
 498
 499 static struct dsiescclk dsiescclk[3] = {
 500         {
 501                 .en = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_EN,
 502                 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,
 503                 .div_shift = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_SHIFT,
 504         },
 505         {
 506                 .en = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_EN,
 507                 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,
 508                 .div_shift = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_SHIFT,
 509         },
 510         {
 511                 .en = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_EN,
 512                 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,
 513                 .div_shift = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_SHIFT,
 514         }
 515 };
 516
 517
 518 /*
 519 * Used by MCDE to setup all necessary PRCMU registers
 520 */
 521 #define PRCMU_RESET_DSIPLL              0x00004000
 522 #define PRCMU_UNCLAMP_DSIPLL            0x00400800
 523
 524 #define PRCMU_CLK_PLL_DIV_SHIFT         0
 525 #define PRCMU_CLK_PLL_SW_SHIFT          5
 526 #define PRCMU_CLK_38                    (1 << 9)
 527 #define PRCMU_CLK_38_SRC                (1 << 10)
 528 #define PRCMU_CLK_38_DIV                (1 << 11)
 529
 530 /* PLLDIV=12, PLLSW=4 (PLLDDR) */
 531 #define PRCMU_DSI_CLOCK_SETTING         0x0000008C
 532
 533 /* DPI 50000000 Hz */
 534 #define PRCMU_DPI_CLOCK_SETTING         ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
 535                                           (16 << PRCMU_CLK_PLL_DIV_SHIFT))
 536 #define PRCMU_DSI_LP_CLOCK_SETTING      0x00000E00
 537
 538 /* D=101, N=1, R=4, SELDIV2=0 */
 539 #define PRCMU_PLLDSI_FREQ_SETTING       0x00040165
 540
 541 #define PRCMU_ENABLE_PLLDSI             0x00000001
 542 #define PRCMU_DISABLE_PLLDSI            0x00000000
 543 #define PRCMU_RELEASE_RESET_DSS         0x0000400C
 544 #define PRCMU_DSI_PLLOUT_SEL_SETTING    0x00000202
 545 /* ESC clk, div0=1, div1=1, div2=3 */
 546 #define PRCMU_ENABLE_ESCAPE_CLOCK_DIV   0x07030101
 547 #define PRCMU_DISABLE_ESCAPE_CLOCK_DIV  0x00030101
 548 #define PRCMU_DSI_RESET_SW              0x00000007
 549
 550 #define PRCMU_PLLDSI_LOCKP_LOCKED       0x3
 551
 552 int db8500_prcmu_enable_dsipll(void)
 553 {
 554         int i;
 555
 556         /* Clear DSIPLL_RESETN */
 557         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
 558         /* Unclamp DSIPLL in/out */
 559         writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
 560
 561         /* Set DSI PLL FREQ */
 562         writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
 563         writel(PRCMU_DSI_PLLOUT_SEL_SETTING, PRCM_DSI_PLLOUT_SEL);
 564         /* Enable Escape clocks */
 565         writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 566
 567         /* Start DSI PLL */
 568         writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 569         /* Reset DSI PLL */
 570         writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
 571         for (i = 0; i < 10; i++) {
 572                 if ((readl(PRCM_PLLDSI_LOCKP) & PRCMU_PLLDSI_LOCKP_LOCKED)
 573                                         == PRCMU_PLLDSI_LOCKP_LOCKED)
 574                         break;
 575                 udelay(100);
 576         }
 577         /* Set DSIPLL_RESETN */
 578         writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
 579         return 0;
 580 }
 581
 582 int db8500_prcmu_disable_dsipll(void)
 583 {
 584         /* Disable dsi pll */
 585         writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
 586         /* Disable  escapeclock */
 587         writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
 588         return 0;
 589 }
 590
 591 int db8500_prcmu_set_display_clocks(void)
 592 {
 593         unsigned long flags;
 594
 595         spin_lock_irqsave(&clk_mgt_lock, flags);
 596
 597         /* Grab the HW semaphore. */
 598         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
 599                 cpu_relax();
 600
 601         writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
 602         writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
 603         writel(PRCMU_DPI_CLOCK_SETTING, PRCM_LCDCLK_MGT);
 604
 605         /* Release the HW semaphore. */
 606         writel(0, PRCM_SEM);
 607
 608         spin_unlock_irqrestore(&clk_mgt_lock, flags);
 609
 610         return 0;
 611 }
 612
 613 u32 db8500_prcmu_read(unsigned int reg)
 614 {
 615         return readl(_PRCMU_BASE + reg);
 616 }
 617
 618 void db8500_prcmu_write(unsigned int reg, u32 value)
 619 {
 620         unsigned long flags;
 621
 622         spin_lock_irqsave(&prcmu_lock, flags);
 623         writel(value, (_PRCMU_BASE + reg));
 624         spin_unlock_irqrestore(&prcmu_lock, flags);
 625 }
 626
 627 void db8500_prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
 628 {
 629         u32 val;
 630         unsigned long flags;
 631
 632         spin_lock_irqsave(&prcmu_lock, flags);
 633         val = readl(_PRCMU_BASE + reg);
 634         val = ((val & ~mask) | (value & mask));
 635         writel(val, (_PRCMU_BASE + reg));
 636         spin_unlock_irqrestore(&prcmu_lock, flags);
 637 }
 638
 639 struct prcmu_fw_version *prcmu_get_fw_version(void)
 640 {
 641         return fw_info.valid ? &fw_info.version : NULL;
 642 }
 643
 644 bool prcmu_has_arm_maxopp(void)
 645 {
 646         return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
 647                 PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
 648 }
 649
 650 /**
 651  * prcmu_get_boot_status - PRCMU boot status checking
 652  * Returns: the current PRCMU boot status
 653  */
 654 int prcmu_get_boot_status(void)
 655 {
 656         return readb(tcdm_base + PRCM_BOOT_STATUS);
 657 }
 658
 659 /**
 660  * prcmu_set_rc_a2p - This function is used to run few power state sequences
 661  * @val: Value to be set, i.e. transition requested
 662  * Returns: 0 on success, -EINVAL on invalid argument
 663  *
 664  * This function is used to run the following power state sequences -
 665  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 666  */
 667 int prcmu_set_rc_a2p(enum romcode_write val)
 668 {
 669         if (val < RDY_2_DS || val > RDY_2_XP70_RST)
 670                 return -EINVAL;
 671         writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
 672         return 0;
 673 }
 674
 675 /**
 676  * prcmu_get_rc_p2a - This function is used to get power state sequences
 677  * Returns: the power transition that has last happened
 678  *
 679  * This function can return the following transitions-
 680  * any state to ApReset,  ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
 681  */
 682 enum romcode_read prcmu_get_rc_p2a(void)
 683 {
 684         return readb(tcdm_base + PRCM_ROMCODE_P2A);
 685 }
 686
 687 /**
 688  * prcmu_get_current_mode - Return the current XP70 power mode
 689  * Returns: Returns the current AP(ARM) power mode: init,
 690  * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
 691  */
 692 enum ap_pwrst prcmu_get_xp70_current_state(void)
 693 {
 694         return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
 695 }
 696
 697 /**
 698  * prcmu_config_clkout - Configure one of the programmable clock outputs.
 699  * @clkout:     The CLKOUT number (0 or 1).
 700  * @source:     The clock to be used (one of the PRCMU_CLKSRC_*).
 701  * @div:        The divider to be applied.
 702  *
 703  * Configures one of the programmable clock outputs (CLKOUTs).
 704  * @div should be in the range [1,63] to request a configuration, or 0 to
 705  * inform that the configuration is no longer requested.
 706  */
 707 int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
 708 {
 709         static int requests[2];
 710         int r = 0;
 711         unsigned long flags;
 712         u32 val;
 713         u32 bits;
 714         u32 mask;
 715         u32 div_mask;
 716
 717         BUG_ON(clkout > 1);
 718         BUG_ON(div > 63);
 719         BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
 720
 721         if (!div && !requests[clkout])
 722                 return -EINVAL;
 723
 724         switch (clkout) {
 725         case 0:
 726                 div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
 727                 mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
 728                 bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
 729                         (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
 730                 break;
 731         case 1:
 732                 div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
 733                 mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
 734                         PRCM_CLKOCR_CLK1TYPE);
 735                 bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
 736                         (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
 737                 break;
 738         }
 739         bits &= mask;
 740
 741         spin_lock_irqsave(&clkout_lock, flags);
 742
 743         val = readl(PRCM_CLKOCR);
 744         if (val & div_mask) {
 745                 if (div) {
 746                         if ((val & mask) != bits) {
 747                                 r = -EBUSY;
 748                                 goto unlock_and_return;
 749                         }
 750                 } else {
 751                         if ((val & mask & ~div_mask) != bits) {
 752                                 r = -EINVAL;
 753                                 goto unlock_and_return;
 754                         }
 755                 }
 756         }
 757         writel((bits | (val & ~mask)), PRCM_CLKOCR);
 758         requests[clkout] += (div ? 1 : -1);
 759
 760 unlock_and_return:
 761         spin_unlock_irqrestore(&clkout_lock, flags);
 762
 763         return r;
 764 }
 765
 766 int db8500_prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
 767 {
 768         unsigned long flags;
 769
 770         BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
 771
 772         spin_lock_irqsave(&mb0_transfer.lock, flags);
 773
 774         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 775                 cpu_relax();
 776
 777         writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 778         writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
 779         writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
 780         writeb((keep_ulp_clk ? 1 : 0),
 781                 (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
 782         writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
 783         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 784
 785         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 786
 787         return 0;
 788 }
 789
 790 u8 db8500_prcmu_get_power_state_result(void)
 791 {
 792         return readb(tcdm_base + PRCM_ACK_MB0_AP_PWRSTTR_STATUS);
 793 }
 794
 795 /* This function decouple the gic from the prcmu */
 796 int db8500_prcmu_gic_decouple(void)
 797 {
 798         u32 val = readl(PRCM_A9_MASK_REQ);
 799
 800         /* Set bit 0 register value to 1 */
 801         writel(val | PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ,
 802                PRCM_A9_MASK_REQ);
 803
 804         /* Make sure the register is updated */
 805         readl(PRCM_A9_MASK_REQ);
 806
 807         /* Wait a few cycles for the gic mask completion */
 808         udelay(1);
 809
 810         return 0;
 811 }
 812
 813 /* This function recouple the gic with the prcmu */
 814 int db8500_prcmu_gic_recouple(void)
 815 {
 816         u32 val = readl(PRCM_A9_MASK_REQ);
 817
 818         /* Set bit 0 register value to 0 */
 819         writel(val & ~PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ, PRCM_A9_MASK_REQ);
 820
 821         return 0;
 822 }
 823
 824 #define PRCMU_GIC_NUMBER_REGS 5
 825
 826 /*
 827  * This function checks if there are pending irq on the gic. It only
 828  * makes sense if the gic has been decoupled before with the
 829  * db8500_prcmu_gic_decouple function. Disabling an interrupt only
 830  * disables the forwarding of the interrupt to any CPU interface. It
 831  * does not prevent the interrupt from changing state, for example
 832  * becoming pending, or active and pending if it is already
 833  * active. Hence, we have to check the interrupt is pending *and* is
 834  * active.
 835  */
 836 bool db8500_prcmu_gic_pending_irq(void)
 837 {
 838         u32 pr; /* Pending register */
 839         u32 er; /* Enable register */
 840         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 841         int i;
 842
 843         /* 5 registers. STI & PPI not skipped */
 844         for (i = 0; i < PRCMU_GIC_NUMBER_REGS; i++) {
 845
 846                 pr = readl_relaxed(dist_base + GIC_DIST_PENDING_SET + i * 4);
 847                 er = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
 848
 849                 if (pr & er)
 850                         return true; /* There is a pending interrupt */
 851         }
 852
 853         return false;
 854 }
 855
 856 /*
 857  * This function checks if there are pending interrupt on the
 858  * prcmu which has been delegated to monitor the irqs with the
 859  * db8500_prcmu_copy_gic_settings function.
 860  */
 861 bool db8500_prcmu_pending_irq(void)
 862 {
 863         u32 it, im;
 864         int i;
 865
 866         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 867                 it = readl(PRCM_ARMITVAL31TO0 + i * 4);
 868                 im = readl(PRCM_ARMITMSK31TO0 + i * 4);
 869                 if (it & im)
 870                         return true; /* There is a pending interrupt */
 871         }
 872
 873         return false;
 874 }
 875
 876 /*
 877  * This function checks if the specified cpu is in in WFI. It's usage
 878  * makes sense only if the gic is decoupled with the db8500_prcmu_gic_decouple
 879  * function. Of course passing smp_processor_id() to this function will
 880  * always return false...
 881  */
 882 bool db8500_prcmu_is_cpu_in_wfi(int cpu)
 883 {
 884         return readl(PRCM_ARM_WFI_STANDBY) & cpu ? PRCM_ARM_WFI_STANDBY_WFI1 :
 885                      PRCM_ARM_WFI_STANDBY_WFI0;
 886 }
 887
 888 /*
 889  * This function copies the gic SPI settings to the prcmu in order to
 890  * monitor them and abort/finish the retention/off sequence or state.
 891  */
 892 int db8500_prcmu_copy_gic_settings(void)
 893 {
 894         u32 er; /* Enable register */
 895         void __iomem *dist_base = __io_address(U8500_GIC_DIST_BASE);
 896         int i;
 897
 898         /* We skip the STI and PPI */
 899         for (i = 0; i < PRCMU_GIC_NUMBER_REGS - 1; i++) {
 900                 er = readl_relaxed(dist_base +
 901                                    GIC_DIST_ENABLE_SET + (i + 1) * 4);
 902                 writel(er, PRCM_ARMITMSK31TO0 + i * 4);
 903         }
 904
 905         return 0;
 906 }
 907
 908 /* This function should only be called while mb0_transfer.lock is held. */
 909 static void config_wakeups(void)
 910 {
 911         const u8 header[2] = {
 912                 MB0H_CONFIG_WAKEUPS_EXE,
 913                 MB0H_CONFIG_WAKEUPS_SLEEP
 914         };
 915         static u32 last_dbb_events;
 916         static u32 last_abb_events;
 917         u32 dbb_events;
 918         u32 abb_events;
 919         unsigned int i;
 920
 921         dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
 922         dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
 923
 924         abb_events = mb0_transfer.req.abb_events;
 925
 926         if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
 927                 return;
 928
 929         for (i = 0; i < 2; i++) {
 930                 while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
 931                         cpu_relax();
 932                 writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
 933                 writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
 934                 writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
 935                 writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
 936         }
 937         last_dbb_events = dbb_events;
 938         last_abb_events = abb_events;
 939 }
 940
 941 void db8500_prcmu_enable_wakeups(u32 wakeups)
 942 {
 943         unsigned long flags;
 944         u32 bits;
 945         int i;
 946
 947         BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
 948
 949         for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
 950                 if (wakeups & BIT(i))
 951                         bits |= prcmu_wakeup_bit[i];
 952         }
 953
 954         spin_lock_irqsave(&mb0_transfer.lock, flags);
 955
 956         mb0_transfer.req.dbb_wakeups = bits;
 957         config_wakeups();
 958
 959         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 960 }
 961
 962 void db8500_prcmu_config_abb_event_readout(u32 abb_events)
 963 {
 964         unsigned long flags;
 965
 966         spin_lock_irqsave(&mb0_transfer.lock, flags);
 967
 968         mb0_transfer.req.abb_events = abb_events;
 969         config_wakeups();
 970
 971         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
 972 }
 973
 974 void db8500_prcmu_get_abb_event_buffer(void __iomem **buf)
 975 {
 976         if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
 977                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
 978         else
 979                 *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
 980 }
 981
 982 /**
 983  * db8500_prcmu_set_arm_opp - set the appropriate ARM OPP
 984  * @opp: The new ARM operating point to which transition is to be made
 985  * Returns: 0 on success, non-zero on failure
 986  *
 987  * This function sets the the operating point of the ARM.
 988  */
 989 int db8500_prcmu_set_arm_opp(u8 opp)
 990 {
 991         int r;
 992
 993         if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
 994                 return -EINVAL;
 995
 996         r = 0;
 997
 998         mutex_lock(&mb1_transfer.lock);
 999
1000         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1001                 cpu_relax();
1002
1003         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1004         writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1005         writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1006
1007         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1008         wait_for_completion(&mb1_transfer.work);
1009
1010         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1011                 (mb1_transfer.ack.arm_opp != opp))
1012                 r = -EIO;
1013
1014         mutex_unlock(&mb1_transfer.lock);
1015
1016         return r;
1017 }
1018
1019 /**
1020  * db8500_prcmu_get_arm_opp - get the current ARM OPP
1021  *
1022  * Returns: the current ARM OPP
1023  */
1024 int db8500_prcmu_get_arm_opp(void)
1025 {
1026         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
1027 }
1028
1029 /**
1030  * db8500_prcmu_get_ddr_opp - get the current DDR OPP
1031  *
1032  * Returns: the current DDR OPP
1033  */
1034 int db8500_prcmu_get_ddr_opp(void)
1035 {
1036         return readb(PRCM_DDR_SUBSYS_APE_MINBW);
1037 }
1038
1039 /**
1040  * db8500_set_ddr_opp - set the appropriate DDR OPP
1041  * @opp: The new DDR operating point to which transition is to be made
1042  * Returns: 0 on success, non-zero on failure
1043  *
1044  * This function sets the operating point of the DDR.
1045  */
1046 static bool enable_set_ddr_opp;
1047 int db8500_prcmu_set_ddr_opp(u8 opp)
1048 {
1049         if (opp < DDR_100_OPP || opp > DDR_25_OPP)
1050                 return -EINVAL;
1051         /* Changing the DDR OPP can hang the hardware pre-v21 */
1052         if (enable_set_ddr_opp)
1053                 writeb(opp, PRCM_DDR_SUBSYS_APE_MINBW);
1054
1055         return 0;
1056 }
1057
1058 /* Divide the frequency of certain clocks by 2 for APE_50_PARTLY_25_OPP. */
1059 static void request_even_slower_clocks(bool enable)
1060 {
1061         void __iomem *clock_reg[] = {
1062                 PRCM_ACLK_MGT,
1063                 PRCM_DMACLK_MGT
1064         };
1065         unsigned long flags;
1066         unsigned int i;
1067
1068         spin_lock_irqsave(&clk_mgt_lock, flags);
1069
1070         /* Grab the HW semaphore. */
1071         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1072                 cpu_relax();
1073
1074         for (i = 0; i < ARRAY_SIZE(clock_reg); i++) {
1075                 u32 val;
1076                 u32 div;
1077
1078                 val = readl(clock_reg[i]);
1079                 div = (val & PRCM_CLK_MGT_CLKPLLDIV_MASK);
1080                 if (enable) {
1081                         if ((div <= 1) || (div > 15)) {
1082                                 pr_err("prcmu: Bad clock divider %d in %s\n",
1083                                         div, __func__);
1084                                 goto unlock_and_return;
1085                         }
1086                         div <<= 1;
1087                 } else {
1088                         if (div <= 2)
1089                                 goto unlock_and_return;
1090                         div >>= 1;
1091                 }
1092                 val = ((val & ~PRCM_CLK_MGT_CLKPLLDIV_MASK) |
1093                         (div & PRCM_CLK_MGT_CLKPLLDIV_MASK));
1094                 writel(val, clock_reg[i]);
1095         }
1096
1097 unlock_and_return:
1098         /* Release the HW semaphore. */
1099         writel(0, PRCM_SEM);
1100
1101         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1102 }
1103
1104 /**
1105  * db8500_set_ape_opp - set the appropriate APE OPP
1106  * @opp: The new APE operating point to which transition is to be made
1107  * Returns: 0 on success, non-zero on failure
1108  *
1109  * This function sets the operating point of the APE.
1110  */
1111 int db8500_prcmu_set_ape_opp(u8 opp)
1112 {
1113         int r = 0;
1114
1115         if (opp == mb1_transfer.ape_opp)
1116                 return 0;
1117
1118         mutex_lock(&mb1_transfer.lock);
1119
1120         if (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)
1121                 request_even_slower_clocks(false);
1122
1123         if ((opp != APE_100_OPP) && (mb1_transfer.ape_opp != APE_100_OPP))
1124                 goto skip_message;
1125
1126         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1127                 cpu_relax();
1128
1129         writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1130         writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
1131         writeb(((opp == APE_50_PARTLY_25_OPP) ? APE_50_OPP : opp),
1132                 (tcdm_base + PRCM_REQ_MB1_APE_OPP));
1133
1134         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1135         wait_for_completion(&mb1_transfer.work);
1136
1137         if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
1138                 (mb1_transfer.ack.ape_opp != opp))
1139                 r = -EIO;
1140
1141 skip_message:
1142         if ((!r && (opp == APE_50_PARTLY_25_OPP)) ||
1143                 (r && (mb1_transfer.ape_opp == APE_50_PARTLY_25_OPP)))
1144                 request_even_slower_clocks(true);
1145         if (!r)
1146                 mb1_transfer.ape_opp = opp;
1147
1148         mutex_unlock(&mb1_transfer.lock);
1149
1150         return r;
1151 }
1152
1153 /**
1154  * db8500_prcmu_get_ape_opp - get the current APE OPP
1155  *
1156  * Returns: the current APE OPP
1157  */
1158 int db8500_prcmu_get_ape_opp(void)
1159 {
1160         return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
1161 }
1162
1163 /**
1164  * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1165  * @enable: true to request the higher voltage, false to drop a request.
1166  *
1167  * Calls to this function to enable and disable requests must be balanced.
1168  */
1169 int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1170 {
1171         int r = 0;
1172         u8 header;
1173         static unsigned int requests;
1174
1175         mutex_lock(&mb1_transfer.lock);
1176
1177         if (enable) {
1178                 if (0 != requests++)
1179                         goto unlock_and_return;
1180                 header = MB1H_REQUEST_APE_OPP_100_VOLT;
1181         } else {
1182                 if (requests == 0) {
1183                         r = -EIO;
1184                         goto unlock_and_return;
1185                 } else if (1 != requests--) {
1186                         goto unlock_and_return;
1187                 }
1188                 header = MB1H_RELEASE_APE_OPP_100_VOLT;
1189         }
1190
1191         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1192                 cpu_relax();
1193
1194         writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1195
1196         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1197         wait_for_completion(&mb1_transfer.work);
1198
1199         if ((mb1_transfer.ack.header != header) ||
1200                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1201                 r = -EIO;
1202
1203 unlock_and_return:
1204         mutex_unlock(&mb1_transfer.lock);
1205
1206         return r;
1207 }
1208
1209 /**
1210  * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
1211  *
1212  * This function releases the power state requirements of a USB wakeup.
1213  */
1214 int prcmu_release_usb_wakeup_state(void)
1215 {
1216         int r = 0;
1217
1218         mutex_lock(&mb1_transfer.lock);
1219
1220         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1221                 cpu_relax();
1222
1223         writeb(MB1H_RELEASE_USB_WAKEUP,
1224                 (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1225
1226         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1227         wait_for_completion(&mb1_transfer.work);
1228
1229         if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
1230                 ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
1231                 r = -EIO;
1232
1233         mutex_unlock(&mb1_transfer.lock);
1234
1235         return r;
1236 }
1237
1238 static int request_pll(u8 clock, bool enable)
1239 {
1240         int r = 0;
1241
1242         if (clock == PRCMU_PLLSOC0)
1243                 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF);
1244         else if (clock == PRCMU_PLLSOC1)
1245                 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF);
1246         else
1247                 return -EINVAL;
1248
1249         mutex_lock(&mb1_transfer.lock);
1250
1251         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
1252                 cpu_relax();
1253
1254         writeb(MB1H_PLL_ON_OFF, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
1255         writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF));
1256
1257         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
1258         wait_for_completion(&mb1_transfer.work);
1259
1260         if (mb1_transfer.ack.header != MB1H_PLL_ON_OFF)
1261                 r = -EIO;
1262
1263         mutex_unlock(&mb1_transfer.lock);
1264
1265         return r;
1266 }
1267
1268 /**
1269  * db8500_prcmu_set_epod - set the state of a EPOD (power domain)
1270  * @epod_id: The EPOD to set
1271  * @epod_state: The new EPOD state
1272  *
1273  * This function sets the state of a EPOD (power domain). It may not be called
1274  * from interrupt context.
1275  */
1276 int db8500_prcmu_set_epod(u16 epod_id, u8 epod_state)
1277 {
1278         int r = 0;
1279         bool ram_retention = false;
1280         int i;
1281
1282         /* check argument */
1283         BUG_ON(epod_id >= NUM_EPOD_ID);
1284
1285         /* set flag if retention is possible */
1286         switch (epod_id) {
1287         case EPOD_ID_SVAMMDSP:
1288         case EPOD_ID_SIAMMDSP:
1289         case EPOD_ID_ESRAM12:
1290         case EPOD_ID_ESRAM34:
1291                 ram_retention = true;
1292                 break;
1293         }
1294
1295         /* check argument */
1296         BUG_ON(epod_state > EPOD_STATE_ON);
1297         BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
1298
1299         /* get lock */
1300         mutex_lock(&mb2_transfer.lock);
1301
1302         /* wait for mailbox */
1303         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
1304                 cpu_relax();
1305
1306         /* fill in mailbox */
1307         for (i = 0; i < NUM_EPOD_ID; i++)
1308                 writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
1309         writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
1310
1311         writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
1312
1313         writel(MBOX_BIT(2), PRCM_MBOX_CPU_SET);
1314
1315         /*
1316          * The current firmware version does not handle errors correctly,
1317          * and we cannot recover if there is an error.
1318          * This is expected to change when the firmware is updated.
1319          */
1320         if (!wait_for_completion_timeout(&mb2_transfer.work,
1321                         msecs_to_jiffies(20000))) {
1322                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1323                         __func__);
1324                 r = -EIO;
1325                 goto unlock_and_return;
1326         }
1327
1328         if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
1329                 r = -EIO;
1330
1331 unlock_and_return:
1332         mutex_unlock(&mb2_transfer.lock);
1333         return r;
1334 }
1335
1336 /**
1337  * prcmu_configure_auto_pm - Configure autonomous power management.
1338  * @sleep: Configuration for ApSleep.
1339  * @idle:  Configuration for ApIdle.
1340  */
1341 void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
1342         struct prcmu_auto_pm_config *idle)
1343 {
1344         u32 sleep_cfg;
1345         u32 idle_cfg;
1346         unsigned long flags;
1347
1348         BUG_ON((sleep == NULL) || (idle == NULL));
1349
1350         sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
1351         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
1352         sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
1353         sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
1354         sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
1355         sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
1356
1357         idle_cfg = (idle->sva_auto_pm_enable & 0xF);
1358         idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
1359         idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
1360         idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
1361         idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
1362         idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
1363
1364         spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
1365
1366         /*
1367          * The autonomous power management configuration is done through
1368          * fields in mailbox 2, but these fields are only used as shared
1369          * variables - i.e. there is no need to send a message.
1370          */
1371         writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
1372         writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
1373
1374         mb2_transfer.auto_pm_enabled =
1375                 ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1376                  (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1377                  (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
1378                  (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
1379
1380         spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
1381 }
1382 EXPORT_SYMBOL(prcmu_configure_auto_pm);
1383
1384 bool prcmu_is_auto_pm_enabled(void)
1385 {
1386         return mb2_transfer.auto_pm_enabled;
1387 }
1388
1389 static int request_sysclk(bool enable)
1390 {
1391         int r;
1392         unsigned long flags;
1393
1394         r = 0;
1395
1396         mutex_lock(&mb3_transfer.sysclk_lock);
1397
1398         spin_lock_irqsave(&mb3_transfer.lock, flags);
1399
1400         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
1401                 cpu_relax();
1402
1403         writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
1404
1405         writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
1406         writel(MBOX_BIT(3), PRCM_MBOX_CPU_SET);
1407
1408         spin_unlock_irqrestore(&mb3_transfer.lock, flags);
1409
1410         /*
1411          * The firmware only sends an ACK if we want to enable the
1412          * SysClk, and it succeeds.
1413          */
1414         if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
1415                         msecs_to_jiffies(20000))) {
1416                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
1417                         __func__);
1418                 r = -EIO;
1419         }
1420
1421         mutex_unlock(&mb3_transfer.sysclk_lock);
1422
1423         return r;
1424 }
1425
1426 static int request_timclk(bool enable)
1427 {
1428         u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
1429
1430         if (!enable)
1431                 val |= PRCM_TCR_STOP_TIMERS;
1432         writel(val, PRCM_TCR);
1433
1434         return 0;
1435 }
1436
1437 static int request_clock(u8 clock, bool enable)
1438 {
1439         u32 val;
1440         unsigned long flags;
1441
1442         spin_lock_irqsave(&clk_mgt_lock, flags);
1443
1444         /* Grab the HW semaphore. */
1445         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1446                 cpu_relax();
1447
1448         val = readl(clk_mgt[clock].reg);
1449         if (enable) {
1450                 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
1451         } else {
1452                 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1453                 val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
1454         }
1455         writel(val, clk_mgt[clock].reg);
1456
1457         /* Release the HW semaphore. */
1458         writel(0, PRCM_SEM);
1459
1460         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1461
1462         return 0;
1463 }
1464
1465 static int request_sga_clock(u8 clock, bool enable)
1466 {
1467         u32 val;
1468         int ret;
1469
1470         if (enable) {
1471                 val = readl(PRCM_CGATING_BYPASS);
1472                 writel(val | PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1473         }
1474
1475         ret = request_clock(clock, enable);
1476
1477         if (!ret && !enable) {
1478                 val = readl(PRCM_CGATING_BYPASS);
1479                 writel(val & ~PRCM_CGATING_BYPASS_ICN2, PRCM_CGATING_BYPASS);
1480         }
1481
1482         return ret;
1483 }
1484
1485 static inline bool plldsi_locked(void)
1486 {
1487         return (readl(PRCM_PLLDSI_LOCKP) &
1488                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1489                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3)) ==
1490                 (PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP10 |
1491                  PRCM_PLLDSI_LOCKP_PRCM_PLLDSI_LOCKP3);
1492 }
1493
1494 static int request_plldsi(bool enable)
1495 {
1496         int r = 0;
1497         u32 val;
1498
1499         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1500                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI), (enable ?
1501                 PRCM_MMIP_LS_CLAMP_CLR : PRCM_MMIP_LS_CLAMP_SET));
1502
1503         val = readl(PRCM_PLLDSI_ENABLE);
1504         if (enable)
1505                 val |= PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1506         else
1507                 val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1508         writel(val, PRCM_PLLDSI_ENABLE);
1509
1510         if (enable) {
1511                 unsigned int i;
1512                 bool locked = plldsi_locked();
1513
1514                 for (i = 10; !locked && (i > 0); --i) {
1515                         udelay(100);
1516                         locked = plldsi_locked();
1517                 }
1518                 if (locked) {
1519                         writel(PRCM_APE_RESETN_DSIPLL_RESETN,
1520                                 PRCM_APE_RESETN_SET);
1521                 } else {
1522                         writel((PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMP |
1523                                 PRCM_MMIP_LS_CLAMP_DSIPLL_CLAMPI),
1524                                 PRCM_MMIP_LS_CLAMP_SET);
1525                         val &= ~PRCM_PLLDSI_ENABLE_PRCM_PLLDSI_ENABLE;
1526                         writel(val, PRCM_PLLDSI_ENABLE);
1527                         r = -EAGAIN;
1528                 }
1529         } else {
1530                 writel(PRCM_APE_RESETN_DSIPLL_RESETN, PRCM_APE_RESETN_CLR);
1531         }
1532         return r;
1533 }
1534
1535 static int request_dsiclk(u8 n, bool enable)
1536 {
1537         u32 val;
1538
1539         val = readl(PRCM_DSI_PLLOUT_SEL);
1540         val &= ~dsiclk[n].divsel_mask;
1541         val |= ((enable ? dsiclk[n].divsel : PRCM_DSI_PLLOUT_SEL_OFF) <<
1542                 dsiclk[n].divsel_shift);
1543         writel(val, PRCM_DSI_PLLOUT_SEL);
1544         return 0;
1545 }
1546
1547 static int request_dsiescclk(u8 n, bool enable)
1548 {
1549         u32 val;
1550
1551         val = readl(PRCM_DSITVCLK_DIV);
1552         enable ? (val |= dsiescclk[n].en) : (val &= ~dsiescclk[n].en);
1553         writel(val, PRCM_DSITVCLK_DIV);
1554         return 0;
1555 }
1556
1557 /**
1558  * db8500_prcmu_request_clock() - Request for a clock to be enabled or disabled.
1559  * @clock:      The clock for which the request is made.
1560  * @enable:     Whether the clock should be enabled (true) or disabled (false).
1561  *
1562  * This function should only be used by the clock implementation.
1563  * Do not use it from any other place!
1564  */
1565 int db8500_prcmu_request_clock(u8 clock, bool enable)
1566 {
1567         if (clock == PRCMU_SGACLK)
1568                 return request_sga_clock(clock, enable);
1569         else if (clock < PRCMU_NUM_REG_CLOCKS)
1570                 return request_clock(clock, enable);
1571         else if (clock == PRCMU_TIMCLK)
1572                 return request_timclk(enable);
1573         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1574                 return request_dsiclk((clock - PRCMU_DSI0CLK), enable);
1575         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1576                 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable);
1577         else if (clock == PRCMU_PLLDSI)
1578                 return request_plldsi(enable);
1579         else if (clock == PRCMU_SYSCLK)
1580                 return request_sysclk(enable);
1581         else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1))
1582                 return request_pll(clock, enable);
1583         else
1584                 return -EINVAL;
1585 }
1586
1587 static unsigned long pll_rate(void __iomem *reg, unsigned long src_rate,
1588         int branch)
1589 {
1590         u64 rate;
1591         u32 val;
1592         u32 d;
1593         u32 div = 1;
1594
1595         val = readl(reg);
1596
1597         rate = src_rate;
1598         rate *= ((val & PRCM_PLL_FREQ_D_MASK) >> PRCM_PLL_FREQ_D_SHIFT);
1599
1600         d = ((val & PRCM_PLL_FREQ_N_MASK) >> PRCM_PLL_FREQ_N_SHIFT);
1601         if (d > 1)
1602                 div *= d;
1603
1604         d = ((val & PRCM_PLL_FREQ_R_MASK) >> PRCM_PLL_FREQ_R_SHIFT);
1605         if (d > 1)
1606                 div *= d;
1607
1608         if (val & PRCM_PLL_FREQ_SELDIV2)
1609                 div *= 2;
1610
1611         if ((branch == PLL_FIX) || ((branch == PLL_DIV) &&
1612                 (val & PRCM_PLL_FREQ_DIV2EN) &&
1613                 ((reg == PRCM_PLLSOC0_FREQ) ||
1614                  (reg == PRCM_PLLARM_FREQ) ||
1615                  (reg == PRCM_PLLDDR_FREQ))))
1616                 div *= 2;
1617
1618         (void)do_div(rate, div);
1619
1620         return (unsigned long)rate;
1621 }
1622
1623 #define ROOT_CLOCK_RATE 38400000
1624
1625 static unsigned long clock_rate(u8 clock)
1626 {
1627         u32 val;
1628         u32 pllsw;
1629         unsigned long rate = ROOT_CLOCK_RATE;
1630
1631         val = readl(clk_mgt[clock].reg);
1632
1633         if (val & PRCM_CLK_MGT_CLK38) {
1634                 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV))
1635                         rate /= 2;
1636                 return rate;
1637         }
1638
1639         val |= clk_mgt[clock].pllsw;
1640         pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
1641
1642         if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1643                 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch);
1644         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1645                 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch);
1646         else if (pllsw == PRCM_CLK_MGT_CLKPLLSW_DDR)
1647                 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch);
1648         else
1649                 return 0;
1650
1651         if ((clock == PRCMU_SGACLK) &&
1652                 (val & PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN)) {
1653                 u64 r = (rate * 10);
1654
1655                 (void)do_div(r, 25);
1656                 return (unsigned long)r;
1657         }
1658         val &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1659         if (val)
1660                 return rate / val;
1661         else
1662                 return 0;
1663 }
1664
1665 static unsigned long armss_rate(void)
1666 {
1667         u32 r;
1668         unsigned long rate;
1669
1670         r = readl(PRCM_ARM_CHGCLKREQ);
1671
1672         if (r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ) {
1673                 /* External ARMCLKFIX clock */
1674
1675                 rate = pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_FIX);
1676
1677                 /* Check PRCM_ARM_CHGCLKREQ divider */
1678                 if (!(r & PRCM_ARM_CHGCLKREQ_PRCM_ARM_DIVSEL))
1679                         rate /= 2;
1680
1681                 /* Check PRCM_ARMCLKFIX_MGT divider */
1682                 r = readl(PRCM_ARMCLKFIX_MGT);
1683                 r &= PRCM_CLK_MGT_CLKPLLDIV_MASK;
1684                 rate /= r;
1685
1686         } else {/* ARM PLL */
1687                 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1688         }
1689
1690         return rate;
1691 }
1692
1693 static unsigned long dsiclk_rate(u8 n)
1694 {
1695         u32 divsel;
1696         u32 div = 1;
1697
1698         divsel = readl(PRCM_DSI_PLLOUT_SEL);
1699         divsel = ((divsel & dsiclk[n].divsel_mask) >> dsiclk[n].divsel_shift);
1700
1701         if (divsel == PRCM_DSI_PLLOUT_SEL_OFF)
1702                 divsel = dsiclk[n].divsel;
1703
1704         switch (divsel) {
1705         case PRCM_DSI_PLLOUT_SEL_PHI_4:
1706                 div *= 2;
1707         case PRCM_DSI_PLLOUT_SEL_PHI_2:
1708                 div *= 2;
1709         case PRCM_DSI_PLLOUT_SEL_PHI:
1710                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1711                         PLL_RAW) / div;
1712         default:
1713                 return 0;
1714         }
1715 }
1716
1717 static unsigned long dsiescclk_rate(u8 n)
1718 {
1719         u32 div;
1720
1721         div = readl(PRCM_DSITVCLK_DIV);
1722         div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift));
1723         return clock_rate(PRCMU_TVCLK) / max((u32)1, div);
1724 }
1725
1726 unsigned long prcmu_clock_rate(u8 clock)
1727 {
1728         if (clock < PRCMU_NUM_REG_CLOCKS)
1729                 return clock_rate(clock);
1730         else if (clock == PRCMU_TIMCLK)
1731                 return ROOT_CLOCK_RATE / 16;
1732         else if (clock == PRCMU_SYSCLK)
1733                 return ROOT_CLOCK_RATE;
1734         else if (clock == PRCMU_PLLSOC0)
1735                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1736         else if (clock == PRCMU_PLLSOC1)
1737                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1738         else if (clock == PRCMU_ARMSS)
1739                 return armss_rate();
1740         else if (clock == PRCMU_PLLDDR)
1741                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, PLL_RAW);
1742         else if (clock == PRCMU_PLLDSI)
1743                 return pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1744                         PLL_RAW);
1745         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1746                 return dsiclk_rate(clock - PRCMU_DSI0CLK);
1747         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1748                 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK);
1749         else
1750                 return 0;
1751 }
1752
1753 static unsigned long clock_source_rate(u32 clk_mgt_val, int branch)
1754 {
1755         if (clk_mgt_val & PRCM_CLK_MGT_CLK38)
1756                 return ROOT_CLOCK_RATE;
1757         clk_mgt_val &= PRCM_CLK_MGT_CLKPLLSW_MASK;
1758         if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC0)
1759                 return pll_rate(PRCM_PLLSOC0_FREQ, ROOT_CLOCK_RATE, branch);
1760         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_SOC1)
1761                 return pll_rate(PRCM_PLLSOC1_FREQ, ROOT_CLOCK_RATE, branch);
1762         else if (clk_mgt_val == PRCM_CLK_MGT_CLKPLLSW_DDR)
1763                 return pll_rate(PRCM_PLLDDR_FREQ, ROOT_CLOCK_RATE, branch);
1764         else
1765                 return 0;
1766 }
1767
1768 static u32 clock_divider(unsigned long src_rate, unsigned long rate)
1769 {
1770         u32 div;
1771
1772         div = (src_rate / rate);
1773         if (div == 0)
1774                 return 1;
1775         if (rate < (src_rate / div))
1776                 div++;
1777         return div;
1778 }
1779
1780 static long round_clock_rate(u8 clock, unsigned long rate)
1781 {
1782         u32 val;
1783         u32 div;
1784         unsigned long src_rate;
1785         long rounded_rate;
1786
1787         val = readl(clk_mgt[clock].reg);
1788         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1789                 clk_mgt[clock].branch);
1790         div = clock_divider(src_rate, rate);
1791         if (val & PRCM_CLK_MGT_CLK38) {
1792                 if (clk_mgt[clock].clk38div) {
1793                         if (div > 2)
1794                                 div = 2;
1795                 } else {
1796                         div = 1;
1797                 }
1798         } else if ((clock == PRCMU_SGACLK) && (div == 3)) {
1799                 u64 r = (src_rate * 10);
1800
1801                 (void)do_div(r, 25);
1802                 if (r <= rate)
1803                         return (unsigned long)r;
1804         }
1805         rounded_rate = (src_rate / min(div, (u32)31));
1806
1807         return rounded_rate;
1808 }
1809
1810 /* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1811 static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1812         { .frequency = 200000, .index = ARM_EXTCLK,},
1813         { .frequency = 400000, .index = ARM_50_OPP,},
1814         { .frequency = 800000, .index = ARM_100_OPP,},
1815         { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1816         { .frequency = CPUFREQ_TABLE_END,},
1817 };
1818
1819 static long round_armss_rate(unsigned long rate)
1820 {
1821         long freq = 0;
1822         int i = 0;
1823
1824         /* cpufreq table frequencies is in KHz. */
1825         rate = rate / 1000;
1826
1827         /* Find the corresponding arm opp from the cpufreq table. */
1828         while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1829                 freq = db8500_cpufreq_table[i].frequency;
1830                 if (freq == rate)
1831                         break;
1832                 i++;
1833         }
1834
1835         /* Return the last valid value, even if a match was not found. */
1836         return freq * 1000;
1837 }
1838
1839 #define MIN_PLL_VCO_RATE 600000000ULL
1840 #define MAX_PLL_VCO_RATE 1680640000ULL
1841
1842 static long round_plldsi_rate(unsigned long rate)
1843 {
1844         long rounded_rate = 0;
1845         unsigned long src_rate;
1846         unsigned long rem;
1847         u32 r;
1848
1849         src_rate = clock_rate(PRCMU_HDMICLK);
1850         rem = rate;
1851
1852         for (r = 7; (rem > 0) && (r > 0); r--) {
1853                 u64 d;
1854
1855                 d = (r * rate);
1856                 (void)do_div(d, src_rate);
1857                 if (d < 6)
1858                         d = 6;
1859                 else if (d > 255)
1860                         d = 255;
1861                 d *= src_rate;
1862                 if (((2 * d) < (r * MIN_PLL_VCO_RATE)) ||
1863                         ((r * MAX_PLL_VCO_RATE) < (2 * d)))
1864                         continue;
1865                 (void)do_div(d, r);
1866                 if (rate < d) {
1867                         if (rounded_rate == 0)
1868                                 rounded_rate = (long)d;
1869                         break;
1870                 }
1871                 if ((rate - d) < rem) {
1872                         rem = (rate - d);
1873                         rounded_rate = (long)d;
1874                 }
1875         }
1876         return rounded_rate;
1877 }
1878
1879 static long round_dsiclk_rate(unsigned long rate)
1880 {
1881         u32 div;
1882         unsigned long src_rate;
1883         long rounded_rate;
1884
1885         src_rate = pll_rate(PRCM_PLLDSI_FREQ, clock_rate(PRCMU_HDMICLK),
1886                 PLL_RAW);
1887         div = clock_divider(src_rate, rate);
1888         rounded_rate = (src_rate / ((div > 2) ? 4 : div));
1889
1890         return rounded_rate;
1891 }
1892
1893 static long round_dsiescclk_rate(unsigned long rate)
1894 {
1895         u32 div;
1896         unsigned long src_rate;
1897         long rounded_rate;
1898
1899         src_rate = clock_rate(PRCMU_TVCLK);
1900         div = clock_divider(src_rate, rate);
1901         rounded_rate = (src_rate / min(div, (u32)255));
1902
1903         return rounded_rate;
1904 }
1905
1906 long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1907 {
1908         if (clock < PRCMU_NUM_REG_CLOCKS)
1909                 return round_clock_rate(clock, rate);
1910         else if (clock == PRCMU_ARMSS)
1911                 return round_armss_rate(rate);
1912         else if (clock == PRCMU_PLLDSI)
1913                 return round_plldsi_rate(rate);
1914         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
1915                 return round_dsiclk_rate(rate);
1916         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
1917                 return round_dsiescclk_rate(rate);
1918         else
1919                 return (long)prcmu_clock_rate(clock);
1920 }
1921
1922 static void set_clock_rate(u8 clock, unsigned long rate)
1923 {
1924         u32 val;
1925         u32 div;
1926         unsigned long src_rate;
1927         unsigned long flags;
1928
1929         spin_lock_irqsave(&clk_mgt_lock, flags);
1930
1931         /* Grab the HW semaphore. */
1932         while ((readl(PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
1933                 cpu_relax();
1934
1935         val = readl(clk_mgt[clock].reg);
1936         src_rate = clock_source_rate((val | clk_mgt[clock].pllsw),
1937                 clk_mgt[clock].branch);
1938         div = clock_divider(src_rate, rate);
1939         if (val & PRCM_CLK_MGT_CLK38) {
1940                 if (clk_mgt[clock].clk38div) {
1941                         if (div > 1)
1942                                 val |= PRCM_CLK_MGT_CLK38DIV;
1943                         else
1944                                 val &= ~PRCM_CLK_MGT_CLK38DIV;
1945                 }
1946         } else if (clock == PRCMU_SGACLK) {
1947                 val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK |
1948                         PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN);
1949                 if (div == 3) {
1950                         u64 r = (src_rate * 10);
1951
1952                         (void)do_div(r, 25);
1953                         if (r <= rate) {
1954                                 val |= PRCM_SGACLK_MGT_SGACLKDIV_BY_2_5_EN;
1955                                 div = 0;
1956                         }
1957                 }
1958                 val |= min(div, (u32)31);
1959         } else {
1960                 val &= ~PRCM_CLK_MGT_CLKPLLDIV_MASK;
1961                 val |= min(div, (u32)31);
1962         }
1963         writel(val, clk_mgt[clock].reg);
1964
1965         /* Release the HW semaphore. */
1966         writel(0, PRCM_SEM);
1967
1968         spin_unlock_irqrestore(&clk_mgt_lock, flags);
1969 }
1970
1971 static int set_armss_rate(unsigned long rate)
1972 {
1973         int i = 0;
1974
1975         /* cpufreq table frequencies is in KHz. */
1976         rate = rate / 1000;
1977
1978         /* Find the corresponding arm opp from the cpufreq table. */
1979         while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1980                 if (db8500_cpufreq_table[i].frequency == rate)
1981                         break;
1982                 i++;
1983         }
1984
1985         if (db8500_cpufreq_table[i].frequency != rate)
1986                 return -EINVAL;
1987
1988         /* Set the new arm opp. */
1989         return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index);
1990 }
1991
1992 static int set_plldsi_rate(unsigned long rate)
1993 {
1994         unsigned long src_rate;
1995         unsigned long rem;
1996         u32 pll_freq = 0;
1997         u32 r;
1998
1999         src_rate = clock_rate(PRCMU_HDMICLK);
2000         rem = rate;
2001
2002         for (r = 7; (rem > 0) && (r > 0); r--) {
2003                 u64 d;
2004                 u64 hwrate;
2005
2006                 d = (r * rate);
2007                 (void)do_div(d, src_rate);
2008                 if (d < 6)
2009                         d = 6;
2010                 else if (d > 255)
2011                         d = 255;
2012                 hwrate = (d * src_rate);
2013                 if (((2 * hwrate) < (r * MIN_PLL_VCO_RATE)) ||
2014                         ((r * MAX_PLL_VCO_RATE) < (2 * hwrate)))
2015                         continue;
2016                 (void)do_div(hwrate, r);
2017                 if (rate < hwrate) {
2018                         if (pll_freq == 0)
2019                                 pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2020                                         (r << PRCM_PLL_FREQ_R_SHIFT));
2021                         break;
2022                 }
2023                 if ((rate - hwrate) < rem) {
2024                         rem = (rate - hwrate);
2025                         pll_freq = (((u32)d << PRCM_PLL_FREQ_D_SHIFT) |
2026                                 (r << PRCM_PLL_FREQ_R_SHIFT));
2027                 }
2028         }
2029         if (pll_freq == 0)
2030                 return -EINVAL;
2031
2032         pll_freq |= (1 << PRCM_PLL_FREQ_N_SHIFT);
2033         writel(pll_freq, PRCM_PLLDSI_FREQ);
2034
2035         return 0;
2036 }
2037
2038 static void set_dsiclk_rate(u8 n, unsigned long rate)
2039 {
2040         u32 val;
2041         u32 div;
2042
2043         div = clock_divider(pll_rate(PRCM_PLLDSI_FREQ,
2044                         clock_rate(PRCMU_HDMICLK), PLL_RAW), rate);
2045
2046         dsiclk[n].divsel = (div == 1) ? PRCM_DSI_PLLOUT_SEL_PHI :
2047                            (div == 2) ? PRCM_DSI_PLLOUT_SEL_PHI_2 :
2048                            /* else */   PRCM_DSI_PLLOUT_SEL_PHI_4;
2049
2050         val = readl(PRCM_DSI_PLLOUT_SEL);
2051         val &= ~dsiclk[n].divsel_mask;
2052         val |= (dsiclk[n].divsel << dsiclk[n].divsel_shift);
2053         writel(val, PRCM_DSI_PLLOUT_SEL);
2054 }
2055
2056 static void set_dsiescclk_rate(u8 n, unsigned long rate)
2057 {
2058         u32 val;
2059         u32 div;
2060
2061         div = clock_divider(clock_rate(PRCMU_TVCLK), rate);
2062         val = readl(PRCM_DSITVCLK_DIV);
2063         val &= ~dsiescclk[n].div_mask;
2064         val |= (min(div, (u32)255) << dsiescclk[n].div_shift);
2065         writel(val, PRCM_DSITVCLK_DIV);
2066 }
2067
2068 int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2069 {
2070         if (clock < PRCMU_NUM_REG_CLOCKS)
2071                 set_clock_rate(clock, rate);
2072         else if (clock == PRCMU_ARMSS)
2073                 return set_armss_rate(rate);
2074         else if (clock == PRCMU_PLLDSI)
2075                 return set_plldsi_rate(rate);
2076         else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
2077                 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate);
2078         else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK))
2079                 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate);
2080         return 0;
2081 }
2082
2083 int db8500_prcmu_config_esram0_deep_sleep(u8 state)
2084 {
2085         if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
2086             (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
2087                 return -EINVAL;
2088
2089         mutex_lock(&mb4_transfer.lock);
2090
2091         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2092                 cpu_relax();
2093
2094         writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2095         writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
2096                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
2097         writeb(DDR_PWR_STATE_ON,
2098                (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
2099         writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
2100
2101         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2102         wait_for_completion(&mb4_transfer.work);
2103
2104         mutex_unlock(&mb4_transfer.lock);
2105
2106         return 0;
2107 }
2108
2109 int db8500_prcmu_config_hotdog(u8 threshold)
2110 {
2111         mutex_lock(&mb4_transfer.lock);
2112
2113         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2114                 cpu_relax();
2115
2116         writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
2117         writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2118
2119         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2120         wait_for_completion(&mb4_transfer.work);
2121
2122         mutex_unlock(&mb4_transfer.lock);
2123
2124         return 0;
2125 }
2126
2127 int db8500_prcmu_config_hotmon(u8 low, u8 high)
2128 {
2129         mutex_lock(&mb4_transfer.lock);
2130
2131         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2132                 cpu_relax();
2133
2134         writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
2135         writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
2136         writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
2137                 (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
2138         writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2139
2140         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2141         wait_for_completion(&mb4_transfer.work);
2142
2143         mutex_unlock(&mb4_transfer.lock);
2144
2145         return 0;
2146 }
2147
2148 static int config_hot_period(u16 val)
2149 {
2150         mutex_lock(&mb4_transfer.lock);
2151
2152         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2153                 cpu_relax();
2154
2155         writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
2156         writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2157
2158         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2159         wait_for_completion(&mb4_transfer.work);
2160
2161         mutex_unlock(&mb4_transfer.lock);
2162
2163         return 0;
2164 }
2165
2166 int db8500_prcmu_start_temp_sense(u16 cycles32k)
2167 {
2168         if (cycles32k == 0xFFFF)
2169                 return -EINVAL;
2170
2171         return config_hot_period(cycles32k);
2172 }
2173
2174 int db8500_prcmu_stop_temp_sense(void)
2175 {
2176         return config_hot_period(0xFFFF);
2177 }
2178
2179 static int prcmu_a9wdog(u8 cmd, u8 d0, u8 d1, u8 d2, u8 d3)
2180 {
2181
2182         mutex_lock(&mb4_transfer.lock);
2183
2184         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
2185                 cpu_relax();
2186
2187         writeb(d0, (tcdm_base + PRCM_REQ_MB4_A9WDOG_0));
2188         writeb(d1, (tcdm_base + PRCM_REQ_MB4_A9WDOG_1));
2189         writeb(d2, (tcdm_base + PRCM_REQ_MB4_A9WDOG_2));
2190         writeb(d3, (tcdm_base + PRCM_REQ_MB4_A9WDOG_3));
2191
2192         writeb(cmd, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
2193
2194         writel(MBOX_BIT(4), PRCM_MBOX_CPU_SET);
2195         wait_for_completion(&mb4_transfer.work);
2196
2197         mutex_unlock(&mb4_transfer.lock);
2198
2199         return 0;
2200
2201 }
2202
2203 int db8500_prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
2204 {
2205         BUG_ON(num == 0 || num > 0xf);
2206         return prcmu_a9wdog(MB4H_A9WDOG_CONF, num, 0, 0,
2207                             sleep_auto_off ? A9WDOG_AUTO_OFF_EN :
2208                             A9WDOG_AUTO_OFF_DIS);
2209 }
2210
2211 int db8500_prcmu_enable_a9wdog(u8 id)
2212 {
2213         return prcmu_a9wdog(MB4H_A9WDOG_EN, id, 0, 0, 0);
2214 }
2215
2216 int db8500_prcmu_disable_a9wdog(u8 id)
2217 {
2218         return prcmu_a9wdog(MB4H_A9WDOG_DIS, id, 0, 0, 0);
2219 }
2220
2221 int db8500_prcmu_kick_a9wdog(u8 id)
2222 {
2223         return prcmu_a9wdog(MB4H_A9WDOG_KICK, id, 0, 0, 0);
2224 }
2225
2226 /*
2227  * timeout is 28 bit, in ms.
2228  */
2229 int db8500_prcmu_load_a9wdog(u8 id, u32 timeout)
2230 {
2231         return prcmu_a9wdog(MB4H_A9WDOG_LOAD,
2232                             (id & A9WDOG_ID_MASK) |
2233                             /*
2234                              * Put the lowest 28 bits of timeout at
2235                              * offset 4. Four first bits are used for id.
2236                              */
2237                             (u8)((timeout << 4) & 0xf0),
2238                             (u8)((timeout >> 4) & 0xff),
2239                             (u8)((timeout >> 12) & 0xff),
2240                             (u8)((timeout >> 20) & 0xff));
2241 }
2242
2243 /**
2244  * prcmu_abb_read() - Read register value(s) from the ABB.
2245  * @slave:      The I2C slave address.
2246  * @reg:        The (start) register address.
2247  * @value:      The read out value(s).
2248  * @size:       The number of registers to read.
2249  *
2250  * Reads register value(s) from the ABB.
2251  * @size has to be 1 for the current firmware version.
2252  */
2253 int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
2254 {
2255         int r;
2256
2257         if (size != 1)
2258                 return -EINVAL;
2259
2260         mutex_lock(&mb5_transfer.lock);
2261
2262         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2263                 cpu_relax();
2264
2265         writeb(0, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2266         writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2267         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2268         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2269         writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2270
2271         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2272
2273         if (!wait_for_completion_timeout(&mb5_transfer.work,
2274                                 msecs_to_jiffies(20000))) {
2275                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2276                         __func__);
2277                 r = -EIO;
2278         } else {
2279                 r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
2280         }
2281
2282         if (!r)
2283                 *value = mb5_transfer.ack.value;
2284
2285         mutex_unlock(&mb5_transfer.lock);
2286
2287         return r;
2288 }
2289
2290 /**
2291  * prcmu_abb_write_masked() - Write masked register value(s) to the ABB.
2292  * @slave:      The I2C slave address.
2293  * @reg:        The (start) register address.
2294  * @value:      The value(s) to write.
2295  * @mask:       The mask(s) to use.
2296  * @size:       The number of registers to write.
2297  *
2298  * Writes masked register value(s) to the ABB.
2299  * For each @value, only the bits set to 1 in the corresponding @mask
2300  * will be written. The other bits are not changed.
2301  * @size has to be 1 for the current firmware version.
2302  */
2303 int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size)
2304 {
2305         int r;
2306
2307         if (size != 1)
2308                 return -EINVAL;
2309
2310         mutex_lock(&mb5_transfer.lock);
2311
2312         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
2313                 cpu_relax();
2314
2315         writeb(~*mask, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB5));
2316         writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
2317         writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
2318         writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
2319         writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
2320
2321         writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
2322
2323         if (!wait_for_completion_timeout(&mb5_transfer.work,
2324                                 msecs_to_jiffies(20000))) {
2325                 pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
2326                         __func__);
2327                 r = -EIO;
2328         } else {
2329                 r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
2330         }
2331
2332         mutex_unlock(&mb5_transfer.lock);
2333
2334         return r;
2335 }
2336
2337 /**
2338  * prcmu_abb_write() - Write register value(s) to the ABB.
2339  * @slave:      The I2C slave address.
2340  * @reg:        The (start) register address.
2341  * @value:      The value(s) to write.
2342  * @size:       The number of registers to write.
2343  *
2344  * Writes register value(s) to the ABB.
2345  * @size has to be 1 for the current firmware version.
2346  */
2347 int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
2348 {
2349         u8 mask = ~0;
2350
2351         return prcmu_abb_write_masked(slave, reg, value, &mask, size);
2352 }
2353
2354 /**
2355  * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
2356  */
2357 int prcmu_ac_wake_req(void)
2358 {
2359         u32 val;
2360         int ret = 0;
2361
2362         mutex_lock(&mb0_transfer.ac_wake_lock);
2363
2364         val = readl(PRCM_HOSTACCESS_REQ);
2365         if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
2366                 goto unlock_and_return;
2367
2368         atomic_set(&ac_wake_req_state, 1);
2369
2370         /*
2371          * Force Modem Wake-up before hostaccess_req ping-pong.
2372          * It prevents Modem to enter in Sleep while acking the hostaccess
2373          * request. The 31us delay has been calculated by HWI.
2374          */
2375         val |= PRCM_HOSTACCESS_REQ_WAKE_REQ;
2376         writel(val, PRCM_HOSTACCESS_REQ);
2377
2378         udelay(31);
2379
2380         val |= PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ;
2381         writel(val, PRCM_HOSTACCESS_REQ);
2382
2383         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2384                         msecs_to_jiffies(5000))) {
2385 #if defined(CONFIG_DBX500_PRCMU_DEBUG)
2386                 db8500_prcmu_debug_dump(__func__, true, true);
2387 #endif
2388                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2389                         __func__);
2390                 ret = -EFAULT;
2391         }
2392
2393 unlock_and_return:
2394         mutex_unlock(&mb0_transfer.ac_wake_lock);
2395         return ret;
2396 }
2397
2398 /**
2399  * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
2400  */
2401 void prcmu_ac_sleep_req()
2402 {
2403         u32 val;
2404
2405         mutex_lock(&mb0_transfer.ac_wake_lock);
2406
2407         val = readl(PRCM_HOSTACCESS_REQ);
2408         if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
2409                 goto unlock_and_return;
2410
2411         writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
2412                 PRCM_HOSTACCESS_REQ);
2413
2414         if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
2415                         msecs_to_jiffies(5000))) {
2416                 pr_crit("prcmu: %s timed out (5 s) waiting for a reply.\n",
2417                         __func__);
2418         }
2419
2420         atomic_set(&ac_wake_req_state, 0);
2421
2422 unlock_and_return:
2423         mutex_unlock(&mb0_transfer.ac_wake_lock);
2424 }
2425
2426 bool db8500_prcmu_is_ac_wake_requested(void)
2427 {
2428         return (atomic_read(&ac_wake_req_state) != 0);
2429 }
2430
2431 /**
2432  * db8500_prcmu_system_reset - System reset
2433  *
2434  * Saves the reset reason code and then sets the APE_SOFTRST register which
2435  * fires interrupt to fw
2436  */
2437 void db8500_prcmu_system_reset(u16 reset_code)
2438 {
2439         writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
2440         writel(1, PRCM_APE_SOFTRST);
2441 }
2442
2443 /**
2444  * db8500_prcmu_get_reset_code - Retrieve SW reset reason code
2445  *
2446  * Retrieves the reset reason code stored by prcmu_system_reset() before
2447  * last restart.
2448  */
2449 u16 db8500_prcmu_get_reset_code(void)
2450 {
2451         return readw(tcdm_base + PRCM_SW_RST_REASON);
2452 }
2453
2454 /**
2455  * db8500_prcmu_reset_modem - ask the PRCMU to reset modem
2456  */
2457 void db8500_prcmu_modem_reset(void)
2458 {
2459         mutex_lock(&mb1_transfer.lock);
2460
2461         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
2462                 cpu_relax();
2463
2464         writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
2465         writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
2466         wait_for_completion(&mb1_transfer.work);
2467
2468         /*
2469          * No need to check return from PRCMU as modem should go in reset state
2470          * This state is already managed by upper layer
2471          */
2472
2473         mutex_unlock(&mb1_transfer.lock);
2474 }
2475
2476 static void ack_dbb_wakeup(void)
2477 {
2478         unsigned long flags;
2479
2480         spin_lock_irqsave(&mb0_transfer.lock, flags);
2481
2482         while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
2483                 cpu_relax();
2484
2485         writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
2486         writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
2487
2488         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2489 }
2490
2491 static inline void print_unknown_header_warning(u8 n, u8 header)
2492 {
2493         pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
2494                 header, n);
2495 }
2496
2497 static bool read_mailbox_0(void)
2498 {
2499         bool r;
2500         u32 ev;
2501         unsigned int n;
2502         u8 header;
2503
2504         header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
2505         switch (header) {
2506         case MB0H_WAKEUP_EXE:
2507         case MB0H_WAKEUP_SLEEP:
2508                 if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
2509                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
2510                 else
2511                         ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
2512
2513                 if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
2514                         complete(&mb0_transfer.ac_wake_work);
2515                 if (ev & WAKEUP_BIT_SYSCLK_OK)
2516                         complete(&mb3_transfer.sysclk_work);
2517
2518                 ev &= mb0_transfer.req.dbb_irqs;
2519
2520                 for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
2521                         if (ev & prcmu_irq_bit[n])
2522                                 generic_handle_irq(irq_find_mapping(db8500_irq_domain, n));
2523                 }
2524                 r = true;
2525                 break;
2526         default:
2527                 print_unknown_header_warning(0, header);
2528                 r = false;
2529                 break;
2530         }
2531         writel(MBOX_BIT(0), PRCM_ARM_IT1_CLR);
2532         return r;
2533 }
2534
2535 static bool read_mailbox_1(void)
2536 {
2537         mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
2538         mb1_transfer.ack.arm_opp = readb(tcdm_base +
2539                 PRCM_ACK_MB1_CURRENT_ARM_OPP);
2540         mb1_transfer.ack.ape_opp = readb(tcdm_base +
2541                 PRCM_ACK_MB1_CURRENT_APE_OPP);
2542         mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
2543                 PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
2544         writel(MBOX_BIT(1), PRCM_ARM_IT1_CLR);
2545         complete(&mb1_transfer.work);
2546         return false;
2547 }
2548
2549 static bool read_mailbox_2(void)
2550 {
2551         mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
2552         writel(MBOX_BIT(2), PRCM_ARM_IT1_CLR);
2553         complete(&mb2_transfer.work);
2554         return false;
2555 }
2556
2557 static bool read_mailbox_3(void)
2558 {
2559         writel(MBOX_BIT(3), PRCM_ARM_IT1_CLR);
2560         return false;
2561 }
2562
2563 static bool read_mailbox_4(void)
2564 {
2565         u8 header;
2566         bool do_complete = true;
2567
2568         header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
2569         switch (header) {
2570         case MB4H_MEM_ST:
2571         case MB4H_HOTDOG:
2572         case MB4H_HOTMON:
2573         case MB4H_HOT_PERIOD:
2574         case MB4H_A9WDOG_CONF:
2575         case MB4H_A9WDOG_EN:
2576         case MB4H_A9WDOG_DIS:
2577         case MB4H_A9WDOG_LOAD:
2578         case MB4H_A9WDOG_KICK:
2579                 break;
2580         default:
2581                 print_unknown_header_warning(4, header);
2582                 do_complete = false;
2583                 break;
2584         }
2585
2586         writel(MBOX_BIT(4), PRCM_ARM_IT1_CLR);
2587
2588         if (do_complete)
2589                 complete(&mb4_transfer.work);
2590
2591         return false;
2592 }
2593
2594 static bool read_mailbox_5(void)
2595 {
2596         mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
2597         mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
2598         writel(MBOX_BIT(5), PRCM_ARM_IT1_CLR);
2599         complete(&mb5_transfer.work);
2600         return false;
2601 }
2602
2603 static bool read_mailbox_6(void)
2604 {
2605         writel(MBOX_BIT(6), PRCM_ARM_IT1_CLR);
2606         return false;
2607 }
2608
2609 static bool read_mailbox_7(void)
2610 {
2611         writel(MBOX_BIT(7), PRCM_ARM_IT1_CLR);
2612         return false;
2613 }
2614
2615 static bool (* const read_mailbox[NUM_MB])(void) = {
2616         read_mailbox_0,
2617         read_mailbox_1,
2618         read_mailbox_2,
2619         read_mailbox_3,
2620         read_mailbox_4,
2621         read_mailbox_5,
2622         read_mailbox_6,
2623         read_mailbox_7
2624 };
2625
2626 static irqreturn_t prcmu_irq_handler(int irq, void *data)
2627 {
2628         u32 bits;
2629         u8 n;
2630         irqreturn_t r;
2631
2632         bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
2633         if (unlikely(!bits))
2634                 return IRQ_NONE;
2635
2636         r = IRQ_HANDLED;
2637         for (n = 0; bits; n++) {
2638                 if (bits & MBOX_BIT(n)) {
2639                         bits -= MBOX_BIT(n);
2640                         if (read_mailbox[n]())
2641                                 r = IRQ_WAKE_THREAD;
2642                 }
2643         }
2644         return r;
2645 }
2646
2647 static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
2648 {
2649         ack_dbb_wakeup();
2650         return IRQ_HANDLED;
2651 }
2652
2653 static void prcmu_mask_work(struct work_struct *work)
2654 {
2655         unsigned long flags;
2656
2657         spin_lock_irqsave(&mb0_transfer.lock, flags);
2658
2659         config_wakeups();
2660
2661         spin_unlock_irqrestore(&mb0_transfer.lock, flags);
2662 }
2663
2664 static void prcmu_irq_mask(struct irq_data *d)
2665 {
2666         unsigned long flags;
2667
2668         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2669
2670         mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->hwirq];
2671
2672         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2673
2674         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2675                 schedule_work(&mb0_transfer.mask_work);
2676 }
2677
2678 static void prcmu_irq_unmask(struct irq_data *d)
2679 {
2680         unsigned long flags;
2681
2682         spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
2683
2684         mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->hwirq];
2685
2686         spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
2687
2688         if (d->irq != IRQ_PRCMU_CA_SLEEP)
2689                 schedule_work(&mb0_transfer.mask_work);
2690 }
2691
2692 static void noop(struct irq_data *d)
2693 {
2694 }
2695
2696 static struct irq_chip prcmu_irq_chip = {
2697         .name           = "prcmu",
2698         .irq_disable    = prcmu_irq_mask,
2699         .irq_ack        = noop,
2700         .irq_mask       = prcmu_irq_mask,
2701         .irq_unmask     = prcmu_irq_unmask,
2702 };
2703
2704 static __init char *fw_project_name(u32 project)
2705 {
2706         switch (project) {
2707         case PRCMU_FW_PROJECT_U8500:
2708                 return "U8500";
2709         case PRCMU_FW_PROJECT_U8400:
2710                 return "U8400";
2711         case PRCMU_FW_PROJECT_U9500:
2712                 return "U9500";
2713         case PRCMU_FW_PROJECT_U8500_MBB:
2714                 return "U8500 MBB";
2715         case PRCMU_FW_PROJECT_U8500_C1:
2716                 return "U8500 C1";
2717         case PRCMU_FW_PROJECT_U8500_C2:
2718                 return "U8500 C2";
2719         case PRCMU_FW_PROJECT_U8500_C3:
2720                 return "U8500 C3";
2721         case PRCMU_FW_PROJECT_U8500_C4:
2722                 return "U8500 C4";
2723         case PRCMU_FW_PROJECT_U9500_MBL:
2724                 return "U9500 MBL";
2725         case PRCMU_FW_PROJECT_U8500_MBL:
2726                 return "U8500 MBL";
2727         case PRCMU_FW_PROJECT_U8500_MBL2:
2728                 return "U8500 MBL2";
2729         case PRCMU_FW_PROJECT_U8520:
2730                 return "U8520 MBL";
2731         case PRCMU_FW_PROJECT_U8420:
2732                 return "U8420";
2733         case PRCMU_FW_PROJECT_U9540:
2734                 return "U9540";
2735         case PRCMU_FW_PROJECT_A9420:
2736                 return "A9420";
2737         case PRCMU_FW_PROJECT_L8540:
2738                 return "L8540";
2739         case PRCMU_FW_PROJECT_L8580:
2740                 return "L8580";
2741         default:
2742                 return "Unknown";
2743         }
2744 }
2745
2746 static int db8500_irq_map(struct irq_domain *d, unsigned int virq,
2747                                 irq_hw_number_t hwirq)
2748 {
2749         irq_set_chip_and_handler(virq, &prcmu_irq_chip,
2750                                 handle_simple_irq);
2751         set_irq_flags(virq, IRQF_VALID);
2752
2753         return 0;
2754 }
2755
2756 static struct irq_domain_ops db8500_irq_ops = {
2757         .map    = db8500_irq_map,
2758         .xlate  = irq_domain_xlate_twocell,
2759 };
2760
2761 static int db8500_irq_init(struct device_node *np)
2762 {
2763         int irq_base = 0;
2764         int i;
2765
2766         /* In the device tree case, just take some IRQs */
2767         if (!np)
2768                 irq_base = IRQ_PRCMU_BASE;
2769
2770         db8500_irq_domain = irq_domain_add_simple(
2771                 np, NUM_PRCMU_WAKEUPS, irq_base,
2772                 &db8500_irq_ops, NULL);
2773
2774         if (!db8500_irq_domain) {
2775                 pr_err("Failed to create irqdomain\n");
2776                 return -ENOSYS;
2777         }
2778
2779         /* All wakeups will be used, so create mappings for all */
2780         for (i = 0; i < NUM_PRCMU_WAKEUPS; i++)
2781                 irq_create_mapping(db8500_irq_domain, i);
2782
2783         return 0;
2784 }
2785
2786 static void dbx500_fw_version_init(struct platform_device *pdev,
2787                             u32 version_offset)
2788 {
2789         struct resource *res;
2790         void __iomem *tcpm_base;
2791
2792         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
2793                                            "prcmu-tcpm");
2794         if (!res) {
2795                 dev_err(&pdev->dev,
2796                         "Error: no prcmu tcpm memory region provided\n");
2797                 return;
2798         }
2799         tcpm_base = ioremap(res->start, resource_size(res));
2800         if (tcpm_base != NULL) {
2801                 u32 version;
2802
2803                 version = readl(tcpm_base + version_offset);
2804                 fw_info.version.project = (version & 0xFF);
2805                 fw_info.version.api_version = (version >> 8) & 0xFF;
2806                 fw_info.version.func_version = (version >> 16) & 0xFF;
2807                 fw_info.version.errata = (version >> 24) & 0xFF;
2808                 strncpy(fw_info.version.project_name,
2809                         fw_project_name(fw_info.version.project),
2810                         PRCMU_FW_PROJECT_NAME_LEN);
2811                 fw_info.valid = true;
2812                 pr_info("PRCMU firmware: %s(%d), version %d.%d.%d\n",
2813                         fw_info.version.project_name,
2814                         fw_info.version.project,
2815                         fw_info.version.api_version,
2816                         fw_info.version.func_version,
2817                         fw_info.version.errata);
2818                 iounmap(tcpm_base);
2819         }
2820 }
2821
2822 void __init db8500_prcmu_early_init(void)
2823 {
2824         spin_lock_init(&mb0_transfer.lock);
2825         spin_lock_init(&mb0_transfer.dbb_irqs_lock);
2826         mutex_init(&mb0_transfer.ac_wake_lock);
2827         init_completion(&mb0_transfer.ac_wake_work);
2828         mutex_init(&mb1_transfer.lock);
2829         init_completion(&mb1_transfer.work);
2830         mb1_transfer.ape_opp = APE_NO_CHANGE;
2831         mutex_init(&mb2_transfer.lock);
2832         init_completion(&mb2_transfer.work);
2833         spin_lock_init(&mb2_transfer.auto_pm_lock);
2834         spin_lock_init(&mb3_transfer.lock);
2835         mutex_init(&mb3_transfer.sysclk_lock);
2836         init_completion(&mb3_transfer.sysclk_work);
2837         mutex_init(&mb4_transfer.lock);
2838         init_completion(&mb4_transfer.work);
2839         mutex_init(&mb5_transfer.lock);
2840         init_completion(&mb5_transfer.work);
2841
2842         INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2843 }
2844
2845 static void __init init_prcm_registers(void)
2846 {
2847         u32 val;
2848
2849         val = readl(PRCM_A9PL_FORCE_CLKEN);
2850         val &= ~(PRCM_A9PL_FORCE_CLKEN_PRCM_A9PL_FORCE_CLKEN |
2851                 PRCM_A9PL_FORCE_CLKEN_PRCM_A9AXI_FORCE_CLKEN);
2852         writel(val, (PRCM_A9PL_FORCE_CLKEN));
2853 }
2854
2855 /*
2856  * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
2857  */
2858 static struct regulator_consumer_supply db8500_vape_consumers[] = {
2859         REGULATOR_SUPPLY("v-ape", NULL),
2860         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
2861         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
2862         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
2863         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
2864         REGULATOR_SUPPLY("v-i2c", "nmk-i2c.4"),
2865         /* "v-mmc" changed to "vcore" in the mainline kernel */
2866         REGULATOR_SUPPLY("vcore", "sdi0"),
2867         REGULATOR_SUPPLY("vcore", "sdi1"),
2868         REGULATOR_SUPPLY("vcore", "sdi2"),
2869         REGULATOR_SUPPLY("vcore", "sdi3"),
2870         REGULATOR_SUPPLY("vcore", "sdi4"),
2871         REGULATOR_SUPPLY("v-dma", "dma40.0"),
2872         REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
2873         /* "v-uart" changed to "vcore" in the mainline kernel */
2874         REGULATOR_SUPPLY("vcore", "uart0"),
2875         REGULATOR_SUPPLY("vcore", "uart1"),
2876         REGULATOR_SUPPLY("vcore", "uart2"),
2877         REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
2878         REGULATOR_SUPPLY("v-hsi", "ste_hsi.0"),
2879         REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
2880 };
2881
2882 static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
2883         REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
2884         /* AV8100 regulator */
2885         REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
2886 };
2887
2888 static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
2889         REGULATOR_SUPPLY("vsupply", "b2r2_bus"),
2890         REGULATOR_SUPPLY("vsupply", "mcde"),
2891 };
2892
2893 /* SVA MMDSP regulator switch */
2894 static struct regulator_consumer_supply db8500_svammdsp_consumers[] = {
2895         REGULATOR_SUPPLY("sva-mmdsp", "cm_control"),
2896 };
2897
2898 /* SVA pipe regulator switch */
2899 static struct regulator_consumer_supply db8500_svapipe_consumers[] = {
2900         REGULATOR_SUPPLY("sva-pipe", "cm_control"),
2901 };
2902
2903 /* SIA MMDSP regulator switch */
2904 static struct regulator_consumer_supply db8500_siammdsp_consumers[] = {
2905         REGULATOR_SUPPLY("sia-mmdsp", "cm_control"),
2906 };
2907
2908 /* SIA pipe regulator switch */
2909 static struct regulator_consumer_supply db8500_siapipe_consumers[] = {
2910         REGULATOR_SUPPLY("sia-pipe", "cm_control"),
2911 };
2912
2913 static struct regulator_consumer_supply db8500_sga_consumers[] = {
2914         REGULATOR_SUPPLY("v-mali", NULL),
2915 };
2916
2917 /* ESRAM1 and 2 regulator switch */
2918 static struct regulator_consumer_supply db8500_esram12_consumers[] = {
2919         REGULATOR_SUPPLY("esram12", "cm_control"),
2920 };
2921
2922 /* ESRAM3 and 4 regulator switch */
2923 static struct regulator_consumer_supply db8500_esram34_consumers[] = {
2924         REGULATOR_SUPPLY("v-esram34", "mcde"),
2925         REGULATOR_SUPPLY("esram34", "cm_control"),
2926         REGULATOR_SUPPLY("lcla_esram", "dma40.0"),
2927 };
2928
2929 static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
2930         [DB8500_REGULATOR_VAPE] = {
2931                 .constraints = {
2932                         .name = "db8500-vape",
2933                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2934                         .always_on = true,
2935                 },
2936                 .consumer_supplies = db8500_vape_consumers,
2937                 .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
2938         },
2939         [DB8500_REGULATOR_VARM] = {
2940                 .constraints = {
2941                         .name = "db8500-varm",
2942                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2943                 },
2944         },
2945         [DB8500_REGULATOR_VMODEM] = {
2946                 .constraints = {
2947                         .name = "db8500-vmodem",
2948                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2949                 },
2950         },
2951         [DB8500_REGULATOR_VPLL] = {
2952                 .constraints = {
2953                         .name = "db8500-vpll",
2954                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2955                 },
2956         },
2957         [DB8500_REGULATOR_VSMPS1] = {
2958                 .constraints = {
2959                         .name = "db8500-vsmps1",
2960                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2961                 },
2962         },
2963         [DB8500_REGULATOR_VSMPS2] = {
2964                 .constraints = {
2965                         .name = "db8500-vsmps2",
2966                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2967                 },
2968                 .consumer_supplies = db8500_vsmps2_consumers,
2969                 .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
2970         },
2971         [DB8500_REGULATOR_VSMPS3] = {
2972                 .constraints = {
2973                         .name = "db8500-vsmps3",
2974                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2975                 },
2976         },
2977         [DB8500_REGULATOR_VRF1] = {
2978                 .constraints = {
2979                         .name = "db8500-vrf1",
2980                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2981                 },
2982         },
2983         [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
2984                 /* dependency to u8500-vape is handled outside regulator framework */
2985                 .constraints = {
2986                         .name = "db8500-sva-mmdsp",
2987                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2988                 },
2989                 .consumer_supplies = db8500_svammdsp_consumers,
2990                 .num_consumer_supplies = ARRAY_SIZE(db8500_svammdsp_consumers),
2991         },
2992         [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
2993                 .constraints = {
2994                         /* "ret" means "retention" */
2995                         .name = "db8500-sva-mmdsp-ret",
2996                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
2997                 },
2998         },
2999         [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
3000                 /* dependency to u8500-vape is handled outside regulator framework */
3001                 .constraints = {
3002                         .name = "db8500-sva-pipe",
3003                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3004                 },
3005                 .consumer_supplies = db8500_svapipe_consumers,
3006                 .num_consumer_supplies = ARRAY_SIZE(db8500_svapipe_consumers),
3007         },
3008         [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
3009                 /* dependency to u8500-vape is handled outside regulator framework */
3010                 .constraints = {
3011                         .name = "db8500-sia-mmdsp",
3012                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3013                 },
3014                 .consumer_supplies = db8500_siammdsp_consumers,
3015                 .num_consumer_supplies = ARRAY_SIZE(db8500_siammdsp_consumers),
3016         },
3017         [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
3018                 .constraints = {
3019                         .name = "db8500-sia-mmdsp-ret",
3020                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3021                 },
3022         },
3023         [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
3024                 /* dependency to u8500-vape is handled outside regulator framework */
3025                 .constraints = {
3026                         .name = "db8500-sia-pipe",
3027                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3028                 },
3029                 .consumer_supplies = db8500_siapipe_consumers,
3030                 .num_consumer_supplies = ARRAY_SIZE(db8500_siapipe_consumers),
3031         },
3032         [DB8500_REGULATOR_SWITCH_SGA] = {
3033                 .supply_regulator = "db8500-vape",
3034                 .constraints = {
3035                         .name = "db8500-sga",
3036                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3037                 },
3038                 .consumer_supplies = db8500_sga_consumers,
3039                 .num_consumer_supplies = ARRAY_SIZE(db8500_sga_consumers),
3040
3041         },
3042         [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
3043                 .supply_regulator = "db8500-vape",
3044                 .constraints = {
3045                         .name = "db8500-b2r2-mcde",
3046                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3047                 },
3048                 .consumer_supplies = db8500_b2r2_mcde_consumers,
3049                 .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
3050         },
3051         [DB8500_REGULATOR_SWITCH_ESRAM12] = {
3052                 /*
3053                  * esram12 is set in retention and supplied by Vsafe when Vape is off,
3054                  * no need to hold Vape
3055                  */
3056                 .constraints = {
3057                         .name = "db8500-esram12",
3058                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3059                 },
3060                 .consumer_supplies = db8500_esram12_consumers,
3061                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram12_consumers),
3062         },
3063         [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
3064                 .constraints = {
3065                         .name = "db8500-esram12-ret",
3066                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3067                 },
3068         },
3069         [DB8500_REGULATOR_SWITCH_ESRAM34] = {
3070                 /*
3071                  * esram34 is set in retention and supplied by Vsafe when Vape is off,
3072                  * no need to hold Vape
3073                  */
3074                 .constraints = {
3075                         .name = "db8500-esram34",
3076                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3077                 },
3078                 .consumer_supplies = db8500_esram34_consumers,
3079                 .num_consumer_supplies = ARRAY_SIZE(db8500_esram34_consumers),
3080         },
3081         [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
3082                 .constraints = {
3083                         .name = "db8500-esram34-ret",
3084                         .valid_ops_mask = REGULATOR_CHANGE_STATUS,
3085                 },
3086         },
3087 };
3088
3089 static struct resource ab8500_resources[] = {
3090         [0] = {
3091                 .start  = IRQ_DB8500_AB8500,
3092                 .end    = IRQ_DB8500_AB8500,
3093                 .flags  = IORESOURCE_IRQ
3094         }
3095 };
3096
3097 static struct mfd_cell db8500_prcmu_devs[] = {
3098         {
3099                 .name = "db8500-prcmu-regulators",
3100                 .of_compatible = "stericsson,db8500-prcmu-regulator",
3101                 .platform_data = &db8500_regulators,
3102                 .pdata_size = sizeof(db8500_regulators),
3103         },
3104         {
3105                 .name = "cpufreq-ux500",
3106                 .of_compatible = "stericsson,cpufreq-ux500",
3107                 .platform_data = &db8500_cpufreq_table,
3108                 .pdata_size = sizeof(db8500_cpufreq_table),
3109         },
3110         {
3111                 .name = "ab8500-core",
3112                 .of_compatible = "stericsson,ab8500",
3113                 .num_resources = ARRAY_SIZE(ab8500_resources),
3114                 .resources = ab8500_resources,
3115                 .id = AB8500_VERSION_AB8500,
3116         },
3117 };
3118
3119 static void db8500_prcmu_update_cpufreq(void)
3120 {
3121         if (prcmu_has_arm_maxopp()) {
3122                 db8500_cpufreq_table[3].frequency = 1000000;
3123                 db8500_cpufreq_table[3].index = ARM_MAX_OPP;
3124         }
3125 }
3126
3127 /**
3128  * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3129  *
3130  */
3131 static int db8500_prcmu_probe(struct platform_device *pdev)
3132 {
3133         struct device_node *np = pdev->dev.of_node;
3134         struct prcmu_pdata *pdata = dev_get_platdata(&pdev->dev);
3135         int irq = 0, err = 0, i;
3136         struct resource *res;
3137
3138         init_prcm_registers();
3139
3140         dbx500_fw_version_init(pdev, pdata->version_offset);
3141         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "prcmu-tcdm");
3142         if (!res) {
3143                 dev_err(&pdev->dev, "no prcmu tcdm region provided\n");
3144                 return -ENOENT;
3145         }
3146         tcdm_base = devm_ioremap(&pdev->dev, res->start,
3147                         resource_size(res));
3148
3149         /* Clean up the mailbox interrupts after pre-kernel code. */
3150         writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLR);
3151
3152         irq = platform_get_irq(pdev, 0);
3153         if (irq <= 0) {
3154                 dev_err(&pdev->dev, "no prcmu irq provided\n");
3155                 return -ENOENT;
3156         }
3157
3158         err = request_threaded_irq(irq, prcmu_irq_handler,
3159                 prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
3160         if (err < 0) {
3161                 pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
3162                 err = -EBUSY;
3163                 goto no_irq_return;
3164         }
3165
3166         db8500_irq_init(np);
3167
3168         for (i = 0; i < ARRAY_SIZE(db8500_prcmu_devs); i++) {
3169                 if (!strcmp(db8500_prcmu_devs[i].name, "ab8500-core")) {
3170                         db8500_prcmu_devs[i].platform_data = pdata->ab_platdata;
3171                         db8500_prcmu_devs[i].pdata_size = sizeof(struct ab8500_platform_data);
3172                 }
3173         }
3174
3175         prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3176
3177         db8500_prcmu_update_cpufreq();
3178
3179         err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3180                               ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL);
3181         if (err) {
3182                 pr_err("prcmu: Failed to add subdevices\n");
3183                 return err;
3184         }
3185
3186         pr_info("DB8500 PRCMU initialized\n");
3187
3188 no_irq_return:
3189         return err;
3190 }
3191 static const struct of_device_id db8500_prcmu_match[] = {
3192         { .compatible = "stericsson,db8500-prcmu"},
3193         { },
3194 };
3195
3196 static struct platform_driver db8500_prcmu_driver = {
3197         .driver = {
3198                 .name = "db8500-prcmu",
3199                 .owner = THIS_MODULE,
3200                 .of_match_table = db8500_prcmu_match,
3201         },
3202         .probe = db8500_prcmu_probe,
3203 };
3204
3205 static int __init db8500_prcmu_init(void)
3206 {
3207         return platform_driver_register(&db8500_prcmu_driver);
3208 }
3209
3210 core_initcall(db8500_prcmu_init);
3211
3212 MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
3213 MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
3214 MODULE_LICENSE("GPL v2");