drivers/memory/tegra/tegra124.c

   1 /*
   2  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/of.h>
  10 #include <linux/mm.h>
  11
  12 #include <dt-bindings/memory/tegra124-mc.h>
  13
  14 #include "mc.h"
  15
  16 #define MC_EMEM_ARB_CFG                         0x90
  17 #define MC_EMEM_ARB_OUTSTANDING_REQ             0x94
  18 #define MC_EMEM_ARB_TIMING_RCD                  0x98
  19 #define MC_EMEM_ARB_TIMING_RP                   0x9c
  20 #define MC_EMEM_ARB_TIMING_RC                   0xa0
  21 #define MC_EMEM_ARB_TIMING_RAS                  0xa4
  22 #define MC_EMEM_ARB_TIMING_FAW                  0xa8
  23 #define MC_EMEM_ARB_TIMING_RRD                  0xac
  24 #define MC_EMEM_ARB_TIMING_RAP2PRE              0xb0
  25 #define MC_EMEM_ARB_TIMING_WAP2PRE              0xb4
  26 #define MC_EMEM_ARB_TIMING_R2R                  0xb8
  27 #define MC_EMEM_ARB_TIMING_W2W                  0xbc
  28 #define MC_EMEM_ARB_TIMING_R2W                  0xc0
  29 #define MC_EMEM_ARB_TIMING_W2R                  0xc4
  30 #define MC_EMEM_ARB_DA_TURNS                    0xd0
  31 #define MC_EMEM_ARB_DA_COVERS                   0xd4
  32 #define MC_EMEM_ARB_MISC0                       0xd8
  33 #define MC_EMEM_ARB_MISC1                       0xdc
  34 #define MC_EMEM_ARB_RING1_THROTTLE              0xe0
  35
  36 static const struct tegra_mc_client tegra124_mc_clients[] = {
  37         {
  38                 .id = 0x00,
  39                 .name = "ptcr",
  40                 .swgroup = TEGRA_SWGROUP_PTC,
  41         }, {
  42                 .id = 0x01,
  43                 .name = "display0a",
  44                 .swgroup = TEGRA_SWGROUP_DC,
  45                 .smmu = {
  46                         .reg = 0x228,
  47                         .bit = 1,
  48                 },
  49                 .la = {
  50                         .reg = 0x2e8,
  51                         .shift = 0,
  52                         .mask = 0xff,
  53                         .def = 0xc2,
  54                 },
  55         }, {
  56                 .id = 0x02,
  57                 .name = "display0ab",
  58                 .swgroup = TEGRA_SWGROUP_DCB,
  59                 .smmu = {
  60                         .reg = 0x228,
  61                         .bit = 2,
  62                 },
  63                 .la = {
  64                         .reg = 0x2f4,
  65                         .shift = 0,
  66                         .mask = 0xff,
  67                         .def = 0xc6,
  68                 },
  69         }, {
  70                 .id = 0x03,
  71                 .name = "display0b",
  72                 .swgroup = TEGRA_SWGROUP_DC,
  73                 .smmu = {
  74                         .reg = 0x228,
  75                         .bit = 3,
  76                 },
  77                 .la = {
  78                         .reg = 0x2e8,
  79                         .shift = 16,
  80                         .mask = 0xff,
  81                         .def = 0x50,
  82                 },
  83         }, {
  84                 .id = 0x04,
  85                 .name = "display0bb",
  86                 .swgroup = TEGRA_SWGROUP_DCB,
  87                 .smmu = {
  88                         .reg = 0x228,
  89                         .bit = 4,
  90                 },
  91                 .la = {
  92                         .reg = 0x2f4,
  93                         .shift = 16,
  94                         .mask = 0xff,
  95                         .def = 0x50,
  96                 },
  97         }, {
  98                 .id = 0x05,
  99                 .name = "display0c",
 100                 .swgroup = TEGRA_SWGROUP_DC,
 101                 .smmu = {
 102                         .reg = 0x228,
 103                         .bit = 5,
 104                 },
 105                 .la = {
 106                         .reg = 0x2ec,
 107                         .shift = 0,
 108                         .mask = 0xff,
 109                         .def = 0x50,
 110                 },
 111         }, {
 112                 .id = 0x06,
 113                 .name = "display0cb",
 114                 .swgroup = TEGRA_SWGROUP_DCB,
 115                 .smmu = {
 116                         .reg = 0x228,
 117                         .bit = 6,
 118                 },
 119                 .la = {
 120                         .reg = 0x2f8,
 121                         .shift = 0,
 122                         .mask = 0xff,
 123                         .def = 0x50,
 124                 },
 125         }, {
 126                 .id = 0x0e,
 127                 .name = "afir",
 128                 .swgroup = TEGRA_SWGROUP_AFI,
 129                 .smmu = {
 130                         .reg = 0x228,
 131                         .bit = 14,
 132                 },
 133                 .la = {
 134                         .reg = 0x2e0,
 135                         .shift = 0,
 136                         .mask = 0xff,
 137                         .def = 0x13,
 138                 },
 139         }, {
 140                 .id = 0x0f,
 141                 .name = "avpcarm7r",
 142                 .swgroup = TEGRA_SWGROUP_AVPC,
 143                 .smmu = {
 144                         .reg = 0x228,
 145                         .bit = 15,
 146                 },
 147                 .la = {
 148                         .reg = 0x2e4,
 149                         .shift = 0,
 150                         .mask = 0xff,
 151                         .def = 0x04,
 152                 },
 153         }, {
 154                 .id = 0x10,
 155                 .name = "displayhc",
 156                 .swgroup = TEGRA_SWGROUP_DC,
 157                 .smmu = {
 158                         .reg = 0x228,
 159                         .bit = 16,
 160                 },
 161                 .la = {
 162                         .reg = 0x2f0,
 163                         .shift = 0,
 164                         .mask = 0xff,
 165                         .def = 0x50,
 166                 },
 167         }, {
 168                 .id = 0x11,
 169                 .name = "displayhcb",
 170                 .swgroup = TEGRA_SWGROUP_DCB,
 171                 .smmu = {
 172                         .reg = 0x228,
 173                         .bit = 17,
 174                 },
 175                 .la = {
 176                         .reg = 0x2fc,
 177                         .shift = 0,
 178                         .mask = 0xff,
 179                         .def = 0x50,
 180                 },
 181         }, {
 182                 .id = 0x15,
 183                 .name = "hdar",
 184                 .swgroup = TEGRA_SWGROUP_HDA,
 185                 .smmu = {
 186                         .reg = 0x228,
 187                         .bit = 21,
 188                 },
 189                 .la = {
 190                         .reg = 0x318,
 191                         .shift = 0,
 192                         .mask = 0xff,
 193                         .def = 0x24,
 194                 },
 195         }, {
 196                 .id = 0x16,
 197                 .name = "host1xdmar",
 198                 .swgroup = TEGRA_SWGROUP_HC,
 199                 .smmu = {
 200                         .reg = 0x228,
 201                         .bit = 22,
 202                 },
 203                 .la = {
 204                         .reg = 0x310,
 205                         .shift = 0,
 206                         .mask = 0xff,
 207                         .def = 0x1e,
 208                 },
 209         }, {
 210                 .id = 0x17,
 211                 .name = "host1xr",
 212                 .swgroup = TEGRA_SWGROUP_HC,
 213                 .smmu = {
 214                         .reg = 0x228,
 215                         .bit = 23,
 216                 },
 217                 .la = {
 218                         .reg = 0x310,
 219                         .shift = 16,
 220                         .mask = 0xff,
 221                         .def = 0x50,
 222                 },
 223         }, {
 224                 .id = 0x1c,
 225                 .name = "msencsrd",
 226                 .swgroup = TEGRA_SWGROUP_MSENC,
 227                 .smmu = {
 228                         .reg = 0x228,
 229                         .bit = 28,
 230                 },
 231                 .la = {
 232                         .reg = 0x328,
 233                         .shift = 0,
 234                         .mask = 0xff,
 235                         .def = 0x23,
 236                 },
 237         }, {
 238                 .id = 0x1d,
 239                 .name = "ppcsahbdmar",
 240                 .swgroup = TEGRA_SWGROUP_PPCS,
 241                 .smmu = {
 242                         .reg = 0x228,
 243                         .bit = 29,
 244                 },
 245                 .la = {
 246                         .reg = 0x344,
 247                         .shift = 0,
 248                         .mask = 0xff,
 249                         .def = 0x49,
 250                 },
 251         }, {
 252                 .id = 0x1e,
 253                 .name = "ppcsahbslvr",
 254                 .swgroup = TEGRA_SWGROUP_PPCS,
 255                 .smmu = {
 256                         .reg = 0x228,
 257                         .bit = 30,
 258                 },
 259                 .la = {
 260                         .reg = 0x344,
 261                         .shift = 16,
 262                         .mask = 0xff,
 263                         .def = 0x1a,
 264                 },
 265         }, {
 266                 .id = 0x1f,
 267                 .name = "satar",
 268                 .swgroup = TEGRA_SWGROUP_SATA,
 269                 .smmu = {
 270                         .reg = 0x228,
 271                         .bit = 31,
 272                 },
 273                 .la = {
 274                         .reg = 0x350,
 275                         .shift = 0,
 276                         .mask = 0xff,
 277                         .def = 0x65,
 278                 },
 279         }, {
 280                 .id = 0x22,
 281                 .name = "vdebsevr",
 282                 .swgroup = TEGRA_SWGROUP_VDE,
 283                 .smmu = {
 284                         .reg = 0x22c,
 285                         .bit = 2,
 286                 },
 287                 .la = {
 288                         .reg = 0x354,
 289                         .shift = 0,
 290                         .mask = 0xff,
 291                         .def = 0x4f,
 292                 },
 293         }, {
 294                 .id = 0x23,
 295                 .name = "vdember",
 296                 .swgroup = TEGRA_SWGROUP_VDE,
 297                 .smmu = {
 298                         .reg = 0x22c,
 299                         .bit = 3,
 300                 },
 301                 .la = {
 302                         .reg = 0x354,
 303                         .shift = 16,
 304                         .mask = 0xff,
 305                         .def = 0x3d,
 306                 },
 307         }, {
 308                 .id = 0x24,
 309                 .name = "vdemcer",
 310                 .swgroup = TEGRA_SWGROUP_VDE,
 311                 .smmu = {
 312                         .reg = 0x22c,
 313                         .bit = 4,
 314                 },
 315                 .la = {
 316                         .reg = 0x358,
 317                         .shift = 0,
 318                         .mask = 0xff,
 319                         .def = 0x66,
 320                 },
 321         }, {
 322                 .id = 0x25,
 323                 .name = "vdetper",
 324                 .swgroup = TEGRA_SWGROUP_VDE,
 325                 .smmu = {
 326                         .reg = 0x22c,
 327                         .bit = 5,
 328                 },
 329                 .la = {
 330                         .reg = 0x358,
 331                         .shift = 16,
 332                         .mask = 0xff,
 333                         .def = 0xa5,
 334                 },
 335         }, {
 336                 .id = 0x26,
 337                 .name = "mpcorelpr",
 338                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 339                 .la = {
 340                         .reg = 0x324,
 341                         .shift = 0,
 342                         .mask = 0xff,
 343                         .def = 0x04,
 344                 },
 345         }, {
 346                 .id = 0x27,
 347                 .name = "mpcorer",
 348                 .swgroup = TEGRA_SWGROUP_MPCORE,
 349                 .la = {
 350                         .reg = 0x320,
 351                         .shift = 0,
 352                         .mask = 0xff,
 353                         .def = 0x04,
 354                 },
 355         }, {
 356                 .id = 0x2b,
 357                 .name = "msencswr",
 358                 .swgroup = TEGRA_SWGROUP_MSENC,
 359                 .smmu = {
 360                         .reg = 0x22c,
 361                         .bit = 11,
 362                 },
 363                 .la = {
 364                         .reg = 0x328,
 365                         .shift = 16,
 366                         .mask = 0xff,
 367                         .def = 0x80,
 368                 },
 369         }, {
 370                 .id = 0x31,
 371                 .name = "afiw",
 372                 .swgroup = TEGRA_SWGROUP_AFI,
 373                 .smmu = {
 374                         .reg = 0x22c,
 375                         .bit = 17,
 376                 },
 377                 .la = {
 378                         .reg = 0x2e0,
 379                         .shift = 16,
 380                         .mask = 0xff,
 381                         .def = 0x80,
 382                 },
 383         }, {
 384                 .id = 0x32,
 385                 .name = "avpcarm7w",
 386                 .swgroup = TEGRA_SWGROUP_AVPC,
 387                 .smmu = {
 388                         .reg = 0x22c,
 389                         .bit = 18,
 390                 },
 391                 .la = {
 392                         .reg = 0x2e4,
 393                         .shift = 16,
 394                         .mask = 0xff,
 395                         .def = 0x80,
 396                 },
 397         }, {
 398                 .id = 0x35,
 399                 .name = "hdaw",
 400                 .swgroup = TEGRA_SWGROUP_HDA,
 401                 .smmu = {
 402                         .reg = 0x22c,
 403                         .bit = 21,
 404                 },
 405                 .la = {
 406                         .reg = 0x318,
 407                         .shift = 16,
 408                         .mask = 0xff,
 409                         .def = 0x80,
 410                 },
 411         }, {
 412                 .id = 0x36,
 413                 .name = "host1xw",
 414                 .swgroup = TEGRA_SWGROUP_HC,
 415                 .smmu = {
 416                         .reg = 0x22c,
 417                         .bit = 22,
 418                 },
 419                 .la = {
 420                         .reg = 0x314,
 421                         .shift = 0,
 422                         .mask = 0xff,
 423                         .def = 0x80,
 424                 },
 425         }, {
 426                 .id = 0x38,
 427                 .name = "mpcorelpw",
 428                 .swgroup = TEGRA_SWGROUP_MPCORELP,
 429                 .la = {
 430                         .reg = 0x324,
 431                         .shift = 16,
 432                         .mask = 0xff,
 433                         .def = 0x80,
 434                 },
 435         }, {
 436                 .id = 0x39,
 437                 .name = "mpcorew",
 438                 .swgroup = TEGRA_SWGROUP_MPCORE,
 439                 .la = {
 440                         .reg = 0x320,
 441                         .shift = 16,
 442                         .mask = 0xff,
 443                         .def = 0x80,
 444                 },
 445         }, {
 446                 .id = 0x3b,
 447                 .name = "ppcsahbdmaw",
 448                 .swgroup = TEGRA_SWGROUP_PPCS,
 449                 .smmu = {
 450                         .reg = 0x22c,
 451                         .bit = 27,
 452                 },
 453                 .la = {
 454                         .reg = 0x348,
 455                         .shift = 0,
 456                         .mask = 0xff,
 457                         .def = 0x80,
 458                 },
 459         }, {
 460                 .id = 0x3c,
 461                 .name = "ppcsahbslvw",
 462                 .swgroup = TEGRA_SWGROUP_PPCS,
 463                 .smmu = {
 464                         .reg = 0x22c,
 465                         .bit = 28,
 466                 },
 467                 .la = {
 468                         .reg = 0x348,
 469                         .shift = 16,
 470                         .mask = 0xff,
 471                         .def = 0x80,
 472                 },
 473         }, {
 474                 .id = 0x3d,
 475                 .name = "sataw",
 476                 .swgroup = TEGRA_SWGROUP_SATA,
 477                 .smmu = {
 478                         .reg = 0x22c,
 479                         .bit = 29,
 480                 },
 481                 .la = {
 482                         .reg = 0x350,
 483                         .shift = 16,
 484                         .mask = 0xff,
 485                         .def = 0x65,
 486                 },
 487         }, {
 488                 .id = 0x3e,
 489                 .name = "vdebsevw",
 490                 .swgroup = TEGRA_SWGROUP_VDE,
 491                 .smmu = {
 492                         .reg = 0x22c,
 493                         .bit = 30,
 494                 },
 495                 .la = {
 496                         .reg = 0x35c,
 497                         .shift = 0,
 498                         .mask = 0xff,
 499                         .def = 0x80,
 500                 },
 501         }, {
 502                 .id = 0x3f,
 503                 .name = "vdedbgw",
 504                 .swgroup = TEGRA_SWGROUP_VDE,
 505                 .smmu = {
 506                         .reg = 0x22c,
 507                         .bit = 31,
 508                 },
 509                 .la = {
 510                         .reg = 0x35c,
 511                         .shift = 16,
 512                         .mask = 0xff,
 513                         .def = 0x80,
 514                 },
 515         }, {
 516                 .id = 0x40,
 517                 .name = "vdembew",
 518                 .swgroup = TEGRA_SWGROUP_VDE,
 519                 .smmu = {
 520                         .reg = 0x230,
 521                         .bit = 0,
 522                 },
 523                 .la = {
 524                         .reg = 0x360,
 525                         .shift = 0,
 526                         .mask = 0xff,
 527                         .def = 0x80,
 528                 },
 529         }, {
 530                 .id = 0x41,
 531                 .name = "vdetpmw",
 532                 .swgroup = TEGRA_SWGROUP_VDE,
 533                 .smmu = {
 534                         .reg = 0x230,
 535                         .bit = 1,
 536                 },
 537                 .la = {
 538                         .reg = 0x360,
 539                         .shift = 16,
 540                         .mask = 0xff,
 541                         .def = 0x80,
 542                 },
 543         }, {
 544                 .id = 0x44,
 545                 .name = "ispra",
 546                 .swgroup = TEGRA_SWGROUP_ISP2,
 547                 .smmu = {
 548                         .reg = 0x230,
 549                         .bit = 4,
 550                 },
 551                 .la = {
 552                         .reg = 0x370,
 553                         .shift = 0,
 554                         .mask = 0xff,
 555                         .def = 0x18,
 556                 },
 557         }, {
 558                 .id = 0x46,
 559                 .name = "ispwa",
 560                 .swgroup = TEGRA_SWGROUP_ISP2,
 561                 .smmu = {
 562                         .reg = 0x230,
 563                         .bit = 6,
 564                 },
 565                 .la = {
 566                         .reg = 0x374,
 567                         .shift = 0,
 568                         .mask = 0xff,
 569                         .def = 0x80,
 570                 },
 571         }, {
 572                 .id = 0x47,
 573                 .name = "ispwb",
 574                 .swgroup = TEGRA_SWGROUP_ISP2,
 575                 .smmu = {
 576                         .reg = 0x230,
 577                         .bit = 7,
 578                 },
 579                 .la = {
 580                         .reg = 0x374,
 581                         .shift = 16,
 582                         .mask = 0xff,
 583                         .def = 0x80,
 584                 },
 585         }, {
 586                 .id = 0x4a,
 587                 .name = "xusb_hostr",
 588                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 589                 .smmu = {
 590                         .reg = 0x230,
 591                         .bit = 10,
 592                 },
 593                 .la = {
 594                         .reg = 0x37c,
 595                         .shift = 0,
 596                         .mask = 0xff,
 597                         .def = 0x39,
 598                 },
 599         }, {
 600                 .id = 0x4b,
 601                 .name = "xusb_hostw",
 602                 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
 603                 .smmu = {
 604                         .reg = 0x230,
 605                         .bit = 11,
 606                 },
 607                 .la = {
 608                         .reg = 0x37c,
 609                         .shift = 16,
 610                         .mask = 0xff,
 611                         .def = 0x80,
 612                 },
 613         }, {
 614                 .id = 0x4c,
 615                 .name = "xusb_devr",
 616                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 617                 .smmu = {
 618                         .reg = 0x230,
 619                         .bit = 12,
 620                 },
 621                 .la = {
 622                         .reg = 0x380,
 623                         .shift = 0,
 624                         .mask = 0xff,
 625                         .def = 0x39,
 626                 },
 627         }, {
 628                 .id = 0x4d,
 629                 .name = "xusb_devw",
 630                 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
 631                 .smmu = {
 632                         .reg = 0x230,
 633                         .bit = 13,
 634                 },
 635                 .la = {
 636                         .reg = 0x380,
 637                         .shift = 16,
 638                         .mask = 0xff,
 639                         .def = 0x80,
 640                 },
 641         }, {
 642                 .id = 0x4e,
 643                 .name = "isprab",
 644                 .swgroup = TEGRA_SWGROUP_ISP2B,
 645                 .smmu = {
 646                         .reg = 0x230,
 647                         .bit = 14,
 648                 },
 649                 .la = {
 650                         .reg = 0x384,
 651                         .shift = 0,
 652                         .mask = 0xff,
 653                         .def = 0x18,
 654                 },
 655         }, {
 656                 .id = 0x50,
 657                 .name = "ispwab",
 658                 .swgroup = TEGRA_SWGROUP_ISP2B,
 659                 .smmu = {
 660                         .reg = 0x230,
 661                         .bit = 16,
 662                 },
 663                 .la = {
 664                         .reg = 0x388,
 665                         .shift = 0,
 666                         .mask = 0xff,
 667                         .def = 0x80,
 668                 },
 669         }, {
 670                 .id = 0x51,
 671                 .name = "ispwbb",
 672                 .swgroup = TEGRA_SWGROUP_ISP2B,
 673                 .smmu = {
 674                         .reg = 0x230,
 675                         .bit = 17,
 676                 },
 677                 .la = {
 678                         .reg = 0x388,
 679                         .shift = 16,
 680                         .mask = 0xff,
 681                         .def = 0x80,
 682                 },
 683         }, {
 684                 .id = 0x54,
 685                 .name = "tsecsrd",
 686                 .swgroup = TEGRA_SWGROUP_TSEC,
 687                 .smmu = {
 688                         .reg = 0x230,
 689                         .bit = 20,
 690                 },
 691                 .la = {
 692                         .reg = 0x390,
 693                         .shift = 0,
 694                         .mask = 0xff,
 695                         .def = 0x9b,
 696                 },
 697         }, {
 698                 .id = 0x55,
 699                 .name = "tsecswr",
 700                 .swgroup = TEGRA_SWGROUP_TSEC,
 701                 .smmu = {
 702                         .reg = 0x230,
 703                         .bit = 21,
 704                 },
 705                 .la = {
 706                         .reg = 0x390,
 707                         .shift = 16,
 708                         .mask = 0xff,
 709                         .def = 0x80,
 710                 },
 711         }, {
 712                 .id = 0x56,
 713                 .name = "a9avpscr",
 714                 .swgroup = TEGRA_SWGROUP_A9AVP,
 715                 .smmu = {
 716                         .reg = 0x230,
 717                         .bit = 22,
 718                 },
 719                 .la = {
 720                         .reg = 0x3a4,
 721                         .shift = 0,
 722                         .mask = 0xff,
 723                         .def = 0x04,
 724                 },
 725         }, {
 726                 .id = 0x57,
 727                 .name = "a9avpscw",
 728                 .swgroup = TEGRA_SWGROUP_A9AVP,
 729                 .smmu = {
 730                         .reg = 0x230,
 731                         .bit = 23,
 732                 },
 733                 .la = {
 734                         .reg = 0x3a4,
 735                         .shift = 16,
 736                         .mask = 0xff,
 737                         .def = 0x80,
 738                 },
 739         }, {
 740                 .id = 0x58,
 741                 .name = "gpusrd",
 742                 .swgroup = TEGRA_SWGROUP_GPU,
 743                 .smmu = {
 744                         /* read-only */
 745                         .reg = 0x230,
 746                         .bit = 24,
 747                 },
 748                 .la = {
 749                         .reg = 0x3c8,
 750                         .shift = 0,
 751                         .mask = 0xff,
 752                         .def = 0x1a,
 753                 },
 754         }, {
 755                 .id = 0x59,
 756                 .name = "gpuswr",
 757                 .swgroup = TEGRA_SWGROUP_GPU,
 758                 .smmu = {
 759                         /* read-only */
 760                         .reg = 0x230,
 761                         .bit = 25,
 762                 },
 763                 .la = {
 764                         .reg = 0x3c8,
 765                         .shift = 16,
 766                         .mask = 0xff,
 767                         .def = 0x80,
 768                 },
 769         }, {
 770                 .id = 0x5a,
 771                 .name = "displayt",
 772                 .swgroup = TEGRA_SWGROUP_DC,
 773                 .smmu = {
 774                         .reg = 0x230,
 775                         .bit = 26,
 776                 },
 777                 .la = {
 778                         .reg = 0x2f0,
 779                         .shift = 16,
 780                         .mask = 0xff,
 781                         .def = 0x50,
 782                 },
 783         }, {
 784                 .id = 0x60,
 785                 .name = "sdmmcra",
 786                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 787                 .smmu = {
 788                         .reg = 0x234,
 789                         .bit = 0,
 790                 },
 791                 .la = {
 792                         .reg = 0x3b8,
 793                         .shift = 0,
 794                         .mask = 0xff,
 795                         .def = 0x49,
 796                 },
 797         }, {
 798                 .id = 0x61,
 799                 .name = "sdmmcraa",
 800                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 801                 .smmu = {
 802                         .reg = 0x234,
 803                         .bit = 1,
 804                 },
 805                 .la = {
 806                         .reg = 0x3bc,
 807                         .shift = 0,
 808                         .mask = 0xff,
 809                         .def = 0x49,
 810                 },
 811         }, {
 812                 .id = 0x62,
 813                 .name = "sdmmcr",
 814                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 815                 .smmu = {
 816                         .reg = 0x234,
 817                         .bit = 2,
 818                 },
 819                 .la = {
 820                         .reg = 0x3c0,
 821                         .shift = 0,
 822                         .mask = 0xff,
 823                         .def = 0x49,
 824                 },
 825         }, {
 826                 .id = 0x63,
 827                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 828                 .name = "sdmmcrab",
 829                 .smmu = {
 830                         .reg = 0x234,
 831                         .bit = 3,
 832                 },
 833                 .la = {
 834                         .reg = 0x3c4,
 835                         .shift = 0,
 836                         .mask = 0xff,
 837                         .def = 0x49,
 838                 },
 839         }, {
 840                 .id = 0x64,
 841                 .name = "sdmmcwa",
 842                 .swgroup = TEGRA_SWGROUP_SDMMC1A,
 843                 .smmu = {
 844                         .reg = 0x234,
 845                         .bit = 4,
 846                 },
 847                 .la = {
 848                         .reg = 0x3b8,
 849                         .shift = 16,
 850                         .mask = 0xff,
 851                         .def = 0x80,
 852                 },
 853         }, {
 854                 .id = 0x65,
 855                 .name = "sdmmcwaa",
 856                 .swgroup = TEGRA_SWGROUP_SDMMC2A,
 857                 .smmu = {
 858                         .reg = 0x234,
 859                         .bit = 5,
 860                 },
 861                 .la = {
 862                         .reg = 0x3bc,
 863                         .shift = 16,
 864                         .mask = 0xff,
 865                         .def = 0x80,
 866                 },
 867         }, {
 868                 .id = 0x66,
 869                 .name = "sdmmcw",
 870                 .swgroup = TEGRA_SWGROUP_SDMMC3A,
 871                 .smmu = {
 872                         .reg = 0x234,
 873                         .bit = 6,
 874                 },
 875                 .la = {
 876                         .reg = 0x3c0,
 877                         .shift = 16,
 878                         .mask = 0xff,
 879                         .def = 0x80,
 880                 },
 881         }, {
 882                 .id = 0x67,
 883                 .name = "sdmmcwab",
 884                 .swgroup = TEGRA_SWGROUP_SDMMC4A,
 885                 .smmu = {
 886                         .reg = 0x234,
 887                         .bit = 7,
 888                 },
 889                 .la = {
 890                         .reg = 0x3c4,
 891                         .shift = 16,
 892                         .mask = 0xff,
 893                         .def = 0x80,
 894                 },
 895         }, {
 896                 .id = 0x6c,
 897                 .name = "vicsrd",
 898                 .swgroup = TEGRA_SWGROUP_VIC,
 899                 .smmu = {
 900                         .reg = 0x234,
 901                         .bit = 12,
 902                 },
 903                 .la = {
 904                         .reg = 0x394,
 905                         .shift = 0,
 906                         .mask = 0xff,
 907                         .def = 0x1a,
 908                 },
 909         }, {
 910                 .id = 0x6d,
 911                 .name = "vicswr",
 912                 .swgroup = TEGRA_SWGROUP_VIC,
 913                 .smmu = {
 914                         .reg = 0x234,
 915                         .bit = 13,
 916                 },
 917                 .la = {
 918                         .reg = 0x394,
 919                         .shift = 16,
 920                         .mask = 0xff,
 921                         .def = 0x80,
 922                 },
 923         }, {
 924                 .id = 0x72,
 925                 .name = "viw",
 926                 .swgroup = TEGRA_SWGROUP_VI,
 927                 .smmu = {
 928                         .reg = 0x234,
 929                         .bit = 18,
 930                 },
 931                 .la = {
 932                         .reg = 0x398,
 933                         .shift = 0,
 934                         .mask = 0xff,
 935                         .def = 0x80,
 936                 },
 937         }, {
 938                 .id = 0x73,
 939                 .name = "displayd",
 940                 .swgroup = TEGRA_SWGROUP_DC,
 941                 .smmu = {
 942                         .reg = 0x234,
 943                         .bit = 19,
 944                 },
 945                 .la = {
 946                         .reg = 0x3c8,
 947                         .shift = 0,
 948                         .mask = 0xff,
 949                         .def = 0x50,
 950                 },
 951         },
 952 };
 953
 954 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
 955         { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
 956         { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
 957         { .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
 958         { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
 959         { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
 960         { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
 961         { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
 962         { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
 963         { .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
 964         { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
 965         { .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
 966         { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
 967         { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
 968         { .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
 969         { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
 970         { .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
 971         { .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
 972         { .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
 973         { .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
 974         { .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
 975         { .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
 976         { .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
 977         { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
 978 };
 979
 980 static const unsigned int tegra124_group_display[] = {
 981         TEGRA_SWGROUP_DC,
 982         TEGRA_SWGROUP_DCB,
 983 };
 984
 985 static const struct tegra_smmu_group_soc tegra124_groups[] = {
 986         {
 987                 .name = "display",
 988                 .swgroups = tegra124_group_display,
 989                 .num_swgroups = ARRAY_SIZE(tegra124_group_display),
 990         },
 991 };
 992
 993 #define TEGRA124_MC_RESET(_name, _control, _status, _bit)       \
 994         {                                                       \
 995                 .name = #_name,                                 \
 996                 .id = TEGRA124_MC_RESET_##_name,                \
 997                 .control = _control,                            \
 998                 .status = _status,                              \
 999                 .bit = _bit,                                    \
1000         }
1001
1002 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1003         TEGRA124_MC_RESET(AFI,       0x200, 0x204,  0),
1004         TEGRA124_MC_RESET(AVPC,      0x200, 0x204,  1),
1005         TEGRA124_MC_RESET(DC,        0x200, 0x204,  2),
1006         TEGRA124_MC_RESET(DCB,       0x200, 0x204,  3),
1007         TEGRA124_MC_RESET(HC,        0x200, 0x204,  6),
1008         TEGRA124_MC_RESET(HDA,       0x200, 0x204,  7),
1009         TEGRA124_MC_RESET(ISP2,      0x200, 0x204,  8),
1010         TEGRA124_MC_RESET(MPCORE,    0x200, 0x204,  9),
1011         TEGRA124_MC_RESET(MPCORELP,  0x200, 0x204, 10),
1012         TEGRA124_MC_RESET(MSENC,     0x200, 0x204, 11),
1013         TEGRA124_MC_RESET(PPCS,      0x200, 0x204, 14),
1014         TEGRA124_MC_RESET(SATA,      0x200, 0x204, 15),
1015         TEGRA124_MC_RESET(VDE,       0x200, 0x204, 16),
1016         TEGRA124_MC_RESET(VI,        0x200, 0x204, 17),
1017         TEGRA124_MC_RESET(VIC,       0x200, 0x204, 18),
1018         TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1019         TEGRA124_MC_RESET(XUSB_DEV,  0x200, 0x204, 20),
1020         TEGRA124_MC_RESET(TSEC,      0x200, 0x204, 21),
1021         TEGRA124_MC_RESET(SDMMC1,    0x200, 0x204, 22),
1022         TEGRA124_MC_RESET(SDMMC2,    0x200, 0x204, 23),
1023         TEGRA124_MC_RESET(SDMMC3,    0x200, 0x204, 25),
1024         TEGRA124_MC_RESET(SDMMC4,    0x970, 0x974,  0),
1025         TEGRA124_MC_RESET(ISP2B,     0x970, 0x974,  1),
1026         TEGRA124_MC_RESET(GPU,       0x970, 0x974,  2),
1027 };
1028
1029 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1030 static const unsigned long tegra124_mc_emem_regs[] = {
1031         MC_EMEM_ARB_CFG,
1032         MC_EMEM_ARB_OUTSTANDING_REQ,
1033         MC_EMEM_ARB_TIMING_RCD,
1034         MC_EMEM_ARB_TIMING_RP,
1035         MC_EMEM_ARB_TIMING_RC,
1036         MC_EMEM_ARB_TIMING_RAS,
1037         MC_EMEM_ARB_TIMING_FAW,
1038         MC_EMEM_ARB_TIMING_RRD,
1039         MC_EMEM_ARB_TIMING_RAP2PRE,
1040         MC_EMEM_ARB_TIMING_WAP2PRE,
1041         MC_EMEM_ARB_TIMING_R2R,
1042         MC_EMEM_ARB_TIMING_W2W,
1043         MC_EMEM_ARB_TIMING_R2W,
1044         MC_EMEM_ARB_TIMING_W2R,
1045         MC_EMEM_ARB_DA_TURNS,
1046         MC_EMEM_ARB_DA_COVERS,
1047         MC_EMEM_ARB_MISC0,
1048         MC_EMEM_ARB_MISC1,
1049         MC_EMEM_ARB_RING1_THROTTLE
1050 };
1051
1052 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1053         .clients = tegra124_mc_clients,
1054         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1055         .swgroups = tegra124_swgroups,
1056         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1057         .groups = tegra124_groups,
1058         .num_groups = ARRAY_SIZE(tegra124_groups),
1059         .supports_round_robin_arbitration = true,
1060         .supports_request_limit = true,
1061         .num_tlb_lines = 32,
1062         .num_asids = 128,
1063 };
1064
1065 const struct tegra_mc_soc tegra124_mc_soc = {
1066         .clients = tegra124_mc_clients,
1067         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1068         .num_address_bits = 34,
1069         .atom_size = 32,
1070         .client_id_mask = 0x7f,
1071         .smmu = &tegra124_smmu_soc,
1072         .emem_regs = tegra124_mc_emem_regs,
1073         .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1074         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1075                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1076                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1077         .reset_ops = &tegra_mc_reset_ops_common,
1078         .resets = tegra124_mc_resets,
1079         .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1080 };
1081 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1082
1083 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1084 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1085         .clients = tegra124_mc_clients,
1086         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1087         .swgroups = tegra124_swgroups,
1088         .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1089         .groups = tegra124_groups,
1090         .num_groups = ARRAY_SIZE(tegra124_groups),
1091         .supports_round_robin_arbitration = true,
1092         .supports_request_limit = true,
1093         .num_tlb_lines = 32,
1094         .num_asids = 128,
1095 };
1096
1097 const struct tegra_mc_soc tegra132_mc_soc = {
1098         .clients = tegra124_mc_clients,
1099         .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1100         .num_address_bits = 34,
1101         .atom_size = 32,
1102         .client_id_mask = 0x7f,
1103         .smmu = &tegra132_smmu_soc,
1104         .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1105                    MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1106                    MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1107         .reset_ops = &tegra_mc_reset_ops_common,
1108         .resets = tegra124_mc_resets,
1109         .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1110 };
1111 #endif /* CONFIG_ARCH_TEGRA_132_SOC */