drivers/memory/emif.c

   1 /*
   2  * EMIF driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments, Inc.
   5  *
   6  * Aneesh V <aneesh@ti.com>
   7  * Santosh Shilimkar <santosh.shilimkar@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/err.h>
  14 #include <linux/kernel.h>
  15 #include <linux/reboot.h>
  16 #include <linux/platform_data/emif_plat.h>
  17 #include <linux/io.h>
  18 #include <linux/device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/slab.h>
  22 #include <linux/of.h>
  23 #include <linux/debugfs.h>
  24 #include <linux/seq_file.h>
  25 #include <linux/module.h>
  26 #include <linux/list.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pm.h>
  29
  30 #include "emif.h"
  31 #include "jedec_ddr.h"
  32 #include "of_memory.h"
  33
  34 /**
  35  * struct emif_data - Per device static data for driver's use
  36  * @duplicate:                  Whether the DDR devices attached to this EMIF
  37  *                              instance are exactly same as that on EMIF1. In
  38  *                              this case we can save some memory and processing
  39  * @temperature_level:          Maximum temperature of LPDDR2 devices attached
  40  *                              to this EMIF - read from MR4 register. If there
  41  *                              are two devices attached to this EMIF, this
  42  *                              value is the maximum of the two temperature
  43  *                              levels.
  44  * @node:                       node in the device list
  45  * @base:                       base address of memory-mapped IO registers.
  46  * @dev:                        device pointer.
  47  * @addressing                  table with addressing information from the spec
  48  * @regs_cache:                 An array of 'struct emif_regs' that stores
  49  *                              calculated register values for different
  50  *                              frequencies, to avoid re-calculating them on
  51  *                              each DVFS transition.
  52  * @curr_regs:                  The set of register values used in the last
  53  *                              frequency change (i.e. corresponding to the
  54  *                              frequency in effect at the moment)
  55  * @plat_data:                  Pointer to saved platform data.
  56  * @debugfs_root:               dentry to the root folder for EMIF in debugfs
  57  * @np_ddr:                     Pointer to ddr device tree node
  58  */
  59 struct emif_data {
  60         u8                              duplicate;
  61         u8                              temperature_level;
  62         u8                              lpmode;
  63         struct list_head                node;
  64         unsigned long                   irq_state;
  65         void __iomem                    *base;
  66         struct device                   *dev;
  67         const struct lpddr2_addressing  *addressing;
  68         struct emif_regs                *regs_cache[EMIF_MAX_NUM_FREQUENCIES];
  69         struct emif_regs                *curr_regs;
  70         struct emif_platform_data       *plat_data;
  71         struct dentry                   *debugfs_root;
  72         struct device_node              *np_ddr;
  73 };
  74
  75 static struct emif_data *emif1;
  76 static spinlock_t       emif_lock;
  77 static unsigned long    irq_state;
  78 static u32              t_ck; /* DDR clock period in ps */
  79 static LIST_HEAD(device_list);
  80
  81 #ifdef CONFIG_DEBUG_FS
  82 static void do_emif_regdump_show(struct seq_file *s, struct emif_data *emif,
  83         struct emif_regs *regs)
  84 {
  85         u32 type = emif->plat_data->device_info->type;
  86         u32 ip_rev = emif->plat_data->ip_rev;
  87
  88         seq_printf(s, "EMIF register cache dump for %dMHz\n",
  89                 regs->freq/1000000);
  90
  91         seq_printf(s, "ref_ctrl_shdw\t: 0x%08x\n", regs->ref_ctrl_shdw);
  92         seq_printf(s, "sdram_tim1_shdw\t: 0x%08x\n", regs->sdram_tim1_shdw);
  93         seq_printf(s, "sdram_tim2_shdw\t: 0x%08x\n", regs->sdram_tim2_shdw);
  94         seq_printf(s, "sdram_tim3_shdw\t: 0x%08x\n", regs->sdram_tim3_shdw);
  95
  96         if (ip_rev == EMIF_4D) {
  97                 seq_printf(s, "read_idle_ctrl_shdw_normal\t: 0x%08x\n",
  98                         regs->read_idle_ctrl_shdw_normal);
  99                 seq_printf(s, "read_idle_ctrl_shdw_volt_ramp\t: 0x%08x\n",
 100                         regs->read_idle_ctrl_shdw_volt_ramp);
 101         } else if (ip_rev == EMIF_4D5) {
 102                 seq_printf(s, "dll_calib_ctrl_shdw_normal\t: 0x%08x\n",
 103                         regs->dll_calib_ctrl_shdw_normal);
 104                 seq_printf(s, "dll_calib_ctrl_shdw_volt_ramp\t: 0x%08x\n",
 105                         regs->dll_calib_ctrl_shdw_volt_ramp);
 106         }
 107
 108         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
 109                 seq_printf(s, "ref_ctrl_shdw_derated\t: 0x%08x\n",
 110                         regs->ref_ctrl_shdw_derated);
 111                 seq_printf(s, "sdram_tim1_shdw_derated\t: 0x%08x\n",
 112                         regs->sdram_tim1_shdw_derated);
 113                 seq_printf(s, "sdram_tim3_shdw_derated\t: 0x%08x\n",
 114                         regs->sdram_tim3_shdw_derated);
 115         }
 116 }
 117
 118 static int emif_regdump_show(struct seq_file *s, void *unused)
 119 {
 120         struct emif_data        *emif   = s->private;
 121         struct emif_regs        **regs_cache;
 122         int                     i;
 123
 124         if (emif->duplicate)
 125                 regs_cache = emif1->regs_cache;
 126         else
 127                 regs_cache = emif->regs_cache;
 128
 129         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
 130                 do_emif_regdump_show(s, emif, regs_cache[i]);
 131                 seq_putc(s, '\n');
 132         }
 133
 134         return 0;
 135 }
 136
 137 static int emif_regdump_open(struct inode *inode, struct file *file)
 138 {
 139         return single_open(file, emif_regdump_show, inode->i_private);
 140 }
 141
 142 static const struct file_operations emif_regdump_fops = {
 143         .open                   = emif_regdump_open,
 144         .read                   = seq_read,
 145         .release                = single_release,
 146 };
 147
 148 static int emif_mr4_show(struct seq_file *s, void *unused)
 149 {
 150         struct emif_data *emif = s->private;
 151
 152         seq_printf(s, "MR4=%d\n", emif->temperature_level);
 153         return 0;
 154 }
 155
 156 static int emif_mr4_open(struct inode *inode, struct file *file)
 157 {
 158         return single_open(file, emif_mr4_show, inode->i_private);
 159 }
 160
 161 static const struct file_operations emif_mr4_fops = {
 162         .open                   = emif_mr4_open,
 163         .read                   = seq_read,
 164         .release                = single_release,
 165 };
 166
 167 static int __init_or_module emif_debugfs_init(struct emif_data *emif)
 168 {
 169         struct dentry   *dentry;
 170         int             ret;
 171
 172         dentry = debugfs_create_dir(dev_name(emif->dev), NULL);
 173         if (!dentry) {
 174                 ret = -ENOMEM;
 175                 goto err0;
 176         }
 177         emif->debugfs_root = dentry;
 178
 179         dentry = debugfs_create_file("regcache_dump", S_IRUGO,
 180                         emif->debugfs_root, emif, &emif_regdump_fops);
 181         if (!dentry) {
 182                 ret = -ENOMEM;
 183                 goto err1;
 184         }
 185
 186         dentry = debugfs_create_file("mr4", S_IRUGO,
 187                         emif->debugfs_root, emif, &emif_mr4_fops);
 188         if (!dentry) {
 189                 ret = -ENOMEM;
 190                 goto err1;
 191         }
 192
 193         return 0;
 194 err1:
 195         debugfs_remove_recursive(emif->debugfs_root);
 196 err0:
 197         return ret;
 198 }
 199
 200 static void __exit emif_debugfs_exit(struct emif_data *emif)
 201 {
 202         debugfs_remove_recursive(emif->debugfs_root);
 203         emif->debugfs_root = NULL;
 204 }
 205 #else
 206 static inline int __init_or_module emif_debugfs_init(struct emif_data *emif)
 207 {
 208         return 0;
 209 }
 210
 211 static inline void __exit emif_debugfs_exit(struct emif_data *emif)
 212 {
 213 }
 214 #endif
 215
 216 /*
 217  * Calculate the period of DDR clock from frequency value
 218  */
 219 static void set_ddr_clk_period(u32 freq)
 220 {
 221         /* Divide 10^12 by frequency to get period in ps */
 222         t_ck = (u32)DIV_ROUND_UP_ULL(1000000000000ull, freq);
 223 }
 224
 225 /*
 226  * Get bus width used by EMIF. Note that this may be different from the
 227  * bus width of the DDR devices used. For instance two 16-bit DDR devices
 228  * may be connected to a given CS of EMIF. In this case bus width as far
 229  * as EMIF is concerned is 32, where as the DDR bus width is 16 bits.
 230  */
 231 static u32 get_emif_bus_width(struct emif_data *emif)
 232 {
 233         u32             width;
 234         void __iomem    *base = emif->base;
 235
 236         width = (readl(base + EMIF_SDRAM_CONFIG) & NARROW_MODE_MASK)
 237                         >> NARROW_MODE_SHIFT;
 238         width = width == 0 ? 32 : 16;
 239
 240         return width;
 241 }
 242
 243 /*
 244  * Get the CL from SDRAM_CONFIG register
 245  */
 246 static u32 get_cl(struct emif_data *emif)
 247 {
 248         u32             cl;
 249         void __iomem    *base = emif->base;
 250
 251         cl = (readl(base + EMIF_SDRAM_CONFIG) & CL_MASK) >> CL_SHIFT;
 252
 253         return cl;
 254 }
 255
 256 static void set_lpmode(struct emif_data *emif, u8 lpmode)
 257 {
 258         u32 temp;
 259         void __iomem *base = emif->base;
 260
 261         /*
 262          * Workaround for errata i743 - LPDDR2 Power-Down State is Not
 263          * Efficient
 264          *
 265          * i743 DESCRIPTION:
 266          * The EMIF supports power-down state for low power. The EMIF
 267          * automatically puts the SDRAM into power-down after the memory is
 268          * not accessed for a defined number of cycles and the
 269          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4.
 270          * As the EMIF supports automatic output impedance calibration, a ZQ
 271          * calibration long command is issued every time it exits active
 272          * power-down and precharge power-down modes. The EMIF waits and
 273          * blocks any other command during this calibration.
 274          * The EMIF does not allow selective disabling of ZQ calibration upon
 275          * exit of power-down mode. Due to very short periods of power-down
 276          * cycles, ZQ calibration overhead creates bandwidth issues and
 277          * increases overall system power consumption. On the other hand,
 278          * issuing ZQ calibration long commands when exiting self-refresh is
 279          * still required.
 280          *
 281          * WORKAROUND
 282          * Because there is no power consumption benefit of the power-down due
 283          * to the calibration and there is a performance risk, the guideline
 284          * is to not allow power-down state and, therefore, to not have set
 285          * the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4.
 286          */
 287         if ((emif->plat_data->ip_rev == EMIF_4D) &&
 288             (EMIF_LP_MODE_PWR_DN == lpmode)) {
 289                 WARN_ONCE(1,
 290                           "REG_LP_MODE = LP_MODE_PWR_DN(4) is prohibited by"
 291                           "erratum i743 switch to LP_MODE_SELF_REFRESH(2)\n");
 292                 /* rollback LP_MODE to Self-refresh mode */
 293                 lpmode = EMIF_LP_MODE_SELF_REFRESH;
 294         }
 295
 296         temp = readl(base + EMIF_POWER_MANAGEMENT_CONTROL);
 297         temp &= ~LP_MODE_MASK;
 298         temp |= (lpmode << LP_MODE_SHIFT);
 299         writel(temp, base + EMIF_POWER_MANAGEMENT_CONTROL);
 300 }
 301
 302 static void do_freq_update(void)
 303 {
 304         struct emif_data *emif;
 305
 306         /*
 307          * Workaround for errata i728: Disable LPMODE during FREQ_UPDATE
 308          *
 309          * i728 DESCRIPTION:
 310          * The EMIF automatically puts the SDRAM into self-refresh mode
 311          * after the EMIF has not performed accesses during
 312          * EMIF_PWR_MGMT_CTRL[7:4] REG_SR_TIM number of DDR clock cycles
 313          * and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set
 314          * to 0x2. If during a small window the following three events
 315          * occur:
 316          * - The SR_TIMING counter expires
 317          * - And frequency change is requested
 318          * - And OCP access is requested
 319          * Then it causes instable clock on the DDR interface.
 320          *
 321          * WORKAROUND
 322          * To avoid the occurrence of the three events, the workaround
 323          * is to disable the self-refresh when requesting a frequency
 324          * change. Before requesting a frequency change the software must
 325          * program EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x0. When the
 326          * frequency change has been done, the software can reprogram
 327          * EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE to 0x2
 328          */
 329         list_for_each_entry(emif, &device_list, node) {
 330                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 331                         set_lpmode(emif, EMIF_LP_MODE_DISABLE);
 332         }
 333
 334         /*
 335          * TODO: Do FREQ_UPDATE here when an API
 336          * is available for this as part of the new
 337          * clock framework
 338          */
 339
 340         list_for_each_entry(emif, &device_list, node) {
 341                 if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
 342                         set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
 343         }
 344 }
 345
 346 /* Find addressing table entry based on the device's type and density */
 347 static const struct lpddr2_addressing *get_addressing_table(
 348         const struct ddr_device_info *device_info)
 349 {
 350         u32             index, type, density;
 351
 352         type = device_info->type;
 353         density = device_info->density;
 354
 355         switch (type) {
 356         case DDR_TYPE_LPDDR2_S4:
 357                 index = density - 1;
 358                 break;
 359         case DDR_TYPE_LPDDR2_S2:
 360                 switch (density) {
 361                 case DDR_DENSITY_1Gb:
 362                 case DDR_DENSITY_2Gb:
 363                         index = density + 3;
 364                         break;
 365                 default:
 366                         index = density - 1;
 367                 }
 368                 break;
 369         default:
 370                 return NULL;
 371         }
 372
 373         return &lpddr2_jedec_addressing_table[index];
 374 }
 375
 376 /*
 377  * Find the the right timing table from the array of timing
 378  * tables of the device using DDR clock frequency
 379  */
 380 static const struct lpddr2_timings *get_timings_table(struct emif_data *emif,
 381                 u32 freq)
 382 {
 383         u32                             i, min, max, freq_nearest;
 384         const struct lpddr2_timings     *timings = NULL;
 385         const struct lpddr2_timings     *timings_arr = emif->plat_data->timings;
 386         struct                          device *dev = emif->dev;
 387
 388         /* Start with a very high frequency - 1GHz */
 389         freq_nearest = 1000000000;
 390
 391         /*
 392          * Find the timings table such that:
 393          *  1. the frequency range covers the required frequency(safe) AND
 394          *  2. the max_freq is closest to the required frequency(optimal)
 395          */
 396         for (i = 0; i < emif->plat_data->timings_arr_size; i++) {
 397                 max = timings_arr[i].max_freq;
 398                 min = timings_arr[i].min_freq;
 399                 if ((freq >= min) && (freq <= max) && (max < freq_nearest)) {
 400                         freq_nearest = max;
 401                         timings = &timings_arr[i];
 402                 }
 403         }
 404
 405         if (!timings)
 406                 dev_err(dev, "%s: couldn't find timings for - %dHz\n",
 407                         __func__, freq);
 408
 409         dev_dbg(dev, "%s: timings table: freq %d, speed bin freq %d\n",
 410                 __func__, freq, freq_nearest);
 411
 412         return timings;
 413 }
 414
 415 static u32 get_sdram_ref_ctrl_shdw(u32 freq,
 416                 const struct lpddr2_addressing *addressing)
 417 {
 418         u32 ref_ctrl_shdw = 0, val = 0, freq_khz, t_refi;
 419
 420         /* Scale down frequency and t_refi to avoid overflow */
 421         freq_khz = freq / 1000;
 422         t_refi = addressing->tREFI_ns / 100;
 423
 424         /*
 425          * refresh rate to be set is 'tREFI(in us) * freq in MHz
 426          * division by 10000 to account for change in units
 427          */
 428         val = t_refi * freq_khz / 10000;
 429         ref_ctrl_shdw |= val << REFRESH_RATE_SHIFT;
 430
 431         return ref_ctrl_shdw;
 432 }
 433
 434 static u32 get_sdram_tim_1_shdw(const struct lpddr2_timings *timings,
 435                 const struct lpddr2_min_tck *min_tck,
 436                 const struct lpddr2_addressing *addressing)
 437 {
 438         u32 tim1 = 0, val = 0;
 439
 440         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 441         tim1 |= val << T_WTR_SHIFT;
 442
 443         if (addressing->num_banks == B8)
 444                 val = DIV_ROUND_UP(timings->tFAW, t_ck*4);
 445         else
 446                 val = max(min_tck->tRRD, DIV_ROUND_UP(timings->tRRD, t_ck));
 447         tim1 |= (val - 1) << T_RRD_SHIFT;
 448
 449         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab, t_ck) - 1;
 450         tim1 |= val << T_RC_SHIFT;
 451
 452         val = max(min_tck->tRASmin, DIV_ROUND_UP(timings->tRAS_min, t_ck));
 453         tim1 |= (val - 1) << T_RAS_SHIFT;
 454
 455         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 456         tim1 |= val << T_WR_SHIFT;
 457
 458         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD, t_ck)) - 1;
 459         tim1 |= val << T_RCD_SHIFT;
 460
 461         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab, t_ck)) - 1;
 462         tim1 |= val << T_RP_SHIFT;
 463
 464         return tim1;
 465 }
 466
 467 static u32 get_sdram_tim_1_shdw_derated(const struct lpddr2_timings *timings,
 468                 const struct lpddr2_min_tck *min_tck,
 469                 const struct lpddr2_addressing *addressing)
 470 {
 471         u32 tim1 = 0, val = 0;
 472
 473         val = max(min_tck->tWTR, DIV_ROUND_UP(timings->tWTR, t_ck)) - 1;
 474         tim1 = val << T_WTR_SHIFT;
 475
 476         /*
 477          * tFAW is approximately 4 times tRRD. So add 1875*4 = 7500ps
 478          * to tFAW for de-rating
 479          */
 480         if (addressing->num_banks == B8) {
 481                 val = DIV_ROUND_UP(timings->tFAW + 7500, 4 * t_ck) - 1;
 482         } else {
 483                 val = DIV_ROUND_UP(timings->tRRD + 1875, t_ck);
 484                 val = max(min_tck->tRRD, val) - 1;
 485         }
 486         tim1 |= val << T_RRD_SHIFT;
 487
 488         val = DIV_ROUND_UP(timings->tRAS_min + timings->tRPab + 1875, t_ck);
 489         tim1 |= (val - 1) << T_RC_SHIFT;
 490
 491         val = DIV_ROUND_UP(timings->tRAS_min + 1875, t_ck);
 492         val = max(min_tck->tRASmin, val) - 1;
 493         tim1 |= val << T_RAS_SHIFT;
 494
 495         val = max(min_tck->tWR, DIV_ROUND_UP(timings->tWR, t_ck)) - 1;
 496         tim1 |= val << T_WR_SHIFT;
 497
 498         val = max(min_tck->tRCD, DIV_ROUND_UP(timings->tRCD + 1875, t_ck));
 499         tim1 |= (val - 1) << T_RCD_SHIFT;
 500
 501         val = max(min_tck->tRPab, DIV_ROUND_UP(timings->tRPab + 1875, t_ck));
 502         tim1 |= (val - 1) << T_RP_SHIFT;
 503
 504         return tim1;
 505 }
 506
 507 static u32 get_sdram_tim_2_shdw(const struct lpddr2_timings *timings,
 508                 const struct lpddr2_min_tck *min_tck,
 509                 const struct lpddr2_addressing *addressing,
 510                 u32 type)
 511 {
 512         u32 tim2 = 0, val = 0;
 513
 514         val = min_tck->tCKE - 1;
 515         tim2 |= val << T_CKE_SHIFT;
 516
 517         val = max(min_tck->tRTP, DIV_ROUND_UP(timings->tRTP, t_ck)) - 1;
 518         tim2 |= val << T_RTP_SHIFT;
 519
 520         /* tXSNR = tRFCab_ps + 10 ns(tRFCab_ps for LPDDR2). */
 521         val = DIV_ROUND_UP(addressing->tRFCab_ps + 10000, t_ck) - 1;
 522         tim2 |= val << T_XSNR_SHIFT;
 523
 524         /* XSRD same as XSNR for LPDDR2 */
 525         tim2 |= val << T_XSRD_SHIFT;
 526
 527         val = max(min_tck->tXP, DIV_ROUND_UP(timings->tXP, t_ck)) - 1;
 528         tim2 |= val << T_XP_SHIFT;
 529
 530         return tim2;
 531 }
 532
 533 static u32 get_sdram_tim_3_shdw(const struct lpddr2_timings *timings,
 534                 const struct lpddr2_min_tck *min_tck,
 535                 const struct lpddr2_addressing *addressing,
 536                 u32 type, u32 ip_rev, u32 derated)
 537 {
 538         u32 tim3 = 0, val = 0, t_dqsck;
 539
 540         val = timings->tRAS_max_ns / addressing->tREFI_ns - 1;
 541         val = val > 0xF ? 0xF : val;
 542         tim3 |= val << T_RAS_MAX_SHIFT;
 543
 544         val = DIV_ROUND_UP(addressing->tRFCab_ps, t_ck) - 1;
 545         tim3 |= val << T_RFC_SHIFT;
 546
 547         t_dqsck = (derated == EMIF_DERATED_TIMINGS) ?
 548                 timings->tDQSCK_max_derated : timings->tDQSCK_max;
 549         if (ip_rev == EMIF_4D5)
 550                 val = DIV_ROUND_UP(t_dqsck + 1000, t_ck) - 1;
 551         else
 552                 val = DIV_ROUND_UP(t_dqsck, t_ck) - 1;
 553
 554         tim3 |= val << T_TDQSCKMAX_SHIFT;
 555
 556         val = DIV_ROUND_UP(timings->tZQCS, t_ck) - 1;
 557         tim3 |= val << ZQ_ZQCS_SHIFT;
 558
 559         val = DIV_ROUND_UP(timings->tCKESR, t_ck);
 560         val = max(min_tck->tCKESR, val) - 1;
 561         tim3 |= val << T_CKESR_SHIFT;
 562
 563         if (ip_rev == EMIF_4D5) {
 564                 tim3 |= (EMIF_T_CSTA - 1) << T_CSTA_SHIFT;
 565
 566                 val = DIV_ROUND_UP(EMIF_T_PDLL_UL, 128) - 1;
 567                 tim3 |= val << T_PDLL_UL_SHIFT;
 568         }
 569
 570         return tim3;
 571 }
 572
 573 static u32 get_zq_config_reg(const struct lpddr2_addressing *addressing,
 574                 bool cs1_used, bool cal_resistors_per_cs)
 575 {
 576         u32 zq = 0, val = 0;
 577
 578         val = EMIF_ZQCS_INTERVAL_US * 1000 / addressing->tREFI_ns;
 579         zq |= val << ZQ_REFINTERVAL_SHIFT;
 580
 581         val = DIV_ROUND_UP(T_ZQCL_DEFAULT_NS, T_ZQCS_DEFAULT_NS) - 1;
 582         zq |= val << ZQ_ZQCL_MULT_SHIFT;
 583
 584         val = DIV_ROUND_UP(T_ZQINIT_DEFAULT_NS, T_ZQCL_DEFAULT_NS) - 1;
 585         zq |= val << ZQ_ZQINIT_MULT_SHIFT;
 586
 587         zq |= ZQ_SFEXITEN_ENABLE << ZQ_SFEXITEN_SHIFT;
 588
 589         if (cal_resistors_per_cs)
 590                 zq |= ZQ_DUALCALEN_ENABLE << ZQ_DUALCALEN_SHIFT;
 591         else
 592                 zq |= ZQ_DUALCALEN_DISABLE << ZQ_DUALCALEN_SHIFT;
 593
 594         zq |= ZQ_CS0EN_MASK; /* CS0 is used for sure */
 595
 596         val = cs1_used ? 1 : 0;
 597         zq |= val << ZQ_CS1EN_SHIFT;
 598
 599         return zq;
 600 }
 601
 602 static u32 get_temp_alert_config(const struct lpddr2_addressing *addressing,
 603                 const struct emif_custom_configs *custom_configs, bool cs1_used,
 604                 u32 sdram_io_width, u32 emif_bus_width)
 605 {
 606         u32 alert = 0, interval, devcnt;
 607
 608         if (custom_configs && (custom_configs->mask &
 609                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL))
 610                 interval = custom_configs->temp_alert_poll_interval_ms;
 611         else
 612                 interval = TEMP_ALERT_POLL_INTERVAL_DEFAULT_MS;
 613
 614         interval *= 1000000;                    /* Convert to ns */
 615         interval /= addressing->tREFI_ns;       /* Convert to refresh cycles */
 616         alert |= (interval << TA_REFINTERVAL_SHIFT);
 617
 618         /*
 619          * sdram_io_width is in 'log2(x) - 1' form. Convert emif_bus_width
 620          * also to this form and subtract to get TA_DEVCNT, which is
 621          * in log2(x) form.
 622          */
 623         emif_bus_width = __fls(emif_bus_width) - 1;
 624         devcnt = emif_bus_width - sdram_io_width;
 625         alert |= devcnt << TA_DEVCNT_SHIFT;
 626
 627         /* DEVWDT is in 'log2(x) - 3' form */
 628         alert |= (sdram_io_width - 2) << TA_DEVWDT_SHIFT;
 629
 630         alert |= 1 << TA_SFEXITEN_SHIFT;
 631         alert |= 1 << TA_CS0EN_SHIFT;
 632         alert |= (cs1_used ? 1 : 0) << TA_CS1EN_SHIFT;
 633
 634         return alert;
 635 }
 636
 637 static u32 get_read_idle_ctrl_shdw(u8 volt_ramp)
 638 {
 639         u32 idle = 0, val = 0;
 640
 641         /*
 642          * Maximum value in normal conditions and increased frequency
 643          * when voltage is ramping
 644          */
 645         if (volt_ramp)
 646                 val = READ_IDLE_INTERVAL_DVFS / t_ck / 64 - 1;
 647         else
 648                 val = 0x1FF;
 649
 650         /*
 651          * READ_IDLE_CTRL register in EMIF4D has same offset and fields
 652          * as DLL_CALIB_CTRL in EMIF4D5, so use the same shifts
 653          */
 654         idle |= val << DLL_CALIB_INTERVAL_SHIFT;
 655         idle |= EMIF_READ_IDLE_LEN_VAL << ACK_WAIT_SHIFT;
 656
 657         return idle;
 658 }
 659
 660 static u32 get_dll_calib_ctrl_shdw(u8 volt_ramp)
 661 {
 662         u32 calib = 0, val = 0;
 663
 664         if (volt_ramp == DDR_VOLTAGE_RAMPING)
 665                 val = DLL_CALIB_INTERVAL_DVFS / t_ck / 16 - 1;
 666         else
 667                 val = 0; /* Disabled when voltage is stable */
 668
 669         calib |= val << DLL_CALIB_INTERVAL_SHIFT;
 670         calib |= DLL_CALIB_ACK_WAIT_VAL << ACK_WAIT_SHIFT;
 671
 672         return calib;
 673 }
 674
 675 static u32 get_ddr_phy_ctrl_1_attilaphy_4d(const struct lpddr2_timings *timings,
 676         u32 freq, u8 RL)
 677 {
 678         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_ATTILAPHY, val = 0;
 679
 680         val = RL + DIV_ROUND_UP(timings->tDQSCK_max, t_ck) - 1;
 681         phy |= val << READ_LATENCY_SHIFT_4D;
 682
 683         if (freq <= 100000000)
 684                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS_ATTILAPHY;
 685         else if (freq <= 200000000)
 686                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ_ATTILAPHY;
 687         else
 688                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ_ATTILAPHY;
 689
 690         phy |= val << DLL_SLAVE_DLY_CTRL_SHIFT_4D;
 691
 692         return phy;
 693 }
 694
 695 static u32 get_phy_ctrl_1_intelliphy_4d5(u32 freq, u8 cl)
 696 {
 697         u32 phy = EMIF_DDR_PHY_CTRL_1_BASE_VAL_INTELLIPHY, half_delay;
 698
 699         /*
 700          * DLL operates at 266 MHz. If DDR frequency is near 266 MHz,
 701          * half-delay is not needed else set half-delay
 702          */
 703         if (freq >= 265000000 && freq < 267000000)
 704                 half_delay = 0;
 705         else
 706                 half_delay = 1;
 707
 708         phy |= half_delay << DLL_HALF_DELAY_SHIFT_4D5;
 709         phy |= ((cl + DIV_ROUND_UP(EMIF_PHY_TOTAL_READ_LATENCY_INTELLIPHY_PS,
 710                         t_ck) - 1) << READ_LATENCY_SHIFT_4D5);
 711
 712         return phy;
 713 }
 714
 715 static u32 get_ext_phy_ctrl_2_intelliphy_4d5(void)
 716 {
 717         u32 fifo_we_slave_ratio;
 718
 719         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 720                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 721
 722         return fifo_we_slave_ratio | fifo_we_slave_ratio << 11 |
 723                 fifo_we_slave_ratio << 22;
 724 }
 725
 726 static u32 get_ext_phy_ctrl_3_intelliphy_4d5(void)
 727 {
 728         u32 fifo_we_slave_ratio;
 729
 730         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 731                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 732
 733         return fifo_we_slave_ratio >> 10 | fifo_we_slave_ratio << 1 |
 734                 fifo_we_slave_ratio << 12 | fifo_we_slave_ratio << 23;
 735 }
 736
 737 static u32 get_ext_phy_ctrl_4_intelliphy_4d5(void)
 738 {
 739         u32 fifo_we_slave_ratio;
 740
 741         fifo_we_slave_ratio =  DIV_ROUND_CLOSEST(
 742                 EMIF_INTELLI_PHY_DQS_GATE_OPENING_DELAY_PS * 256 , t_ck);
 743
 744         return fifo_we_slave_ratio >> 9 | fifo_we_slave_ratio << 2 |
 745                 fifo_we_slave_ratio << 13;
 746 }
 747
 748 static u32 get_pwr_mgmt_ctrl(u32 freq, struct emif_data *emif, u32 ip_rev)
 749 {
 750         u32 pwr_mgmt_ctrl       = 0, timeout;
 751         u32 lpmode              = EMIF_LP_MODE_SELF_REFRESH;
 752         u32 timeout_perf        = EMIF_LP_MODE_TIMEOUT_PERFORMANCE;
 753         u32 timeout_pwr         = EMIF_LP_MODE_TIMEOUT_POWER;
 754         u32 freq_threshold      = EMIF_LP_MODE_FREQ_THRESHOLD;
 755         u32 mask;
 756         u8 shift;
 757
 758         struct emif_custom_configs *cust_cfgs = emif->plat_data->custom_configs;
 759
 760         if (cust_cfgs && (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE)) {
 761                 lpmode          = cust_cfgs->lpmode;
 762                 timeout_perf    = cust_cfgs->lpmode_timeout_performance;
 763                 timeout_pwr     = cust_cfgs->lpmode_timeout_power;
 764                 freq_threshold  = cust_cfgs->lpmode_freq_threshold;
 765         }
 766
 767         /* Timeout based on DDR frequency */
 768         timeout = freq >= freq_threshold ? timeout_perf : timeout_pwr;
 769
 770         /*
 771          * The value to be set in register is "log2(timeout) - 3"
 772          * if timeout < 16 load 0 in register
 773          * if timeout is not a power of 2, round to next highest power of 2
 774          */
 775         if (timeout < 16) {
 776                 timeout = 0;
 777         } else {
 778                 if (timeout & (timeout - 1))
 779                         timeout <<= 1;
 780                 timeout = __fls(timeout) - 3;
 781         }
 782
 783         switch (lpmode) {
 784         case EMIF_LP_MODE_CLOCK_STOP:
 785                 shift = CS_TIM_SHIFT;
 786                 mask = CS_TIM_MASK;
 787                 break;
 788         case EMIF_LP_MODE_SELF_REFRESH:
 789                 /* Workaround for errata i735 */
 790                 if (timeout < 6)
 791                         timeout = 6;
 792
 793                 shift = SR_TIM_SHIFT;
 794                 mask = SR_TIM_MASK;
 795                 break;
 796         case EMIF_LP_MODE_PWR_DN:
 797                 shift = PD_TIM_SHIFT;
 798                 mask = PD_TIM_MASK;
 799                 break;
 800         case EMIF_LP_MODE_DISABLE:
 801         default:
 802                 mask = 0;
 803                 shift = 0;
 804                 break;
 805         }
 806         /* Round to maximum in case of overflow, BUT warn! */
 807         if (lpmode != EMIF_LP_MODE_DISABLE && timeout > mask >> shift) {
 808                 pr_err("TIMEOUT Overflow - lpmode=%d perf=%d pwr=%d freq=%d\n",
 809                        lpmode,
 810                        timeout_perf,
 811                        timeout_pwr,
 812                        freq_threshold);
 813                 WARN(1, "timeout=0x%02x greater than 0x%02x. Using max\n",
 814                      timeout, mask >> shift);
 815                 timeout = mask >> shift;
 816         }
 817
 818         /* Setup required timing */
 819         pwr_mgmt_ctrl = (timeout << shift) & mask;
 820         /* setup a default mask for rest of the modes */
 821         pwr_mgmt_ctrl |= (SR_TIM_MASK | CS_TIM_MASK | PD_TIM_MASK) &
 822                           ~mask;
 823
 824         /* No CS_TIM in EMIF_4D5 */
 825         if (ip_rev == EMIF_4D5)
 826                 pwr_mgmt_ctrl &= ~CS_TIM_MASK;
 827
 828         pwr_mgmt_ctrl |= lpmode << LP_MODE_SHIFT;
 829
 830         return pwr_mgmt_ctrl;
 831 }
 832
 833 /*
 834  * Get the temperature level of the EMIF instance:
 835  * Reads the MR4 register of attached SDRAM parts to find out the temperature
 836  * level. If there are two parts attached(one on each CS), then the temperature
 837  * level for the EMIF instance is the higher of the two temperatures.
 838  */
 839 static void get_temperature_level(struct emif_data *emif)
 840 {
 841         u32             temp, temperature_level;
 842         void __iomem    *base;
 843
 844         base = emif->base;
 845
 846         /* Read mode register 4 */
 847         writel(DDR_MR4, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 848         temperature_level = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 849         temperature_level = (temperature_level & MR4_SDRAM_REF_RATE_MASK) >>
 850                                 MR4_SDRAM_REF_RATE_SHIFT;
 851
 852         if (emif->plat_data->device_info->cs1_used) {
 853                 writel(DDR_MR4 | CS_MASK, base + EMIF_LPDDR2_MODE_REG_CONFIG);
 854                 temp = readl(base + EMIF_LPDDR2_MODE_REG_DATA);
 855                 temp = (temp & MR4_SDRAM_REF_RATE_MASK)
 856                                 >> MR4_SDRAM_REF_RATE_SHIFT;
 857                 temperature_level = max(temp, temperature_level);
 858         }
 859
 860         /* treat everything less than nominal(3) in MR4 as nominal */
 861         if (unlikely(temperature_level < SDRAM_TEMP_NOMINAL))
 862                 temperature_level = SDRAM_TEMP_NOMINAL;
 863
 864         /* if we get reserved value in MR4 persist with the existing value */
 865         if (likely(temperature_level != SDRAM_TEMP_RESERVED_4))
 866                 emif->temperature_level = temperature_level;
 867 }
 868
 869 /*
 870  * Program EMIF shadow registers that are not dependent on temperature
 871  * or voltage
 872  */
 873 static void setup_registers(struct emif_data *emif, struct emif_regs *regs)
 874 {
 875         void __iomem    *base = emif->base;
 876
 877         writel(regs->sdram_tim2_shdw, base + EMIF_SDRAM_TIMING_2_SHDW);
 878         writel(regs->phy_ctrl_1_shdw, base + EMIF_DDR_PHY_CTRL_1_SHDW);
 879         writel(regs->pwr_mgmt_ctrl_shdw,
 880                base + EMIF_POWER_MANAGEMENT_CTRL_SHDW);
 881
 882         /* Settings specific for EMIF4D5 */
 883         if (emif->plat_data->ip_rev != EMIF_4D5)
 884                 return;
 885         writel(regs->ext_phy_ctrl_2_shdw, base + EMIF_EXT_PHY_CTRL_2_SHDW);
 886         writel(regs->ext_phy_ctrl_3_shdw, base + EMIF_EXT_PHY_CTRL_3_SHDW);
 887         writel(regs->ext_phy_ctrl_4_shdw, base + EMIF_EXT_PHY_CTRL_4_SHDW);
 888 }
 889
 890 /*
 891  * When voltage ramps dll calibration and forced read idle should
 892  * happen more often
 893  */
 894 static void setup_volt_sensitive_regs(struct emif_data *emif,
 895                 struct emif_regs *regs, u32 volt_state)
 896 {
 897         u32             calib_ctrl;
 898         void __iomem    *base = emif->base;
 899
 900         /*
 901          * EMIF_READ_IDLE_CTRL in EMIF4D refers to the same register as
 902          * EMIF_DLL_CALIB_CTRL in EMIF4D5 and dll_calib_ctrl_shadow_*
 903          * is an alias of the respective read_idle_ctrl_shdw_* (members of
 904          * a union). So, the below code takes care of both cases
 905          */
 906         if (volt_state == DDR_VOLTAGE_RAMPING)
 907                 calib_ctrl = regs->dll_calib_ctrl_shdw_volt_ramp;
 908         else
 909                 calib_ctrl = regs->dll_calib_ctrl_shdw_normal;
 910
 911         writel(calib_ctrl, base + EMIF_DLL_CALIB_CTRL_SHDW);
 912 }
 913
 914 /*
 915  * setup_temperature_sensitive_regs() - set the timings for temperature
 916  * sensitive registers. This happens once at initialisation time based
 917  * on the temperature at boot time and subsequently based on the temperature
 918  * alert interrupt. Temperature alert can happen when the temperature
 919  * increases or drops. So this function can have the effect of either
 920  * derating the timings or going back to nominal values.
 921  */
 922 static void setup_temperature_sensitive_regs(struct emif_data *emif,
 923                 struct emif_regs *regs)
 924 {
 925         u32             tim1, tim3, ref_ctrl, type;
 926         void __iomem    *base = emif->base;
 927         u32             temperature;
 928
 929         type = emif->plat_data->device_info->type;
 930
 931         tim1 = regs->sdram_tim1_shdw;
 932         tim3 = regs->sdram_tim3_shdw;
 933         ref_ctrl = regs->ref_ctrl_shdw;
 934
 935         /* No de-rating for non-lpddr2 devices */
 936         if (type != DDR_TYPE_LPDDR2_S2 && type != DDR_TYPE_LPDDR2_S4)
 937                 goto out;
 938
 939         temperature = emif->temperature_level;
 940         if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 941                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 942         } else if (temperature == SDRAM_TEMP_HIGH_DERATE_REFRESH_AND_TIMINGS) {
 943                 tim1 = regs->sdram_tim1_shdw_derated;
 944                 tim3 = regs->sdram_tim3_shdw_derated;
 945                 ref_ctrl = regs->ref_ctrl_shdw_derated;
 946         }
 947
 948 out:
 949         writel(tim1, base + EMIF_SDRAM_TIMING_1_SHDW);
 950         writel(tim3, base + EMIF_SDRAM_TIMING_3_SHDW);
 951         writel(ref_ctrl, base + EMIF_SDRAM_REFRESH_CTRL_SHDW);
 952 }
 953
 954 static irqreturn_t handle_temp_alert(void __iomem *base, struct emif_data *emif)
 955 {
 956         u32             old_temp_level;
 957         irqreturn_t     ret = IRQ_HANDLED;
 958         struct emif_custom_configs *custom_configs;
 959
 960         spin_lock_irqsave(&emif_lock, irq_state);
 961         old_temp_level = emif->temperature_level;
 962         get_temperature_level(emif);
 963
 964         if (unlikely(emif->temperature_level == old_temp_level)) {
 965                 goto out;
 966         } else if (!emif->curr_regs) {
 967                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
 968                 goto out;
 969         }
 970
 971         custom_configs = emif->plat_data->custom_configs;
 972
 973         /*
 974          * IF we detect higher than "nominal rating" from DDR sensor
 975          * on an unsupported DDR part, shutdown system
 976          */
 977         if (custom_configs && !(custom_configs->mask &
 978                                 EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART)) {
 979                 if (emif->temperature_level >= SDRAM_TEMP_HIGH_DERATE_REFRESH) {
 980                         dev_err(emif->dev,
 981                                 "%s:NOT Extended temperature capable memory."
 982                                 "Converting MR4=0x%02x as shutdown event\n",
 983                                 __func__, emif->temperature_level);
 984                         /*
 985                          * Temperature far too high - do kernel_power_off()
 986                          * from thread context
 987                          */
 988                         emif->temperature_level = SDRAM_TEMP_VERY_HIGH_SHUTDOWN;
 989                         ret = IRQ_WAKE_THREAD;
 990                         goto out;
 991                 }
 992         }
 993
 994         if (emif->temperature_level < old_temp_level ||
 995                 emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
 996                 /*
 997                  * Temperature coming down - defer handling to thread OR
 998                  * Temperature far too high - do kernel_power_off() from
 999                  * thread context
1000                  */
1001                 ret = IRQ_WAKE_THREAD;
1002         } else {
1003                 /* Temperature is going up - handle immediately */
1004                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1005                 do_freq_update();
1006         }
1007
1008 out:
1009         spin_unlock_irqrestore(&emif_lock, irq_state);
1010         return ret;
1011 }
1012
1013 static irqreturn_t emif_interrupt_handler(int irq, void *dev_id)
1014 {
1015         u32                     interrupts;
1016         struct emif_data        *emif = dev_id;
1017         void __iomem            *base = emif->base;
1018         struct device           *dev = emif->dev;
1019         irqreturn_t             ret = IRQ_HANDLED;
1020
1021         /* Save the status and clear it */
1022         interrupts = readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1023         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1024
1025         /*
1026          * Handle temperature alert
1027          * Temperature alert should be same for all ports
1028          * So, it's enough to process it only for one of the ports
1029          */
1030         if (interrupts & TA_SYS_MASK)
1031                 ret = handle_temp_alert(base, emif);
1032
1033         if (interrupts & ERR_SYS_MASK)
1034                 dev_err(dev, "Access error from SYS port - %x\n", interrupts);
1035
1036         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1037                 /* Save the status and clear it */
1038                 interrupts = readl(base + EMIF_LL_OCP_INTERRUPT_STATUS);
1039                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_STATUS);
1040
1041                 if (interrupts & ERR_LL_MASK)
1042                         dev_err(dev, "Access error from LL port - %x\n",
1043                                 interrupts);
1044         }
1045
1046         return ret;
1047 }
1048
1049 static irqreturn_t emif_threaded_isr(int irq, void *dev_id)
1050 {
1051         struct emif_data        *emif = dev_id;
1052
1053         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN) {
1054                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1055
1056                 /* If we have Power OFF ability, use it, else try restarting */
1057                 if (pm_power_off) {
1058                         kernel_power_off();
1059                 } else {
1060                         WARN(1, "FIXME: NO pm_power_off!!! trying restart\n");
1061                         kernel_restart("SDRAM Over-temp Emergency restart");
1062                 }
1063                 return IRQ_HANDLED;
1064         }
1065
1066         spin_lock_irqsave(&emif_lock, irq_state);
1067
1068         if (emif->curr_regs) {
1069                 setup_temperature_sensitive_regs(emif, emif->curr_regs);
1070                 do_freq_update();
1071         } else {
1072                 dev_err(emif->dev, "temperature alert before registers are calculated, not de-rating timings\n");
1073         }
1074
1075         spin_unlock_irqrestore(&emif_lock, irq_state);
1076
1077         return IRQ_HANDLED;
1078 }
1079
1080 static void clear_all_interrupts(struct emif_data *emif)
1081 {
1082         void __iomem    *base = emif->base;
1083
1084         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS),
1085                 base + EMIF_SYSTEM_OCP_INTERRUPT_STATUS);
1086         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1087                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_STATUS),
1088                         base + EMIF_LL_OCP_INTERRUPT_STATUS);
1089 }
1090
1091 static void disable_and_clear_all_interrupts(struct emif_data *emif)
1092 {
1093         void __iomem            *base = emif->base;
1094
1095         /* Disable all interrupts */
1096         writel(readl(base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET),
1097                 base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_CLEAR);
1098         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE)
1099                 writel(readl(base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET),
1100                         base + EMIF_LL_OCP_INTERRUPT_ENABLE_CLEAR);
1101
1102         /* Clear all interrupts */
1103         clear_all_interrupts(emif);
1104 }
1105
1106 static int __init_or_module setup_interrupts(struct emif_data *emif, u32 irq)
1107 {
1108         u32             interrupts, type;
1109         void __iomem    *base = emif->base;
1110
1111         type = emif->plat_data->device_info->type;
1112
1113         clear_all_interrupts(emif);
1114
1115         /* Enable interrupts for SYS interface */
1116         interrupts = EN_ERR_SYS_MASK;
1117         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4)
1118                 interrupts |= EN_TA_SYS_MASK;
1119         writel(interrupts, base + EMIF_SYSTEM_OCP_INTERRUPT_ENABLE_SET);
1120
1121         /* Enable interrupts for LL interface */
1122         if (emif->plat_data->hw_caps & EMIF_HW_CAPS_LL_INTERFACE) {
1123                 /* TA need not be enabled for LL */
1124                 interrupts = EN_ERR_LL_MASK;
1125                 writel(interrupts, base + EMIF_LL_OCP_INTERRUPT_ENABLE_SET);
1126         }
1127
1128         /* setup IRQ handlers */
1129         return devm_request_threaded_irq(emif->dev, irq,
1130                                     emif_interrupt_handler,
1131                                     emif_threaded_isr,
1132                                     0, dev_name(emif->dev),
1133                                     emif);
1134
1135 }
1136
1137 static void __init_or_module emif_onetime_settings(struct emif_data *emif)
1138 {
1139         u32                             pwr_mgmt_ctrl, zq, temp_alert_cfg;
1140         void __iomem                    *base = emif->base;
1141         const struct lpddr2_addressing  *addressing;
1142         const struct ddr_device_info    *device_info;
1143
1144         device_info = emif->plat_data->device_info;
1145         addressing = get_addressing_table(device_info);
1146
1147         /*
1148          * Init power management settings
1149          * We don't know the frequency yet. Use a high frequency
1150          * value for a conservative timeout setting
1151          */
1152         pwr_mgmt_ctrl = get_pwr_mgmt_ctrl(1000000000, emif,
1153                         emif->plat_data->ip_rev);
1154         emif->lpmode = (pwr_mgmt_ctrl & LP_MODE_MASK) >> LP_MODE_SHIFT;
1155         writel(pwr_mgmt_ctrl, base + EMIF_POWER_MANAGEMENT_CONTROL);
1156
1157         /* Init ZQ calibration settings */
1158         zq = get_zq_config_reg(addressing, device_info->cs1_used,
1159                 device_info->cal_resistors_per_cs);
1160         writel(zq, base + EMIF_SDRAM_OUTPUT_IMPEDANCE_CALIBRATION_CONFIG);
1161
1162         /* Check temperature level temperature level*/
1163         get_temperature_level(emif);
1164         if (emif->temperature_level == SDRAM_TEMP_VERY_HIGH_SHUTDOWN)
1165                 dev_emerg(emif->dev, "SDRAM temperature exceeds operating limit.. Needs shut down!!!\n");
1166
1167         /* Init temperature polling */
1168         temp_alert_cfg = get_temp_alert_config(addressing,
1169                 emif->plat_data->custom_configs, device_info->cs1_used,
1170                 device_info->io_width, get_emif_bus_width(emif));
1171         writel(temp_alert_cfg, base + EMIF_TEMPERATURE_ALERT_CONFIG);
1172
1173         /*
1174          * Program external PHY control registers that are not frequency
1175          * dependent
1176          */
1177         if (emif->plat_data->phy_type != EMIF_PHY_TYPE_INTELLIPHY)
1178                 return;
1179         writel(EMIF_EXT_PHY_CTRL_1_VAL, base + EMIF_EXT_PHY_CTRL_1_SHDW);
1180         writel(EMIF_EXT_PHY_CTRL_5_VAL, base + EMIF_EXT_PHY_CTRL_5_SHDW);
1181         writel(EMIF_EXT_PHY_CTRL_6_VAL, base + EMIF_EXT_PHY_CTRL_6_SHDW);
1182         writel(EMIF_EXT_PHY_CTRL_7_VAL, base + EMIF_EXT_PHY_CTRL_7_SHDW);
1183         writel(EMIF_EXT_PHY_CTRL_8_VAL, base + EMIF_EXT_PHY_CTRL_8_SHDW);
1184         writel(EMIF_EXT_PHY_CTRL_9_VAL, base + EMIF_EXT_PHY_CTRL_9_SHDW);
1185         writel(EMIF_EXT_PHY_CTRL_10_VAL, base + EMIF_EXT_PHY_CTRL_10_SHDW);
1186         writel(EMIF_EXT_PHY_CTRL_11_VAL, base + EMIF_EXT_PHY_CTRL_11_SHDW);
1187         writel(EMIF_EXT_PHY_CTRL_12_VAL, base + EMIF_EXT_PHY_CTRL_12_SHDW);
1188         writel(EMIF_EXT_PHY_CTRL_13_VAL, base + EMIF_EXT_PHY_CTRL_13_SHDW);
1189         writel(EMIF_EXT_PHY_CTRL_14_VAL, base + EMIF_EXT_PHY_CTRL_14_SHDW);
1190         writel(EMIF_EXT_PHY_CTRL_15_VAL, base + EMIF_EXT_PHY_CTRL_15_SHDW);
1191         writel(EMIF_EXT_PHY_CTRL_16_VAL, base + EMIF_EXT_PHY_CTRL_16_SHDW);
1192         writel(EMIF_EXT_PHY_CTRL_17_VAL, base + EMIF_EXT_PHY_CTRL_17_SHDW);
1193         writel(EMIF_EXT_PHY_CTRL_18_VAL, base + EMIF_EXT_PHY_CTRL_18_SHDW);
1194         writel(EMIF_EXT_PHY_CTRL_19_VAL, base + EMIF_EXT_PHY_CTRL_19_SHDW);
1195         writel(EMIF_EXT_PHY_CTRL_20_VAL, base + EMIF_EXT_PHY_CTRL_20_SHDW);
1196         writel(EMIF_EXT_PHY_CTRL_21_VAL, base + EMIF_EXT_PHY_CTRL_21_SHDW);
1197         writel(EMIF_EXT_PHY_CTRL_22_VAL, base + EMIF_EXT_PHY_CTRL_22_SHDW);
1198         writel(EMIF_EXT_PHY_CTRL_23_VAL, base + EMIF_EXT_PHY_CTRL_23_SHDW);
1199         writel(EMIF_EXT_PHY_CTRL_24_VAL, base + EMIF_EXT_PHY_CTRL_24_SHDW);
1200 }
1201
1202 static void get_default_timings(struct emif_data *emif)
1203 {
1204         struct emif_platform_data *pd = emif->plat_data;
1205
1206         pd->timings             = lpddr2_jedec_timings;
1207         pd->timings_arr_size    = ARRAY_SIZE(lpddr2_jedec_timings);
1208
1209         dev_warn(emif->dev, "%s: using default timings\n", __func__);
1210 }
1211
1212 static int is_dev_data_valid(u32 type, u32 density, u32 io_width, u32 phy_type,
1213                 u32 ip_rev, struct device *dev)
1214 {
1215         int valid;
1216
1217         valid = (type == DDR_TYPE_LPDDR2_S4 ||
1218                         type == DDR_TYPE_LPDDR2_S2)
1219                 && (density >= DDR_DENSITY_64Mb
1220                         && density <= DDR_DENSITY_8Gb)
1221                 && (io_width >= DDR_IO_WIDTH_8
1222                         && io_width <= DDR_IO_WIDTH_32);
1223
1224         /* Combinations of EMIF and PHY revisions that we support today */
1225         switch (ip_rev) {
1226         case EMIF_4D:
1227                 valid = valid && (phy_type == EMIF_PHY_TYPE_ATTILAPHY);
1228                 break;
1229         case EMIF_4D5:
1230                 valid = valid && (phy_type == EMIF_PHY_TYPE_INTELLIPHY);
1231                 break;
1232         default:
1233                 valid = 0;
1234         }
1235
1236         if (!valid)
1237                 dev_err(dev, "%s: invalid DDR details\n", __func__);
1238         return valid;
1239 }
1240
1241 static int is_custom_config_valid(struct emif_custom_configs *cust_cfgs,
1242                 struct device *dev)
1243 {
1244         int valid = 1;
1245
1246         if ((cust_cfgs->mask & EMIF_CUSTOM_CONFIG_LPMODE) &&
1247                 (cust_cfgs->lpmode != EMIF_LP_MODE_DISABLE))
1248                 valid = cust_cfgs->lpmode_freq_threshold &&
1249                         cust_cfgs->lpmode_timeout_performance &&
1250                         cust_cfgs->lpmode_timeout_power;
1251
1252         if (cust_cfgs->mask & EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL)
1253                 valid = valid && cust_cfgs->temp_alert_poll_interval_ms;
1254
1255         if (!valid)
1256                 dev_warn(dev, "%s: invalid custom configs\n", __func__);
1257
1258         return valid;
1259 }
1260
1261 #if defined(CONFIG_OF)
1262 static void __init_or_module of_get_custom_configs(struct device_node *np_emif,
1263                 struct emif_data *emif)
1264 {
1265         struct emif_custom_configs      *cust_cfgs = NULL;
1266         int                             len;
1267         const __be32                    *lpmode, *poll_intvl;
1268
1269         lpmode = of_get_property(np_emif, "low-power-mode", &len);
1270         poll_intvl = of_get_property(np_emif, "temp-alert-poll-interval", &len);
1271
1272         if (lpmode || poll_intvl)
1273                 cust_cfgs = devm_kzalloc(emif->dev, sizeof(*cust_cfgs),
1274                         GFP_KERNEL);
1275
1276         if (!cust_cfgs)
1277                 return;
1278
1279         if (lpmode) {
1280                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_LPMODE;
1281                 cust_cfgs->lpmode = be32_to_cpup(lpmode);
1282                 of_property_read_u32(np_emif,
1283                                 "low-power-mode-timeout-performance",
1284                                 &cust_cfgs->lpmode_timeout_performance);
1285                 of_property_read_u32(np_emif,
1286                                 "low-power-mode-timeout-power",
1287                                 &cust_cfgs->lpmode_timeout_power);
1288                 of_property_read_u32(np_emif,
1289                                 "low-power-mode-freq-threshold",
1290                                 &cust_cfgs->lpmode_freq_threshold);
1291         }
1292
1293         if (poll_intvl) {
1294                 cust_cfgs->mask |=
1295                                 EMIF_CUSTOM_CONFIG_TEMP_ALERT_POLL_INTERVAL;
1296                 cust_cfgs->temp_alert_poll_interval_ms =
1297                                                 be32_to_cpup(poll_intvl);
1298         }
1299
1300         if (of_find_property(np_emif, "extended-temp-part", &len))
1301                 cust_cfgs->mask |= EMIF_CUSTOM_CONFIG_EXTENDED_TEMP_PART;
1302
1303         if (!is_custom_config_valid(cust_cfgs, emif->dev)) {
1304                 devm_kfree(emif->dev, cust_cfgs);
1305                 return;
1306         }
1307
1308         emif->plat_data->custom_configs = cust_cfgs;
1309 }
1310
1311 static void __init_or_module of_get_ddr_info(struct device_node *np_emif,
1312                 struct device_node *np_ddr,
1313                 struct ddr_device_info *dev_info)
1314 {
1315         u32 density = 0, io_width = 0;
1316         int len;
1317
1318         if (of_find_property(np_emif, "cs1-used", &len))
1319                 dev_info->cs1_used = true;
1320
1321         if (of_find_property(np_emif, "cal-resistor-per-cs", &len))
1322                 dev_info->cal_resistors_per_cs = true;
1323
1324         if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s4"))
1325                 dev_info->type = DDR_TYPE_LPDDR2_S4;
1326         else if (of_device_is_compatible(np_ddr , "jedec,lpddr2-s2"))
1327                 dev_info->type = DDR_TYPE_LPDDR2_S2;
1328
1329         of_property_read_u32(np_ddr, "density", &density);
1330         of_property_read_u32(np_ddr, "io-width", &io_width);
1331
1332         /* Convert from density in Mb to the density encoding in jedc_ddr.h */
1333         if (density & (density - 1))
1334                 dev_info->density = 0;
1335         else
1336                 dev_info->density = __fls(density) - 5;
1337
1338         /* Convert from io_width in bits to io_width encoding in jedc_ddr.h */
1339         if (io_width & (io_width - 1))
1340                 dev_info->io_width = 0;
1341         else
1342                 dev_info->io_width = __fls(io_width) - 1;
1343 }
1344
1345 static struct emif_data * __init_or_module of_get_memory_device_details(
1346                 struct device_node *np_emif, struct device *dev)
1347 {
1348         struct emif_data                *emif = NULL;
1349         struct ddr_device_info          *dev_info = NULL;
1350         struct emif_platform_data       *pd = NULL;
1351         struct device_node              *np_ddr;
1352         int                             len;
1353
1354         np_ddr = of_parse_phandle(np_emif, "device-handle", 0);
1355         if (!np_ddr)
1356                 goto error;
1357         emif    = devm_kzalloc(dev, sizeof(struct emif_data), GFP_KERNEL);
1358         pd      = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1359         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1360
1361         if (!emif || !pd || !dev_info) {
1362                 dev_err(dev, "%s: Out of memory!!\n",
1363                         __func__);
1364                 goto error;
1365         }
1366
1367         emif->plat_data         = pd;
1368         pd->device_info         = dev_info;
1369         emif->dev               = dev;
1370         emif->np_ddr            = np_ddr;
1371         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1372
1373         if (of_device_is_compatible(np_emif, "ti,emif-4d"))
1374                 emif->plat_data->ip_rev = EMIF_4D;
1375         else if (of_device_is_compatible(np_emif, "ti,emif-4d5"))
1376                 emif->plat_data->ip_rev = EMIF_4D5;
1377
1378         of_property_read_u32(np_emif, "phy-type", &pd->phy_type);
1379
1380         if (of_find_property(np_emif, "hw-caps-ll-interface", &len))
1381                 pd->hw_caps |= EMIF_HW_CAPS_LL_INTERFACE;
1382
1383         of_get_ddr_info(np_emif, np_ddr, dev_info);
1384         if (!is_dev_data_valid(pd->device_info->type, pd->device_info->density,
1385                         pd->device_info->io_width, pd->phy_type, pd->ip_rev,
1386                         emif->dev)) {
1387                 dev_err(dev, "%s: invalid device data!!\n", __func__);
1388                 goto error;
1389         }
1390         /*
1391          * For EMIF instances other than EMIF1 see if the devices connected
1392          * are exactly same as on EMIF1(which is typically the case). If so,
1393          * mark it as a duplicate of EMIF1. This will save some memory and
1394          * computation.
1395          */
1396         if (emif1 && emif1->np_ddr == np_ddr) {
1397                 emif->duplicate = true;
1398                 goto out;
1399         } else if (emif1) {
1400                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1401                         __func__);
1402         }
1403
1404         of_get_custom_configs(np_emif, emif);
1405         emif->plat_data->timings = of_get_ddr_timings(np_ddr, emif->dev,
1406                                         emif->plat_data->device_info->type,
1407                                         &emif->plat_data->timings_arr_size);
1408
1409         emif->plat_data->min_tck = of_get_min_tck(np_ddr, emif->dev);
1410         goto out;
1411
1412 error:
1413         return NULL;
1414 out:
1415         return emif;
1416 }
1417
1418 #else
1419
1420 static struct emif_data * __init_or_module of_get_memory_device_details(
1421                 struct device_node *np_emif, struct device *dev)
1422 {
1423         return NULL;
1424 }
1425 #endif
1426
1427 static struct emif_data *__init_or_module get_device_details(
1428                 struct platform_device *pdev)
1429 {
1430         u32                             size;
1431         struct emif_data                *emif = NULL;
1432         struct ddr_device_info          *dev_info;
1433         struct emif_custom_configs      *cust_cfgs;
1434         struct emif_platform_data       *pd;
1435         struct device                   *dev;
1436         void                            *temp;
1437
1438         pd = pdev->dev.platform_data;
1439         dev = &pdev->dev;
1440
1441         if (!(pd && pd->device_info && is_dev_data_valid(pd->device_info->type,
1442                         pd->device_info->density, pd->device_info->io_width,
1443                         pd->phy_type, pd->ip_rev, dev))) {
1444                 dev_err(dev, "%s: invalid device data\n", __func__);
1445                 goto error;
1446         }
1447
1448         emif    = devm_kzalloc(dev, sizeof(*emif), GFP_KERNEL);
1449         temp    = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
1450         dev_info = devm_kzalloc(dev, sizeof(*dev_info), GFP_KERNEL);
1451
1452         if (!emif || !pd || !dev_info) {
1453                 dev_err(dev, "%s:%d: allocation error\n", __func__, __LINE__);
1454                 goto error;
1455         }
1456
1457         memcpy(temp, pd, sizeof(*pd));
1458         pd = temp;
1459         memcpy(dev_info, pd->device_info, sizeof(*dev_info));
1460
1461         pd->device_info         = dev_info;
1462         emif->plat_data         = pd;
1463         emif->dev               = dev;
1464         emif->temperature_level = SDRAM_TEMP_NOMINAL;
1465
1466         /*
1467          * For EMIF instances other than EMIF1 see if the devices connected
1468          * are exactly same as on EMIF1(which is typically the case). If so,
1469          * mark it as a duplicate of EMIF1 and skip copying timings data.
1470          * This will save some memory and some computation later.
1471          */
1472         emif->duplicate = emif1 && (memcmp(dev_info,
1473                 emif1->plat_data->device_info,
1474                 sizeof(struct ddr_device_info)) == 0);
1475
1476         if (emif->duplicate) {
1477                 pd->timings = NULL;
1478                 pd->min_tck = NULL;
1479                 goto out;
1480         } else if (emif1) {
1481                 dev_warn(emif->dev, "%s: Non-symmetric DDR geometry\n",
1482                         __func__);
1483         }
1484
1485         /*
1486          * Copy custom configs - ignore allocation error, if any, as
1487          * custom_configs is not very critical
1488          */
1489         cust_cfgs = pd->custom_configs;
1490         if (cust_cfgs && is_custom_config_valid(cust_cfgs, dev)) {
1491                 temp = devm_kzalloc(dev, sizeof(*cust_cfgs), GFP_KERNEL);
1492                 if (temp)
1493                         memcpy(temp, cust_cfgs, sizeof(*cust_cfgs));
1494                 else
1495                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1496                                 __LINE__);
1497                 pd->custom_configs = temp;
1498         }
1499
1500         /*
1501          * Copy timings and min-tck values from platform data. If it is not
1502          * available or if memory allocation fails, use JEDEC defaults
1503          */
1504         size = sizeof(struct lpddr2_timings) * pd->timings_arr_size;
1505         if (pd->timings) {
1506                 temp = devm_kzalloc(dev, size, GFP_KERNEL);
1507                 if (temp) {
1508                         memcpy(temp, pd->timings, size);
1509                         pd->timings = temp;
1510                 } else {
1511                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1512                                 __LINE__);
1513                         get_default_timings(emif);
1514                 }
1515         } else {
1516                 get_default_timings(emif);
1517         }
1518
1519         if (pd->min_tck) {
1520                 temp = devm_kzalloc(dev, sizeof(*pd->min_tck), GFP_KERNEL);
1521                 if (temp) {
1522                         memcpy(temp, pd->min_tck, sizeof(*pd->min_tck));
1523                         pd->min_tck = temp;
1524                 } else {
1525                         dev_warn(dev, "%s:%d: allocation error\n", __func__,
1526                                 __LINE__);
1527                         pd->min_tck = &lpddr2_jedec_min_tck;
1528                 }
1529         } else {
1530                 pd->min_tck = &lpddr2_jedec_min_tck;
1531         }
1532
1533 out:
1534         return emif;
1535
1536 error:
1537         return NULL;
1538 }
1539
1540 static int __init_or_module emif_probe(struct platform_device *pdev)
1541 {
1542         struct emif_data        *emif;
1543         struct resource         *res;
1544         int                     irq;
1545
1546         if (pdev->dev.of_node)
1547                 emif = of_get_memory_device_details(pdev->dev.of_node, &pdev->dev);
1548         else
1549                 emif = get_device_details(pdev);
1550
1551         if (!emif) {
1552                 pr_err("%s: error getting device data\n", __func__);
1553                 goto error;
1554         }
1555
1556         list_add(&emif->node, &device_list);
1557         emif->addressing = get_addressing_table(emif->plat_data->device_info);
1558
1559         /* Save pointers to each other in emif and device structures */
1560         emif->dev = &pdev->dev;
1561         platform_set_drvdata(pdev, emif);
1562
1563         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1564         emif->base = devm_ioremap_resource(emif->dev, res);
1565         if (IS_ERR(emif->base))
1566                 goto error;
1567
1568         irq = platform_get_irq(pdev, 0);
1569         if (irq < 0) {
1570                 dev_err(emif->dev, "%s: error getting IRQ resource - %d\n",
1571                         __func__, irq);
1572                 goto error;
1573         }
1574
1575         emif_onetime_settings(emif);
1576         emif_debugfs_init(emif);
1577         disable_and_clear_all_interrupts(emif);
1578         setup_interrupts(emif, irq);
1579
1580         /* One-time actions taken on probing the first device */
1581         if (!emif1) {
1582                 emif1 = emif;
1583                 spin_lock_init(&emif_lock);
1584
1585                 /*
1586                  * TODO: register notifiers for frequency and voltage
1587                  * change here once the respective frameworks are
1588                  * available
1589                  */
1590         }
1591
1592         dev_info(&pdev->dev, "%s: device configured with addr = %p and IRQ%d\n",
1593                 __func__, emif->base, irq);
1594
1595         return 0;
1596 error:
1597         return -ENODEV;
1598 }
1599
1600 static int __exit emif_remove(struct platform_device *pdev)
1601 {
1602         struct emif_data *emif = platform_get_drvdata(pdev);
1603
1604         emif_debugfs_exit(emif);
1605
1606         return 0;
1607 }
1608
1609 static void emif_shutdown(struct platform_device *pdev)
1610 {
1611         struct emif_data        *emif = platform_get_drvdata(pdev);
1612
1613         disable_and_clear_all_interrupts(emif);
1614 }
1615
1616 static int get_emif_reg_values(struct emif_data *emif, u32 freq,
1617                 struct emif_regs *regs)
1618 {
1619         u32                             cs1_used, ip_rev, phy_type;
1620         u32                             cl, type;
1621         const struct lpddr2_timings     *timings;
1622         const struct lpddr2_min_tck     *min_tck;
1623         const struct ddr_device_info    *device_info;
1624         const struct lpddr2_addressing  *addressing;
1625         struct emif_data                *emif_for_calc;
1626         struct device                   *dev;
1627         const struct emif_custom_configs *custom_configs;
1628
1629         dev = emif->dev;
1630         /*
1631          * If the devices on this EMIF instance is duplicate of EMIF1,
1632          * use EMIF1 details for the calculation
1633          */
1634         emif_for_calc   = emif->duplicate ? emif1 : emif;
1635         timings         = get_timings_table(emif_for_calc, freq);
1636         addressing      = emif_for_calc->addressing;
1637         if (!timings || !addressing) {
1638                 dev_err(dev, "%s: not enough data available for %dHz",
1639                         __func__, freq);
1640                 return -1;
1641         }
1642
1643         device_info     = emif_for_calc->plat_data->device_info;
1644         type            = device_info->type;
1645         cs1_used        = device_info->cs1_used;
1646         ip_rev          = emif_for_calc->plat_data->ip_rev;
1647         phy_type        = emif_for_calc->plat_data->phy_type;
1648
1649         min_tck         = emif_for_calc->plat_data->min_tck;
1650         custom_configs  = emif_for_calc->plat_data->custom_configs;
1651
1652         set_ddr_clk_period(freq);
1653
1654         regs->ref_ctrl_shdw = get_sdram_ref_ctrl_shdw(freq, addressing);
1655         regs->sdram_tim1_shdw = get_sdram_tim_1_shdw(timings, min_tck,
1656                         addressing);
1657         regs->sdram_tim2_shdw = get_sdram_tim_2_shdw(timings, min_tck,
1658                         addressing, type);
1659         regs->sdram_tim3_shdw = get_sdram_tim_3_shdw(timings, min_tck,
1660                 addressing, type, ip_rev, EMIF_NORMAL_TIMINGS);
1661
1662         cl = get_cl(emif);
1663
1664         if (phy_type == EMIF_PHY_TYPE_ATTILAPHY && ip_rev == EMIF_4D) {
1665                 regs->phy_ctrl_1_shdw = get_ddr_phy_ctrl_1_attilaphy_4d(
1666                         timings, freq, cl);
1667         } else if (phy_type == EMIF_PHY_TYPE_INTELLIPHY && ip_rev == EMIF_4D5) {
1668                 regs->phy_ctrl_1_shdw = get_phy_ctrl_1_intelliphy_4d5(freq, cl);
1669                 regs->ext_phy_ctrl_2_shdw = get_ext_phy_ctrl_2_intelliphy_4d5();
1670                 regs->ext_phy_ctrl_3_shdw = get_ext_phy_ctrl_3_intelliphy_4d5();
1671                 regs->ext_phy_ctrl_4_shdw = get_ext_phy_ctrl_4_intelliphy_4d5();
1672         } else {
1673                 return -1;
1674         }
1675
1676         /* Only timeout values in pwr_mgmt_ctrl_shdw register */
1677         regs->pwr_mgmt_ctrl_shdw =
1678                 get_pwr_mgmt_ctrl(freq, emif_for_calc, ip_rev) &
1679                 (CS_TIM_MASK | SR_TIM_MASK | PD_TIM_MASK);
1680
1681         if (ip_rev & EMIF_4D) {
1682                 regs->read_idle_ctrl_shdw_normal =
1683                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_STABLE);
1684
1685                 regs->read_idle_ctrl_shdw_volt_ramp =
1686                         get_read_idle_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1687         } else if (ip_rev & EMIF_4D5) {
1688                 regs->dll_calib_ctrl_shdw_normal =
1689                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_STABLE);
1690
1691                 regs->dll_calib_ctrl_shdw_volt_ramp =
1692                         get_dll_calib_ctrl_shdw(DDR_VOLTAGE_RAMPING);
1693         }
1694
1695         if (type == DDR_TYPE_LPDDR2_S2 || type == DDR_TYPE_LPDDR2_S4) {
1696                 regs->ref_ctrl_shdw_derated = get_sdram_ref_ctrl_shdw(freq / 4,
1697                         addressing);
1698
1699                 regs->sdram_tim1_shdw_derated =
1700                         get_sdram_tim_1_shdw_derated(timings, min_tck,
1701                                 addressing);
1702
1703                 regs->sdram_tim3_shdw_derated = get_sdram_tim_3_shdw(timings,
1704                         min_tck, addressing, type, ip_rev,
1705                         EMIF_DERATED_TIMINGS);
1706         }
1707
1708         regs->freq = freq;
1709
1710         return 0;
1711 }
1712
1713 /*
1714  * get_regs() - gets the cached emif_regs structure for a given EMIF instance
1715  * given frequency(freq):
1716  *
1717  * As an optimisation, every EMIF instance other than EMIF1 shares the
1718  * register cache with EMIF1 if the devices connected on this instance
1719  * are same as that on EMIF1(indicated by the duplicate flag)
1720  *
1721  * If we do not have an entry corresponding to the frequency given, we
1722  * allocate a new entry and calculate the values
1723  *
1724  * Upon finding the right reg dump, save it in curr_regs. It can be
1725  * directly used for thermal de-rating and voltage ramping changes.
1726  */
1727 static struct emif_regs *get_regs(struct emif_data *emif, u32 freq)
1728 {
1729         int                     i;
1730         struct emif_regs        **regs_cache;
1731         struct emif_regs        *regs = NULL;
1732         struct device           *dev;
1733
1734         dev = emif->dev;
1735         if (emif->curr_regs && emif->curr_regs->freq == freq) {
1736                 dev_dbg(dev, "%s: using curr_regs - %u Hz", __func__, freq);
1737                 return emif->curr_regs;
1738         }
1739
1740         if (emif->duplicate)
1741                 regs_cache = emif1->regs_cache;
1742         else
1743                 regs_cache = emif->regs_cache;
1744
1745         for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++) {
1746                 if (regs_cache[i]->freq == freq) {
1747                         regs = regs_cache[i];
1748                         dev_dbg(dev,
1749                                 "%s: reg dump found in reg cache for %u Hz\n",
1750                                 __func__, freq);
1751                         break;
1752                 }
1753         }
1754
1755         /*
1756          * If we don't have an entry for this frequency in the cache create one
1757          * and calculate the values
1758          */
1759         if (!regs) {
1760                 regs = devm_kzalloc(emif->dev, sizeof(*regs), GFP_ATOMIC);
1761                 if (!regs)
1762                         return NULL;
1763
1764                 if (get_emif_reg_values(emif, freq, regs)) {
1765                         devm_kfree(emif->dev, regs);
1766                         return NULL;
1767                 }
1768
1769                 /*
1770                  * Now look for an un-used entry in the cache and save the
1771                  * newly created struct. If there are no free entries
1772                  * over-write the last entry
1773                  */
1774                 for (i = 0; i < EMIF_MAX_NUM_FREQUENCIES && regs_cache[i]; i++)
1775                         ;
1776
1777                 if (i >= EMIF_MAX_NUM_FREQUENCIES) {
1778                         dev_warn(dev, "%s: regs_cache full - reusing a slot!!\n",
1779                                 __func__);
1780                         i = EMIF_MAX_NUM_FREQUENCIES - 1;
1781                         devm_kfree(emif->dev, regs_cache[i]);
1782                 }
1783                 regs_cache[i] = regs;
1784         }
1785
1786         return regs;
1787 }
1788
1789 static void do_volt_notify_handling(struct emif_data *emif, u32 volt_state)
1790 {
1791         dev_dbg(emif->dev, "%s: voltage notification : %d", __func__,
1792                 volt_state);
1793
1794         if (!emif->curr_regs) {
1795                 dev_err(emif->dev,
1796                         "%s: volt-notify before registers are ready: %d\n",
1797                         __func__, volt_state);
1798                 return;
1799         }
1800
1801         setup_volt_sensitive_regs(emif, emif->curr_regs, volt_state);
1802 }
1803
1804 /*
1805  * TODO: voltage notify handling should be hooked up to
1806  * regulator framework as soon as the necessary support
1807  * is available in mainline kernel. This function is un-used
1808  * right now.
1809  */
1810 static void __attribute__((unused)) volt_notify_handling(u32 volt_state)
1811 {
1812         struct emif_data *emif;
1813
1814         spin_lock_irqsave(&emif_lock, irq_state);
1815
1816         list_for_each_entry(emif, &device_list, node)
1817                 do_volt_notify_handling(emif, volt_state);
1818         do_freq_update();
1819
1820         spin_unlock_irqrestore(&emif_lock, irq_state);
1821 }
1822
1823 static void do_freq_pre_notify_handling(struct emif_data *emif, u32 new_freq)
1824 {
1825         struct emif_regs *regs;
1826
1827         regs = get_regs(emif, new_freq);
1828         if (!regs)
1829                 return;
1830
1831         emif->curr_regs = regs;
1832
1833         /*
1834          * Update the shadow registers:
1835          * Temperature and voltage-ramp sensitive settings are also configured
1836          * in terms of DDR cycles. So, we need to update them too when there
1837          * is a freq change
1838          */
1839         dev_dbg(emif->dev, "%s: setting up shadow registers for %uHz",
1840                 __func__, new_freq);
1841         setup_registers(emif, regs);
1842         setup_temperature_sensitive_regs(emif, regs);
1843         setup_volt_sensitive_regs(emif, regs, DDR_VOLTAGE_STABLE);
1844
1845         /*
1846          * Part of workaround for errata i728. See do_freq_update()
1847          * for more details
1848          */
1849         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1850                 set_lpmode(emif, EMIF_LP_MODE_DISABLE);
1851 }
1852
1853 /*
1854  * TODO: frequency notify handling should be hooked up to
1855  * clock framework as soon as the necessary support is
1856  * available in mainline kernel. This function is un-used
1857  * right now.
1858  */
1859 static void __attribute__((unused)) freq_pre_notify_handling(u32 new_freq)
1860 {
1861         struct emif_data *emif;
1862
1863         /*
1864          * NOTE: we are taking the spin-lock here and releases it
1865          * only in post-notifier. This doesn't look good and
1866          * Sparse complains about it, but this seems to be
1867          * un-avoidable. We need to lock a sequence of events
1868          * that is split between EMIF and clock framework.
1869          *
1870          * 1. EMIF driver updates EMIF timings in shadow registers in the
1871          *    frequency pre-notify callback from clock framework
1872          * 2. clock framework sets up the registers for the new frequency
1873          * 3. clock framework initiates a hw-sequence that updates
1874          *    the frequency EMIF timings synchronously.
1875          *
1876          * All these 3 steps should be performed as an atomic operation
1877          * vis-a-vis similar sequence in the EMIF interrupt handler
1878          * for temperature events. Otherwise, there could be race
1879          * conditions that could result in incorrect EMIF timings for
1880          * a given frequency
1881          */
1882         spin_lock_irqsave(&emif_lock, irq_state);
1883
1884         list_for_each_entry(emif, &device_list, node)
1885                 do_freq_pre_notify_handling(emif, new_freq);
1886 }
1887
1888 static void do_freq_post_notify_handling(struct emif_data *emif)
1889 {
1890         /*
1891          * Part of workaround for errata i728. See do_freq_update()
1892          * for more details
1893          */
1894         if (emif->lpmode == EMIF_LP_MODE_SELF_REFRESH)
1895                 set_lpmode(emif, EMIF_LP_MODE_SELF_REFRESH);
1896 }
1897
1898 /*
1899  * TODO: frequency notify handling should be hooked up to
1900  * clock framework as soon as the necessary support is
1901  * available in mainline kernel. This function is un-used
1902  * right now.
1903  */
1904 static void __attribute__((unused)) freq_post_notify_handling(void)
1905 {
1906         struct emif_data *emif;
1907
1908         list_for_each_entry(emif, &device_list, node)
1909                 do_freq_post_notify_handling(emif);
1910
1911         /*
1912          * Lock is done in pre-notify handler. See freq_pre_notify_handling()
1913          * for more details
1914          */
1915         spin_unlock_irqrestore(&emif_lock, irq_state);
1916 }
1917
1918 #if defined(CONFIG_OF)
1919 static const struct of_device_id emif_of_match[] = {
1920                 { .compatible = "ti,emif-4d" },
1921                 { .compatible = "ti,emif-4d5" },
1922                 {},
1923 };
1924 MODULE_DEVICE_TABLE(of, emif_of_match);
1925 #endif
1926
1927 static struct platform_driver emif_driver = {
1928         .remove         = __exit_p(emif_remove),
1929         .shutdown       = emif_shutdown,
1930         .driver = {
1931                 .name = "emif",
1932                 .of_match_table = of_match_ptr(emif_of_match),
1933         },
1934 };
1935
1936 module_platform_driver_probe(emif_driver, emif_probe);
1937
1938 MODULE_DESCRIPTION("TI EMIF SDRAM Controller Driver");
1939 MODULE_LICENSE("GPL");
1940 MODULE_ALIAS("platform:emif");
1941 MODULE_AUTHOR("Texas Instruments Inc");