drivers/media/video/s5p-fimc/mipi-csis.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
   3  *
   4  * Copyright (C) 2011 Samsung Electronics Co., Ltd.
   5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/clk.h>
  13 #include <linux/delay.h>
  14 #include <linux/device.h>
  15 #include <linux/errno.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/irq.h>
  19 #include <linux/kernel.h>
  20 #include <linux/memory.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/pm_runtime.h>
  24 #include <linux/regulator/consumer.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/videodev2.h>
  28 #include <media/v4l2-subdev.h>
  29 #include <plat/mipi_csis.h>
  30 #include "mipi-csis.h"
  31
  32 static int debug;
  33 module_param(debug, int, 0644);
  34 MODULE_PARM_DESC(debug, "Debug level (0-1)");
  35
  36 /* Register map definition */
  37
  38 /* CSIS global control */
  39 #define S5PCSIS_CTRL                    0x00
  40 #define S5PCSIS_CTRL_DPDN_DEFAULT       (0 << 31)
  41 #define S5PCSIS_CTRL_DPDN_SWAP          (1 << 31)
  42 #define S5PCSIS_CTRL_ALIGN_32BIT        (1 << 20)
  43 #define S5PCSIS_CTRL_UPDATE_SHADOW      (1 << 16)
  44 #define S5PCSIS_CTRL_WCLK_EXTCLK        (1 << 8)
  45 #define S5PCSIS_CTRL_RESET              (1 << 4)
  46 #define S5PCSIS_CTRL_ENABLE             (1 << 0)
  47
  48 /* D-PHY control */
  49 #define S5PCSIS_DPHYCTRL                0x04
  50 #define S5PCSIS_DPHYCTRL_HSS_MASK       (0x1f << 27)
  51 #define S5PCSIS_DPHYCTRL_ENABLE         (0x1f << 0)
  52
  53 #define S5PCSIS_CONFIG                  0x08
  54 #define S5PCSIS_CFG_FMT_YCBCR422_8BIT   (0x1e << 2)
  55 #define S5PCSIS_CFG_FMT_RAW8            (0x2a << 2)
  56 #define S5PCSIS_CFG_FMT_RAW10           (0x2b << 2)
  57 #define S5PCSIS_CFG_FMT_RAW12           (0x2c << 2)
  58 /* User defined formats, x = 1...4 */
  59 #define S5PCSIS_CFG_FMT_USER(x)         ((0x30 + x - 1) << 2)
  60 #define S5PCSIS_CFG_FMT_MASK            (0x3f << 2)
  61 #define S5PCSIS_CFG_NR_LANE_MASK        3
  62
  63 /* Interrupt mask. */
  64 #define S5PCSIS_INTMSK                  0x10
  65 #define S5PCSIS_INTMSK_EN_ALL           0xf000003f
  66 #define S5PCSIS_INTSRC                  0x14
  67
  68 /* Pixel resolution */
  69 #define S5PCSIS_RESOL                   0x2c
  70 #define CSIS_MAX_PIX_WIDTH              0xffff
  71 #define CSIS_MAX_PIX_HEIGHT             0xffff
  72
  73 enum {
  74         CSIS_CLK_MUX,
  75         CSIS_CLK_GATE,
  76 };
  77
  78 static char *csi_clock_name[] = {
  79         [CSIS_CLK_MUX]  = "sclk_csis",
  80         [CSIS_CLK_GATE] = "csis",
  81 };
  82 #define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
  83
  84 static const char * const csis_supply_name[] = {
  85         "vdd11", /* 1.1V or 1.2V (s5pc100) MIPI CSI suppply */
  86         "vdd18", /* VDD 1.8V and MIPI CSI PLL supply */
  87 };
  88 #define CSIS_NUM_SUPPLIES ARRAY_SIZE(csis_supply_name)
  89
  90 enum {
  91         ST_POWERED      = 1,
  92         ST_STREAMING    = 2,
  93         ST_SUSPENDED    = 4,
  94 };
  95
  96 /**
  97  * struct csis_state - the driver's internal state data structure
  98  * @lock: mutex serializing the subdev and power management operations,
  99  *        protecting @format and @flags members
 100  * @pads: CSIS pads array
 101  * @sd: v4l2_subdev associated with CSIS device instance
 102  * @pdev: CSIS platform device
 103  * @regs_res: requested I/O register memory resource
 104  * @regs: mmaped I/O registers memory
 105  * @clock: CSIS clocks
 106  * @irq: requested s5p-mipi-csis irq number
 107  * @flags: the state variable for power and streaming control
 108  * @csis_fmt: current CSIS pixel format
 109  * @format: common media bus format for the source and sink pad
 110  */
 111 struct csis_state {
 112         struct mutex lock;
 113         struct media_pad pads[CSIS_PADS_NUM];
 114         struct v4l2_subdev sd;
 115         struct platform_device *pdev;
 116         struct resource *regs_res;
 117         void __iomem *regs;
 118         struct regulator_bulk_data supplies[CSIS_NUM_SUPPLIES];
 119         struct clk *clock[NUM_CSIS_CLOCKS];
 120         int irq;
 121         u32 flags;
 122         const struct csis_pix_format *csis_fmt;
 123         struct v4l2_mbus_framefmt format;
 124 };
 125
 126 /**
 127  * struct csis_pix_format - CSIS pixel format description
 128  * @pix_width_alignment: horizontal pixel alignment, width will be
 129  *                       multiple of 2^pix_width_alignment
 130  * @code: corresponding media bus code
 131  * @fmt_reg: S5PCSIS_CONFIG register value
 132  */
 133 struct csis_pix_format {
 134         unsigned int pix_width_alignment;
 135         enum v4l2_mbus_pixelcode code;
 136         u32 fmt_reg;
 137 };
 138
 139 static const struct csis_pix_format s5pcsis_formats[] = {
 140         {
 141                 .code = V4L2_MBUS_FMT_VYUY8_2X8,
 142                 .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
 143         }, {
 144                 .code = V4L2_MBUS_FMT_JPEG_1X8,
 145                 .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
 146         },
 147 };
 148
 149 #define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
 150 #define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
 151
 152 static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
 153 {
 154         return container_of(sdev, struct csis_state, sd);
 155 }
 156
 157 static const struct csis_pix_format *find_csis_format(
 158         struct v4l2_mbus_framefmt *mf)
 159 {
 160         int i;
 161
 162         for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
 163                 if (mf->code == s5pcsis_formats[i].code)
 164                         return &s5pcsis_formats[i];
 165         return NULL;
 166 }
 167
 168 static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
 169 {
 170         u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
 171
 172         val = on ? val | S5PCSIS_INTMSK_EN_ALL :
 173                    val & ~S5PCSIS_INTMSK_EN_ALL;
 174         s5pcsis_write(state, S5PCSIS_INTMSK, val);
 175 }
 176
 177 static void s5pcsis_reset(struct csis_state *state)
 178 {
 179         u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
 180
 181         s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
 182         udelay(10);
 183 }
 184
 185 static void s5pcsis_system_enable(struct csis_state *state, int on)
 186 {
 187         u32 val;
 188
 189         val = s5pcsis_read(state, S5PCSIS_CTRL);
 190         if (on)
 191                 val |= S5PCSIS_CTRL_ENABLE;
 192         else
 193                 val &= ~S5PCSIS_CTRL_ENABLE;
 194         s5pcsis_write(state, S5PCSIS_CTRL, val);
 195
 196         val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
 197         if (on)
 198                 val |= S5PCSIS_DPHYCTRL_ENABLE;
 199         else
 200                 val &= ~S5PCSIS_DPHYCTRL_ENABLE;
 201         s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
 202 }
 203
 204 /* Called with the state.lock mutex held */
 205 static void __s5pcsis_set_format(struct csis_state *state)
 206 {
 207         struct v4l2_mbus_framefmt *mf = &state->format;
 208         u32 val;
 209
 210         v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
 211                  mf->code, mf->width, mf->height);
 212
 213         /* Color format */
 214         val = s5pcsis_read(state, S5PCSIS_CONFIG);
 215         val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
 216         s5pcsis_write(state, S5PCSIS_CONFIG, val);
 217
 218         /* Pixel resolution */
 219         val = (mf->width << 16) | mf->height;
 220         s5pcsis_write(state, S5PCSIS_RESOL, val);
 221 }
 222
 223 static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
 224 {
 225         u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
 226
 227         val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
 228         s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
 229 }
 230
 231 static void s5pcsis_set_params(struct csis_state *state)
 232 {
 233         struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
 234         u32 val;
 235
 236         val = s5pcsis_read(state, S5PCSIS_CONFIG);
 237         val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
 238         s5pcsis_write(state, S5PCSIS_CONFIG, val);
 239
 240         __s5pcsis_set_format(state);
 241         s5pcsis_set_hsync_settle(state, pdata->hs_settle);
 242
 243         val = s5pcsis_read(state, S5PCSIS_CTRL);
 244         if (pdata->alignment == 32)
 245                 val |= S5PCSIS_CTRL_ALIGN_32BIT;
 246         else /* 24-bits */
 247                 val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
 248         /* Not using external clock. */
 249         val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
 250         s5pcsis_write(state, S5PCSIS_CTRL, val);
 251
 252         /* Update the shadow register. */
 253         val = s5pcsis_read(state, S5PCSIS_CTRL);
 254         s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
 255 }
 256
 257 static void s5pcsis_clk_put(struct csis_state *state)
 258 {
 259         int i;
 260
 261         for (i = 0; i < NUM_CSIS_CLOCKS; i++)
 262                 if (!IS_ERR_OR_NULL(state->clock[i]))
 263                         clk_put(state->clock[i]);
 264 }
 265
 266 static int s5pcsis_clk_get(struct csis_state *state)
 267 {
 268         struct device *dev = &state->pdev->dev;
 269         int i;
 270
 271         for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
 272                 state->clock[i] = clk_get(dev, csi_clock_name[i]);
 273                 if (IS_ERR(state->clock[i])) {
 274                         s5pcsis_clk_put(state);
 275                         dev_err(dev, "failed to get clock: %s\n",
 276                                 csi_clock_name[i]);
 277                         return -ENXIO;
 278                 }
 279         }
 280         return 0;
 281 }
 282
 283 static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
 284 {
 285         struct csis_state *state = sd_to_csis_state(sd);
 286         struct device *dev = &state->pdev->dev;
 287
 288         if (on)
 289                 return pm_runtime_get_sync(dev);
 290
 291         return pm_runtime_put_sync(dev);
 292 }
 293
 294 static void s5pcsis_start_stream(struct csis_state *state)
 295 {
 296         s5pcsis_reset(state);
 297         s5pcsis_set_params(state);
 298         s5pcsis_system_enable(state, true);
 299         s5pcsis_enable_interrupts(state, true);
 300 }
 301
 302 static void s5pcsis_stop_stream(struct csis_state *state)
 303 {
 304         s5pcsis_enable_interrupts(state, false);
 305         s5pcsis_system_enable(state, false);
 306 }
 307
 308 /* v4l2_subdev operations */
 309 static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
 310 {
 311         struct csis_state *state = sd_to_csis_state(sd);
 312         int ret = 0;
 313
 314         v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
 315                  __func__, enable, state->flags);
 316
 317         if (enable) {
 318                 ret = pm_runtime_get_sync(&state->pdev->dev);
 319                 if (ret && ret != 1)
 320                         return ret;
 321         }
 322         mutex_lock(&state->lock);
 323         if (enable) {
 324                 if (state->flags & ST_SUSPENDED) {
 325                         ret = -EBUSY;
 326                         goto unlock;
 327                 }
 328                 s5pcsis_start_stream(state);
 329                 state->flags |= ST_STREAMING;
 330         } else {
 331                 s5pcsis_stop_stream(state);
 332                 state->flags &= ~ST_STREAMING;
 333         }
 334 unlock:
 335         mutex_unlock(&state->lock);
 336         if (!enable)
 337                 pm_runtime_put(&state->pdev->dev);
 338
 339         return ret == 1 ? 0 : ret;
 340 }
 341
 342 static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
 343                                   struct v4l2_subdev_fh *fh,
 344                                   struct v4l2_subdev_mbus_code_enum *code)
 345 {
 346         if (code->index >= ARRAY_SIZE(s5pcsis_formats))
 347                 return -EINVAL;
 348
 349         code->code = s5pcsis_formats[code->index].code;
 350         return 0;
 351 }
 352
 353 static struct csis_pix_format const *s5pcsis_try_format(
 354         struct v4l2_mbus_framefmt *mf)
 355 {
 356         struct csis_pix_format const *csis_fmt;
 357
 358         csis_fmt = find_csis_format(mf);
 359         if (csis_fmt == NULL)
 360                 csis_fmt = &s5pcsis_formats[0];
 361
 362         mf->code = csis_fmt->code;
 363         v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
 364                               csis_fmt->pix_width_alignment,
 365                               &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
 366                               0);
 367         return csis_fmt;
 368 }
 369
 370 static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
 371                 struct csis_state *state, struct v4l2_subdev_fh *fh,
 372                 u32 pad, enum v4l2_subdev_format_whence which)
 373 {
 374         if (which == V4L2_SUBDEV_FORMAT_TRY)
 375                 return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
 376
 377         return &state->format;
 378 }
 379
 380 static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 381                            struct v4l2_subdev_format *fmt)
 382 {
 383         struct csis_state *state = sd_to_csis_state(sd);
 384         struct csis_pix_format const *csis_fmt;
 385         struct v4l2_mbus_framefmt *mf;
 386
 387         if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
 388                 return -EINVAL;
 389
 390         mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
 391
 392         if (fmt->pad == CSIS_PAD_SOURCE) {
 393                 if (mf) {
 394                         mutex_lock(&state->lock);
 395                         fmt->format = *mf;
 396                         mutex_unlock(&state->lock);
 397                 }
 398                 return 0;
 399         }
 400         csis_fmt = s5pcsis_try_format(&fmt->format);
 401         if (mf) {
 402                 mutex_lock(&state->lock);
 403                 *mf = fmt->format;
 404                 if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
 405                         state->csis_fmt = csis_fmt;
 406                 mutex_unlock(&state->lock);
 407         }
 408         return 0;
 409 }
 410
 411 static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
 412                            struct v4l2_subdev_format *fmt)
 413 {
 414         struct csis_state *state = sd_to_csis_state(sd);
 415         struct v4l2_mbus_framefmt *mf;
 416
 417         if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
 418                 return -EINVAL;
 419
 420         mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
 421         if (!mf)
 422                 return -EINVAL;
 423
 424         mutex_lock(&state->lock);
 425         fmt->format = *mf;
 426         mutex_unlock(&state->lock);
 427         return 0;
 428 }
 429
 430 static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
 431         .s_power = s5pcsis_s_power,
 432 };
 433
 434 static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
 435         .enum_mbus_code = s5pcsis_enum_mbus_code,
 436         .get_fmt = s5pcsis_get_fmt,
 437         .set_fmt = s5pcsis_set_fmt,
 438 };
 439
 440 static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
 441         .s_stream = s5pcsis_s_stream,
 442 };
 443
 444 static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
 445         .core = &s5pcsis_core_ops,
 446         .pad = &s5pcsis_pad_ops,
 447         .video = &s5pcsis_video_ops,
 448 };
 449
 450 static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
 451 {
 452         struct csis_state *state = dev_id;
 453         u32 val;
 454
 455         /* Just clear the interrupt pending bits. */
 456         val = s5pcsis_read(state, S5PCSIS_INTSRC);
 457         s5pcsis_write(state, S5PCSIS_INTSRC, val);
 458
 459         return IRQ_HANDLED;
 460 }
 461
 462 static int __devinit s5pcsis_probe(struct platform_device *pdev)
 463 {
 464         struct s5p_platform_mipi_csis *pdata;
 465         struct resource *mem_res;
 466         struct resource *regs_res;
 467         struct csis_state *state;
 468         int ret = -ENOMEM;
 469         int i;
 470
 471         state = kzalloc(sizeof(*state), GFP_KERNEL);
 472         if (!state)
 473                 return -ENOMEM;
 474
 475         mutex_init(&state->lock);
 476         state->pdev = pdev;
 477
 478         pdata = pdev->dev.platform_data;
 479         if (pdata == NULL || pdata->phy_enable == NULL) {
 480                 dev_err(&pdev->dev, "Platform data not fully specified\n");
 481                 goto e_free;
 482         }
 483
 484         if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
 485             pdata->lanes > CSIS0_MAX_LANES) {
 486                 ret = -EINVAL;
 487                 dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
 488                         pdata->lanes);
 489                 goto e_free;
 490         }
 491
 492         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 493         if (!mem_res) {
 494                 dev_err(&pdev->dev, "Failed to get IO memory region\n");
 495                 goto e_free;
 496         }
 497
 498         regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
 499                                       pdev->name);
 500         if (!regs_res) {
 501                 dev_err(&pdev->dev, "Failed to request IO memory region\n");
 502                 goto e_free;
 503         }
 504         state->regs_res = regs_res;
 505
 506         state->regs = ioremap(mem_res->start, resource_size(mem_res));
 507         if (!state->regs) {
 508                 dev_err(&pdev->dev, "Failed to remap IO region\n");
 509                 goto e_reqmem;
 510         }
 511
 512         ret = s5pcsis_clk_get(state);
 513         if (ret)
 514                 goto e_unmap;
 515
 516         clk_enable(state->clock[CSIS_CLK_MUX]);
 517         if (pdata->clk_rate)
 518                 clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
 519         else
 520                 dev_WARN(&pdev->dev, "No clock frequency specified!\n");
 521
 522         state->irq = platform_get_irq(pdev, 0);
 523         if (state->irq < 0) {
 524                 ret = state->irq;
 525                 dev_err(&pdev->dev, "Failed to get irq\n");
 526                 goto e_clkput;
 527         }
 528
 529         for (i = 0; i < CSIS_NUM_SUPPLIES; i++)
 530                 state->supplies[i].supply = csis_supply_name[i];
 531
 532         ret = regulator_bulk_get(&pdev->dev, CSIS_NUM_SUPPLIES,
 533                                  state->supplies);
 534         if (ret)
 535                 goto e_clkput;
 536
 537         ret = request_irq(state->irq, s5pcsis_irq_handler, 0,
 538                           dev_name(&pdev->dev), state);
 539         if (ret) {
 540                 dev_err(&pdev->dev, "request_irq failed\n");
 541                 goto e_regput;
 542         }
 543
 544         v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
 545         state->sd.owner = THIS_MODULE;
 546         strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name));
 547         state->csis_fmt = &s5pcsis_formats[0];
 548
 549         state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
 550         state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
 551         ret = media_entity_init(&state->sd.entity,
 552                                 CSIS_PADS_NUM, state->pads, 0);
 553         if (ret < 0)
 554                 goto e_irqfree;
 555
 556         /* This allows to retrieve the platform device id by the host driver */
 557         v4l2_set_subdevdata(&state->sd, pdev);
 558
 559         /* .. and a pointer to the subdev. */
 560         platform_set_drvdata(pdev, &state->sd);
 561
 562         pm_runtime_enable(&pdev->dev);
 563
 564         return 0;
 565
 566 e_irqfree:
 567         free_irq(state->irq, state);
 568 e_regput:
 569         regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies);
 570 e_clkput:
 571         clk_disable(state->clock[CSIS_CLK_MUX]);
 572         s5pcsis_clk_put(state);
 573 e_unmap:
 574         iounmap(state->regs);
 575 e_reqmem:
 576         release_mem_region(regs_res->start, resource_size(regs_res));
 577 e_free:
 578         kfree(state);
 579         return ret;
 580 }
 581
 582 static int s5pcsis_pm_suspend(struct device *dev, bool runtime)
 583 {
 584         struct s5p_platform_mipi_csis *pdata = dev->platform_data;
 585         struct platform_device *pdev = to_platform_device(dev);
 586         struct v4l2_subdev *sd = platform_get_drvdata(pdev);
 587         struct csis_state *state = sd_to_csis_state(sd);
 588         int ret = 0;
 589
 590         v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
 591                  __func__, state->flags);
 592
 593         mutex_lock(&state->lock);
 594         if (state->flags & ST_POWERED) {
 595                 s5pcsis_stop_stream(state);
 596                 ret = pdata->phy_enable(state->pdev, false);
 597                 if (ret)
 598                         goto unlock;
 599                 ret = regulator_bulk_disable(CSIS_NUM_SUPPLIES,
 600                                              state->supplies);
 601                 if (ret)
 602                         goto unlock;
 603                 clk_disable(state->clock[CSIS_CLK_GATE]);
 604                 state->flags &= ~ST_POWERED;
 605                 if (!runtime)
 606                         state->flags |= ST_SUSPENDED;
 607         }
 608  unlock:
 609         mutex_unlock(&state->lock);
 610         return ret ? -EAGAIN : 0;
 611 }
 612
 613 static int s5pcsis_pm_resume(struct device *dev, bool runtime)
 614 {
 615         struct s5p_platform_mipi_csis *pdata = dev->platform_data;
 616         struct platform_device *pdev = to_platform_device(dev);
 617         struct v4l2_subdev *sd = platform_get_drvdata(pdev);
 618         struct csis_state *state = sd_to_csis_state(sd);
 619         int ret = 0;
 620
 621         v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
 622                  __func__, state->flags);
 623
 624         mutex_lock(&state->lock);
 625         if (!runtime && !(state->flags & ST_SUSPENDED))
 626                 goto unlock;
 627
 628         if (!(state->flags & ST_POWERED)) {
 629                 ret = regulator_bulk_enable(CSIS_NUM_SUPPLIES,
 630                                             state->supplies);
 631                 if (ret)
 632                         goto unlock;
 633                 ret = pdata->phy_enable(state->pdev, true);
 634                 if (!ret) {
 635                         state->flags |= ST_POWERED;
 636                 } else {
 637                         regulator_bulk_disable(CSIS_NUM_SUPPLIES,
 638                                                state->supplies);
 639                         goto unlock;
 640                 }
 641                 clk_enable(state->clock[CSIS_CLK_GATE]);
 642         }
 643         if (state->flags & ST_STREAMING)
 644                 s5pcsis_start_stream(state);
 645
 646         state->flags &= ~ST_SUSPENDED;
 647  unlock:
 648         mutex_unlock(&state->lock);
 649         return ret ? -EAGAIN : 0;
 650 }
 651
 652 #ifdef CONFIG_PM_SLEEP
 653 static int s5pcsis_suspend(struct device *dev)
 654 {
 655         return s5pcsis_pm_suspend(dev, false);
 656 }
 657
 658 static int s5pcsis_resume(struct device *dev)
 659 {
 660         return s5pcsis_pm_resume(dev, false);
 661 }
 662 #endif
 663
 664 #ifdef CONFIG_PM_RUNTIME
 665 static int s5pcsis_runtime_suspend(struct device *dev)
 666 {
 667         return s5pcsis_pm_suspend(dev, true);
 668 }
 669
 670 static int s5pcsis_runtime_resume(struct device *dev)
 671 {
 672         return s5pcsis_pm_resume(dev, true);
 673 }
 674 #endif
 675
 676 static int __devexit s5pcsis_remove(struct platform_device *pdev)
 677 {
 678         struct v4l2_subdev *sd = platform_get_drvdata(pdev);
 679         struct csis_state *state = sd_to_csis_state(sd);
 680         struct resource *res = state->regs_res;
 681
 682         pm_runtime_disable(&pdev->dev);
 683         s5pcsis_suspend(&pdev->dev);
 684         clk_disable(state->clock[CSIS_CLK_MUX]);
 685         pm_runtime_set_suspended(&pdev->dev);
 686
 687         s5pcsis_clk_put(state);
 688         regulator_bulk_free(CSIS_NUM_SUPPLIES, state->supplies);
 689
 690         media_entity_cleanup(&state->sd.entity);
 691         free_irq(state->irq, state);
 692         iounmap(state->regs);
 693         release_mem_region(res->start, resource_size(res));
 694         kfree(state);
 695
 696         return 0;
 697 }
 698
 699 static const struct dev_pm_ops s5pcsis_pm_ops = {
 700         SET_RUNTIME_PM_OPS(s5pcsis_runtime_suspend, s5pcsis_runtime_resume,
 701                            NULL)
 702         SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_suspend, s5pcsis_resume)
 703 };
 704
 705 static struct platform_driver s5pcsis_driver = {
 706         .probe          = s5pcsis_probe,
 707         .remove         = __devexit_p(s5pcsis_remove),
 708         .driver         = {
 709                 .name   = CSIS_DRIVER_NAME,
 710                 .owner  = THIS_MODULE,
 711                 .pm     = &s5pcsis_pm_ops,
 712         },
 713 };
 714
 715 static int __init s5pcsis_init(void)
 716 {
 717         return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe);
 718 }
 719
 720 static void __exit s5pcsis_exit(void)
 721 {
 722         platform_driver_unregister(&s5pcsis_driver);
 723 }
 724
 725 module_init(s5pcsis_init);
 726 module_exit(s5pcsis_exit);
 727
 728 MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
 729 MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver");
 730 MODULE_LICENSE("GPL");