drivers/media/video/s5p-fimc/fimc-core.c

   1 /*
   2  * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
   3  *
   4  * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
   5  * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published
   9  * by the Free Software Foundation, either version 2 of the License,
  10  * or (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/errno.h>
  17 #include <linux/bug.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/list.h>
  23 #include <linux/io.h>
  24 #include <linux/slab.h>
  25 #include <linux/clk.h>
  26 #include <media/v4l2-ioctl.h>
  27 #include <media/videobuf2-core.h>
  28 #include <media/videobuf2-dma-contig.h>
  29
  30 #include "fimc-core.h"
  31 #include "fimc-mdevice.h"
  32
  33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
  34         "sclk_fimc", "fimc"
  35 };
  36
  37 static struct fimc_fmt fimc_formats[] = {
  38         {
  39                 .name           = "RGB565",
  40                 .fourcc         = V4L2_PIX_FMT_RGB565,
  41                 .depth          = { 16 },
  42                 .color          = S5P_FIMC_RGB565,
  43                 .memplanes      = 1,
  44                 .colplanes      = 1,
  45                 .flags          = FMT_FLAGS_M2M,
  46         }, {
  47                 .name           = "BGR666",
  48                 .fourcc         = V4L2_PIX_FMT_BGR666,
  49                 .depth          = { 32 },
  50                 .color          = S5P_FIMC_RGB666,
  51                 .memplanes      = 1,
  52                 .colplanes      = 1,
  53                 .flags          = FMT_FLAGS_M2M,
  54         }, {
  55                 .name           = "ARGB8888, 32 bpp",
  56                 .fourcc         = V4L2_PIX_FMT_RGB32,
  57                 .depth          = { 32 },
  58                 .color          = S5P_FIMC_RGB888,
  59                 .memplanes      = 1,
  60                 .colplanes      = 1,
  61                 .flags          = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
  62         }, {
  63                 .name           = "ARGB1555",
  64                 .fourcc         = V4L2_PIX_FMT_RGB555,
  65                 .depth          = { 16 },
  66                 .color          = S5P_FIMC_RGB555,
  67                 .memplanes      = 1,
  68                 .colplanes      = 1,
  69                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  70         }, {
  71                 .name           = "ARGB4444",
  72                 .fourcc         = V4L2_PIX_FMT_RGB444,
  73                 .depth          = { 16 },
  74                 .color          = S5P_FIMC_RGB444,
  75                 .memplanes      = 1,
  76                 .colplanes      = 1,
  77                 .flags          = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
  78         }, {
  79                 .name           = "YUV 4:2:2 packed, YCbYCr",
  80                 .fourcc         = V4L2_PIX_FMT_YUYV,
  81                 .depth          = { 16 },
  82                 .color          = S5P_FIMC_YCBYCR422,
  83                 .memplanes      = 1,
  84                 .colplanes      = 1,
  85                 .mbus_code      = V4L2_MBUS_FMT_YUYV8_2X8,
  86                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  87         }, {
  88                 .name           = "YUV 4:2:2 packed, CbYCrY",
  89                 .fourcc         = V4L2_PIX_FMT_UYVY,
  90                 .depth          = { 16 },
  91                 .color          = S5P_FIMC_CBYCRY422,
  92                 .memplanes      = 1,
  93                 .colplanes      = 1,
  94                 .mbus_code      = V4L2_MBUS_FMT_UYVY8_2X8,
  95                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
  96         }, {
  97                 .name           = "YUV 4:2:2 packed, CrYCbY",
  98                 .fourcc         = V4L2_PIX_FMT_VYUY,
  99                 .depth          = { 16 },
 100                 .color          = S5P_FIMC_CRYCBY422,
 101                 .memplanes      = 1,
 102                 .colplanes      = 1,
 103                 .mbus_code      = V4L2_MBUS_FMT_VYUY8_2X8,
 104                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 105         }, {
 106                 .name           = "YUV 4:2:2 packed, YCrYCb",
 107                 .fourcc         = V4L2_PIX_FMT_YVYU,
 108                 .depth          = { 16 },
 109                 .color          = S5P_FIMC_YCRYCB422,
 110                 .memplanes      = 1,
 111                 .colplanes      = 1,
 112                 .mbus_code      = V4L2_MBUS_FMT_YVYU8_2X8,
 113                 .flags          = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
 114         }, {
 115                 .name           = "YUV 4:2:2 planar, Y/Cb/Cr",
 116                 .fourcc         = V4L2_PIX_FMT_YUV422P,
 117                 .depth          = { 12 },
 118                 .color          = S5P_FIMC_YCBYCR422,
 119                 .memplanes      = 1,
 120                 .colplanes      = 3,
 121                 .flags          = FMT_FLAGS_M2M,
 122         }, {
 123                 .name           = "YUV 4:2:2 planar, Y/CbCr",
 124                 .fourcc         = V4L2_PIX_FMT_NV16,
 125                 .depth          = { 16 },
 126                 .color          = S5P_FIMC_YCBYCR422,
 127                 .memplanes      = 1,
 128                 .colplanes      = 2,
 129                 .flags          = FMT_FLAGS_M2M,
 130         }, {
 131                 .name           = "YUV 4:2:2 planar, Y/CrCb",
 132                 .fourcc         = V4L2_PIX_FMT_NV61,
 133                 .depth          = { 16 },
 134                 .color          = S5P_FIMC_YCRYCB422,
 135                 .memplanes      = 1,
 136                 .colplanes      = 2,
 137                 .flags          = FMT_FLAGS_M2M,
 138         }, {
 139                 .name           = "YUV 4:2:0 planar, YCbCr",
 140                 .fourcc         = V4L2_PIX_FMT_YUV420,
 141                 .depth          = { 12 },
 142                 .color          = S5P_FIMC_YCBCR420,
 143                 .memplanes      = 1,
 144                 .colplanes      = 3,
 145                 .flags          = FMT_FLAGS_M2M,
 146         }, {
 147                 .name           = "YUV 4:2:0 planar, Y/CbCr",
 148                 .fourcc         = V4L2_PIX_FMT_NV12,
 149                 .depth          = { 12 },
 150                 .color          = S5P_FIMC_YCBCR420,
 151                 .memplanes      = 1,
 152                 .colplanes      = 2,
 153                 .flags          = FMT_FLAGS_M2M,
 154         }, {
 155                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
 156                 .fourcc         = V4L2_PIX_FMT_NV12M,
 157                 .color          = S5P_FIMC_YCBCR420,
 158                 .depth          = { 8, 4 },
 159                 .memplanes      = 2,
 160                 .colplanes      = 2,
 161                 .flags          = FMT_FLAGS_M2M,
 162         }, {
 163                 .name           = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
 164                 .fourcc         = V4L2_PIX_FMT_YUV420M,
 165                 .color          = S5P_FIMC_YCBCR420,
 166                 .depth          = { 8, 2, 2 },
 167                 .memplanes      = 3,
 168                 .colplanes      = 3,
 169                 .flags          = FMT_FLAGS_M2M,
 170         }, {
 171                 .name           = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
 172                 .fourcc         = V4L2_PIX_FMT_NV12MT,
 173                 .color          = S5P_FIMC_YCBCR420,
 174                 .depth          = { 8, 4 },
 175                 .memplanes      = 2,
 176                 .colplanes      = 2,
 177                 .flags          = FMT_FLAGS_M2M,
 178         }, {
 179                 .name           = "JPEG encoded data",
 180                 .fourcc         = V4L2_PIX_FMT_JPEG,
 181                 .color          = S5P_FIMC_JPEG,
 182                 .depth          = { 8 },
 183                 .memplanes      = 1,
 184                 .colplanes      = 1,
 185                 .mbus_code      = V4L2_MBUS_FMT_JPEG_1X8,
 186                 .flags          = FMT_FLAGS_CAM,
 187         },
 188 };
 189
 190 static unsigned int get_m2m_fmt_flags(unsigned int stream_type)
 191 {
 192         if (stream_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
 193                 return FMT_FLAGS_M2M_IN;
 194         else
 195                 return FMT_FLAGS_M2M_OUT;
 196 }
 197
 198 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
 199                             int dw, int dh, int rotation)
 200 {
 201         if (rotation == 90 || rotation == 270)
 202                 swap(dw, dh);
 203
 204         if (!ctx->scaler.enabled)
 205                 return (sw == dw && sh == dh) ? 0 : -EINVAL;
 206
 207         if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
 208                 return -EINVAL;
 209
 210         return 0;
 211 }
 212
 213 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
 214 {
 215         u32 sh = 6;
 216
 217         if (src >= 64 * tar)
 218                 return -EINVAL;
 219
 220         while (sh--) {
 221                 u32 tmp = 1 << sh;
 222                 if (src >= tar * tmp) {
 223                         *shift = sh, *ratio = tmp;
 224                         return 0;
 225                 }
 226         }
 227         *shift = 0, *ratio = 1;
 228         return 0;
 229 }
 230
 231 int fimc_set_scaler_info(struct fimc_ctx *ctx)
 232 {
 233         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 234         struct device *dev = &ctx->fimc_dev->pdev->dev;
 235         struct fimc_scaler *sc = &ctx->scaler;
 236         struct fimc_frame *s_frame = &ctx->s_frame;
 237         struct fimc_frame *d_frame = &ctx->d_frame;
 238         int tx, ty, sx, sy;
 239         int ret;
 240
 241         if (ctx->rotation == 90 || ctx->rotation == 270) {
 242                 ty = d_frame->width;
 243                 tx = d_frame->height;
 244         } else {
 245                 tx = d_frame->width;
 246                 ty = d_frame->height;
 247         }
 248         if (tx <= 0 || ty <= 0) {
 249                 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
 250                 return -EINVAL;
 251         }
 252
 253         sx = s_frame->width;
 254         sy = s_frame->height;
 255         if (sx <= 0 || sy <= 0) {
 256                 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
 257                 return -EINVAL;
 258         }
 259         sc->real_width = sx;
 260         sc->real_height = sy;
 261
 262         ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
 263         if (ret)
 264                 return ret;
 265
 266         ret = fimc_get_scaler_factor(sy, ty,  &sc->pre_vratio, &sc->vfactor);
 267         if (ret)
 268                 return ret;
 269
 270         sc->pre_dst_width = sx / sc->pre_hratio;
 271         sc->pre_dst_height = sy / sc->pre_vratio;
 272
 273         if (variant->has_mainscaler_ext) {
 274                 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
 275                 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
 276         } else {
 277                 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
 278                 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
 279
 280         }
 281
 282         sc->scaleup_h = (tx >= sx) ? 1 : 0;
 283         sc->scaleup_v = (ty >= sy) ? 1 : 0;
 284
 285         /* check to see if input and output size/format differ */
 286         if (s_frame->fmt->color == d_frame->fmt->color
 287                 && s_frame->width == d_frame->width
 288                 && s_frame->height == d_frame->height)
 289                 sc->copy_mode = 1;
 290         else
 291                 sc->copy_mode = 0;
 292
 293         return 0;
 294 }
 295
 296 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
 297 {
 298         struct vb2_buffer *src_vb, *dst_vb;
 299
 300         if (!ctx || !ctx->m2m_ctx)
 301                 return;
 302
 303         src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
 304         dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
 305
 306         if (src_vb && dst_vb) {
 307                 v4l2_m2m_buf_done(src_vb, vb_state);
 308                 v4l2_m2m_buf_done(dst_vb, vb_state);
 309                 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
 310                                     ctx->m2m_ctx);
 311         }
 312 }
 313
 314 /* Complete the transaction which has been scheduled for execution. */
 315 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
 316 {
 317         struct fimc_dev *fimc = ctx->fimc_dev;
 318         int ret;
 319
 320         if (!fimc_m2m_pending(fimc))
 321                 return 0;
 322
 323         fimc_ctx_state_set(FIMC_CTX_SHUT, ctx);
 324
 325         ret = wait_event_timeout(fimc->irq_queue,
 326                            !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
 327                            FIMC_SHUTDOWN_TIMEOUT);
 328
 329         return ret == 0 ? -ETIMEDOUT : ret;
 330 }
 331
 332 static int start_streaming(struct vb2_queue *q, unsigned int count)
 333 {
 334         struct fimc_ctx *ctx = q->drv_priv;
 335         int ret;
 336
 337         ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
 338         return ret > 0 ? 0 : ret;
 339 }
 340
 341 static int stop_streaming(struct vb2_queue *q)
 342 {
 343         struct fimc_ctx *ctx = q->drv_priv;
 344         int ret;
 345
 346         ret = fimc_m2m_shutdown(ctx);
 347         if (ret == -ETIMEDOUT)
 348                 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
 349
 350         pm_runtime_put(&ctx->fimc_dev->pdev->dev);
 351         return 0;
 352 }
 353
 354 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
 355 {
 356         struct fimc_vid_cap *cap = &fimc->vid_cap;
 357         struct fimc_vid_buffer *v_buf;
 358         struct timeval *tv;
 359         struct timespec ts;
 360
 361         if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
 362                 wake_up(&fimc->irq_queue);
 363                 return;
 364         }
 365
 366         if (!list_empty(&cap->active_buf_q) &&
 367             test_bit(ST_CAPT_RUN, &fimc->state) && final) {
 368                 ktime_get_real_ts(&ts);
 369
 370                 v_buf = fimc_active_queue_pop(cap);
 371
 372                 tv = &v_buf->vb.v4l2_buf.timestamp;
 373                 tv->tv_sec = ts.tv_sec;
 374                 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
 375                 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
 376
 377                 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
 378         }
 379
 380         if (!list_empty(&cap->pending_buf_q)) {
 381
 382                 v_buf = fimc_pending_queue_pop(cap);
 383                 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
 384                 v_buf->index = cap->buf_index;
 385
 386                 /* Move the buffer to the capture active queue */
 387                 fimc_active_queue_add(cap, v_buf);
 388
 389                 dbg("next frame: %d, done frame: %d",
 390                     fimc_hw_get_frame_index(fimc), v_buf->index);
 391
 392                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 393                         cap->buf_index = 0;
 394         }
 395
 396         if (cap->active_buf_cnt == 0) {
 397                 if (final)
 398                         clear_bit(ST_CAPT_RUN, &fimc->state);
 399
 400                 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
 401                         cap->buf_index = 0;
 402         } else {
 403                 set_bit(ST_CAPT_RUN, &fimc->state);
 404         }
 405
 406         fimc_capture_config_update(cap->ctx);
 407
 408         dbg("frame: %d, active_buf_cnt: %d",
 409             fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
 410 }
 411
 412 static irqreturn_t fimc_irq_handler(int irq, void *priv)
 413 {
 414         struct fimc_dev *fimc = priv;
 415         struct fimc_vid_cap *cap = &fimc->vid_cap;
 416         struct fimc_ctx *ctx;
 417
 418         fimc_hw_clear_irq(fimc);
 419
 420         spin_lock(&fimc->slock);
 421
 422         if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
 423                 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
 424                         set_bit(ST_M2M_SUSPENDED, &fimc->state);
 425                         wake_up(&fimc->irq_queue);
 426                         goto out;
 427                 }
 428                 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
 429                 if (ctx != NULL) {
 430                         spin_unlock(&fimc->slock);
 431                         fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
 432
 433                         if (ctx->state & FIMC_CTX_SHUT) {
 434                                 ctx->state &= ~FIMC_CTX_SHUT;
 435                                 wake_up(&fimc->irq_queue);
 436                         }
 437                         return IRQ_HANDLED;
 438                 }
 439         } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
 440                 fimc_capture_irq_handler(fimc,
 441                                  !test_bit(ST_CAPT_JPEG, &fimc->state));
 442                 if (cap->active_buf_cnt == 1) {
 443                         fimc_deactivate_capture(fimc);
 444                         clear_bit(ST_CAPT_STREAM, &fimc->state);
 445                 }
 446         }
 447 out:
 448         spin_unlock(&fimc->slock);
 449         return IRQ_HANDLED;
 450 }
 451
 452 /* The color format (colplanes, memplanes) must be already configured. */
 453 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
 454                       struct fimc_frame *frame, struct fimc_addr *paddr)
 455 {
 456         int ret = 0;
 457         u32 pix_size;
 458
 459         if (vb == NULL || frame == NULL)
 460                 return -EINVAL;
 461
 462         pix_size = frame->width * frame->height;
 463
 464         dbg("memplanes= %d, colplanes= %d, pix_size= %d",
 465                 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
 466
 467         paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
 468
 469         if (frame->fmt->memplanes == 1) {
 470                 switch (frame->fmt->colplanes) {
 471                 case 1:
 472                         paddr->cb = 0;
 473                         paddr->cr = 0;
 474                         break;
 475                 case 2:
 476                         /* decompose Y into Y/Cb */
 477                         paddr->cb = (u32)(paddr->y + pix_size);
 478                         paddr->cr = 0;
 479                         break;
 480                 case 3:
 481                         paddr->cb = (u32)(paddr->y + pix_size);
 482                         /* decompose Y into Y/Cb/Cr */
 483                         if (S5P_FIMC_YCBCR420 == frame->fmt->color)
 484                                 paddr->cr = (u32)(paddr->cb
 485                                                 + (pix_size >> 2));
 486                         else /* 422 */
 487                                 paddr->cr = (u32)(paddr->cb
 488                                                 + (pix_size >> 1));
 489                         break;
 490                 default:
 491                         return -EINVAL;
 492                 }
 493         } else {
 494                 if (frame->fmt->memplanes >= 2)
 495                         paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
 496
 497                 if (frame->fmt->memplanes == 3)
 498                         paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
 499         }
 500
 501         dbg("PHYS_ADDR: y= 0x%X  cb= 0x%X cr= 0x%X ret= %d",
 502             paddr->y, paddr->cb, paddr->cr, ret);
 503
 504         return ret;
 505 }
 506
 507 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
 508 void fimc_set_yuv_order(struct fimc_ctx *ctx)
 509 {
 510         /* The one only mode supported in SoC. */
 511         ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
 512         ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
 513
 514         /* Set order for 1 plane input formats. */
 515         switch (ctx->s_frame.fmt->color) {
 516         case S5P_FIMC_YCRYCB422:
 517                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
 518                 break;
 519         case S5P_FIMC_CBYCRY422:
 520                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
 521                 break;
 522         case S5P_FIMC_CRYCBY422:
 523                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
 524                 break;
 525         case S5P_FIMC_YCBYCR422:
 526         default:
 527                 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
 528                 break;
 529         }
 530         dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
 531
 532         switch (ctx->d_frame.fmt->color) {
 533         case S5P_FIMC_YCRYCB422:
 534                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
 535                 break;
 536         case S5P_FIMC_CBYCRY422:
 537                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
 538                 break;
 539         case S5P_FIMC_CRYCBY422:
 540                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
 541                 break;
 542         case S5P_FIMC_YCBYCR422:
 543         default:
 544                 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
 545                 break;
 546         }
 547         dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
 548 }
 549
 550 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
 551 {
 552         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 553         u32 i, depth = 0;
 554
 555         for (i = 0; i < f->fmt->colplanes; i++)
 556                 depth += f->fmt->depth[i];
 557
 558         f->dma_offset.y_h = f->offs_h;
 559         if (!variant->pix_hoff)
 560                 f->dma_offset.y_h *= (depth >> 3);
 561
 562         f->dma_offset.y_v = f->offs_v;
 563
 564         f->dma_offset.cb_h = f->offs_h;
 565         f->dma_offset.cb_v = f->offs_v;
 566
 567         f->dma_offset.cr_h = f->offs_h;
 568         f->dma_offset.cr_v = f->offs_v;
 569
 570         if (!variant->pix_hoff) {
 571                 if (f->fmt->colplanes == 3) {
 572                         f->dma_offset.cb_h >>= 1;
 573                         f->dma_offset.cr_h >>= 1;
 574                 }
 575                 if (f->fmt->color == S5P_FIMC_YCBCR420) {
 576                         f->dma_offset.cb_v >>= 1;
 577                         f->dma_offset.cr_v >>= 1;
 578                 }
 579         }
 580
 581         dbg("in_offset: color= %d, y_h= %d, y_v= %d",
 582             f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
 583 }
 584
 585 static void fimc_dma_run(void *priv)
 586 {
 587         struct vb2_buffer *vb = NULL;
 588         struct fimc_ctx *ctx = priv;
 589         struct fimc_frame *sf, *df;
 590         struct fimc_dev *fimc;
 591         unsigned long flags;
 592         u32 ret;
 593
 594         if (WARN(!ctx, "null hardware context\n"))
 595                 return;
 596
 597         fimc = ctx->fimc_dev;
 598         spin_lock_irqsave(&fimc->slock, flags);
 599         set_bit(ST_M2M_PEND, &fimc->state);
 600         sf = &ctx->s_frame;
 601         df = &ctx->d_frame;
 602
 603         if (ctx->state & FIMC_PARAMS) {
 604                 /* Prepare the DMA offsets for scaler */
 605                 fimc_prepare_dma_offset(ctx, sf);
 606                 fimc_prepare_dma_offset(ctx, df);
 607         }
 608
 609         vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
 610         ret = fimc_prepare_addr(ctx, vb, sf, &sf->paddr);
 611         if (ret)
 612                 goto dma_unlock;
 613
 614         vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 615         ret = fimc_prepare_addr(ctx, vb, df, &df->paddr);
 616         if (ret)
 617                 goto dma_unlock;
 618
 619         /* Reconfigure hardware if the context has changed. */
 620         if (fimc->m2m.ctx != ctx) {
 621                 ctx->state |= FIMC_PARAMS;
 622                 fimc->m2m.ctx = ctx;
 623         }
 624
 625         if (ctx->state & FIMC_PARAMS) {
 626                 fimc_set_yuv_order(ctx);
 627                 fimc_hw_set_input_path(ctx);
 628                 fimc_hw_set_in_dma(ctx);
 629                 ret = fimc_set_scaler_info(ctx);
 630                 if (ret)
 631                         goto dma_unlock;
 632                 fimc_hw_set_prescaler(ctx);
 633                 fimc_hw_set_mainscaler(ctx);
 634                 fimc_hw_set_target_format(ctx);
 635                 fimc_hw_set_rotation(ctx);
 636                 fimc_hw_set_effect(ctx, false);
 637                 fimc_hw_set_out_dma(ctx);
 638                 if (fimc->variant->has_alpha)
 639                         fimc_hw_set_rgb_alpha(ctx);
 640                 fimc_hw_set_output_path(ctx);
 641         }
 642         fimc_hw_set_input_addr(fimc, &sf->paddr);
 643         fimc_hw_set_output_addr(fimc, &df->paddr, -1);
 644
 645         fimc_activate_capture(ctx);
 646
 647         ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
 648                        FIMC_SRC_FMT | FIMC_DST_FMT);
 649         fimc_hw_activate_input_dma(fimc, true);
 650 dma_unlock:
 651         spin_unlock_irqrestore(&fimc->slock, flags);
 652 }
 653
 654 static void fimc_job_abort(void *priv)
 655 {
 656         fimc_m2m_shutdown(priv);
 657 }
 658
 659 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
 660                             unsigned int *num_buffers, unsigned int *num_planes,
 661                             unsigned int sizes[], void *allocators[])
 662 {
 663         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 664         struct fimc_frame *f;
 665         int i;
 666
 667         f = ctx_get_frame(ctx, vq->type);
 668         if (IS_ERR(f))
 669                 return PTR_ERR(f);
 670         /*
 671          * Return number of non-contigous planes (plane buffers)
 672          * depending on the configured color format.
 673          */
 674         if (!f->fmt)
 675                 return -EINVAL;
 676
 677         *num_planes = f->fmt->memplanes;
 678         for (i = 0; i < f->fmt->memplanes; i++) {
 679                 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
 680                 allocators[i] = ctx->fimc_dev->alloc_ctx;
 681         }
 682         return 0;
 683 }
 684
 685 static int fimc_buf_prepare(struct vb2_buffer *vb)
 686 {
 687         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 688         struct fimc_frame *frame;
 689         int i;
 690
 691         frame = ctx_get_frame(ctx, vb->vb2_queue->type);
 692         if (IS_ERR(frame))
 693                 return PTR_ERR(frame);
 694
 695         for (i = 0; i < frame->fmt->memplanes; i++)
 696                 vb2_set_plane_payload(vb, i, frame->payload[i]);
 697
 698         return 0;
 699 }
 700
 701 static void fimc_buf_queue(struct vb2_buffer *vb)
 702 {
 703         struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
 704
 705         dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
 706
 707         if (ctx->m2m_ctx)
 708                 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
 709 }
 710
 711 static void fimc_lock(struct vb2_queue *vq)
 712 {
 713         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 714         mutex_lock(&ctx->fimc_dev->lock);
 715 }
 716
 717 static void fimc_unlock(struct vb2_queue *vq)
 718 {
 719         struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
 720         mutex_unlock(&ctx->fimc_dev->lock);
 721 }
 722
 723 static struct vb2_ops fimc_qops = {
 724         .queue_setup     = fimc_queue_setup,
 725         .buf_prepare     = fimc_buf_prepare,
 726         .buf_queue       = fimc_buf_queue,
 727         .wait_prepare    = fimc_unlock,
 728         .wait_finish     = fimc_lock,
 729         .stop_streaming  = stop_streaming,
 730         .start_streaming = start_streaming,
 731 };
 732
 733 /*
 734  * V4L2 controls handling
 735  */
 736 #define ctrl_to_ctx(__ctrl) \
 737         container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
 738
 739 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
 740 {
 741         struct fimc_dev *fimc = ctx->fimc_dev;
 742         struct samsung_fimc_variant *variant = fimc->variant;
 743         unsigned int flags = FIMC_DST_FMT | FIMC_SRC_FMT;
 744         int ret = 0;
 745
 746         if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
 747                 return 0;
 748
 749         switch (ctrl->id) {
 750         case V4L2_CID_HFLIP:
 751                 ctx->hflip = ctrl->val;
 752                 break;
 753
 754         case V4L2_CID_VFLIP:
 755                 ctx->vflip = ctrl->val;
 756                 break;
 757
 758         case V4L2_CID_ROTATE:
 759                 if (fimc_capture_pending(fimc) ||
 760                     (ctx->state & flags) == flags) {
 761                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
 762                                         ctx->s_frame.height, ctx->d_frame.width,
 763                                         ctx->d_frame.height, ctrl->val);
 764                         if (ret)
 765                                 return -EINVAL;
 766                 }
 767                 if ((ctrl->val == 90 || ctrl->val == 270) &&
 768                     !variant->has_out_rot)
 769                         return -EINVAL;
 770
 771                 ctx->rotation = ctrl->val;
 772                 break;
 773
 774         case V4L2_CID_ALPHA_COMPONENT:
 775                 ctx->d_frame.alpha = ctrl->val;
 776                 break;
 777         }
 778         ctx->state |= FIMC_PARAMS;
 779         set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
 780         return 0;
 781 }
 782
 783 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
 784 {
 785         struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
 786         unsigned long flags;
 787         int ret;
 788
 789         spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
 790         ret = __fimc_s_ctrl(ctx, ctrl);
 791         spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
 792
 793         return ret;
 794 }
 795
 796 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
 797         .s_ctrl = fimc_s_ctrl,
 798 };
 799
 800 int fimc_ctrls_create(struct fimc_ctx *ctx)
 801 {
 802         struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
 803         unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
 804
 805         if (ctx->ctrls_rdy)
 806                 return 0;
 807         v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
 808
 809         ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 810                                         V4L2_CID_ROTATE, 0, 270, 90, 0);
 811         ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 812                                         V4L2_CID_HFLIP, 0, 1, 1, 0);
 813         ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
 814                                         V4L2_CID_VFLIP, 0, 1, 1, 0);
 815         if (variant->has_alpha)
 816                 ctx->ctrl_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
 817                                     &fimc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
 818                                     0, max_alpha, 1, 0);
 819         else
 820                 ctx->ctrl_alpha = NULL;
 821
 822         ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
 823
 824         return ctx->ctrl_handler.error;
 825 }
 826
 827 void fimc_ctrls_delete(struct fimc_ctx *ctx)
 828 {
 829         if (ctx->ctrls_rdy) {
 830                 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
 831                 ctx->ctrls_rdy = false;
 832                 ctx->ctrl_alpha = NULL;
 833         }
 834 }
 835
 836 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
 837 {
 838         unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
 839
 840         if (!ctx->ctrls_rdy)
 841                 return;
 842
 843         mutex_lock(&ctx->ctrl_handler.lock);
 844         v4l2_ctrl_activate(ctx->ctrl_rotate, active);
 845         v4l2_ctrl_activate(ctx->ctrl_hflip, active);
 846         v4l2_ctrl_activate(ctx->ctrl_vflip, active);
 847         if (ctx->ctrl_alpha)
 848                 v4l2_ctrl_activate(ctx->ctrl_alpha, active && has_alpha);
 849
 850         if (active) {
 851                 ctx->rotation = ctx->ctrl_rotate->val;
 852                 ctx->hflip    = ctx->ctrl_hflip->val;
 853                 ctx->vflip    = ctx->ctrl_vflip->val;
 854         } else {
 855                 ctx->rotation = 0;
 856                 ctx->hflip    = 0;
 857                 ctx->vflip    = 0;
 858         }
 859         mutex_unlock(&ctx->ctrl_handler.lock);
 860 }
 861
 862 /* Update maximum value of the alpha color control */
 863 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
 864 {
 865         struct fimc_dev *fimc = ctx->fimc_dev;
 866         struct v4l2_ctrl *ctrl = ctx->ctrl_alpha;
 867
 868         if (ctrl == NULL || !fimc->variant->has_alpha)
 869                 return;
 870
 871         v4l2_ctrl_lock(ctrl);
 872         ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
 873
 874         if (ctrl->cur.val > ctrl->maximum)
 875                 ctrl->cur.val = ctrl->maximum;
 876
 877         v4l2_ctrl_unlock(ctrl);
 878 }
 879
 880 /*
 881  * V4L2 ioctl handlers
 882  */
 883 static int fimc_m2m_querycap(struct file *file, void *fh,
 884                              struct v4l2_capability *cap)
 885 {
 886         struct fimc_ctx *ctx = fh_to_ctx(fh);
 887         struct fimc_dev *fimc = ctx->fimc_dev;
 888
 889         strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
 890         strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
 891         cap->bus_info[0] = 0;
 892         cap->capabilities = V4L2_CAP_STREAMING |
 893                 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
 894
 895         return 0;
 896 }
 897
 898 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
 899                                     struct v4l2_fmtdesc *f)
 900 {
 901         struct fimc_fmt *fmt;
 902
 903         fmt = fimc_find_format(NULL, NULL, get_m2m_fmt_flags(f->type),
 904                                f->index);
 905         if (!fmt)
 906                 return -EINVAL;
 907
 908         strncpy(f->description, fmt->name, sizeof(f->description) - 1);
 909         f->pixelformat = fmt->fourcc;
 910         return 0;
 911 }
 912
 913 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
 914 {
 915         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 916         int i;
 917
 918         pixm->width = frame->o_width;
 919         pixm->height = frame->o_height;
 920         pixm->field = V4L2_FIELD_NONE;
 921         pixm->pixelformat = frame->fmt->fourcc;
 922         pixm->colorspace = V4L2_COLORSPACE_JPEG;
 923         pixm->num_planes = frame->fmt->memplanes;
 924
 925         for (i = 0; i < pixm->num_planes; ++i) {
 926                 int bpl = frame->f_width;
 927                 if (frame->fmt->colplanes == 1) /* packed formats */
 928                         bpl = (bpl * frame->fmt->depth[0]) / 8;
 929                 pixm->plane_fmt[i].bytesperline = bpl;
 930                 pixm->plane_fmt[i].sizeimage = (frame->o_width *
 931                         frame->o_height * frame->fmt->depth[i]) / 8;
 932         }
 933         return 0;
 934 }
 935
 936 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
 937 {
 938         struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
 939
 940         frame->f_width  = pixm->plane_fmt[0].bytesperline;
 941         if (frame->fmt->colplanes == 1)
 942                 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
 943         frame->f_height = pixm->height;
 944         frame->width    = pixm->width;
 945         frame->height   = pixm->height;
 946         frame->o_width  = pixm->width;
 947         frame->o_height = pixm->height;
 948         frame->offs_h   = 0;
 949         frame->offs_v   = 0;
 950 }
 951
 952 /**
 953  * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
 954  * @fmt: fimc pixel format description (input)
 955  * @width: requested pixel width
 956  * @height: requested pixel height
 957  * @pix: multi-plane format to adjust
 958  */
 959 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
 960                                struct v4l2_pix_format_mplane *pix)
 961 {
 962         u32 bytesperline = 0;
 963         int i;
 964
 965         pix->colorspace = V4L2_COLORSPACE_JPEG;
 966         pix->field = V4L2_FIELD_NONE;
 967         pix->num_planes = fmt->memplanes;
 968         pix->pixelformat = fmt->fourcc;
 969         pix->height = height;
 970         pix->width = width;
 971
 972         for (i = 0; i < pix->num_planes; ++i) {
 973                 u32 bpl = pix->plane_fmt[i].bytesperline;
 974                 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
 975
 976                 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
 977                         bpl = pix->width; /* Planar */
 978
 979                 if (fmt->colplanes == 1 && /* Packed */
 980                     (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
 981                         bpl = (pix->width * fmt->depth[0]) / 8;
 982
 983                 if (i == 0) /* Same bytesperline for each plane. */
 984                         bytesperline = bpl;
 985
 986                 pix->plane_fmt[i].bytesperline = bytesperline;
 987                 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
 988         }
 989 }
 990
 991 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
 992                                  struct v4l2_format *f)
 993 {
 994         struct fimc_ctx *ctx = fh_to_ctx(fh);
 995         struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
 996
 997         if (IS_ERR(frame))
 998                 return PTR_ERR(frame);
 999
1000         return fimc_fill_format(frame, f);
1001 }
1002
1003 /**
1004  * fimc_find_format - lookup fimc color format by fourcc or media bus format
1005  * @pixelformat: fourcc to match, ignored if null
1006  * @mbus_code: media bus code to match, ignored if null
1007  * @mask: the color flags to match
1008  * @index: offset in the fimc_formats array, ignored if negative
1009  */
1010 struct fimc_fmt *fimc_find_format(u32 *pixelformat, u32 *mbus_code,
1011                                   unsigned int mask, int index)
1012 {
1013         struct fimc_fmt *fmt, *def_fmt = NULL;
1014         unsigned int i;
1015         int id = 0;
1016
1017         if (index >= ARRAY_SIZE(fimc_formats))
1018                 return NULL;
1019
1020         for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
1021                 fmt = &fimc_formats[i];
1022                 if (!(fmt->flags & mask))
1023                         continue;
1024                 if (pixelformat && fmt->fourcc == *pixelformat)
1025                         return fmt;
1026                 if (mbus_code && fmt->mbus_code == *mbus_code)
1027                         return fmt;
1028                 if (index == id)
1029                         def_fmt = fmt;
1030                 id++;
1031         }
1032         return def_fmt;
1033 }
1034
1035 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1036 {
1037         struct fimc_dev *fimc = ctx->fimc_dev;
1038         struct samsung_fimc_variant *variant = fimc->variant;
1039         struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1040         struct fimc_fmt *fmt;
1041         u32 max_w, mod_x, mod_y;
1042
1043         if (!IS_M2M(f->type))
1044                 return -EINVAL;
1045
1046         dbg("w: %d, h: %d", pix->width, pix->height);
1047
1048         fmt = fimc_find_format(&pix->pixelformat, NULL,
1049                                get_m2m_fmt_flags(f->type), 0);
1050         if (WARN(fmt == NULL, "Pixel format lookup failed"))
1051                 return -EINVAL;
1052
1053         if (pix->field == V4L2_FIELD_ANY)
1054                 pix->field = V4L2_FIELD_NONE;
1055         else if (pix->field != V4L2_FIELD_NONE)
1056                 return -EINVAL;
1057
1058         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1059                 max_w = variant->pix_limit->scaler_dis_w;
1060                 mod_x = ffs(variant->min_inp_pixsize) - 1;
1061         } else {
1062                 max_w = variant->pix_limit->out_rot_dis_w;
1063                 mod_x = ffs(variant->min_out_pixsize) - 1;
1064         }
1065
1066         if (tiled_fmt(fmt)) {
1067                 mod_x = 6; /* 64 x 32 pixels tile */
1068                 mod_y = 5;
1069         } else {
1070                 if (variant->min_vsize_align == 1)
1071                         mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1072                 else
1073                         mod_y = ffs(variant->min_vsize_align) - 1;
1074         }
1075
1076         v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1077                 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1078
1079         fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1080         return 0;
1081 }
1082
1083 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1084                                    struct v4l2_format *f)
1085 {
1086         struct fimc_ctx *ctx = fh_to_ctx(fh);
1087
1088         return fimc_try_fmt_mplane(ctx, f);
1089 }
1090
1091 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1092                                  struct v4l2_format *f)
1093 {
1094         struct fimc_ctx *ctx = fh_to_ctx(fh);
1095         struct fimc_dev *fimc = ctx->fimc_dev;
1096         struct vb2_queue *vq;
1097         struct fimc_frame *frame;
1098         struct v4l2_pix_format_mplane *pix;
1099         int i, ret = 0;
1100
1101         ret = fimc_try_fmt_mplane(ctx, f);
1102         if (ret)
1103                 return ret;
1104
1105         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1106
1107         if (vb2_is_busy(vq)) {
1108                 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1109                 return -EBUSY;
1110         }
1111
1112         if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1113                 frame = &ctx->s_frame;
1114         else
1115                 frame = &ctx->d_frame;
1116
1117         pix = &f->fmt.pix_mp;
1118         frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1119                                       get_m2m_fmt_flags(f->type), 0);
1120         if (!frame->fmt)
1121                 return -EINVAL;
1122
1123         /* Update RGB Alpha control state and value range */
1124         fimc_alpha_ctrl_update(ctx);
1125
1126         for (i = 0; i < frame->fmt->colplanes; i++) {
1127                 frame->payload[i] =
1128                         (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1129         }
1130
1131         fimc_fill_frame(frame, f);
1132
1133         ctx->scaler.enabled = 1;
1134
1135         if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1136                 fimc_ctx_state_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1137         else
1138                 fimc_ctx_state_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1139
1140         dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1141
1142         return 0;
1143 }
1144
1145 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1146                             struct v4l2_requestbuffers *reqbufs)
1147 {
1148         struct fimc_ctx *ctx = fh_to_ctx(fh);
1149
1150         return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1151 }
1152
1153 static int fimc_m2m_querybuf(struct file *file, void *fh,
1154                              struct v4l2_buffer *buf)
1155 {
1156         struct fimc_ctx *ctx = fh_to_ctx(fh);
1157
1158         return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1159 }
1160
1161 static int fimc_m2m_qbuf(struct file *file, void *fh,
1162                          struct v4l2_buffer *buf)
1163 {
1164         struct fimc_ctx *ctx = fh_to_ctx(fh);
1165
1166         return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1167 }
1168
1169 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1170                           struct v4l2_buffer *buf)
1171 {
1172         struct fimc_ctx *ctx = fh_to_ctx(fh);
1173
1174         return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1175 }
1176
1177 static int fimc_m2m_streamon(struct file *file, void *fh,
1178                              enum v4l2_buf_type type)
1179 {
1180         struct fimc_ctx *ctx = fh_to_ctx(fh);
1181
1182         /* The source and target color format need to be set */
1183         if (V4L2_TYPE_IS_OUTPUT(type)) {
1184                 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1185                         return -EINVAL;
1186         } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1187                 return -EINVAL;
1188         }
1189
1190         return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1191 }
1192
1193 static int fimc_m2m_streamoff(struct file *file, void *fh,
1194                             enum v4l2_buf_type type)
1195 {
1196         struct fimc_ctx *ctx = fh_to_ctx(fh);
1197
1198         return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1199 }
1200
1201 static int fimc_m2m_cropcap(struct file *file, void *fh,
1202                             struct v4l2_cropcap *cr)
1203 {
1204         struct fimc_ctx *ctx = fh_to_ctx(fh);
1205         struct fimc_frame *frame;
1206
1207         frame = ctx_get_frame(ctx, cr->type);
1208         if (IS_ERR(frame))
1209                 return PTR_ERR(frame);
1210
1211         cr->bounds.left         = 0;
1212         cr->bounds.top          = 0;
1213         cr->bounds.width        = frame->o_width;
1214         cr->bounds.height       = frame->o_height;
1215         cr->defrect             = cr->bounds;
1216
1217         return 0;
1218 }
1219
1220 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1221 {
1222         struct fimc_ctx *ctx = fh_to_ctx(fh);
1223         struct fimc_frame *frame;
1224
1225         frame = ctx_get_frame(ctx, cr->type);
1226         if (IS_ERR(frame))
1227                 return PTR_ERR(frame);
1228
1229         cr->c.left = frame->offs_h;
1230         cr->c.top = frame->offs_v;
1231         cr->c.width = frame->width;
1232         cr->c.height = frame->height;
1233
1234         return 0;
1235 }
1236
1237 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1238 {
1239         struct fimc_dev *fimc = ctx->fimc_dev;
1240         struct fimc_frame *f;
1241         u32 min_size, halign, depth = 0;
1242         int i;
1243
1244         if (cr->c.top < 0 || cr->c.left < 0) {
1245                 v4l2_err(fimc->m2m.vfd,
1246                         "doesn't support negative values for top & left\n");
1247                 return -EINVAL;
1248         }
1249         if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1250                 f = &ctx->d_frame;
1251         else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1252                 f = &ctx->s_frame;
1253         else
1254                 return -EINVAL;
1255
1256         min_size = (f == &ctx->s_frame) ?
1257                 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1258
1259         /* Get pixel alignment constraints. */
1260         if (fimc->variant->min_vsize_align == 1)
1261                 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1262         else
1263                 halign = ffs(fimc->variant->min_vsize_align) - 1;
1264
1265         for (i = 0; i < f->fmt->colplanes; i++)
1266                 depth += f->fmt->depth[i];
1267
1268         v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1269                               ffs(min_size) - 1,
1270                               &cr->c.height, min_size, f->o_height,
1271                               halign, 64/(ALIGN(depth, 8)));
1272
1273         /* adjust left/top if cropping rectangle is out of bounds */
1274         if (cr->c.left + cr->c.width > f->o_width)
1275                 cr->c.left = f->o_width - cr->c.width;
1276         if (cr->c.top + cr->c.height > f->o_height)
1277                 cr->c.top = f->o_height - cr->c.height;
1278
1279         cr->c.left = round_down(cr->c.left, min_size);
1280         cr->c.top  = round_down(cr->c.top, fimc->variant->hor_offs_align);
1281
1282         dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1283             cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1284             f->f_width, f->f_height);
1285
1286         return 0;
1287 }
1288
1289 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1290 {
1291         struct fimc_ctx *ctx = fh_to_ctx(fh);
1292         struct fimc_dev *fimc = ctx->fimc_dev;
1293         struct fimc_frame *f;
1294         int ret;
1295
1296         ret = fimc_m2m_try_crop(ctx, cr);
1297         if (ret)
1298                 return ret;
1299
1300         f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1301                 &ctx->s_frame : &ctx->d_frame;
1302
1303         /* Check to see if scaling ratio is within supported range */
1304         if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1305                 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1306                         ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1307                                         cr->c.height, ctx->d_frame.width,
1308                                         ctx->d_frame.height, ctx->rotation);
1309                 } else {
1310                         ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1311                                         ctx->s_frame.height, cr->c.width,
1312                                         cr->c.height, ctx->rotation);
1313                 }
1314                 if (ret) {
1315                         v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1316                         return -EINVAL;
1317                 }
1318         }
1319
1320         f->offs_h = cr->c.left;
1321         f->offs_v = cr->c.top;
1322         f->width  = cr->c.width;
1323         f->height = cr->c.height;
1324
1325         fimc_ctx_state_set(FIMC_PARAMS, ctx);
1326
1327         return 0;
1328 }
1329
1330 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1331         .vidioc_querycap                = fimc_m2m_querycap,
1332
1333         .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1334         .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1335
1336         .vidioc_g_fmt_vid_cap_mplane    = fimc_m2m_g_fmt_mplane,
1337         .vidioc_g_fmt_vid_out_mplane    = fimc_m2m_g_fmt_mplane,
1338
1339         .vidioc_try_fmt_vid_cap_mplane  = fimc_m2m_try_fmt_mplane,
1340         .vidioc_try_fmt_vid_out_mplane  = fimc_m2m_try_fmt_mplane,
1341
1342         .vidioc_s_fmt_vid_cap_mplane    = fimc_m2m_s_fmt_mplane,
1343         .vidioc_s_fmt_vid_out_mplane    = fimc_m2m_s_fmt_mplane,
1344
1345         .vidioc_reqbufs                 = fimc_m2m_reqbufs,
1346         .vidioc_querybuf                = fimc_m2m_querybuf,
1347
1348         .vidioc_qbuf                    = fimc_m2m_qbuf,
1349         .vidioc_dqbuf                   = fimc_m2m_dqbuf,
1350
1351         .vidioc_streamon                = fimc_m2m_streamon,
1352         .vidioc_streamoff               = fimc_m2m_streamoff,
1353
1354         .vidioc_g_crop                  = fimc_m2m_g_crop,
1355         .vidioc_s_crop                  = fimc_m2m_s_crop,
1356         .vidioc_cropcap                 = fimc_m2m_cropcap
1357
1358 };
1359
1360 static int queue_init(void *priv, struct vb2_queue *src_vq,
1361                       struct vb2_queue *dst_vq)
1362 {
1363         struct fimc_ctx *ctx = priv;
1364         int ret;
1365
1366         memset(src_vq, 0, sizeof(*src_vq));
1367         src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1368         src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1369         src_vq->drv_priv = ctx;
1370         src_vq->ops = &fimc_qops;
1371         src_vq->mem_ops = &vb2_dma_contig_memops;
1372         src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1373
1374         ret = vb2_queue_init(src_vq);
1375         if (ret)
1376                 return ret;
1377
1378         memset(dst_vq, 0, sizeof(*dst_vq));
1379         dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1380         dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1381         dst_vq->drv_priv = ctx;
1382         dst_vq->ops = &fimc_qops;
1383         dst_vq->mem_ops = &vb2_dma_contig_memops;
1384         dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1385
1386         return vb2_queue_init(dst_vq);
1387 }
1388
1389 static int fimc_m2m_open(struct file *file)
1390 {
1391         struct fimc_dev *fimc = video_drvdata(file);
1392         struct fimc_ctx *ctx;
1393         int ret;
1394
1395         dbg("pid: %d, state: 0x%lx, refcnt: %d",
1396                 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1397
1398         /*
1399          * Return if the corresponding video capture node
1400          * is already opened.
1401          */
1402         if (fimc->vid_cap.refcnt > 0)
1403                 return -EBUSY;
1404
1405         ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1406         if (!ctx)
1407                 return -ENOMEM;
1408         v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1409         ctx->fimc_dev = fimc;
1410
1411         /* Default color format */
1412         ctx->s_frame.fmt = &fimc_formats[0];
1413         ctx->d_frame.fmt = &fimc_formats[0];
1414
1415         ret = fimc_ctrls_create(ctx);
1416         if (ret)
1417                 goto error_fh;
1418
1419         /* Use separate control handler per file handle */
1420         ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1421         file->private_data = &ctx->fh;
1422         v4l2_fh_add(&ctx->fh);
1423
1424         /* Setup the device context for memory-to-memory mode */
1425         ctx->state = FIMC_CTX_M2M;
1426         ctx->flags = 0;
1427         ctx->in_path = FIMC_DMA;
1428         ctx->out_path = FIMC_DMA;
1429
1430         ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1431         if (IS_ERR(ctx->m2m_ctx)) {
1432                 ret = PTR_ERR(ctx->m2m_ctx);
1433                 goto error_c;
1434         }
1435
1436         if (fimc->m2m.refcnt++ == 0)
1437                 set_bit(ST_M2M_RUN, &fimc->state);
1438         return 0;
1439
1440 error_c:
1441         fimc_ctrls_delete(ctx);
1442 error_fh:
1443         v4l2_fh_del(&ctx->fh);
1444         v4l2_fh_exit(&ctx->fh);
1445         kfree(ctx);
1446         return ret;
1447 }
1448
1449 static int fimc_m2m_release(struct file *file)
1450 {
1451         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1452         struct fimc_dev *fimc = ctx->fimc_dev;
1453
1454         dbg("pid: %d, state: 0x%lx, refcnt= %d",
1455                 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1456
1457         v4l2_m2m_ctx_release(ctx->m2m_ctx);
1458         fimc_ctrls_delete(ctx);
1459         v4l2_fh_del(&ctx->fh);
1460         v4l2_fh_exit(&ctx->fh);
1461
1462         if (--fimc->m2m.refcnt <= 0)
1463                 clear_bit(ST_M2M_RUN, &fimc->state);
1464         kfree(ctx);
1465         return 0;
1466 }
1467
1468 static unsigned int fimc_m2m_poll(struct file *file,
1469                                   struct poll_table_struct *wait)
1470 {
1471         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1472
1473         return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1474 }
1475
1476
1477 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1478 {
1479         struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1480
1481         return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1482 }
1483
1484 static const struct v4l2_file_operations fimc_m2m_fops = {
1485         .owner          = THIS_MODULE,
1486         .open           = fimc_m2m_open,
1487         .release        = fimc_m2m_release,
1488         .poll           = fimc_m2m_poll,
1489         .unlocked_ioctl = video_ioctl2,
1490         .mmap           = fimc_m2m_mmap,
1491 };
1492
1493 static struct v4l2_m2m_ops m2m_ops = {
1494         .device_run     = fimc_dma_run,
1495         .job_abort      = fimc_job_abort,
1496 };
1497
1498 int fimc_register_m2m_device(struct fimc_dev *fimc,
1499                              struct v4l2_device *v4l2_dev)
1500 {
1501         struct video_device *vfd;
1502         struct platform_device *pdev;
1503         int ret = 0;
1504
1505         if (!fimc)
1506                 return -ENODEV;
1507
1508         pdev = fimc->pdev;
1509         fimc->v4l2_dev = v4l2_dev;
1510
1511         vfd = video_device_alloc();
1512         if (!vfd) {
1513                 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1514                 return -ENOMEM;
1515         }
1516
1517         vfd->fops       = &fimc_m2m_fops;
1518         vfd->ioctl_ops  = &fimc_m2m_ioctl_ops;
1519         vfd->v4l2_dev   = v4l2_dev;
1520         vfd->minor      = -1;
1521         vfd->release    = video_device_release;
1522         vfd->lock       = &fimc->lock;
1523
1524         snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1525         video_set_drvdata(vfd, fimc);
1526
1527         fimc->m2m.vfd = vfd;
1528         fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1529         if (IS_ERR(fimc->m2m.m2m_dev)) {
1530                 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1531                 ret = PTR_ERR(fimc->m2m.m2m_dev);
1532                 goto err_init;
1533         }
1534
1535         ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1536         if (!ret)
1537                 return 0;
1538
1539         v4l2_m2m_release(fimc->m2m.m2m_dev);
1540 err_init:
1541         video_device_release(fimc->m2m.vfd);
1542         return ret;
1543 }
1544
1545 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1546 {
1547         if (!fimc)
1548                 return;
1549
1550         if (fimc->m2m.m2m_dev)
1551                 v4l2_m2m_release(fimc->m2m.m2m_dev);
1552         if (fimc->m2m.vfd) {
1553                 media_entity_cleanup(&fimc->m2m.vfd->entity);
1554                 /* Can also be called if video device wasn't registered */
1555                 video_unregister_device(fimc->m2m.vfd);
1556         }
1557 }
1558
1559 static void fimc_clk_put(struct fimc_dev *fimc)
1560 {
1561         int i;
1562         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
1563                 if (IS_ERR_OR_NULL(fimc->clock[i]))
1564                         continue;
1565                 clk_unprepare(fimc->clock[i]);
1566                 clk_put(fimc->clock[i]);
1567                 fimc->clock[i] = NULL;
1568         }
1569 }
1570
1571 static int fimc_clk_get(struct fimc_dev *fimc)
1572 {
1573         int i, ret;
1574
1575         for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
1576                 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1577                 if (IS_ERR(fimc->clock[i]))
1578                         goto err;
1579                 ret = clk_prepare(fimc->clock[i]);
1580                 if (ret < 0) {
1581                         clk_put(fimc->clock[i]);
1582                         fimc->clock[i] = NULL;
1583                         goto err;
1584                 }
1585         }
1586         return 0;
1587 err:
1588         fimc_clk_put(fimc);
1589         dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
1590                 fimc_clocks[i]);
1591         return -ENXIO;
1592 }
1593
1594 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1595 {
1596         unsigned long flags;
1597         int timeout;
1598
1599         spin_lock_irqsave(&fimc->slock, flags);
1600         if (!fimc_m2m_pending(fimc)) {
1601                 spin_unlock_irqrestore(&fimc->slock, flags);
1602                 return 0;
1603         }
1604         clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1605         set_bit(ST_M2M_SUSPENDING, &fimc->state);
1606         spin_unlock_irqrestore(&fimc->slock, flags);
1607
1608         timeout = wait_event_timeout(fimc->irq_queue,
1609                              test_bit(ST_M2M_SUSPENDED, &fimc->state),
1610                              FIMC_SHUTDOWN_TIMEOUT);
1611
1612         clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1613         return timeout == 0 ? -EAGAIN : 0;
1614 }
1615
1616 static int fimc_m2m_resume(struct fimc_dev *fimc)
1617 {
1618         unsigned long flags;
1619
1620         spin_lock_irqsave(&fimc->slock, flags);
1621         /* Clear for full H/W setup in first run after resume */
1622         fimc->m2m.ctx = NULL;
1623         spin_unlock_irqrestore(&fimc->slock, flags);
1624
1625         if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1626                 fimc_m2m_job_finish(fimc->m2m.ctx,
1627                                     VB2_BUF_STATE_ERROR);
1628         return 0;
1629 }
1630
1631 static int fimc_probe(struct platform_device *pdev)
1632 {
1633         struct fimc_dev *fimc;
1634         struct resource *res;
1635         struct samsung_fimc_driverdata *drv_data;
1636         struct s5p_platform_fimc *pdata;
1637         int ret = 0;
1638
1639         drv_data = (struct samsung_fimc_driverdata *)
1640                 platform_get_device_id(pdev)->driver_data;
1641
1642         if (pdev->id >= drv_data->num_entities) {
1643                 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1644                         pdev->id);
1645                 return -EINVAL;
1646         }
1647
1648         fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
1649         if (!fimc)
1650                 return -ENOMEM;
1651
1652         fimc->id = pdev->id;
1653
1654         fimc->variant = drv_data->variant[fimc->id];
1655         fimc->pdev = pdev;
1656         pdata = pdev->dev.platform_data;
1657         fimc->pdata = pdata;
1658
1659         init_waitqueue_head(&fimc->irq_queue);
1660         spin_lock_init(&fimc->slock);
1661         mutex_init(&fimc->lock);
1662
1663         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1664         fimc->regs = devm_request_and_ioremap(&pdev->dev, res);
1665         if (fimc->regs == NULL) {
1666                 dev_err(&pdev->dev, "Failed to obtain io memory\n");
1667                 return -ENOENT;
1668         }
1669
1670         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1671         if (res == NULL) {
1672                 dev_err(&pdev->dev, "Failed to get IRQ resource\n");
1673                 return -ENXIO;
1674         }
1675
1676         ret = fimc_clk_get(fimc);
1677         if (ret)
1678                 return ret;
1679         clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1680         clk_enable(fimc->clock[CLK_BUS]);
1681
1682         platform_set_drvdata(pdev, fimc);
1683
1684         ret = devm_request_irq(&pdev->dev, res->start, fimc_irq_handler,
1685                                0, pdev->name, fimc);
1686         if (ret) {
1687                 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1688                 goto err_clk;
1689         }
1690
1691         pm_runtime_enable(&pdev->dev);
1692         ret = pm_runtime_get_sync(&pdev->dev);
1693         if (ret < 0)
1694                 goto err_clk;
1695         /* Initialize contiguous memory allocator */
1696         fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1697         if (IS_ERR(fimc->alloc_ctx)) {
1698                 ret = PTR_ERR(fimc->alloc_ctx);
1699                 goto err_pm;
1700         }
1701
1702         dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1703
1704         pm_runtime_put(&pdev->dev);
1705         return 0;
1706
1707 err_pm:
1708         pm_runtime_put(&pdev->dev);
1709 err_clk:
1710         fimc_clk_put(fimc);
1711         return ret;
1712 }
1713
1714 static int fimc_runtime_resume(struct device *dev)
1715 {
1716         struct fimc_dev *fimc = dev_get_drvdata(dev);
1717
1718         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1719
1720         /* Enable clocks and perform basic initalization */
1721         clk_enable(fimc->clock[CLK_GATE]);
1722         fimc_hw_reset(fimc);
1723
1724         /* Resume the capture or mem-to-mem device */
1725         if (fimc_capture_busy(fimc))
1726                 return fimc_capture_resume(fimc);
1727
1728         return fimc_m2m_resume(fimc);
1729 }
1730
1731 static int fimc_runtime_suspend(struct device *dev)
1732 {
1733         struct fimc_dev *fimc = dev_get_drvdata(dev);
1734         int ret = 0;
1735
1736         if (fimc_capture_busy(fimc))
1737                 ret = fimc_capture_suspend(fimc);
1738         else
1739                 ret = fimc_m2m_suspend(fimc);
1740         if (!ret)
1741                 clk_disable(fimc->clock[CLK_GATE]);
1742
1743         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1744         return ret;
1745 }
1746
1747 #ifdef CONFIG_PM_SLEEP
1748 static int fimc_resume(struct device *dev)
1749 {
1750         struct fimc_dev *fimc = dev_get_drvdata(dev);
1751         unsigned long flags;
1752
1753         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1754
1755         /* Do not resume if the device was idle before system suspend */
1756         spin_lock_irqsave(&fimc->slock, flags);
1757         if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1758             (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1759                 spin_unlock_irqrestore(&fimc->slock, flags);
1760                 return 0;
1761         }
1762         fimc_hw_reset(fimc);
1763         spin_unlock_irqrestore(&fimc->slock, flags);
1764
1765         if (fimc_capture_busy(fimc))
1766                 return fimc_capture_resume(fimc);
1767
1768         return fimc_m2m_resume(fimc);
1769 }
1770
1771 static int fimc_suspend(struct device *dev)
1772 {
1773         struct fimc_dev *fimc = dev_get_drvdata(dev);
1774
1775         dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1776
1777         if (test_and_set_bit(ST_LPM, &fimc->state))
1778                 return 0;
1779         if (fimc_capture_busy(fimc))
1780                 return fimc_capture_suspend(fimc);
1781
1782         return fimc_m2m_suspend(fimc);
1783 }
1784 #endif /* CONFIG_PM_SLEEP */
1785
1786 static int __devexit fimc_remove(struct platform_device *pdev)
1787 {
1788         struct fimc_dev *fimc = platform_get_drvdata(pdev);
1789
1790         pm_runtime_disable(&pdev->dev);
1791         pm_runtime_set_suspended(&pdev->dev);
1792
1793         vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1794
1795         clk_disable(fimc->clock[CLK_BUS]);
1796         fimc_clk_put(fimc);
1797
1798         dev_info(&pdev->dev, "driver unloaded\n");
1799         return 0;
1800 }
1801
1802 /* Image pixel limits, similar across several FIMC HW revisions. */
1803 static struct fimc_pix_limit s5p_pix_limit[4] = {
1804         [0] = {
1805                 .scaler_en_w    = 3264,
1806                 .scaler_dis_w   = 8192,
1807                 .in_rot_en_h    = 1920,
1808                 .in_rot_dis_w   = 8192,
1809                 .out_rot_en_w   = 1920,
1810                 .out_rot_dis_w  = 4224,
1811         },
1812         [1] = {
1813                 .scaler_en_w    = 4224,
1814                 .scaler_dis_w   = 8192,
1815                 .in_rot_en_h    = 1920,
1816                 .in_rot_dis_w   = 8192,
1817                 .out_rot_en_w   = 1920,
1818                 .out_rot_dis_w  = 4224,
1819         },
1820         [2] = {
1821                 .scaler_en_w    = 1920,
1822                 .scaler_dis_w   = 8192,
1823                 .in_rot_en_h    = 1280,
1824                 .in_rot_dis_w   = 8192,
1825                 .out_rot_en_w   = 1280,
1826                 .out_rot_dis_w  = 1920,
1827         },
1828         [3] = {
1829                 .scaler_en_w    = 1920,
1830                 .scaler_dis_w   = 8192,
1831                 .in_rot_en_h    = 1366,
1832                 .in_rot_dis_w   = 8192,
1833                 .out_rot_en_w   = 1366,
1834                 .out_rot_dis_w  = 1920,
1835         },
1836 };
1837
1838 static struct samsung_fimc_variant fimc0_variant_s5p = {
1839         .has_inp_rot     = 1,
1840         .has_out_rot     = 1,
1841         .has_cam_if      = 1,
1842         .min_inp_pixsize = 16,
1843         .min_out_pixsize = 16,
1844         .hor_offs_align  = 8,
1845         .min_vsize_align = 16,
1846         .out_buf_count   = 4,
1847         .pix_limit       = &s5p_pix_limit[0],
1848 };
1849
1850 static struct samsung_fimc_variant fimc2_variant_s5p = {
1851         .has_cam_if      = 1,
1852         .min_inp_pixsize = 16,
1853         .min_out_pixsize = 16,
1854         .hor_offs_align  = 8,
1855         .min_vsize_align = 16,
1856         .out_buf_count   = 4,
1857         .pix_limit = &s5p_pix_limit[1],
1858 };
1859
1860 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1861         .pix_hoff        = 1,
1862         .has_inp_rot     = 1,
1863         .has_out_rot     = 1,
1864         .has_cam_if      = 1,
1865         .min_inp_pixsize = 16,
1866         .min_out_pixsize = 16,
1867         .hor_offs_align  = 8,
1868         .min_vsize_align = 16,
1869         .out_buf_count   = 4,
1870         .pix_limit       = &s5p_pix_limit[1],
1871 };
1872
1873 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1874         .pix_hoff        = 1,
1875         .has_inp_rot     = 1,
1876         .has_out_rot     = 1,
1877         .has_cam_if      = 1,
1878         .has_mainscaler_ext = 1,
1879         .min_inp_pixsize = 16,
1880         .min_out_pixsize = 16,
1881         .hor_offs_align  = 1,
1882         .min_vsize_align = 1,
1883         .out_buf_count   = 4,
1884         .pix_limit       = &s5p_pix_limit[2],
1885 };
1886
1887 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1888         .has_cam_if      = 1,
1889         .pix_hoff        = 1,
1890         .min_inp_pixsize = 16,
1891         .min_out_pixsize = 16,
1892         .hor_offs_align  = 8,
1893         .min_vsize_align = 16,
1894         .out_buf_count   = 4,
1895         .pix_limit       = &s5p_pix_limit[2],
1896 };
1897
1898 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1899         .pix_hoff        = 1,
1900         .has_inp_rot     = 1,
1901         .has_out_rot     = 1,
1902         .has_cam_if      = 1,
1903         .has_cistatus2   = 1,
1904         .has_mainscaler_ext = 1,
1905         .has_alpha       = 1,
1906         .min_inp_pixsize = 16,
1907         .min_out_pixsize = 16,
1908         .hor_offs_align  = 2,
1909         .min_vsize_align = 1,
1910         .out_buf_count   = 32,
1911         .pix_limit       = &s5p_pix_limit[1],
1912 };
1913
1914 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1915         .pix_hoff        = 1,
1916         .has_cam_if      = 1,
1917         .has_cistatus2   = 1,
1918         .has_mainscaler_ext = 1,
1919         .has_alpha       = 1,
1920         .min_inp_pixsize = 16,
1921         .min_out_pixsize = 16,
1922         .hor_offs_align  = 2,
1923         .min_vsize_align = 1,
1924         .out_buf_count   = 32,
1925         .pix_limit       = &s5p_pix_limit[3],
1926 };
1927
1928 /* S5PC100 */
1929 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1930         .variant = {
1931                 [0] = &fimc0_variant_s5p,
1932                 [1] = &fimc0_variant_s5p,
1933                 [2] = &fimc2_variant_s5p,
1934         },
1935         .num_entities = 3,
1936         .lclk_frequency = 133000000UL,
1937 };
1938
1939 /* S5PV210, S5PC110 */
1940 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1941         .variant = {
1942                 [0] = &fimc0_variant_s5pv210,
1943                 [1] = &fimc1_variant_s5pv210,
1944                 [2] = &fimc2_variant_s5pv210,
1945         },
1946         .num_entities = 3,
1947         .lclk_frequency = 166000000UL,
1948 };
1949
1950 /* S5PV310, S5PC210 */
1951 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1952         .variant = {
1953                 [0] = &fimc0_variant_exynos4,
1954                 [1] = &fimc0_variant_exynos4,
1955                 [2] = &fimc0_variant_exynos4,
1956                 [3] = &fimc3_variant_exynos4,
1957         },
1958         .num_entities = 4,
1959         .lclk_frequency = 166000000UL,
1960 };
1961
1962 static struct platform_device_id fimc_driver_ids[] = {
1963         {
1964                 .name           = "s5p-fimc",
1965                 .driver_data    = (unsigned long)&fimc_drvdata_s5p,
1966         }, {
1967                 .name           = "s5pv210-fimc",
1968                 .driver_data    = (unsigned long)&fimc_drvdata_s5pv210,
1969         }, {
1970                 .name           = "exynos4-fimc",
1971                 .driver_data    = (unsigned long)&fimc_drvdata_exynos4,
1972         },
1973         {},
1974 };
1975 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1976
1977 static const struct dev_pm_ops fimc_pm_ops = {
1978         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1979         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1980 };
1981
1982 static struct platform_driver fimc_driver = {
1983         .probe          = fimc_probe,
1984         .remove         = __devexit_p(fimc_remove),
1985         .id_table       = fimc_driver_ids,
1986         .driver = {
1987                 .name   = FIMC_MODULE_NAME,
1988                 .owner  = THIS_MODULE,
1989                 .pm     = &fimc_pm_ops,
1990         }
1991 };
1992
1993 int __init fimc_register_driver(void)
1994 {
1995         return platform_driver_register(&fimc_driver);
1996 }
1997
1998 void __exit fimc_unregister_driver(void)
1999 {
2000         platform_driver_unregister(&fimc_driver);
2001 }