2 * Samsung S5P/EXYNOS4 SoC series camera interface (video postprocessor) driver
4 * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
5 * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published
9 * by the Free Software Foundation, either version 2 of the License,
10 * or (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/errno.h>
17 #include <linux/bug.h>
18 #include <linux/interrupt.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/list.h>
24 #include <linux/slab.h>
25 #include <linux/clk.h>
26 #include <media/v4l2-ioctl.h>
27 #include <media/videobuf2-core.h>
28 #include <media/videobuf2-dma-contig.h>
30 #include "fimc-core.h"
31 #include "fimc-mdevice.h"
33 static char *fimc_clocks[MAX_FIMC_CLOCKS] = {
37 static struct fimc_fmt fimc_formats[] = {
40 .fourcc = V4L2_PIX_FMT_RGB565,
42 .color = S5P_FIMC_RGB565,
45 .flags = FMT_FLAGS_M2M,
48 .fourcc = V4L2_PIX_FMT_BGR666,
50 .color = S5P_FIMC_RGB666,
53 .flags = FMT_FLAGS_M2M,
55 .name = "ARGB8888, 32 bpp",
56 .fourcc = V4L2_PIX_FMT_RGB32,
58 .color = S5P_FIMC_RGB888,
61 .flags = FMT_FLAGS_M2M | FMT_HAS_ALPHA,
64 .fourcc = V4L2_PIX_FMT_RGB555,
66 .color = S5P_FIMC_RGB555,
69 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
72 .fourcc = V4L2_PIX_FMT_RGB444,
74 .color = S5P_FIMC_RGB444,
77 .flags = FMT_FLAGS_M2M_OUT | FMT_HAS_ALPHA,
79 .name = "YUV 4:2:2 packed, YCbYCr",
80 .fourcc = V4L2_PIX_FMT_YUYV,
82 .color = S5P_FIMC_YCBYCR422,
85 .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
86 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
88 .name = "YUV 4:2:2 packed, CbYCrY",
89 .fourcc = V4L2_PIX_FMT_UYVY,
91 .color = S5P_FIMC_CBYCRY422,
94 .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
95 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
97 .name = "YUV 4:2:2 packed, CrYCbY",
98 .fourcc = V4L2_PIX_FMT_VYUY,
100 .color = S5P_FIMC_CRYCBY422,
103 .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
104 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
106 .name = "YUV 4:2:2 packed, YCrYCb",
107 .fourcc = V4L2_PIX_FMT_YVYU,
109 .color = S5P_FIMC_YCRYCB422,
112 .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
113 .flags = FMT_FLAGS_M2M | FMT_FLAGS_CAM,
115 .name = "YUV 4:2:2 planar, Y/Cb/Cr",
116 .fourcc = V4L2_PIX_FMT_YUV422P,
118 .color = S5P_FIMC_YCBYCR422,
121 .flags = FMT_FLAGS_M2M,
123 .name = "YUV 4:2:2 planar, Y/CbCr",
124 .fourcc = V4L2_PIX_FMT_NV16,
126 .color = S5P_FIMC_YCBYCR422,
129 .flags = FMT_FLAGS_M2M,
131 .name = "YUV 4:2:2 planar, Y/CrCb",
132 .fourcc = V4L2_PIX_FMT_NV61,
134 .color = S5P_FIMC_YCRYCB422,
137 .flags = FMT_FLAGS_M2M,
139 .name = "YUV 4:2:0 planar, YCbCr",
140 .fourcc = V4L2_PIX_FMT_YUV420,
142 .color = S5P_FIMC_YCBCR420,
145 .flags = FMT_FLAGS_M2M,
147 .name = "YUV 4:2:0 planar, Y/CbCr",
148 .fourcc = V4L2_PIX_FMT_NV12,
150 .color = S5P_FIMC_YCBCR420,
153 .flags = FMT_FLAGS_M2M,
155 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr",
156 .fourcc = V4L2_PIX_FMT_NV12M,
157 .color = S5P_FIMC_YCBCR420,
161 .flags = FMT_FLAGS_M2M,
163 .name = "YUV 4:2:0 non-contiguous 3-planar, Y/Cb/Cr",
164 .fourcc = V4L2_PIX_FMT_YUV420M,
165 .color = S5P_FIMC_YCBCR420,
166 .depth = { 8, 2, 2 },
169 .flags = FMT_FLAGS_M2M,
171 .name = "YUV 4:2:0 non-contiguous 2-planar, Y/CbCr, tiled",
172 .fourcc = V4L2_PIX_FMT_NV12MT,
173 .color = S5P_FIMC_YCBCR420,
177 .flags = FMT_FLAGS_M2M,
179 .name = "JPEG encoded data",
180 .fourcc = V4L2_PIX_FMT_JPEG,
181 .color = S5P_FIMC_JPEG,
185 .mbus_code = V4L2_MBUS_FMT_JPEG_1X8,
186 .flags = FMT_FLAGS_CAM,
190 static unsigned int get_m2m_fmt_flags(unsigned int stream_type)
192 if (stream_type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
193 return FMT_FLAGS_M2M_IN;
195 return FMT_FLAGS_M2M_OUT;
198 int fimc_check_scaler_ratio(struct fimc_ctx *ctx, int sw, int sh,
199 int dw, int dh, int rotation)
201 if (rotation == 90 || rotation == 270)
204 if (!ctx->scaler.enabled)
205 return (sw == dw && sh == dh) ? 0 : -EINVAL;
207 if ((sw >= SCALER_MAX_HRATIO * dw) || (sh >= SCALER_MAX_VRATIO * dh))
213 static int fimc_get_scaler_factor(u32 src, u32 tar, u32 *ratio, u32 *shift)
222 if (src >= tar * tmp) {
223 *shift = sh, *ratio = tmp;
227 *shift = 0, *ratio = 1;
231 int fimc_set_scaler_info(struct fimc_ctx *ctx)
233 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
234 struct device *dev = &ctx->fimc_dev->pdev->dev;
235 struct fimc_scaler *sc = &ctx->scaler;
236 struct fimc_frame *s_frame = &ctx->s_frame;
237 struct fimc_frame *d_frame = &ctx->d_frame;
241 if (ctx->rotation == 90 || ctx->rotation == 270) {
243 tx = d_frame->height;
246 ty = d_frame->height;
248 if (tx <= 0 || ty <= 0) {
249 dev_err(dev, "Invalid target size: %dx%d", tx, ty);
254 sy = s_frame->height;
255 if (sx <= 0 || sy <= 0) {
256 dev_err(dev, "Invalid source size: %dx%d", sx, sy);
260 sc->real_height = sy;
262 ret = fimc_get_scaler_factor(sx, tx, &sc->pre_hratio, &sc->hfactor);
266 ret = fimc_get_scaler_factor(sy, ty, &sc->pre_vratio, &sc->vfactor);
270 sc->pre_dst_width = sx / sc->pre_hratio;
271 sc->pre_dst_height = sy / sc->pre_vratio;
273 if (variant->has_mainscaler_ext) {
274 sc->main_hratio = (sx << 14) / (tx << sc->hfactor);
275 sc->main_vratio = (sy << 14) / (ty << sc->vfactor);
277 sc->main_hratio = (sx << 8) / (tx << sc->hfactor);
278 sc->main_vratio = (sy << 8) / (ty << sc->vfactor);
282 sc->scaleup_h = (tx >= sx) ? 1 : 0;
283 sc->scaleup_v = (ty >= sy) ? 1 : 0;
285 /* check to see if input and output size/format differ */
286 if (s_frame->fmt->color == d_frame->fmt->color
287 && s_frame->width == d_frame->width
288 && s_frame->height == d_frame->height)
296 static void fimc_m2m_job_finish(struct fimc_ctx *ctx, int vb_state)
298 struct vb2_buffer *src_vb, *dst_vb;
300 if (!ctx || !ctx->m2m_ctx)
303 src_vb = v4l2_m2m_src_buf_remove(ctx->m2m_ctx);
304 dst_vb = v4l2_m2m_dst_buf_remove(ctx->m2m_ctx);
306 if (src_vb && dst_vb) {
307 v4l2_m2m_buf_done(src_vb, vb_state);
308 v4l2_m2m_buf_done(dst_vb, vb_state);
309 v4l2_m2m_job_finish(ctx->fimc_dev->m2m.m2m_dev,
314 /* Complete the transaction which has been scheduled for execution. */
315 static int fimc_m2m_shutdown(struct fimc_ctx *ctx)
317 struct fimc_dev *fimc = ctx->fimc_dev;
320 if (!fimc_m2m_pending(fimc))
323 fimc_ctx_state_set(FIMC_CTX_SHUT, ctx);
325 ret = wait_event_timeout(fimc->irq_queue,
326 !fimc_ctx_state_is_set(FIMC_CTX_SHUT, ctx),
327 FIMC_SHUTDOWN_TIMEOUT);
329 return ret == 0 ? -ETIMEDOUT : ret;
332 static int start_streaming(struct vb2_queue *q, unsigned int count)
334 struct fimc_ctx *ctx = q->drv_priv;
337 ret = pm_runtime_get_sync(&ctx->fimc_dev->pdev->dev);
338 return ret > 0 ? 0 : ret;
341 static int stop_streaming(struct vb2_queue *q)
343 struct fimc_ctx *ctx = q->drv_priv;
346 ret = fimc_m2m_shutdown(ctx);
347 if (ret == -ETIMEDOUT)
348 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_ERROR);
350 pm_runtime_put(&ctx->fimc_dev->pdev->dev);
354 void fimc_capture_irq_handler(struct fimc_dev *fimc, bool final)
356 struct fimc_vid_cap *cap = &fimc->vid_cap;
357 struct fimc_vid_buffer *v_buf;
361 if (test_and_clear_bit(ST_CAPT_SHUT, &fimc->state)) {
362 wake_up(&fimc->irq_queue);
366 if (!list_empty(&cap->active_buf_q) &&
367 test_bit(ST_CAPT_RUN, &fimc->state) && final) {
368 ktime_get_real_ts(&ts);
370 v_buf = fimc_active_queue_pop(cap);
372 tv = &v_buf->vb.v4l2_buf.timestamp;
373 tv->tv_sec = ts.tv_sec;
374 tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
375 v_buf->vb.v4l2_buf.sequence = cap->frame_count++;
377 vb2_buffer_done(&v_buf->vb, VB2_BUF_STATE_DONE);
380 if (!list_empty(&cap->pending_buf_q)) {
382 v_buf = fimc_pending_queue_pop(cap);
383 fimc_hw_set_output_addr(fimc, &v_buf->paddr, cap->buf_index);
384 v_buf->index = cap->buf_index;
386 /* Move the buffer to the capture active queue */
387 fimc_active_queue_add(cap, v_buf);
389 dbg("next frame: %d, done frame: %d",
390 fimc_hw_get_frame_index(fimc), v_buf->index);
392 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
396 if (cap->active_buf_cnt == 0) {
398 clear_bit(ST_CAPT_RUN, &fimc->state);
400 if (++cap->buf_index >= FIMC_MAX_OUT_BUFS)
403 set_bit(ST_CAPT_RUN, &fimc->state);
406 fimc_capture_config_update(cap->ctx);
408 dbg("frame: %d, active_buf_cnt: %d",
409 fimc_hw_get_frame_index(fimc), cap->active_buf_cnt);
412 static irqreturn_t fimc_irq_handler(int irq, void *priv)
414 struct fimc_dev *fimc = priv;
415 struct fimc_vid_cap *cap = &fimc->vid_cap;
416 struct fimc_ctx *ctx;
418 fimc_hw_clear_irq(fimc);
420 spin_lock(&fimc->slock);
422 if (test_and_clear_bit(ST_M2M_PEND, &fimc->state)) {
423 if (test_and_clear_bit(ST_M2M_SUSPENDING, &fimc->state)) {
424 set_bit(ST_M2M_SUSPENDED, &fimc->state);
425 wake_up(&fimc->irq_queue);
428 ctx = v4l2_m2m_get_curr_priv(fimc->m2m.m2m_dev);
430 spin_unlock(&fimc->slock);
431 fimc_m2m_job_finish(ctx, VB2_BUF_STATE_DONE);
433 if (ctx->state & FIMC_CTX_SHUT) {
434 ctx->state &= ~FIMC_CTX_SHUT;
435 wake_up(&fimc->irq_queue);
439 } else if (test_bit(ST_CAPT_PEND, &fimc->state)) {
440 fimc_capture_irq_handler(fimc,
441 !test_bit(ST_CAPT_JPEG, &fimc->state));
442 if (cap->active_buf_cnt == 1) {
443 fimc_deactivate_capture(fimc);
444 clear_bit(ST_CAPT_STREAM, &fimc->state);
448 spin_unlock(&fimc->slock);
452 /* The color format (colplanes, memplanes) must be already configured. */
453 int fimc_prepare_addr(struct fimc_ctx *ctx, struct vb2_buffer *vb,
454 struct fimc_frame *frame, struct fimc_addr *paddr)
459 if (vb == NULL || frame == NULL)
462 pix_size = frame->width * frame->height;
464 dbg("memplanes= %d, colplanes= %d, pix_size= %d",
465 frame->fmt->memplanes, frame->fmt->colplanes, pix_size);
467 paddr->y = vb2_dma_contig_plane_dma_addr(vb, 0);
469 if (frame->fmt->memplanes == 1) {
470 switch (frame->fmt->colplanes) {
476 /* decompose Y into Y/Cb */
477 paddr->cb = (u32)(paddr->y + pix_size);
481 paddr->cb = (u32)(paddr->y + pix_size);
482 /* decompose Y into Y/Cb/Cr */
483 if (S5P_FIMC_YCBCR420 == frame->fmt->color)
484 paddr->cr = (u32)(paddr->cb
487 paddr->cr = (u32)(paddr->cb
494 if (frame->fmt->memplanes >= 2)
495 paddr->cb = vb2_dma_contig_plane_dma_addr(vb, 1);
497 if (frame->fmt->memplanes == 3)
498 paddr->cr = vb2_dma_contig_plane_dma_addr(vb, 2);
501 dbg("PHYS_ADDR: y= 0x%X cb= 0x%X cr= 0x%X ret= %d",
502 paddr->y, paddr->cb, paddr->cr, ret);
507 /* Set order for 1 and 2 plane YCBCR 4:2:2 formats. */
508 void fimc_set_yuv_order(struct fimc_ctx *ctx)
510 /* The one only mode supported in SoC. */
511 ctx->in_order_2p = S5P_FIMC_LSB_CRCB;
512 ctx->out_order_2p = S5P_FIMC_LSB_CRCB;
514 /* Set order for 1 plane input formats. */
515 switch (ctx->s_frame.fmt->color) {
516 case S5P_FIMC_YCRYCB422:
517 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CBYCRY;
519 case S5P_FIMC_CBYCRY422:
520 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCRYCB;
522 case S5P_FIMC_CRYCBY422:
523 ctx->in_order_1p = S5P_MSCTRL_ORDER422_YCBYCR;
525 case S5P_FIMC_YCBYCR422:
527 ctx->in_order_1p = S5P_MSCTRL_ORDER422_CRYCBY;
530 dbg("ctx->in_order_1p= %d", ctx->in_order_1p);
532 switch (ctx->d_frame.fmt->color) {
533 case S5P_FIMC_YCRYCB422:
534 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CBYCRY;
536 case S5P_FIMC_CBYCRY422:
537 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCRYCB;
539 case S5P_FIMC_CRYCBY422:
540 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_YCBYCR;
542 case S5P_FIMC_YCBYCR422:
544 ctx->out_order_1p = S5P_CIOCTRL_ORDER422_CRYCBY;
547 dbg("ctx->out_order_1p= %d", ctx->out_order_1p);
550 void fimc_prepare_dma_offset(struct fimc_ctx *ctx, struct fimc_frame *f)
552 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
555 for (i = 0; i < f->fmt->colplanes; i++)
556 depth += f->fmt->depth[i];
558 f->dma_offset.y_h = f->offs_h;
559 if (!variant->pix_hoff)
560 f->dma_offset.y_h *= (depth >> 3);
562 f->dma_offset.y_v = f->offs_v;
564 f->dma_offset.cb_h = f->offs_h;
565 f->dma_offset.cb_v = f->offs_v;
567 f->dma_offset.cr_h = f->offs_h;
568 f->dma_offset.cr_v = f->offs_v;
570 if (!variant->pix_hoff) {
571 if (f->fmt->colplanes == 3) {
572 f->dma_offset.cb_h >>= 1;
573 f->dma_offset.cr_h >>= 1;
575 if (f->fmt->color == S5P_FIMC_YCBCR420) {
576 f->dma_offset.cb_v >>= 1;
577 f->dma_offset.cr_v >>= 1;
581 dbg("in_offset: color= %d, y_h= %d, y_v= %d",
582 f->fmt->color, f->dma_offset.y_h, f->dma_offset.y_v);
585 static void fimc_dma_run(void *priv)
587 struct vb2_buffer *vb = NULL;
588 struct fimc_ctx *ctx = priv;
589 struct fimc_frame *sf, *df;
590 struct fimc_dev *fimc;
594 if (WARN(!ctx, "null hardware context\n"))
597 fimc = ctx->fimc_dev;
598 spin_lock_irqsave(&fimc->slock, flags);
599 set_bit(ST_M2M_PEND, &fimc->state);
603 if (ctx->state & FIMC_PARAMS) {
604 /* Prepare the DMA offsets for scaler */
605 fimc_prepare_dma_offset(ctx, sf);
606 fimc_prepare_dma_offset(ctx, df);
609 vb = v4l2_m2m_next_src_buf(ctx->m2m_ctx);
610 ret = fimc_prepare_addr(ctx, vb, sf, &sf->paddr);
614 vb = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
615 ret = fimc_prepare_addr(ctx, vb, df, &df->paddr);
619 /* Reconfigure hardware if the context has changed. */
620 if (fimc->m2m.ctx != ctx) {
621 ctx->state |= FIMC_PARAMS;
625 if (ctx->state & FIMC_PARAMS) {
626 fimc_set_yuv_order(ctx);
627 fimc_hw_set_input_path(ctx);
628 fimc_hw_set_in_dma(ctx);
629 ret = fimc_set_scaler_info(ctx);
632 fimc_hw_set_prescaler(ctx);
633 fimc_hw_set_mainscaler(ctx);
634 fimc_hw_set_target_format(ctx);
635 fimc_hw_set_rotation(ctx);
636 fimc_hw_set_effect(ctx, false);
637 fimc_hw_set_out_dma(ctx);
638 if (fimc->variant->has_alpha)
639 fimc_hw_set_rgb_alpha(ctx);
640 fimc_hw_set_output_path(ctx);
642 fimc_hw_set_input_addr(fimc, &sf->paddr);
643 fimc_hw_set_output_addr(fimc, &df->paddr, -1);
645 fimc_activate_capture(ctx);
647 ctx->state &= (FIMC_CTX_M2M | FIMC_CTX_CAP |
648 FIMC_SRC_FMT | FIMC_DST_FMT);
649 fimc_hw_activate_input_dma(fimc, true);
651 spin_unlock_irqrestore(&fimc->slock, flags);
654 static void fimc_job_abort(void *priv)
656 fimc_m2m_shutdown(priv);
659 static int fimc_queue_setup(struct vb2_queue *vq, const struct v4l2_format *fmt,
660 unsigned int *num_buffers, unsigned int *num_planes,
661 unsigned int sizes[], void *allocators[])
663 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
664 struct fimc_frame *f;
667 f = ctx_get_frame(ctx, vq->type);
671 * Return number of non-contigous planes (plane buffers)
672 * depending on the configured color format.
677 *num_planes = f->fmt->memplanes;
678 for (i = 0; i < f->fmt->memplanes; i++) {
679 sizes[i] = (f->f_width * f->f_height * f->fmt->depth[i]) / 8;
680 allocators[i] = ctx->fimc_dev->alloc_ctx;
685 static int fimc_buf_prepare(struct vb2_buffer *vb)
687 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
688 struct fimc_frame *frame;
691 frame = ctx_get_frame(ctx, vb->vb2_queue->type);
693 return PTR_ERR(frame);
695 for (i = 0; i < frame->fmt->memplanes; i++)
696 vb2_set_plane_payload(vb, i, frame->payload[i]);
701 static void fimc_buf_queue(struct vb2_buffer *vb)
703 struct fimc_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
705 dbg("ctx: %p, ctx->state: 0x%x", ctx, ctx->state);
708 v4l2_m2m_buf_queue(ctx->m2m_ctx, vb);
711 static void fimc_lock(struct vb2_queue *vq)
713 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
714 mutex_lock(&ctx->fimc_dev->lock);
717 static void fimc_unlock(struct vb2_queue *vq)
719 struct fimc_ctx *ctx = vb2_get_drv_priv(vq);
720 mutex_unlock(&ctx->fimc_dev->lock);
723 static struct vb2_ops fimc_qops = {
724 .queue_setup = fimc_queue_setup,
725 .buf_prepare = fimc_buf_prepare,
726 .buf_queue = fimc_buf_queue,
727 .wait_prepare = fimc_unlock,
728 .wait_finish = fimc_lock,
729 .stop_streaming = stop_streaming,
730 .start_streaming = start_streaming,
734 * V4L2 controls handling
736 #define ctrl_to_ctx(__ctrl) \
737 container_of((__ctrl)->handler, struct fimc_ctx, ctrl_handler)
739 static int __fimc_s_ctrl(struct fimc_ctx *ctx, struct v4l2_ctrl *ctrl)
741 struct fimc_dev *fimc = ctx->fimc_dev;
742 struct samsung_fimc_variant *variant = fimc->variant;
743 unsigned int flags = FIMC_DST_FMT | FIMC_SRC_FMT;
746 if (ctrl->flags & V4L2_CTRL_FLAG_INACTIVE)
751 ctx->hflip = ctrl->val;
755 ctx->vflip = ctrl->val;
758 case V4L2_CID_ROTATE:
759 if (fimc_capture_pending(fimc) ||
760 (ctx->state & flags) == flags) {
761 ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
762 ctx->s_frame.height, ctx->d_frame.width,
763 ctx->d_frame.height, ctrl->val);
767 if ((ctrl->val == 90 || ctrl->val == 270) &&
768 !variant->has_out_rot)
771 ctx->rotation = ctrl->val;
774 case V4L2_CID_ALPHA_COMPONENT:
775 ctx->d_frame.alpha = ctrl->val;
778 ctx->state |= FIMC_PARAMS;
779 set_bit(ST_CAPT_APPLY_CFG, &fimc->state);
783 static int fimc_s_ctrl(struct v4l2_ctrl *ctrl)
785 struct fimc_ctx *ctx = ctrl_to_ctx(ctrl);
789 spin_lock_irqsave(&ctx->fimc_dev->slock, flags);
790 ret = __fimc_s_ctrl(ctx, ctrl);
791 spin_unlock_irqrestore(&ctx->fimc_dev->slock, flags);
796 static const struct v4l2_ctrl_ops fimc_ctrl_ops = {
797 .s_ctrl = fimc_s_ctrl,
800 int fimc_ctrls_create(struct fimc_ctx *ctx)
802 struct samsung_fimc_variant *variant = ctx->fimc_dev->variant;
803 unsigned int max_alpha = fimc_get_alpha_mask(ctx->d_frame.fmt);
807 v4l2_ctrl_handler_init(&ctx->ctrl_handler, 4);
809 ctx->ctrl_rotate = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
810 V4L2_CID_ROTATE, 0, 270, 90, 0);
811 ctx->ctrl_hflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
812 V4L2_CID_HFLIP, 0, 1, 1, 0);
813 ctx->ctrl_vflip = v4l2_ctrl_new_std(&ctx->ctrl_handler, &fimc_ctrl_ops,
814 V4L2_CID_VFLIP, 0, 1, 1, 0);
815 if (variant->has_alpha)
816 ctx->ctrl_alpha = v4l2_ctrl_new_std(&ctx->ctrl_handler,
817 &fimc_ctrl_ops, V4L2_CID_ALPHA_COMPONENT,
820 ctx->ctrl_alpha = NULL;
822 ctx->ctrls_rdy = ctx->ctrl_handler.error == 0;
824 return ctx->ctrl_handler.error;
827 void fimc_ctrls_delete(struct fimc_ctx *ctx)
829 if (ctx->ctrls_rdy) {
830 v4l2_ctrl_handler_free(&ctx->ctrl_handler);
831 ctx->ctrls_rdy = false;
832 ctx->ctrl_alpha = NULL;
836 void fimc_ctrls_activate(struct fimc_ctx *ctx, bool active)
838 unsigned int has_alpha = ctx->d_frame.fmt->flags & FMT_HAS_ALPHA;
843 mutex_lock(&ctx->ctrl_handler.lock);
844 v4l2_ctrl_activate(ctx->ctrl_rotate, active);
845 v4l2_ctrl_activate(ctx->ctrl_hflip, active);
846 v4l2_ctrl_activate(ctx->ctrl_vflip, active);
848 v4l2_ctrl_activate(ctx->ctrl_alpha, active && has_alpha);
851 ctx->rotation = ctx->ctrl_rotate->val;
852 ctx->hflip = ctx->ctrl_hflip->val;
853 ctx->vflip = ctx->ctrl_vflip->val;
859 mutex_unlock(&ctx->ctrl_handler.lock);
862 /* Update maximum value of the alpha color control */
863 void fimc_alpha_ctrl_update(struct fimc_ctx *ctx)
865 struct fimc_dev *fimc = ctx->fimc_dev;
866 struct v4l2_ctrl *ctrl = ctx->ctrl_alpha;
868 if (ctrl == NULL || !fimc->variant->has_alpha)
871 v4l2_ctrl_lock(ctrl);
872 ctrl->maximum = fimc_get_alpha_mask(ctx->d_frame.fmt);
874 if (ctrl->cur.val > ctrl->maximum)
875 ctrl->cur.val = ctrl->maximum;
877 v4l2_ctrl_unlock(ctrl);
881 * V4L2 ioctl handlers
883 static int fimc_m2m_querycap(struct file *file, void *fh,
884 struct v4l2_capability *cap)
886 struct fimc_ctx *ctx = fh_to_ctx(fh);
887 struct fimc_dev *fimc = ctx->fimc_dev;
889 strncpy(cap->driver, fimc->pdev->name, sizeof(cap->driver) - 1);
890 strncpy(cap->card, fimc->pdev->name, sizeof(cap->card) - 1);
891 cap->bus_info[0] = 0;
892 cap->capabilities = V4L2_CAP_STREAMING |
893 V4L2_CAP_VIDEO_CAPTURE_MPLANE | V4L2_CAP_VIDEO_OUTPUT_MPLANE;
898 static int fimc_m2m_enum_fmt_mplane(struct file *file, void *priv,
899 struct v4l2_fmtdesc *f)
901 struct fimc_fmt *fmt;
903 fmt = fimc_find_format(NULL, NULL, get_m2m_fmt_flags(f->type),
908 strncpy(f->description, fmt->name, sizeof(f->description) - 1);
909 f->pixelformat = fmt->fourcc;
913 int fimc_fill_format(struct fimc_frame *frame, struct v4l2_format *f)
915 struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
918 pixm->width = frame->o_width;
919 pixm->height = frame->o_height;
920 pixm->field = V4L2_FIELD_NONE;
921 pixm->pixelformat = frame->fmt->fourcc;
922 pixm->colorspace = V4L2_COLORSPACE_JPEG;
923 pixm->num_planes = frame->fmt->memplanes;
925 for (i = 0; i < pixm->num_planes; ++i) {
926 int bpl = frame->f_width;
927 if (frame->fmt->colplanes == 1) /* packed formats */
928 bpl = (bpl * frame->fmt->depth[0]) / 8;
929 pixm->plane_fmt[i].bytesperline = bpl;
930 pixm->plane_fmt[i].sizeimage = (frame->o_width *
931 frame->o_height * frame->fmt->depth[i]) / 8;
936 void fimc_fill_frame(struct fimc_frame *frame, struct v4l2_format *f)
938 struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
940 frame->f_width = pixm->plane_fmt[0].bytesperline;
941 if (frame->fmt->colplanes == 1)
942 frame->f_width = (frame->f_width * 8) / frame->fmt->depth[0];
943 frame->f_height = pixm->height;
944 frame->width = pixm->width;
945 frame->height = pixm->height;
946 frame->o_width = pixm->width;
947 frame->o_height = pixm->height;
953 * fimc_adjust_mplane_format - adjust bytesperline/sizeimage for each plane
954 * @fmt: fimc pixel format description (input)
955 * @width: requested pixel width
956 * @height: requested pixel height
957 * @pix: multi-plane format to adjust
959 void fimc_adjust_mplane_format(struct fimc_fmt *fmt, u32 width, u32 height,
960 struct v4l2_pix_format_mplane *pix)
962 u32 bytesperline = 0;
965 pix->colorspace = V4L2_COLORSPACE_JPEG;
966 pix->field = V4L2_FIELD_NONE;
967 pix->num_planes = fmt->memplanes;
968 pix->pixelformat = fmt->fourcc;
969 pix->height = height;
972 for (i = 0; i < pix->num_planes; ++i) {
973 u32 bpl = pix->plane_fmt[i].bytesperline;
974 u32 *sizeimage = &pix->plane_fmt[i].sizeimage;
976 if (fmt->colplanes > 1 && (bpl == 0 || bpl < pix->width))
977 bpl = pix->width; /* Planar */
979 if (fmt->colplanes == 1 && /* Packed */
980 (bpl == 0 || ((bpl * 8) / fmt->depth[i]) < pix->width))
981 bpl = (pix->width * fmt->depth[0]) / 8;
983 if (i == 0) /* Same bytesperline for each plane. */
986 pix->plane_fmt[i].bytesperline = bytesperline;
987 *sizeimage = (pix->width * pix->height * fmt->depth[i]) / 8;
991 static int fimc_m2m_g_fmt_mplane(struct file *file, void *fh,
992 struct v4l2_format *f)
994 struct fimc_ctx *ctx = fh_to_ctx(fh);
995 struct fimc_frame *frame = ctx_get_frame(ctx, f->type);
998 return PTR_ERR(frame);
1000 return fimc_fill_format(frame, f);
1004 * fimc_find_format - lookup fimc color format by fourcc or media bus format
1005 * @pixelformat: fourcc to match, ignored if null
1006 * @mbus_code: media bus code to match, ignored if null
1007 * @mask: the color flags to match
1008 * @index: offset in the fimc_formats array, ignored if negative
1010 struct fimc_fmt *fimc_find_format(const u32 *pixelformat, const u32 *mbus_code,
1011 unsigned int mask, int index)
1013 struct fimc_fmt *fmt, *def_fmt = NULL;
1017 if (index >= (int)ARRAY_SIZE(fimc_formats))
1020 for (i = 0; i < ARRAY_SIZE(fimc_formats); ++i) {
1021 fmt = &fimc_formats[i];
1022 if (!(fmt->flags & mask))
1024 if (pixelformat && fmt->fourcc == *pixelformat)
1026 if (mbus_code && fmt->mbus_code == *mbus_code)
1035 static int fimc_try_fmt_mplane(struct fimc_ctx *ctx, struct v4l2_format *f)
1037 struct fimc_dev *fimc = ctx->fimc_dev;
1038 struct samsung_fimc_variant *variant = fimc->variant;
1039 struct v4l2_pix_format_mplane *pix = &f->fmt.pix_mp;
1040 struct fimc_fmt *fmt;
1041 u32 max_w, mod_x, mod_y;
1043 if (!IS_M2M(f->type))
1046 dbg("w: %d, h: %d", pix->width, pix->height);
1048 fmt = fimc_find_format(&pix->pixelformat, NULL,
1049 get_m2m_fmt_flags(f->type), 0);
1050 if (WARN(fmt == NULL, "Pixel format lookup failed"))
1053 if (pix->field == V4L2_FIELD_ANY)
1054 pix->field = V4L2_FIELD_NONE;
1055 else if (pix->field != V4L2_FIELD_NONE)
1058 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1059 max_w = variant->pix_limit->scaler_dis_w;
1060 mod_x = ffs(variant->min_inp_pixsize) - 1;
1062 max_w = variant->pix_limit->out_rot_dis_w;
1063 mod_x = ffs(variant->min_out_pixsize) - 1;
1066 if (tiled_fmt(fmt)) {
1067 mod_x = 6; /* 64 x 32 pixels tile */
1070 if (variant->min_vsize_align == 1)
1071 mod_y = fimc_fmt_is_rgb(fmt->color) ? 0 : 1;
1073 mod_y = ffs(variant->min_vsize_align) - 1;
1076 v4l_bound_align_image(&pix->width, 16, max_w, mod_x,
1077 &pix->height, 8, variant->pix_limit->scaler_dis_w, mod_y, 0);
1079 fimc_adjust_mplane_format(fmt, pix->width, pix->height, &f->fmt.pix_mp);
1083 static int fimc_m2m_try_fmt_mplane(struct file *file, void *fh,
1084 struct v4l2_format *f)
1086 struct fimc_ctx *ctx = fh_to_ctx(fh);
1088 return fimc_try_fmt_mplane(ctx, f);
1091 static int fimc_m2m_s_fmt_mplane(struct file *file, void *fh,
1092 struct v4l2_format *f)
1094 struct fimc_ctx *ctx = fh_to_ctx(fh);
1095 struct fimc_dev *fimc = ctx->fimc_dev;
1096 struct vb2_queue *vq;
1097 struct fimc_frame *frame;
1098 struct v4l2_pix_format_mplane *pix;
1101 ret = fimc_try_fmt_mplane(ctx, f);
1105 vq = v4l2_m2m_get_vq(ctx->m2m_ctx, f->type);
1107 if (vb2_is_busy(vq)) {
1108 v4l2_err(fimc->m2m.vfd, "queue (%d) busy\n", f->type);
1112 if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1113 frame = &ctx->s_frame;
1115 frame = &ctx->d_frame;
1117 pix = &f->fmt.pix_mp;
1118 frame->fmt = fimc_find_format(&pix->pixelformat, NULL,
1119 get_m2m_fmt_flags(f->type), 0);
1123 /* Update RGB Alpha control state and value range */
1124 fimc_alpha_ctrl_update(ctx);
1126 for (i = 0; i < frame->fmt->colplanes; i++) {
1128 (pix->width * pix->height * frame->fmt->depth[i]) / 8;
1131 fimc_fill_frame(frame, f);
1133 ctx->scaler.enabled = 1;
1135 if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1136 fimc_ctx_state_set(FIMC_PARAMS | FIMC_DST_FMT, ctx);
1138 fimc_ctx_state_set(FIMC_PARAMS | FIMC_SRC_FMT, ctx);
1140 dbg("f_w: %d, f_h: %d", frame->f_width, frame->f_height);
1145 static int fimc_m2m_reqbufs(struct file *file, void *fh,
1146 struct v4l2_requestbuffers *reqbufs)
1148 struct fimc_ctx *ctx = fh_to_ctx(fh);
1150 return v4l2_m2m_reqbufs(file, ctx->m2m_ctx, reqbufs);
1153 static int fimc_m2m_querybuf(struct file *file, void *fh,
1154 struct v4l2_buffer *buf)
1156 struct fimc_ctx *ctx = fh_to_ctx(fh);
1158 return v4l2_m2m_querybuf(file, ctx->m2m_ctx, buf);
1161 static int fimc_m2m_qbuf(struct file *file, void *fh,
1162 struct v4l2_buffer *buf)
1164 struct fimc_ctx *ctx = fh_to_ctx(fh);
1166 return v4l2_m2m_qbuf(file, ctx->m2m_ctx, buf);
1169 static int fimc_m2m_dqbuf(struct file *file, void *fh,
1170 struct v4l2_buffer *buf)
1172 struct fimc_ctx *ctx = fh_to_ctx(fh);
1174 return v4l2_m2m_dqbuf(file, ctx->m2m_ctx, buf);
1177 static int fimc_m2m_streamon(struct file *file, void *fh,
1178 enum v4l2_buf_type type)
1180 struct fimc_ctx *ctx = fh_to_ctx(fh);
1182 /* The source and target color format need to be set */
1183 if (V4L2_TYPE_IS_OUTPUT(type)) {
1184 if (!fimc_ctx_state_is_set(FIMC_SRC_FMT, ctx))
1186 } else if (!fimc_ctx_state_is_set(FIMC_DST_FMT, ctx)) {
1190 return v4l2_m2m_streamon(file, ctx->m2m_ctx, type);
1193 static int fimc_m2m_streamoff(struct file *file, void *fh,
1194 enum v4l2_buf_type type)
1196 struct fimc_ctx *ctx = fh_to_ctx(fh);
1198 return v4l2_m2m_streamoff(file, ctx->m2m_ctx, type);
1201 static int fimc_m2m_cropcap(struct file *file, void *fh,
1202 struct v4l2_cropcap *cr)
1204 struct fimc_ctx *ctx = fh_to_ctx(fh);
1205 struct fimc_frame *frame;
1207 frame = ctx_get_frame(ctx, cr->type);
1209 return PTR_ERR(frame);
1211 cr->bounds.left = 0;
1213 cr->bounds.width = frame->o_width;
1214 cr->bounds.height = frame->o_height;
1215 cr->defrect = cr->bounds;
1220 static int fimc_m2m_g_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1222 struct fimc_ctx *ctx = fh_to_ctx(fh);
1223 struct fimc_frame *frame;
1225 frame = ctx_get_frame(ctx, cr->type);
1227 return PTR_ERR(frame);
1229 cr->c.left = frame->offs_h;
1230 cr->c.top = frame->offs_v;
1231 cr->c.width = frame->width;
1232 cr->c.height = frame->height;
1237 static int fimc_m2m_try_crop(struct fimc_ctx *ctx, struct v4l2_crop *cr)
1239 struct fimc_dev *fimc = ctx->fimc_dev;
1240 struct fimc_frame *f;
1241 u32 min_size, halign, depth = 0;
1244 if (cr->c.top < 0 || cr->c.left < 0) {
1245 v4l2_err(fimc->m2m.vfd,
1246 "doesn't support negative values for top & left\n");
1249 if (cr->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
1251 else if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE)
1256 min_size = (f == &ctx->s_frame) ?
1257 fimc->variant->min_inp_pixsize : fimc->variant->min_out_pixsize;
1259 /* Get pixel alignment constraints. */
1260 if (fimc->variant->min_vsize_align == 1)
1261 halign = fimc_fmt_is_rgb(f->fmt->color) ? 0 : 1;
1263 halign = ffs(fimc->variant->min_vsize_align) - 1;
1265 for (i = 0; i < f->fmt->colplanes; i++)
1266 depth += f->fmt->depth[i];
1268 v4l_bound_align_image(&cr->c.width, min_size, f->o_width,
1270 &cr->c.height, min_size, f->o_height,
1271 halign, 64/(ALIGN(depth, 8)));
1273 /* adjust left/top if cropping rectangle is out of bounds */
1274 if (cr->c.left + cr->c.width > f->o_width)
1275 cr->c.left = f->o_width - cr->c.width;
1276 if (cr->c.top + cr->c.height > f->o_height)
1277 cr->c.top = f->o_height - cr->c.height;
1279 cr->c.left = round_down(cr->c.left, min_size);
1280 cr->c.top = round_down(cr->c.top, fimc->variant->hor_offs_align);
1282 dbg("l:%d, t:%d, w:%d, h:%d, f_w: %d, f_h: %d",
1283 cr->c.left, cr->c.top, cr->c.width, cr->c.height,
1284 f->f_width, f->f_height);
1289 static int fimc_m2m_s_crop(struct file *file, void *fh, struct v4l2_crop *cr)
1291 struct fimc_ctx *ctx = fh_to_ctx(fh);
1292 struct fimc_dev *fimc = ctx->fimc_dev;
1293 struct fimc_frame *f;
1296 ret = fimc_m2m_try_crop(ctx, cr);
1300 f = (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) ?
1301 &ctx->s_frame : &ctx->d_frame;
1303 /* Check to see if scaling ratio is within supported range */
1304 if (fimc_ctx_state_is_set(FIMC_DST_FMT | FIMC_SRC_FMT, ctx)) {
1305 if (cr->type == V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE) {
1306 ret = fimc_check_scaler_ratio(ctx, cr->c.width,
1307 cr->c.height, ctx->d_frame.width,
1308 ctx->d_frame.height, ctx->rotation);
1310 ret = fimc_check_scaler_ratio(ctx, ctx->s_frame.width,
1311 ctx->s_frame.height, cr->c.width,
1312 cr->c.height, ctx->rotation);
1315 v4l2_err(fimc->m2m.vfd, "Out of scaler range\n");
1320 f->offs_h = cr->c.left;
1321 f->offs_v = cr->c.top;
1322 f->width = cr->c.width;
1323 f->height = cr->c.height;
1325 fimc_ctx_state_set(FIMC_PARAMS, ctx);
1330 static const struct v4l2_ioctl_ops fimc_m2m_ioctl_ops = {
1331 .vidioc_querycap = fimc_m2m_querycap,
1333 .vidioc_enum_fmt_vid_cap_mplane = fimc_m2m_enum_fmt_mplane,
1334 .vidioc_enum_fmt_vid_out_mplane = fimc_m2m_enum_fmt_mplane,
1336 .vidioc_g_fmt_vid_cap_mplane = fimc_m2m_g_fmt_mplane,
1337 .vidioc_g_fmt_vid_out_mplane = fimc_m2m_g_fmt_mplane,
1339 .vidioc_try_fmt_vid_cap_mplane = fimc_m2m_try_fmt_mplane,
1340 .vidioc_try_fmt_vid_out_mplane = fimc_m2m_try_fmt_mplane,
1342 .vidioc_s_fmt_vid_cap_mplane = fimc_m2m_s_fmt_mplane,
1343 .vidioc_s_fmt_vid_out_mplane = fimc_m2m_s_fmt_mplane,
1345 .vidioc_reqbufs = fimc_m2m_reqbufs,
1346 .vidioc_querybuf = fimc_m2m_querybuf,
1348 .vidioc_qbuf = fimc_m2m_qbuf,
1349 .vidioc_dqbuf = fimc_m2m_dqbuf,
1351 .vidioc_streamon = fimc_m2m_streamon,
1352 .vidioc_streamoff = fimc_m2m_streamoff,
1354 .vidioc_g_crop = fimc_m2m_g_crop,
1355 .vidioc_s_crop = fimc_m2m_s_crop,
1356 .vidioc_cropcap = fimc_m2m_cropcap
1360 static int queue_init(void *priv, struct vb2_queue *src_vq,
1361 struct vb2_queue *dst_vq)
1363 struct fimc_ctx *ctx = priv;
1366 memset(src_vq, 0, sizeof(*src_vq));
1367 src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
1368 src_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1369 src_vq->drv_priv = ctx;
1370 src_vq->ops = &fimc_qops;
1371 src_vq->mem_ops = &vb2_dma_contig_memops;
1372 src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1374 ret = vb2_queue_init(src_vq);
1378 memset(dst_vq, 0, sizeof(*dst_vq));
1379 dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
1380 dst_vq->io_modes = VB2_MMAP | VB2_USERPTR;
1381 dst_vq->drv_priv = ctx;
1382 dst_vq->ops = &fimc_qops;
1383 dst_vq->mem_ops = &vb2_dma_contig_memops;
1384 dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
1386 return vb2_queue_init(dst_vq);
1389 static int fimc_m2m_open(struct file *file)
1391 struct fimc_dev *fimc = video_drvdata(file);
1392 struct fimc_ctx *ctx;
1395 dbg("pid: %d, state: 0x%lx, refcnt: %d",
1396 task_pid_nr(current), fimc->state, fimc->vid_cap.refcnt);
1399 * Return if the corresponding video capture node
1400 * is already opened.
1402 if (fimc->vid_cap.refcnt > 0)
1405 ctx = kzalloc(sizeof *ctx, GFP_KERNEL);
1408 v4l2_fh_init(&ctx->fh, fimc->m2m.vfd);
1409 ctx->fimc_dev = fimc;
1411 /* Default color format */
1412 ctx->s_frame.fmt = &fimc_formats[0];
1413 ctx->d_frame.fmt = &fimc_formats[0];
1415 ret = fimc_ctrls_create(ctx);
1419 /* Use separate control handler per file handle */
1420 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
1421 file->private_data = &ctx->fh;
1422 v4l2_fh_add(&ctx->fh);
1424 /* Setup the device context for memory-to-memory mode */
1425 ctx->state = FIMC_CTX_M2M;
1427 ctx->in_path = FIMC_DMA;
1428 ctx->out_path = FIMC_DMA;
1430 ctx->m2m_ctx = v4l2_m2m_ctx_init(fimc->m2m.m2m_dev, ctx, queue_init);
1431 if (IS_ERR(ctx->m2m_ctx)) {
1432 ret = PTR_ERR(ctx->m2m_ctx);
1436 if (fimc->m2m.refcnt++ == 0)
1437 set_bit(ST_M2M_RUN, &fimc->state);
1441 fimc_ctrls_delete(ctx);
1443 v4l2_fh_del(&ctx->fh);
1444 v4l2_fh_exit(&ctx->fh);
1449 static int fimc_m2m_release(struct file *file)
1451 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1452 struct fimc_dev *fimc = ctx->fimc_dev;
1454 dbg("pid: %d, state: 0x%lx, refcnt= %d",
1455 task_pid_nr(current), fimc->state, fimc->m2m.refcnt);
1457 v4l2_m2m_ctx_release(ctx->m2m_ctx);
1458 fimc_ctrls_delete(ctx);
1459 v4l2_fh_del(&ctx->fh);
1460 v4l2_fh_exit(&ctx->fh);
1462 if (--fimc->m2m.refcnt <= 0)
1463 clear_bit(ST_M2M_RUN, &fimc->state);
1468 static unsigned int fimc_m2m_poll(struct file *file,
1469 struct poll_table_struct *wait)
1471 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1473 return v4l2_m2m_poll(file, ctx->m2m_ctx, wait);
1477 static int fimc_m2m_mmap(struct file *file, struct vm_area_struct *vma)
1479 struct fimc_ctx *ctx = fh_to_ctx(file->private_data);
1481 return v4l2_m2m_mmap(file, ctx->m2m_ctx, vma);
1484 static const struct v4l2_file_operations fimc_m2m_fops = {
1485 .owner = THIS_MODULE,
1486 .open = fimc_m2m_open,
1487 .release = fimc_m2m_release,
1488 .poll = fimc_m2m_poll,
1489 .unlocked_ioctl = video_ioctl2,
1490 .mmap = fimc_m2m_mmap,
1493 static struct v4l2_m2m_ops m2m_ops = {
1494 .device_run = fimc_dma_run,
1495 .job_abort = fimc_job_abort,
1498 int fimc_register_m2m_device(struct fimc_dev *fimc,
1499 struct v4l2_device *v4l2_dev)
1501 struct video_device *vfd;
1502 struct platform_device *pdev;
1509 fimc->v4l2_dev = v4l2_dev;
1511 vfd = video_device_alloc();
1513 v4l2_err(v4l2_dev, "Failed to allocate video device\n");
1517 vfd->fops = &fimc_m2m_fops;
1518 vfd->ioctl_ops = &fimc_m2m_ioctl_ops;
1519 vfd->v4l2_dev = v4l2_dev;
1521 vfd->release = video_device_release;
1522 vfd->lock = &fimc->lock;
1523 /* Locking in file operations other than ioctl should be done
1524 by the driver, not the V4L2 core.
1525 This driver needs auditing so that this flag can be removed. */
1526 set_bit(V4L2_FL_LOCK_ALL_FOPS, &vfd->flags);
1528 snprintf(vfd->name, sizeof(vfd->name), "%s.m2m", dev_name(&pdev->dev));
1529 video_set_drvdata(vfd, fimc);
1531 fimc->m2m.vfd = vfd;
1532 fimc->m2m.m2m_dev = v4l2_m2m_init(&m2m_ops);
1533 if (IS_ERR(fimc->m2m.m2m_dev)) {
1534 v4l2_err(v4l2_dev, "failed to initialize v4l2-m2m device\n");
1535 ret = PTR_ERR(fimc->m2m.m2m_dev);
1539 ret = media_entity_init(&vfd->entity, 0, NULL, 0);
1543 v4l2_m2m_release(fimc->m2m.m2m_dev);
1545 video_device_release(fimc->m2m.vfd);
1549 void fimc_unregister_m2m_device(struct fimc_dev *fimc)
1554 if (fimc->m2m.m2m_dev)
1555 v4l2_m2m_release(fimc->m2m.m2m_dev);
1556 if (fimc->m2m.vfd) {
1557 media_entity_cleanup(&fimc->m2m.vfd->entity);
1558 /* Can also be called if video device wasn't registered */
1559 video_unregister_device(fimc->m2m.vfd);
1563 static void fimc_clk_put(struct fimc_dev *fimc)
1566 for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
1567 if (IS_ERR_OR_NULL(fimc->clock[i]))
1569 clk_unprepare(fimc->clock[i]);
1570 clk_put(fimc->clock[i]);
1571 fimc->clock[i] = NULL;
1575 static int fimc_clk_get(struct fimc_dev *fimc)
1579 for (i = 0; i < MAX_FIMC_CLOCKS; i++) {
1580 fimc->clock[i] = clk_get(&fimc->pdev->dev, fimc_clocks[i]);
1581 if (IS_ERR(fimc->clock[i]))
1583 ret = clk_prepare(fimc->clock[i]);
1585 clk_put(fimc->clock[i]);
1586 fimc->clock[i] = NULL;
1593 dev_err(&fimc->pdev->dev, "failed to get clock: %s\n",
1598 static int fimc_m2m_suspend(struct fimc_dev *fimc)
1600 unsigned long flags;
1603 spin_lock_irqsave(&fimc->slock, flags);
1604 if (!fimc_m2m_pending(fimc)) {
1605 spin_unlock_irqrestore(&fimc->slock, flags);
1608 clear_bit(ST_M2M_SUSPENDED, &fimc->state);
1609 set_bit(ST_M2M_SUSPENDING, &fimc->state);
1610 spin_unlock_irqrestore(&fimc->slock, flags);
1612 timeout = wait_event_timeout(fimc->irq_queue,
1613 test_bit(ST_M2M_SUSPENDED, &fimc->state),
1614 FIMC_SHUTDOWN_TIMEOUT);
1616 clear_bit(ST_M2M_SUSPENDING, &fimc->state);
1617 return timeout == 0 ? -EAGAIN : 0;
1620 static int fimc_m2m_resume(struct fimc_dev *fimc)
1622 unsigned long flags;
1624 spin_lock_irqsave(&fimc->slock, flags);
1625 /* Clear for full H/W setup in first run after resume */
1626 fimc->m2m.ctx = NULL;
1627 spin_unlock_irqrestore(&fimc->slock, flags);
1629 if (test_and_clear_bit(ST_M2M_SUSPENDED, &fimc->state))
1630 fimc_m2m_job_finish(fimc->m2m.ctx,
1631 VB2_BUF_STATE_ERROR);
1635 static int fimc_probe(struct platform_device *pdev)
1637 struct fimc_dev *fimc;
1638 struct resource *res;
1639 struct samsung_fimc_driverdata *drv_data;
1640 struct s5p_platform_fimc *pdata;
1643 drv_data = (struct samsung_fimc_driverdata *)
1644 platform_get_device_id(pdev)->driver_data;
1646 if (pdev->id >= drv_data->num_entities) {
1647 dev_err(&pdev->dev, "Invalid platform device id: %d\n",
1652 fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
1656 fimc->id = pdev->id;
1658 fimc->variant = drv_data->variant[fimc->id];
1660 pdata = pdev->dev.platform_data;
1661 fimc->pdata = pdata;
1663 init_waitqueue_head(&fimc->irq_queue);
1664 spin_lock_init(&fimc->slock);
1665 mutex_init(&fimc->lock);
1667 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1668 fimc->regs = devm_request_and_ioremap(&pdev->dev, res);
1669 if (fimc->regs == NULL) {
1670 dev_err(&pdev->dev, "Failed to obtain io memory\n");
1674 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1676 dev_err(&pdev->dev, "Failed to get IRQ resource\n");
1680 ret = fimc_clk_get(fimc);
1683 clk_set_rate(fimc->clock[CLK_BUS], drv_data->lclk_frequency);
1684 clk_enable(fimc->clock[CLK_BUS]);
1686 platform_set_drvdata(pdev, fimc);
1688 ret = devm_request_irq(&pdev->dev, res->start, fimc_irq_handler,
1689 0, pdev->name, fimc);
1691 dev_err(&pdev->dev, "failed to install irq (%d)\n", ret);
1695 pm_runtime_enable(&pdev->dev);
1696 ret = pm_runtime_get_sync(&pdev->dev);
1699 /* Initialize contiguous memory allocator */
1700 fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
1701 if (IS_ERR(fimc->alloc_ctx)) {
1702 ret = PTR_ERR(fimc->alloc_ctx);
1706 dev_dbg(&pdev->dev, "FIMC.%d registered successfully\n", fimc->id);
1708 pm_runtime_put(&pdev->dev);
1712 pm_runtime_put(&pdev->dev);
1718 static int fimc_runtime_resume(struct device *dev)
1720 struct fimc_dev *fimc = dev_get_drvdata(dev);
1722 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1724 /* Enable clocks and perform basic initalization */
1725 clk_enable(fimc->clock[CLK_GATE]);
1726 fimc_hw_reset(fimc);
1728 /* Resume the capture or mem-to-mem device */
1729 if (fimc_capture_busy(fimc))
1730 return fimc_capture_resume(fimc);
1732 return fimc_m2m_resume(fimc);
1735 static int fimc_runtime_suspend(struct device *dev)
1737 struct fimc_dev *fimc = dev_get_drvdata(dev);
1740 if (fimc_capture_busy(fimc))
1741 ret = fimc_capture_suspend(fimc);
1743 ret = fimc_m2m_suspend(fimc);
1745 clk_disable(fimc->clock[CLK_GATE]);
1747 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1751 #ifdef CONFIG_PM_SLEEP
1752 static int fimc_resume(struct device *dev)
1754 struct fimc_dev *fimc = dev_get_drvdata(dev);
1755 unsigned long flags;
1757 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1759 /* Do not resume if the device was idle before system suspend */
1760 spin_lock_irqsave(&fimc->slock, flags);
1761 if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
1762 (!fimc_m2m_active(fimc) && !fimc_capture_busy(fimc))) {
1763 spin_unlock_irqrestore(&fimc->slock, flags);
1766 fimc_hw_reset(fimc);
1767 spin_unlock_irqrestore(&fimc->slock, flags);
1769 if (fimc_capture_busy(fimc))
1770 return fimc_capture_resume(fimc);
1772 return fimc_m2m_resume(fimc);
1775 static int fimc_suspend(struct device *dev)
1777 struct fimc_dev *fimc = dev_get_drvdata(dev);
1779 dbg("fimc%d: state: 0x%lx", fimc->id, fimc->state);
1781 if (test_and_set_bit(ST_LPM, &fimc->state))
1783 if (fimc_capture_busy(fimc))
1784 return fimc_capture_suspend(fimc);
1786 return fimc_m2m_suspend(fimc);
1788 #endif /* CONFIG_PM_SLEEP */
1790 static int __devexit fimc_remove(struct platform_device *pdev)
1792 struct fimc_dev *fimc = platform_get_drvdata(pdev);
1794 pm_runtime_disable(&pdev->dev);
1795 pm_runtime_set_suspended(&pdev->dev);
1797 vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
1799 clk_disable(fimc->clock[CLK_BUS]);
1802 dev_info(&pdev->dev, "driver unloaded\n");
1806 /* Image pixel limits, similar across several FIMC HW revisions. */
1807 static struct fimc_pix_limit s5p_pix_limit[4] = {
1809 .scaler_en_w = 3264,
1810 .scaler_dis_w = 8192,
1811 .in_rot_en_h = 1920,
1812 .in_rot_dis_w = 8192,
1813 .out_rot_en_w = 1920,
1814 .out_rot_dis_w = 4224,
1817 .scaler_en_w = 4224,
1818 .scaler_dis_w = 8192,
1819 .in_rot_en_h = 1920,
1820 .in_rot_dis_w = 8192,
1821 .out_rot_en_w = 1920,
1822 .out_rot_dis_w = 4224,
1825 .scaler_en_w = 1920,
1826 .scaler_dis_w = 8192,
1827 .in_rot_en_h = 1280,
1828 .in_rot_dis_w = 8192,
1829 .out_rot_en_w = 1280,
1830 .out_rot_dis_w = 1920,
1833 .scaler_en_w = 1920,
1834 .scaler_dis_w = 8192,
1835 .in_rot_en_h = 1366,
1836 .in_rot_dis_w = 8192,
1837 .out_rot_en_w = 1366,
1838 .out_rot_dis_w = 1920,
1842 static struct samsung_fimc_variant fimc0_variant_s5p = {
1846 .min_inp_pixsize = 16,
1847 .min_out_pixsize = 16,
1848 .hor_offs_align = 8,
1849 .min_vsize_align = 16,
1851 .pix_limit = &s5p_pix_limit[0],
1854 static struct samsung_fimc_variant fimc2_variant_s5p = {
1856 .min_inp_pixsize = 16,
1857 .min_out_pixsize = 16,
1858 .hor_offs_align = 8,
1859 .min_vsize_align = 16,
1861 .pix_limit = &s5p_pix_limit[1],
1864 static struct samsung_fimc_variant fimc0_variant_s5pv210 = {
1869 .min_inp_pixsize = 16,
1870 .min_out_pixsize = 16,
1871 .hor_offs_align = 8,
1872 .min_vsize_align = 16,
1874 .pix_limit = &s5p_pix_limit[1],
1877 static struct samsung_fimc_variant fimc1_variant_s5pv210 = {
1882 .has_mainscaler_ext = 1,
1883 .min_inp_pixsize = 16,
1884 .min_out_pixsize = 16,
1885 .hor_offs_align = 1,
1886 .min_vsize_align = 1,
1888 .pix_limit = &s5p_pix_limit[2],
1891 static struct samsung_fimc_variant fimc2_variant_s5pv210 = {
1894 .min_inp_pixsize = 16,
1895 .min_out_pixsize = 16,
1896 .hor_offs_align = 8,
1897 .min_vsize_align = 16,
1899 .pix_limit = &s5p_pix_limit[2],
1902 static struct samsung_fimc_variant fimc0_variant_exynos4 = {
1908 .has_mainscaler_ext = 1,
1910 .min_inp_pixsize = 16,
1911 .min_out_pixsize = 16,
1912 .hor_offs_align = 2,
1913 .min_vsize_align = 1,
1914 .out_buf_count = 32,
1915 .pix_limit = &s5p_pix_limit[1],
1918 static struct samsung_fimc_variant fimc3_variant_exynos4 = {
1922 .has_mainscaler_ext = 1,
1924 .min_inp_pixsize = 16,
1925 .min_out_pixsize = 16,
1926 .hor_offs_align = 2,
1927 .min_vsize_align = 1,
1928 .out_buf_count = 32,
1929 .pix_limit = &s5p_pix_limit[3],
1933 static struct samsung_fimc_driverdata fimc_drvdata_s5p = {
1935 [0] = &fimc0_variant_s5p,
1936 [1] = &fimc0_variant_s5p,
1937 [2] = &fimc2_variant_s5p,
1940 .lclk_frequency = 133000000UL,
1943 /* S5PV210, S5PC110 */
1944 static struct samsung_fimc_driverdata fimc_drvdata_s5pv210 = {
1946 [0] = &fimc0_variant_s5pv210,
1947 [1] = &fimc1_variant_s5pv210,
1948 [2] = &fimc2_variant_s5pv210,
1951 .lclk_frequency = 166000000UL,
1954 /* S5PV310, S5PC210 */
1955 static struct samsung_fimc_driverdata fimc_drvdata_exynos4 = {
1957 [0] = &fimc0_variant_exynos4,
1958 [1] = &fimc0_variant_exynos4,
1959 [2] = &fimc0_variant_exynos4,
1960 [3] = &fimc3_variant_exynos4,
1963 .lclk_frequency = 166000000UL,
1966 static struct platform_device_id fimc_driver_ids[] = {
1969 .driver_data = (unsigned long)&fimc_drvdata_s5p,
1971 .name = "s5pv210-fimc",
1972 .driver_data = (unsigned long)&fimc_drvdata_s5pv210,
1974 .name = "exynos4-fimc",
1975 .driver_data = (unsigned long)&fimc_drvdata_exynos4,
1979 MODULE_DEVICE_TABLE(platform, fimc_driver_ids);
1981 static const struct dev_pm_ops fimc_pm_ops = {
1982 SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1983 SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1986 static struct platform_driver fimc_driver = {
1987 .probe = fimc_probe,
1988 .remove = __devexit_p(fimc_remove),
1989 .id_table = fimc_driver_ids,
1991 .name = FIMC_MODULE_NAME,
1992 .owner = THIS_MODULE,
1997 int __init fimc_register_driver(void)
1999 return platform_driver_register(&fimc_driver);
2002 void __exit fimc_unregister_driver(void)
2004 platform_driver_unregister(&fimc_driver);