drivers/media/video/pvrusb2/pvrusb2-hdw.c

   1 /*
   2  *
   3  *
   4  *  Copyright (C) 2005 Mike Isely <isely@pobox.com>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify
   7  *  it under the terms of the GNU General Public License as published by
   8  *  the Free Software Foundation; either version 2 of the License
   9  *
  10  *  This program is distributed in the hope that it will be useful,
  11  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  *  GNU General Public License for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License
  16  *  along with this program; if not, write to the Free Software
  17  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  *
  19  */
  20
  21 #include <linux/errno.h>
  22 #include <linux/string.h>
  23 #include <linux/slab.h>
  24 #include <linux/module.h>
  25 #include <linux/firmware.h>
  26 #include <linux/videodev2.h>
  27 #include <media/v4l2-common.h>
  28 #include <media/tuner.h>
  29 #include "pvrusb2.h"
  30 #include "pvrusb2-std.h"
  31 #include "pvrusb2-util.h"
  32 #include "pvrusb2-hdw.h"
  33 #include "pvrusb2-i2c-core.h"
  34 #include "pvrusb2-eeprom.h"
  35 #include "pvrusb2-hdw-internal.h"
  36 #include "pvrusb2-encoder.h"
  37 #include "pvrusb2-debug.h"
  38 #include "pvrusb2-fx2-cmd.h"
  39 #include "pvrusb2-wm8775.h"
  40 #include "pvrusb2-video-v4l.h"
  41 #include "pvrusb2-cx2584x-v4l.h"
  42 #include "pvrusb2-cs53l32a.h"
  43 #include "pvrusb2-audio.h"
  44
  45 #define TV_MIN_FREQ     55250000L
  46 #define TV_MAX_FREQ    850000000L
  47
  48 /* This defines a minimum interval that the decoder must remain quiet
  49    before we are allowed to start it running. */
  50 #define TIME_MSEC_DECODER_WAIT 50
  51
  52 /* This defines a minimum interval that the decoder must be allowed to run
  53    before we can safely begin using its streaming output. */
  54 #define TIME_MSEC_DECODER_STABILIZATION_WAIT 300
  55
  56 /* This defines a minimum interval that the encoder must remain quiet
  57    before we are allowed to configure it. */
  58 #define TIME_MSEC_ENCODER_WAIT 50
  59
  60 /* This defines the minimum interval that the encoder must successfully run
  61    before we consider that the encoder has run at least once since its
  62    firmware has been loaded.  This measurement is in important for cases
  63    where we can't do something until we know that the encoder has been run
  64    at least once. */
  65 #define TIME_MSEC_ENCODER_OK 250
  66
  67 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
  68 static DEFINE_MUTEX(pvr2_unit_mtx);
  69
  70 static int ctlchg;
  71 static int procreload;
  72 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
  73 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  74 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
  75 static int init_pause_msec;
  76
  77 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
  78 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
  79 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
  80 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
  81 module_param(procreload, int, S_IRUGO|S_IWUSR);
  82 MODULE_PARM_DESC(procreload,
  83                  "Attempt init failure recovery with firmware reload");
  84 module_param_array(tuner,    int, NULL, 0444);
  85 MODULE_PARM_DESC(tuner,"specify installed tuner type");
  86 module_param_array(video_std,    int, NULL, 0444);
  87 MODULE_PARM_DESC(video_std,"specify initial video standard");
  88 module_param_array(tolerance,    int, NULL, 0444);
  89 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
  90
  91 /* US Broadcast channel 3 (61.25 MHz), to help with testing */
  92 static int default_tv_freq    = 61250000L;
  93 /* 104.3 MHz, a usable FM station for my area */
  94 static int default_radio_freq = 104300000L;
  95
  96 module_param_named(tv_freq, default_tv_freq, int, 0444);
  97 MODULE_PARM_DESC(tv_freq, "specify initial television frequency");
  98 module_param_named(radio_freq, default_radio_freq, int, 0444);
  99 MODULE_PARM_DESC(radio_freq, "specify initial radio frequency");
 100
 101 #define PVR2_CTL_WRITE_ENDPOINT  0x01
 102 #define PVR2_CTL_READ_ENDPOINT   0x81
 103
 104 #define PVR2_GPIO_IN 0x9008
 105 #define PVR2_GPIO_OUT 0x900c
 106 #define PVR2_GPIO_DIR 0x9020
 107
 108 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
 109
 110 #define PVR2_FIRMWARE_ENDPOINT   0x02
 111
 112 /* size of a firmware chunk */
 113 #define FIRMWARE_CHUNK_SIZE 0x2000
 114
 115 typedef void (*pvr2_subdev_update_func)(struct pvr2_hdw *,
 116                                         struct v4l2_subdev *);
 117
 118 static const pvr2_subdev_update_func pvr2_module_update_functions[] = {
 119         [PVR2_CLIENT_ID_WM8775] = pvr2_wm8775_subdev_update,
 120         [PVR2_CLIENT_ID_SAA7115] = pvr2_saa7115_subdev_update,
 121         [PVR2_CLIENT_ID_MSP3400] = pvr2_msp3400_subdev_update,
 122         [PVR2_CLIENT_ID_CX25840] = pvr2_cx25840_subdev_update,
 123         [PVR2_CLIENT_ID_CS53L32A] = pvr2_cs53l32a_subdev_update,
 124 };
 125
 126 static const char *module_names[] = {
 127         [PVR2_CLIENT_ID_MSP3400] = "msp3400",
 128         [PVR2_CLIENT_ID_CX25840] = "cx25840",
 129         [PVR2_CLIENT_ID_SAA7115] = "saa7115",
 130         [PVR2_CLIENT_ID_TUNER] = "tuner",
 131         [PVR2_CLIENT_ID_DEMOD] = "tuner",
 132         [PVR2_CLIENT_ID_CS53L32A] = "cs53l32a",
 133         [PVR2_CLIENT_ID_WM8775] = "wm8775",
 134 };
 135
 136
 137 static const unsigned char *module_i2c_addresses[] = {
 138         [PVR2_CLIENT_ID_TUNER] = "\x60\x61\x62\x63",
 139         [PVR2_CLIENT_ID_DEMOD] = "\x43",
 140         [PVR2_CLIENT_ID_MSP3400] = "\x40",
 141         [PVR2_CLIENT_ID_SAA7115] = "\x21",
 142         [PVR2_CLIENT_ID_WM8775] = "\x1b",
 143         [PVR2_CLIENT_ID_CX25840] = "\x44",
 144         [PVR2_CLIENT_ID_CS53L32A] = "\x11",
 145 };
 146
 147
 148 static const char *ir_scheme_names[] = {
 149         [PVR2_IR_SCHEME_NONE] = "none",
 150         [PVR2_IR_SCHEME_29XXX] = "29xxx",
 151         [PVR2_IR_SCHEME_24XXX] = "24xxx (29xxx emulation)",
 152         [PVR2_IR_SCHEME_24XXX_MCE] = "24xxx (MCE device)",
 153         [PVR2_IR_SCHEME_ZILOG] = "Zilog",
 154 };
 155
 156
 157 /* Define the list of additional controls we'll dynamically construct based
 158    on query of the cx2341x module. */
 159 struct pvr2_mpeg_ids {
 160         const char *strid;
 161         int id;
 162 };
 163 static const struct pvr2_mpeg_ids mpeg_ids[] = {
 164         {
 165                 .strid = "audio_layer",
 166                 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
 167         },{
 168                 .strid = "audio_bitrate",
 169                 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
 170         },{
 171                 /* Already using audio_mode elsewhere :-( */
 172                 .strid = "mpeg_audio_mode",
 173                 .id = V4L2_CID_MPEG_AUDIO_MODE,
 174         },{
 175                 .strid = "mpeg_audio_mode_extension",
 176                 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
 177         },{
 178                 .strid = "audio_emphasis",
 179                 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
 180         },{
 181                 .strid = "audio_crc",
 182                 .id = V4L2_CID_MPEG_AUDIO_CRC,
 183         },{
 184                 .strid = "video_aspect",
 185                 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
 186         },{
 187                 .strid = "video_b_frames",
 188                 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
 189         },{
 190                 .strid = "video_gop_size",
 191                 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
 192         },{
 193                 .strid = "video_gop_closure",
 194                 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
 195         },{
 196                 .strid = "video_bitrate_mode",
 197                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
 198         },{
 199                 .strid = "video_bitrate",
 200                 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
 201         },{
 202                 .strid = "video_bitrate_peak",
 203                 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
 204         },{
 205                 .strid = "video_temporal_decimation",
 206                 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
 207         },{
 208                 .strid = "stream_type",
 209                 .id = V4L2_CID_MPEG_STREAM_TYPE,
 210         },{
 211                 .strid = "video_spatial_filter_mode",
 212                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
 213         },{
 214                 .strid = "video_spatial_filter",
 215                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
 216         },{
 217                 .strid = "video_luma_spatial_filter_type",
 218                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
 219         },{
 220                 .strid = "video_chroma_spatial_filter_type",
 221                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
 222         },{
 223                 .strid = "video_temporal_filter_mode",
 224                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
 225         },{
 226                 .strid = "video_temporal_filter",
 227                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
 228         },{
 229                 .strid = "video_median_filter_type",
 230                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
 231         },{
 232                 .strid = "video_luma_median_filter_top",
 233                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
 234         },{
 235                 .strid = "video_luma_median_filter_bottom",
 236                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
 237         },{
 238                 .strid = "video_chroma_median_filter_top",
 239                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
 240         },{
 241                 .strid = "video_chroma_median_filter_bottom",
 242                 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
 243         }
 244 };
 245 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
 246
 247
 248 static const char *control_values_srate[] = {
 249         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100]   = "44.1 kHz",
 250         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000]   = "48 kHz",
 251         [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000]   = "32 kHz",
 252 };
 253
 254
 255
 256 static const char *control_values_input[] = {
 257         [PVR2_CVAL_INPUT_TV]        = "television",  /*xawtv needs this name*/
 258         [PVR2_CVAL_INPUT_DTV]       = "dtv",
 259         [PVR2_CVAL_INPUT_RADIO]     = "radio",
 260         [PVR2_CVAL_INPUT_SVIDEO]    = "s-video",
 261         [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
 262 };
 263
 264
 265 static const char *control_values_audiomode[] = {
 266         [V4L2_TUNER_MODE_MONO]   = "Mono",
 267         [V4L2_TUNER_MODE_STEREO] = "Stereo",
 268         [V4L2_TUNER_MODE_LANG1]  = "Lang1",
 269         [V4L2_TUNER_MODE_LANG2]  = "Lang2",
 270         [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
 271 };
 272
 273
 274 static const char *control_values_hsm[] = {
 275         [PVR2_CVAL_HSM_FAIL] = "Fail",
 276         [PVR2_CVAL_HSM_HIGH] = "High",
 277         [PVR2_CVAL_HSM_FULL] = "Full",
 278 };
 279
 280
 281 static const char *pvr2_state_names[] = {
 282         [PVR2_STATE_NONE] =    "none",
 283         [PVR2_STATE_DEAD] =    "dead",
 284         [PVR2_STATE_COLD] =    "cold",
 285         [PVR2_STATE_WARM] =    "warm",
 286         [PVR2_STATE_ERROR] =   "error",
 287         [PVR2_STATE_READY] =   "ready",
 288         [PVR2_STATE_RUN] =     "run",
 289 };
 290
 291
 292 struct pvr2_fx2cmd_descdef {
 293         unsigned char id;
 294         unsigned char *desc;
 295 };
 296
 297 static const struct pvr2_fx2cmd_descdef pvr2_fx2cmd_desc[] = {
 298         {FX2CMD_MEM_WRITE_DWORD, "write encoder dword"},
 299         {FX2CMD_MEM_READ_DWORD, "read encoder dword"},
 300         {FX2CMD_HCW_ZILOG_RESET, "zilog IR reset control"},
 301         {FX2CMD_MEM_READ_64BYTES, "read encoder 64bytes"},
 302         {FX2CMD_REG_WRITE, "write encoder register"},
 303         {FX2CMD_REG_READ, "read encoder register"},
 304         {FX2CMD_MEMSEL, "encoder memsel"},
 305         {FX2CMD_I2C_WRITE, "i2c write"},
 306         {FX2CMD_I2C_READ, "i2c read"},
 307         {FX2CMD_GET_USB_SPEED, "get USB speed"},
 308         {FX2CMD_STREAMING_ON, "stream on"},
 309         {FX2CMD_STREAMING_OFF, "stream off"},
 310         {FX2CMD_FWPOST1, "fwpost1"},
 311         {FX2CMD_POWER_OFF, "power off"},
 312         {FX2CMD_POWER_ON, "power on"},
 313         {FX2CMD_DEEP_RESET, "deep reset"},
 314         {FX2CMD_GET_EEPROM_ADDR, "get rom addr"},
 315         {FX2CMD_GET_IR_CODE, "get IR code"},
 316         {FX2CMD_HCW_DEMOD_RESETIN, "hcw demod resetin"},
 317         {FX2CMD_HCW_DTV_STREAMING_ON, "hcw dtv stream on"},
 318         {FX2CMD_HCW_DTV_STREAMING_OFF, "hcw dtv stream off"},
 319         {FX2CMD_ONAIR_DTV_STREAMING_ON, "onair dtv stream on"},
 320         {FX2CMD_ONAIR_DTV_STREAMING_OFF, "onair dtv stream off"},
 321         {FX2CMD_ONAIR_DTV_POWER_ON, "onair dtv power on"},
 322         {FX2CMD_ONAIR_DTV_POWER_OFF, "onair dtv power off"},
 323 };
 324
 325
 326 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v);
 327 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
 328 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
 329 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
 330 static void pvr2_hdw_worker_poll(struct work_struct *work);
 331 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
 332 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
 333 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
 334 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
 335 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
 336 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
 337 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
 338 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
 339 static void pvr2_hdw_quiescent_timeout(unsigned long);
 340 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long);
 341 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
 342 static void pvr2_hdw_encoder_run_timeout(unsigned long);
 343 static int pvr2_issue_simple_cmd(struct pvr2_hdw *,u32);
 344 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
 345                                 unsigned int timeout,int probe_fl,
 346                                 void *write_data,unsigned int write_len,
 347                                 void *read_data,unsigned int read_len);
 348 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw);
 349
 350
 351 static void trace_stbit(const char *name,int val)
 352 {
 353         pvr2_trace(PVR2_TRACE_STBITS,
 354                    "State bit %s <-- %s",
 355                    name,(val ? "true" : "false"));
 356 }
 357
 358 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
 359 {
 360         struct pvr2_hdw *hdw = cptr->hdw;
 361         if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
 362                 *vp = hdw->freqTable[hdw->freqProgSlot-1];
 363         } else {
 364                 *vp = 0;
 365         }
 366         return 0;
 367 }
 368
 369 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
 370 {
 371         struct pvr2_hdw *hdw = cptr->hdw;
 372         unsigned int slotId = hdw->freqProgSlot;
 373         if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
 374                 hdw->freqTable[slotId-1] = v;
 375                 /* Handle side effects correctly - if we're tuned to this
 376                    slot, then forgot the slot id relation since the stored
 377                    frequency has been changed. */
 378                 if (hdw->freqSelector) {
 379                         if (hdw->freqSlotRadio == slotId) {
 380                                 hdw->freqSlotRadio = 0;
 381                         }
 382                 } else {
 383                         if (hdw->freqSlotTelevision == slotId) {
 384                                 hdw->freqSlotTelevision = 0;
 385                         }
 386                 }
 387         }
 388         return 0;
 389 }
 390
 391 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
 392 {
 393         *vp = cptr->hdw->freqProgSlot;
 394         return 0;
 395 }
 396
 397 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
 398 {
 399         struct pvr2_hdw *hdw = cptr->hdw;
 400         if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
 401                 hdw->freqProgSlot = v;
 402         }
 403         return 0;
 404 }
 405
 406 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
 407 {
 408         struct pvr2_hdw *hdw = cptr->hdw;
 409         *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
 410         return 0;
 411 }
 412
 413 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
 414 {
 415         unsigned freq = 0;
 416         struct pvr2_hdw *hdw = cptr->hdw;
 417         if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
 418         if (slotId > 0) {
 419                 freq = hdw->freqTable[slotId-1];
 420                 if (!freq) return 0;
 421                 pvr2_hdw_set_cur_freq(hdw,freq);
 422         }
 423         if (hdw->freqSelector) {
 424                 hdw->freqSlotRadio = slotId;
 425         } else {
 426                 hdw->freqSlotTelevision = slotId;
 427         }
 428         return 0;
 429 }
 430
 431 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
 432 {
 433         *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
 434         return 0;
 435 }
 436
 437 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
 438 {
 439         return cptr->hdw->freqDirty != 0;
 440 }
 441
 442 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
 443 {
 444         cptr->hdw->freqDirty = 0;
 445 }
 446
 447 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
 448 {
 449         pvr2_hdw_set_cur_freq(cptr->hdw,v);
 450         return 0;
 451 }
 452
 453 static int ctrl_cropl_min_get(struct pvr2_ctrl *cptr, int *left)
 454 {
 455         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 456         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 457         if (stat != 0) {
 458                 return stat;
 459         }
 460         *left = cap->bounds.left;
 461         return 0;
 462 }
 463
 464 static int ctrl_cropl_max_get(struct pvr2_ctrl *cptr, int *left)
 465 {
 466         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 467         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 468         if (stat != 0) {
 469                 return stat;
 470         }
 471         *left = cap->bounds.left;
 472         if (cap->bounds.width > cptr->hdw->cropw_val) {
 473                 *left += cap->bounds.width - cptr->hdw->cropw_val;
 474         }
 475         return 0;
 476 }
 477
 478 static int ctrl_cropt_min_get(struct pvr2_ctrl *cptr, int *top)
 479 {
 480         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 481         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 482         if (stat != 0) {
 483                 return stat;
 484         }
 485         *top = cap->bounds.top;
 486         return 0;
 487 }
 488
 489 static int ctrl_cropt_max_get(struct pvr2_ctrl *cptr, int *top)
 490 {
 491         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 492         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 493         if (stat != 0) {
 494                 return stat;
 495         }
 496         *top = cap->bounds.top;
 497         if (cap->bounds.height > cptr->hdw->croph_val) {
 498                 *top += cap->bounds.height - cptr->hdw->croph_val;
 499         }
 500         return 0;
 501 }
 502
 503 static int ctrl_cropw_max_get(struct pvr2_ctrl *cptr, int *width)
 504 {
 505         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 506         int stat, bleftend, cleft;
 507
 508         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 509         if (stat != 0) {
 510                 return stat;
 511         }
 512         bleftend = cap->bounds.left+cap->bounds.width;
 513         cleft = cptr->hdw->cropl_val;
 514
 515         *width = cleft < bleftend ? bleftend-cleft : 0;
 516         return 0;
 517 }
 518
 519 static int ctrl_croph_max_get(struct pvr2_ctrl *cptr, int *height)
 520 {
 521         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 522         int stat, btopend, ctop;
 523
 524         stat = pvr2_hdw_check_cropcap(cptr->hdw);
 525         if (stat != 0) {
 526                 return stat;
 527         }
 528         btopend = cap->bounds.top+cap->bounds.height;
 529         ctop = cptr->hdw->cropt_val;
 530
 531         *height = ctop < btopend ? btopend-ctop : 0;
 532         return 0;
 533 }
 534
 535 static int ctrl_get_cropcapbl(struct pvr2_ctrl *cptr, int *val)
 536 {
 537         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 538         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 539         if (stat != 0) {
 540                 return stat;
 541         }
 542         *val = cap->bounds.left;
 543         return 0;
 544 }
 545
 546 static int ctrl_get_cropcapbt(struct pvr2_ctrl *cptr, int *val)
 547 {
 548         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 549         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 550         if (stat != 0) {
 551                 return stat;
 552         }
 553         *val = cap->bounds.top;
 554         return 0;
 555 }
 556
 557 static int ctrl_get_cropcapbw(struct pvr2_ctrl *cptr, int *val)
 558 {
 559         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 560         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 561         if (stat != 0) {
 562                 return stat;
 563         }
 564         *val = cap->bounds.width;
 565         return 0;
 566 }
 567
 568 static int ctrl_get_cropcapbh(struct pvr2_ctrl *cptr, int *val)
 569 {
 570         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 571         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 572         if (stat != 0) {
 573                 return stat;
 574         }
 575         *val = cap->bounds.height;
 576         return 0;
 577 }
 578
 579 static int ctrl_get_cropcapdl(struct pvr2_ctrl *cptr, int *val)
 580 {
 581         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 582         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 583         if (stat != 0) {
 584                 return stat;
 585         }
 586         *val = cap->defrect.left;
 587         return 0;
 588 }
 589
 590 static int ctrl_get_cropcapdt(struct pvr2_ctrl *cptr, int *val)
 591 {
 592         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 593         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 594         if (stat != 0) {
 595                 return stat;
 596         }
 597         *val = cap->defrect.top;
 598         return 0;
 599 }
 600
 601 static int ctrl_get_cropcapdw(struct pvr2_ctrl *cptr, int *val)
 602 {
 603         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 604         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 605         if (stat != 0) {
 606                 return stat;
 607         }
 608         *val = cap->defrect.width;
 609         return 0;
 610 }
 611
 612 static int ctrl_get_cropcapdh(struct pvr2_ctrl *cptr, int *val)
 613 {
 614         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 615         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 616         if (stat != 0) {
 617                 return stat;
 618         }
 619         *val = cap->defrect.height;
 620         return 0;
 621 }
 622
 623 static int ctrl_get_cropcappan(struct pvr2_ctrl *cptr, int *val)
 624 {
 625         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 626         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 627         if (stat != 0) {
 628                 return stat;
 629         }
 630         *val = cap->pixelaspect.numerator;
 631         return 0;
 632 }
 633
 634 static int ctrl_get_cropcappad(struct pvr2_ctrl *cptr, int *val)
 635 {
 636         struct v4l2_cropcap *cap = &cptr->hdw->cropcap_info;
 637         int stat = pvr2_hdw_check_cropcap(cptr->hdw);
 638         if (stat != 0) {
 639                 return stat;
 640         }
 641         *val = cap->pixelaspect.denominator;
 642         return 0;
 643 }
 644
 645 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
 646 {
 647         /* Actual maximum depends on the video standard in effect. */
 648         if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
 649                 *vp = 480;
 650         } else {
 651                 *vp = 576;
 652         }
 653         return 0;
 654 }
 655
 656 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
 657 {
 658         /* Actual minimum depends on device digitizer type. */
 659         if (cptr->hdw->hdw_desc->flag_has_cx25840) {
 660                 *vp = 75;
 661         } else {
 662                 *vp = 17;
 663         }
 664         return 0;
 665 }
 666
 667 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
 668 {
 669         *vp = cptr->hdw->input_val;
 670         return 0;
 671 }
 672
 673 static int ctrl_check_input(struct pvr2_ctrl *cptr,int v)
 674 {
 675         return ((1 << v) & cptr->hdw->input_allowed_mask) != 0;
 676 }
 677
 678 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
 679 {
 680         return pvr2_hdw_set_input(cptr->hdw,v);
 681 }
 682
 683 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
 684 {
 685         return cptr->hdw->input_dirty != 0;
 686 }
 687
 688 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
 689 {
 690         cptr->hdw->input_dirty = 0;
 691 }
 692
 693
 694 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
 695 {
 696         unsigned long fv;
 697         struct pvr2_hdw *hdw = cptr->hdw;
 698         if (hdw->tuner_signal_stale) {
 699                 pvr2_hdw_status_poll(hdw);
 700         }
 701         fv = hdw->tuner_signal_info.rangehigh;
 702         if (!fv) {
 703                 /* Safety fallback */
 704                 *vp = TV_MAX_FREQ;
 705                 return 0;
 706         }
 707         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 708                 fv = (fv * 125) / 2;
 709         } else {
 710                 fv = fv * 62500;
 711         }
 712         *vp = fv;
 713         return 0;
 714 }
 715
 716 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
 717 {
 718         unsigned long fv;
 719         struct pvr2_hdw *hdw = cptr->hdw;
 720         if (hdw->tuner_signal_stale) {
 721                 pvr2_hdw_status_poll(hdw);
 722         }
 723         fv = hdw->tuner_signal_info.rangelow;
 724         if (!fv) {
 725                 /* Safety fallback */
 726                 *vp = TV_MIN_FREQ;
 727                 return 0;
 728         }
 729         if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
 730                 fv = (fv * 125) / 2;
 731         } else {
 732                 fv = fv * 62500;
 733         }
 734         *vp = fv;
 735         return 0;
 736 }
 737
 738 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
 739 {
 740         return cptr->hdw->enc_stale != 0;
 741 }
 742
 743 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
 744 {
 745         cptr->hdw->enc_stale = 0;
 746         cptr->hdw->enc_unsafe_stale = 0;
 747 }
 748
 749 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
 750 {
 751         int ret;
 752         struct v4l2_ext_controls cs;
 753         struct v4l2_ext_control c1;
 754         memset(&cs,0,sizeof(cs));
 755         memset(&c1,0,sizeof(c1));
 756         cs.controls = &c1;
 757         cs.count = 1;
 758         c1.id = cptr->info->v4l_id;
 759         ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
 760                                 VIDIOC_G_EXT_CTRLS);
 761         if (ret) return ret;
 762         *vp = c1.value;
 763         return 0;
 764 }
 765
 766 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
 767 {
 768         int ret;
 769         struct pvr2_hdw *hdw = cptr->hdw;
 770         struct v4l2_ext_controls cs;
 771         struct v4l2_ext_control c1;
 772         memset(&cs,0,sizeof(cs));
 773         memset(&c1,0,sizeof(c1));
 774         cs.controls = &c1;
 775         cs.count = 1;
 776         c1.id = cptr->info->v4l_id;
 777         c1.value = v;
 778         ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 779                                 hdw->state_encoder_run, &cs,
 780                                 VIDIOC_S_EXT_CTRLS);
 781         if (ret == -EBUSY) {
 782                 /* Oops.  cx2341x is telling us it's not safe to change
 783                    this control while we're capturing.  Make a note of this
 784                    fact so that the pipeline will be stopped the next time
 785                    controls are committed.  Then go on ahead and store this
 786                    change anyway. */
 787                 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
 788                                         0, &cs,
 789                                         VIDIOC_S_EXT_CTRLS);
 790                 if (!ret) hdw->enc_unsafe_stale = !0;
 791         }
 792         if (ret) return ret;
 793         hdw->enc_stale = !0;
 794         return 0;
 795 }
 796
 797 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
 798 {
 799         struct v4l2_queryctrl qctrl;
 800         struct pvr2_ctl_info *info;
 801         qctrl.id = cptr->info->v4l_id;
 802         cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
 803         /* Strip out the const so we can adjust a function pointer.  It's
 804            OK to do this here because we know this is a dynamically created
 805            control, so the underlying storage for the info pointer is (a)
 806            private to us, and (b) not in read-only storage.  Either we do
 807            this or we significantly complicate the underlying control
 808            implementation. */
 809         info = (struct pvr2_ctl_info *)(cptr->info);
 810         if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
 811                 if (info->set_value) {
 812                         info->set_value = NULL;
 813                 }
 814         } else {
 815                 if (!(info->set_value)) {
 816                         info->set_value = ctrl_cx2341x_set;
 817                 }
 818         }
 819         return qctrl.flags;
 820 }
 821
 822 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
 823 {
 824         *vp = cptr->hdw->state_pipeline_req;
 825         return 0;
 826 }
 827
 828 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
 829 {
 830         *vp = cptr->hdw->master_state;
 831         return 0;
 832 }
 833
 834 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
 835 {
 836         int result = pvr2_hdw_is_hsm(cptr->hdw);
 837         *vp = PVR2_CVAL_HSM_FULL;
 838         if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
 839         if (result) *vp = PVR2_CVAL_HSM_HIGH;
 840         return 0;
 841 }
 842
 843 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
 844 {
 845         *vp = cptr->hdw->std_mask_avail;
 846         return 0;
 847 }
 848
 849 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
 850 {
 851         struct pvr2_hdw *hdw = cptr->hdw;
 852         v4l2_std_id ns;
 853         ns = hdw->std_mask_avail;
 854         ns = (ns & ~m) | (v & m);
 855         if (ns == hdw->std_mask_avail) return 0;
 856         hdw->std_mask_avail = ns;
 857         pvr2_hdw_internal_set_std_avail(hdw);
 858         pvr2_hdw_internal_find_stdenum(hdw);
 859         return 0;
 860 }
 861
 862 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
 863                                char *bufPtr,unsigned int bufSize,
 864                                unsigned int *len)
 865 {
 866         *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
 867         return 0;
 868 }
 869
 870 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
 871                                const char *bufPtr,unsigned int bufSize,
 872                                int *mskp,int *valp)
 873 {
 874         int ret;
 875         v4l2_std_id id;
 876         ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
 877         if (ret < 0) return ret;
 878         if (mskp) *mskp = id;
 879         if (valp) *valp = id;
 880         return 0;
 881 }
 882
 883 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
 884 {
 885         *vp = cptr->hdw->std_mask_cur;
 886         return 0;
 887 }
 888
 889 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
 890 {
 891         struct pvr2_hdw *hdw = cptr->hdw;
 892         v4l2_std_id ns;
 893         ns = hdw->std_mask_cur;
 894         ns = (ns & ~m) | (v & m);
 895         if (ns == hdw->std_mask_cur) return 0;
 896         hdw->std_mask_cur = ns;
 897         hdw->std_dirty = !0;
 898         pvr2_hdw_internal_find_stdenum(hdw);
 899         return 0;
 900 }
 901
 902 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
 903 {
 904         return cptr->hdw->std_dirty != 0;
 905 }
 906
 907 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
 908 {
 909         cptr->hdw->std_dirty = 0;
 910 }
 911
 912 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
 913 {
 914         struct pvr2_hdw *hdw = cptr->hdw;
 915         pvr2_hdw_status_poll(hdw);
 916         *vp = hdw->tuner_signal_info.signal;
 917         return 0;
 918 }
 919
 920 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
 921 {
 922         int val = 0;
 923         unsigned int subchan;
 924         struct pvr2_hdw *hdw = cptr->hdw;
 925         pvr2_hdw_status_poll(hdw);
 926         subchan = hdw->tuner_signal_info.rxsubchans;
 927         if (subchan & V4L2_TUNER_SUB_MONO) {
 928                 val |= (1 << V4L2_TUNER_MODE_MONO);
 929         }
 930         if (subchan & V4L2_TUNER_SUB_STEREO) {
 931                 val |= (1 << V4L2_TUNER_MODE_STEREO);
 932         }
 933         if (subchan & V4L2_TUNER_SUB_LANG1) {
 934                 val |= (1 << V4L2_TUNER_MODE_LANG1);
 935         }
 936         if (subchan & V4L2_TUNER_SUB_LANG2) {
 937                 val |= (1 << V4L2_TUNER_MODE_LANG2);
 938         }
 939         *vp = val;
 940         return 0;
 941 }
 942
 943
 944 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
 945 {
 946         struct pvr2_hdw *hdw = cptr->hdw;
 947         if (v < 0) return -EINVAL;
 948         if (v > hdw->std_enum_cnt) return -EINVAL;
 949         hdw->std_enum_cur = v;
 950         if (!v) return 0;
 951         v--;
 952         if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
 953         hdw->std_mask_cur = hdw->std_defs[v].id;
 954         hdw->std_dirty = !0;
 955         return 0;
 956 }
 957
 958
 959 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
 960 {
 961         *vp = cptr->hdw->std_enum_cur;
 962         return 0;
 963 }
 964
 965
 966 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
 967 {
 968         return cptr->hdw->std_dirty != 0;
 969 }
 970
 971
 972 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
 973 {
 974         cptr->hdw->std_dirty = 0;
 975 }
 976
 977
 978 #define DEFINT(vmin,vmax) \
 979         .type = pvr2_ctl_int, \
 980         .def.type_int.min_value = vmin, \
 981         .def.type_int.max_value = vmax
 982
 983 #define DEFENUM(tab) \
 984         .type = pvr2_ctl_enum, \
 985         .def.type_enum.count = ARRAY_SIZE(tab), \
 986         .def.type_enum.value_names = tab
 987
 988 #define DEFBOOL \
 989         .type = pvr2_ctl_bool
 990
 991 #define DEFMASK(msk,tab) \
 992         .type = pvr2_ctl_bitmask, \
 993         .def.type_bitmask.valid_bits = msk, \
 994         .def.type_bitmask.bit_names = tab
 995
 996 #define DEFREF(vname) \
 997         .set_value = ctrl_set_##vname, \
 998         .get_value = ctrl_get_##vname, \
 999         .is_dirty = ctrl_isdirty_##vname, \
1000         .clear_dirty = ctrl_cleardirty_##vname
1001
1002
1003 #define VCREATE_FUNCS(vname) \
1004 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
1005 {*vp = cptr->hdw->vname##_val; return 0;} \
1006 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
1007 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
1008 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
1009 {return cptr->hdw->vname##_dirty != 0;} \
1010 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
1011 {cptr->hdw->vname##_dirty = 0;}
1012
1013 VCREATE_FUNCS(brightness)
1014 VCREATE_FUNCS(contrast)
1015 VCREATE_FUNCS(saturation)
1016 VCREATE_FUNCS(hue)
1017 VCREATE_FUNCS(volume)
1018 VCREATE_FUNCS(balance)
1019 VCREATE_FUNCS(bass)
1020 VCREATE_FUNCS(treble)
1021 VCREATE_FUNCS(mute)
1022 VCREATE_FUNCS(cropl)
1023 VCREATE_FUNCS(cropt)
1024 VCREATE_FUNCS(cropw)
1025 VCREATE_FUNCS(croph)
1026 VCREATE_FUNCS(audiomode)
1027 VCREATE_FUNCS(res_hor)
1028 VCREATE_FUNCS(res_ver)
1029 VCREATE_FUNCS(srate)
1030
1031 /* Table definition of all controls which can be manipulated */
1032 static const struct pvr2_ctl_info control_defs[] = {
1033         {
1034                 .v4l_id = V4L2_CID_BRIGHTNESS,
1035                 .desc = "Brightness",
1036                 .name = "brightness",
1037                 .default_value = 128,
1038                 DEFREF(brightness),
1039                 DEFINT(0,255),
1040         },{
1041                 .v4l_id = V4L2_CID_CONTRAST,
1042                 .desc = "Contrast",
1043                 .name = "contrast",
1044                 .default_value = 68,
1045                 DEFREF(contrast),
1046                 DEFINT(0,127),
1047         },{
1048                 .v4l_id = V4L2_CID_SATURATION,
1049                 .desc = "Saturation",
1050                 .name = "saturation",
1051                 .default_value = 64,
1052                 DEFREF(saturation),
1053                 DEFINT(0,127),
1054         },{
1055                 .v4l_id = V4L2_CID_HUE,
1056                 .desc = "Hue",
1057                 .name = "hue",
1058                 .default_value = 0,
1059                 DEFREF(hue),
1060                 DEFINT(-128,127),
1061         },{
1062                 .v4l_id = V4L2_CID_AUDIO_VOLUME,
1063                 .desc = "Volume",
1064                 .name = "volume",
1065                 .default_value = 62000,
1066                 DEFREF(volume),
1067                 DEFINT(0,65535),
1068         },{
1069                 .v4l_id = V4L2_CID_AUDIO_BALANCE,
1070                 .desc = "Balance",
1071                 .name = "balance",
1072                 .default_value = 0,
1073                 DEFREF(balance),
1074                 DEFINT(-32768,32767),
1075         },{
1076                 .v4l_id = V4L2_CID_AUDIO_BASS,
1077                 .desc = "Bass",
1078                 .name = "bass",
1079                 .default_value = 0,
1080                 DEFREF(bass),
1081                 DEFINT(-32768,32767),
1082         },{
1083                 .v4l_id = V4L2_CID_AUDIO_TREBLE,
1084                 .desc = "Treble",
1085                 .name = "treble",
1086                 .default_value = 0,
1087                 DEFREF(treble),
1088                 DEFINT(-32768,32767),
1089         },{
1090                 .v4l_id = V4L2_CID_AUDIO_MUTE,
1091                 .desc = "Mute",
1092                 .name = "mute",
1093                 .default_value = 0,
1094                 DEFREF(mute),
1095                 DEFBOOL,
1096         }, {
1097                 .desc = "Capture crop left margin",
1098                 .name = "crop_left",
1099                 .internal_id = PVR2_CID_CROPL,
1100                 .default_value = 0,
1101                 DEFREF(cropl),
1102                 DEFINT(-129, 340),
1103                 .get_min_value = ctrl_cropl_min_get,
1104                 .get_max_value = ctrl_cropl_max_get,
1105                 .get_def_value = ctrl_get_cropcapdl,
1106         }, {
1107                 .desc = "Capture crop top margin",
1108                 .name = "crop_top",
1109                 .internal_id = PVR2_CID_CROPT,
1110                 .default_value = 0,
1111                 DEFREF(cropt),
1112                 DEFINT(-35, 544),
1113                 .get_min_value = ctrl_cropt_min_get,
1114                 .get_max_value = ctrl_cropt_max_get,
1115                 .get_def_value = ctrl_get_cropcapdt,
1116         }, {
1117                 .desc = "Capture crop width",
1118                 .name = "crop_width",
1119                 .internal_id = PVR2_CID_CROPW,
1120                 .default_value = 720,
1121                 DEFREF(cropw),
1122                 DEFINT(0, 864),
1123                 .get_max_value = ctrl_cropw_max_get,
1124                 .get_def_value = ctrl_get_cropcapdw,
1125         }, {
1126                 .desc = "Capture crop height",
1127                 .name = "crop_height",
1128                 .internal_id = PVR2_CID_CROPH,
1129                 .default_value = 480,
1130                 DEFREF(croph),
1131                 DEFINT(0, 576),
1132                 .get_max_value = ctrl_croph_max_get,
1133                 .get_def_value = ctrl_get_cropcapdh,
1134         }, {
1135                 .desc = "Capture capability pixel aspect numerator",
1136                 .name = "cropcap_pixel_numerator",
1137                 .internal_id = PVR2_CID_CROPCAPPAN,
1138                 .get_value = ctrl_get_cropcappan,
1139         }, {
1140                 .desc = "Capture capability pixel aspect denominator",
1141                 .name = "cropcap_pixel_denominator",
1142                 .internal_id = PVR2_CID_CROPCAPPAD,
1143                 .get_value = ctrl_get_cropcappad,
1144         }, {
1145                 .desc = "Capture capability bounds top",
1146                 .name = "cropcap_bounds_top",
1147                 .internal_id = PVR2_CID_CROPCAPBT,
1148                 .get_value = ctrl_get_cropcapbt,
1149         }, {
1150                 .desc = "Capture capability bounds left",
1151                 .name = "cropcap_bounds_left",
1152                 .internal_id = PVR2_CID_CROPCAPBL,
1153                 .get_value = ctrl_get_cropcapbl,
1154         }, {
1155                 .desc = "Capture capability bounds width",
1156                 .name = "cropcap_bounds_width",
1157                 .internal_id = PVR2_CID_CROPCAPBW,
1158                 .get_value = ctrl_get_cropcapbw,
1159         }, {
1160                 .desc = "Capture capability bounds height",
1161                 .name = "cropcap_bounds_height",
1162                 .internal_id = PVR2_CID_CROPCAPBH,
1163                 .get_value = ctrl_get_cropcapbh,
1164         },{
1165                 .desc = "Video Source",
1166                 .name = "input",
1167                 .internal_id = PVR2_CID_INPUT,
1168                 .default_value = PVR2_CVAL_INPUT_TV,
1169                 .check_value = ctrl_check_input,
1170                 DEFREF(input),
1171                 DEFENUM(control_values_input),
1172         },{
1173                 .desc = "Audio Mode",
1174                 .name = "audio_mode",
1175                 .internal_id = PVR2_CID_AUDIOMODE,
1176                 .default_value = V4L2_TUNER_MODE_STEREO,
1177                 DEFREF(audiomode),
1178                 DEFENUM(control_values_audiomode),
1179         },{
1180                 .desc = "Horizontal capture resolution",
1181                 .name = "resolution_hor",
1182                 .internal_id = PVR2_CID_HRES,
1183                 .default_value = 720,
1184                 DEFREF(res_hor),
1185                 DEFINT(19,720),
1186         },{
1187                 .desc = "Vertical capture resolution",
1188                 .name = "resolution_ver",
1189                 .internal_id = PVR2_CID_VRES,
1190                 .default_value = 480,
1191                 DEFREF(res_ver),
1192                 DEFINT(17,576),
1193                 /* Hook in check for video standard and adjust maximum
1194                    depending on the standard. */
1195                 .get_max_value = ctrl_vres_max_get,
1196                 .get_min_value = ctrl_vres_min_get,
1197         },{
1198                 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
1199                 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
1200                 .desc = "Audio Sampling Frequency",
1201                 .name = "srate",
1202                 DEFREF(srate),
1203                 DEFENUM(control_values_srate),
1204         },{
1205                 .desc = "Tuner Frequency (Hz)",
1206                 .name = "frequency",
1207                 .internal_id = PVR2_CID_FREQUENCY,
1208                 .default_value = 0,
1209                 .set_value = ctrl_freq_set,
1210                 .get_value = ctrl_freq_get,
1211                 .is_dirty = ctrl_freq_is_dirty,
1212                 .clear_dirty = ctrl_freq_clear_dirty,
1213                 DEFINT(0,0),
1214                 /* Hook in check for input value (tv/radio) and adjust
1215                    max/min values accordingly */
1216                 .get_max_value = ctrl_freq_max_get,
1217                 .get_min_value = ctrl_freq_min_get,
1218         },{
1219                 .desc = "Channel",
1220                 .name = "channel",
1221                 .set_value = ctrl_channel_set,
1222                 .get_value = ctrl_channel_get,
1223                 DEFINT(0,FREQTABLE_SIZE),
1224         },{
1225                 .desc = "Channel Program Frequency",
1226                 .name = "freq_table_value",
1227                 .set_value = ctrl_channelfreq_set,
1228                 .get_value = ctrl_channelfreq_get,
1229                 DEFINT(0,0),
1230                 /* Hook in check for input value (tv/radio) and adjust
1231                    max/min values accordingly */
1232                 .get_max_value = ctrl_freq_max_get,
1233                 .get_min_value = ctrl_freq_min_get,
1234         },{
1235                 .desc = "Channel Program ID",
1236                 .name = "freq_table_channel",
1237                 .set_value = ctrl_channelprog_set,
1238                 .get_value = ctrl_channelprog_get,
1239                 DEFINT(0,FREQTABLE_SIZE),
1240         },{
1241                 .desc = "Streaming Enabled",
1242                 .name = "streaming_enabled",
1243                 .get_value = ctrl_streamingenabled_get,
1244                 DEFBOOL,
1245         },{
1246                 .desc = "USB Speed",
1247                 .name = "usb_speed",
1248                 .get_value = ctrl_hsm_get,
1249                 DEFENUM(control_values_hsm),
1250         },{
1251                 .desc = "Master State",
1252                 .name = "master_state",
1253                 .get_value = ctrl_masterstate_get,
1254                 DEFENUM(pvr2_state_names),
1255         },{
1256                 .desc = "Signal Present",
1257                 .name = "signal_present",
1258                 .get_value = ctrl_signal_get,
1259                 DEFINT(0,65535),
1260         },{
1261                 .desc = "Audio Modes Present",
1262                 .name = "audio_modes_present",
1263                 .get_value = ctrl_audio_modes_present_get,
1264                 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
1265                    v4l.  Nothing outside of this module cares about this,
1266                    but I reuse it in order to also reuse the
1267                    control_values_audiomode string table. */
1268                 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
1269                          (1 << V4L2_TUNER_MODE_STEREO)|
1270                          (1 << V4L2_TUNER_MODE_LANG1)|
1271                          (1 << V4L2_TUNER_MODE_LANG2)),
1272                         control_values_audiomode),
1273         },{
1274                 .desc = "Video Standards Available Mask",
1275                 .name = "video_standard_mask_available",
1276                 .internal_id = PVR2_CID_STDAVAIL,
1277                 .skip_init = !0,
1278                 .get_value = ctrl_stdavail_get,
1279                 .set_value = ctrl_stdavail_set,
1280                 .val_to_sym = ctrl_std_val_to_sym,
1281                 .sym_to_val = ctrl_std_sym_to_val,
1282                 .type = pvr2_ctl_bitmask,
1283         },{
1284                 .desc = "Video Standards In Use Mask",
1285                 .name = "video_standard_mask_active",
1286                 .internal_id = PVR2_CID_STDCUR,
1287                 .skip_init = !0,
1288                 .get_value = ctrl_stdcur_get,
1289                 .set_value = ctrl_stdcur_set,
1290                 .is_dirty = ctrl_stdcur_is_dirty,
1291                 .clear_dirty = ctrl_stdcur_clear_dirty,
1292                 .val_to_sym = ctrl_std_val_to_sym,
1293                 .sym_to_val = ctrl_std_sym_to_val,
1294                 .type = pvr2_ctl_bitmask,
1295         },{
1296                 .desc = "Video Standard Name",
1297                 .name = "video_standard",
1298                 .internal_id = PVR2_CID_STDENUM,
1299                 .skip_init = !0,
1300                 .get_value = ctrl_stdenumcur_get,
1301                 .set_value = ctrl_stdenumcur_set,
1302                 .is_dirty = ctrl_stdenumcur_is_dirty,
1303                 .clear_dirty = ctrl_stdenumcur_clear_dirty,
1304                 .type = pvr2_ctl_enum,
1305         }
1306 };
1307
1308 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
1309
1310
1311 const char *pvr2_config_get_name(enum pvr2_config cfg)
1312 {
1313         switch (cfg) {
1314         case pvr2_config_empty: return "empty";
1315         case pvr2_config_mpeg: return "mpeg";
1316         case pvr2_config_vbi: return "vbi";
1317         case pvr2_config_pcm: return "pcm";
1318         case pvr2_config_rawvideo: return "raw video";
1319         }
1320         return "<unknown>";
1321 }
1322
1323
1324 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
1325 {
1326         return hdw->usb_dev;
1327 }
1328
1329
1330 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
1331 {
1332         return hdw->serial_number;
1333 }
1334
1335
1336 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
1337 {
1338         return hdw->bus_info;
1339 }
1340
1341
1342 const char *pvr2_hdw_get_device_identifier(struct pvr2_hdw *hdw)
1343 {
1344         return hdw->identifier;
1345 }
1346
1347
1348 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
1349 {
1350         return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
1351 }
1352
1353 /* Set the currently tuned frequency and account for all possible
1354    driver-core side effects of this action. */
1355 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
1356 {
1357         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
1358                 if (hdw->freqSelector) {
1359                         /* Swing over to radio frequency selection */
1360                         hdw->freqSelector = 0;
1361                         hdw->freqDirty = !0;
1362                 }
1363                 if (hdw->freqValRadio != val) {
1364                         hdw->freqValRadio = val;
1365                         hdw->freqSlotRadio = 0;
1366                         hdw->freqDirty = !0;
1367                 }
1368         } else {
1369                 if (!(hdw->freqSelector)) {
1370                         /* Swing over to television frequency selection */
1371                         hdw->freqSelector = 1;
1372                         hdw->freqDirty = !0;
1373                 }
1374                 if (hdw->freqValTelevision != val) {
1375                         hdw->freqValTelevision = val;
1376                         hdw->freqSlotTelevision = 0;
1377                         hdw->freqDirty = !0;
1378                 }
1379         }
1380 }
1381
1382 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1383 {
1384         return hdw->unit_number;
1385 }
1386
1387
1388 /* Attempt to locate one of the given set of files.  Messages are logged
1389    appropriate to what has been found.  The return value will be 0 or
1390    greater on success (it will be the index of the file name found) and
1391    fw_entry will be filled in.  Otherwise a negative error is returned on
1392    failure.  If the return value is -ENOENT then no viable firmware file
1393    could be located. */
1394 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1395                                 const struct firmware **fw_entry,
1396                                 const char *fwtypename,
1397                                 unsigned int fwcount,
1398                                 const char *fwnames[])
1399 {
1400         unsigned int idx;
1401         int ret = -EINVAL;
1402         for (idx = 0; idx < fwcount; idx++) {
1403                 ret = request_firmware(fw_entry,
1404                                        fwnames[idx],
1405                                        &hdw->usb_dev->dev);
1406                 if (!ret) {
1407                         trace_firmware("Located %s firmware: %s;"
1408                                        " uploading...",
1409                                        fwtypename,
1410                                        fwnames[idx]);
1411                         return idx;
1412                 }
1413                 if (ret == -ENOENT) continue;
1414                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1415                            "request_firmware fatal error with code=%d",ret);
1416                 return ret;
1417         }
1418         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1419                    "***WARNING***"
1420                    " Device %s firmware"
1421                    " seems to be missing.",
1422                    fwtypename);
1423         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1424                    "Did you install the pvrusb2 firmware files"
1425                    " in their proper location?");
1426         if (fwcount == 1) {
1427                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1428                            "request_firmware unable to locate %s file %s",
1429                            fwtypename,fwnames[0]);
1430         } else {
1431                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1432                            "request_firmware unable to locate"
1433                            " one of the following %s files:",
1434                            fwtypename);
1435                 for (idx = 0; idx < fwcount; idx++) {
1436                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1437                                    "request_firmware: Failed to find %s",
1438                                    fwnames[idx]);
1439                 }
1440         }
1441         return ret;
1442 }
1443
1444
1445 /*
1446  * pvr2_upload_firmware1().
1447  *
1448  * Send the 8051 firmware to the device.  After the upload, arrange for
1449  * device to re-enumerate.
1450  *
1451  * NOTE : the pointer to the firmware data given by request_firmware()
1452  * is not suitable for an usb transaction.
1453  *
1454  */
1455 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1456 {
1457         const struct firmware *fw_entry = NULL;
1458         void  *fw_ptr;
1459         unsigned int pipe;
1460         unsigned int fwsize;
1461         int ret;
1462         u16 address;
1463
1464         if (!hdw->hdw_desc->fx2_firmware.cnt) {
1465                 hdw->fw1_state = FW1_STATE_OK;
1466                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1467                            "Connected device type defines"
1468                            " no firmware to upload; ignoring firmware");
1469                 return -ENOTTY;
1470         }
1471
1472         hdw->fw1_state = FW1_STATE_FAILED; // default result
1473
1474         trace_firmware("pvr2_upload_firmware1");
1475
1476         ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1477                                    hdw->hdw_desc->fx2_firmware.cnt,
1478                                    hdw->hdw_desc->fx2_firmware.lst);
1479         if (ret < 0) {
1480                 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1481                 return ret;
1482         }
1483
1484         usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1485
1486         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1487         fwsize = fw_entry->size;
1488
1489         if ((fwsize != 0x2000) &&
1490             (!(hdw->hdw_desc->flag_fx2_16kb && (fwsize == 0x4000)))) {
1491                 if (hdw->hdw_desc->flag_fx2_16kb) {
1492                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1493                                    "Wrong fx2 firmware size"
1494                                    " (expected 8192 or 16384, got %u)",
1495                                    fwsize);
1496                 } else {
1497                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1498                                    "Wrong fx2 firmware size"
1499                                    " (expected 8192, got %u)",
1500                                    fwsize);
1501                 }
1502                 release_firmware(fw_entry);
1503                 return -ENOMEM;
1504         }
1505
1506         fw_ptr = kmalloc(0x800, GFP_KERNEL);
1507         if (fw_ptr == NULL){
1508                 release_firmware(fw_entry);
1509                 return -ENOMEM;
1510         }
1511
1512         /* We have to hold the CPU during firmware upload. */
1513         pvr2_hdw_cpureset_assert(hdw,1);
1514
1515         /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1516            chunk. */
1517
1518         ret = 0;
1519         for (address = 0; address < fwsize; address += 0x800) {
1520                 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1521                 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1522                                        0, fw_ptr, 0x800, HZ);
1523         }
1524
1525         trace_firmware("Upload done, releasing device's CPU");
1526
1527         /* Now release the CPU.  It will disconnect and reconnect later. */
1528         pvr2_hdw_cpureset_assert(hdw,0);
1529
1530         kfree(fw_ptr);
1531         release_firmware(fw_entry);
1532
1533         trace_firmware("Upload done (%d bytes sent)",ret);
1534
1535         /* We should have written fwsize bytes */
1536         if (ret == fwsize) {
1537                 hdw->fw1_state = FW1_STATE_RELOAD;
1538                 return 0;
1539         }
1540
1541         return -EIO;
1542 }
1543
1544
1545 /*
1546  * pvr2_upload_firmware2()
1547  *
1548  * This uploads encoder firmware on endpoint 2.
1549  *
1550  */
1551
1552 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1553 {
1554         const struct firmware *fw_entry = NULL;
1555         void  *fw_ptr;
1556         unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1557         int actual_length;
1558         int ret = 0;
1559         int fwidx;
1560         static const char *fw_files[] = {
1561                 CX2341X_FIRM_ENC_FILENAME,
1562         };
1563
1564         if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1565                 return 0;
1566         }
1567
1568         trace_firmware("pvr2_upload_firmware2");
1569
1570         ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1571                                    ARRAY_SIZE(fw_files), fw_files);
1572         if (ret < 0) return ret;
1573         fwidx = ret;
1574         ret = 0;
1575         /* Since we're about to completely reinitialize the encoder,
1576            invalidate our cached copy of its configuration state.  Next
1577            time we configure the encoder, then we'll fully configure it. */
1578         hdw->enc_cur_valid = 0;
1579
1580         /* Encoder is about to be reset so note that as far as we're
1581            concerned now, the encoder has never been run. */
1582         del_timer_sync(&hdw->encoder_run_timer);
1583         if (hdw->state_encoder_runok) {
1584                 hdw->state_encoder_runok = 0;
1585                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
1586         }
1587
1588         /* First prepare firmware loading */
1589         ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1590         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1591         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1592         ret |= pvr2_hdw_cmd_deep_reset(hdw);
1593         ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1594         ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1595         ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1596         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1597         ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1598         ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1599         ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1600         ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1601         ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1602         ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1603         ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1604         ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1605         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_FWPOST1);
1606         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1607
1608         if (ret) {
1609                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1610                            "firmware2 upload prep failed, ret=%d",ret);
1611                 release_firmware(fw_entry);
1612                 goto done;
1613         }
1614
1615         /* Now send firmware */
1616
1617         fw_len = fw_entry->size;
1618
1619         if (fw_len % sizeof(u32)) {
1620                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1621                            "size of %s firmware"
1622                            " must be a multiple of %zu bytes",
1623                            fw_files[fwidx],sizeof(u32));
1624                 release_firmware(fw_entry);
1625                 ret = -EINVAL;
1626                 goto done;
1627         }
1628
1629         fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1630         if (fw_ptr == NULL){
1631                 release_firmware(fw_entry);
1632                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1633                            "failed to allocate memory for firmware2 upload");
1634                 ret = -ENOMEM;
1635                 goto done;
1636         }
1637
1638         pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1639
1640         fw_done = 0;
1641         for (fw_done = 0; fw_done < fw_len;) {
1642                 bcnt = fw_len - fw_done;
1643                 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1644                 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1645                 /* Usbsnoop log shows that we must swap bytes... */
1646                 /* Some background info: The data being swapped here is a
1647                    firmware image destined for the mpeg encoder chip that
1648                    lives at the other end of a USB endpoint.  The encoder
1649                    chip always talks in 32 bit chunks and its storage is
1650                    organized into 32 bit words.  However from the file
1651                    system to the encoder chip everything is purely a byte
1652                    stream.  The firmware file's contents are always 32 bit
1653                    swapped from what the encoder expects.  Thus the need
1654                    always exists to swap the bytes regardless of the endian
1655                    type of the host processor and therefore swab32() makes
1656                    the most sense. */
1657                 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1658                         ((u32 *)fw_ptr)[icnt] = swab32(((u32 *)fw_ptr)[icnt]);
1659
1660                 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1661                                     &actual_length, HZ);
1662                 ret |= (actual_length != bcnt);
1663                 if (ret) break;
1664                 fw_done += bcnt;
1665         }
1666
1667         trace_firmware("upload of %s : %i / %i ",
1668                        fw_files[fwidx],fw_done,fw_len);
1669
1670         kfree(fw_ptr);
1671         release_firmware(fw_entry);
1672
1673         if (ret) {
1674                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1675                            "firmware2 upload transfer failure");
1676                 goto done;
1677         }
1678
1679         /* Finish upload */
1680
1681         ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1682         ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1683         ret |= pvr2_issue_simple_cmd(hdw,FX2CMD_MEMSEL | (1 << 8) | (0 << 16));
1684
1685         if (ret) {
1686                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1687                            "firmware2 upload post-proc failure");
1688         }
1689
1690  done:
1691         if (hdw->hdw_desc->signal_routing_scheme ==
1692             PVR2_ROUTING_SCHEME_GOTVIEW) {
1693                 /* Ensure that GPIO 11 is set to output for GOTVIEW
1694                    hardware. */
1695                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
1696         }
1697         return ret;
1698 }
1699
1700
1701 static const char *pvr2_get_state_name(unsigned int st)
1702 {
1703         if (st < ARRAY_SIZE(pvr2_state_names)) {
1704                 return pvr2_state_names[st];
1705         }
1706         return "???";
1707 }
1708
1709 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1710 {
1711         /* Even though we really only care about the video decoder chip at
1712            this point, we'll broadcast stream on/off to all sub-devices
1713            anyway, just in case somebody else wants to hear the
1714            command... */
1715         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 stream=%s",
1716                    (enablefl ? "on" : "off"));
1717         v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_stream, enablefl);
1718         v4l2_device_call_all(&hdw->v4l2_dev, 0, audio, s_stream, enablefl);
1719         if (hdw->decoder_client_id) {
1720                 /* We get here if the encoder has been noticed.  Otherwise
1721                    we'll issue a warning to the user (which should
1722                    normally never happen). */
1723                 return 0;
1724         }
1725         if (!hdw->flag_decoder_missed) {
1726                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1727                            "WARNING: No decoder present");
1728                 hdw->flag_decoder_missed = !0;
1729                 trace_stbit("flag_decoder_missed",
1730                             hdw->flag_decoder_missed);
1731         }
1732         return -EIO;
1733 }
1734
1735
1736 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1737 {
1738         return hdw->master_state;
1739 }
1740
1741
1742 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1743 {
1744         if (!hdw->flag_tripped) return 0;
1745         hdw->flag_tripped = 0;
1746         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1747                    "Clearing driver error statuss");
1748         return !0;
1749 }
1750
1751
1752 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1753 {
1754         int fl;
1755         LOCK_TAKE(hdw->big_lock); do {
1756                 fl = pvr2_hdw_untrip_unlocked(hdw);
1757         } while (0); LOCK_GIVE(hdw->big_lock);
1758         if (fl) pvr2_hdw_state_sched(hdw);
1759         return 0;
1760 }
1761
1762
1763
1764
1765 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1766 {
1767         return hdw->state_pipeline_req != 0;
1768 }
1769
1770
1771 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1772 {
1773         int ret,st;
1774         LOCK_TAKE(hdw->big_lock); do {
1775                 pvr2_hdw_untrip_unlocked(hdw);
1776                 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1777                         hdw->state_pipeline_req = enable_flag != 0;
1778                         pvr2_trace(PVR2_TRACE_START_STOP,
1779                                    "/*--TRACE_STREAM--*/ %s",
1780                                    enable_flag ? "enable" : "disable");
1781                 }
1782                 pvr2_hdw_state_sched(hdw);
1783         } while (0); LOCK_GIVE(hdw->big_lock);
1784         if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1785         if (enable_flag) {
1786                 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1787                         if (st != PVR2_STATE_READY) return -EIO;
1788                         if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1789                 }
1790         }
1791         return 0;
1792 }
1793
1794
1795 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1796 {
1797         int fl;
1798         LOCK_TAKE(hdw->big_lock);
1799         if ((fl = (hdw->desired_stream_type != config)) != 0) {
1800                 hdw->desired_stream_type = config;
1801                 hdw->state_pipeline_config = 0;
1802                 trace_stbit("state_pipeline_config",
1803                             hdw->state_pipeline_config);
1804                 pvr2_hdw_state_sched(hdw);
1805         }
1806         LOCK_GIVE(hdw->big_lock);
1807         if (fl) return 0;
1808         return pvr2_hdw_wait(hdw,0);
1809 }
1810
1811
1812 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1813 {
1814         int unit_number = hdw->unit_number;
1815         int tp = -1;
1816         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1817                 tp = tuner[unit_number];
1818         }
1819         if (tp < 0) return -EINVAL;
1820         hdw->tuner_type = tp;
1821         hdw->tuner_updated = !0;
1822         return 0;
1823 }
1824
1825
1826 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1827 {
1828         int unit_number = hdw->unit_number;
1829         int tp = 0;
1830         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1831                 tp = video_std[unit_number];
1832                 if (tp) return tp;
1833         }
1834         return 0;
1835 }
1836
1837
1838 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1839 {
1840         int unit_number = hdw->unit_number;
1841         int tp = 0;
1842         if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1843                 tp = tolerance[unit_number];
1844         }
1845         return tp;
1846 }
1847
1848
1849 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1850 {
1851         /* Try a harmless request to fetch the eeprom's address over
1852            endpoint 1.  See what happens.  Only the full FX2 image can
1853            respond to this.  If this probe fails then likely the FX2
1854            firmware needs be loaded. */
1855         int result;
1856         LOCK_TAKE(hdw->ctl_lock); do {
1857                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1858                 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1859                                            hdw->cmd_buffer,1,
1860                                            hdw->cmd_buffer,1);
1861                 if (result < 0) break;
1862         } while(0); LOCK_GIVE(hdw->ctl_lock);
1863         if (result) {
1864                 pvr2_trace(PVR2_TRACE_INIT,
1865                            "Probe of device endpoint 1 result status %d",
1866                            result);
1867         } else {
1868                 pvr2_trace(PVR2_TRACE_INIT,
1869                            "Probe of device endpoint 1 succeeded");
1870         }
1871         return result == 0;
1872 }
1873
1874 struct pvr2_std_hack {
1875         v4l2_std_id pat;  /* Pattern to match */
1876         v4l2_std_id msk;  /* Which bits we care about */
1877         v4l2_std_id std;  /* What additional standards or default to set */
1878 };
1879
1880 /* This data structure labels specific combinations of standards from
1881    tveeprom that we'll try to recognize.  If we recognize one, then assume
1882    a specified default standard to use.  This is here because tveeprom only
1883    tells us about available standards not the intended default standard (if
1884    any) for the device in question.  We guess the default based on what has
1885    been reported as available.  Note that this is only for guessing a
1886    default - which can always be overridden explicitly - and if the user
1887    has otherwise named a default then that default will always be used in
1888    place of this table. */
1889 static const struct pvr2_std_hack std_eeprom_maps[] = {
1890         {       /* PAL(B/G) */
1891                 .pat = V4L2_STD_B|V4L2_STD_GH,
1892                 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1893         },
1894         {       /* NTSC(M) */
1895                 .pat = V4L2_STD_MN,
1896                 .std = V4L2_STD_NTSC_M,
1897         },
1898         {       /* PAL(I) */
1899                 .pat = V4L2_STD_PAL_I,
1900                 .std = V4L2_STD_PAL_I,
1901         },
1902         {       /* SECAM(L/L') */
1903                 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1904                 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1905         },
1906         {       /* PAL(D/D1/K) */
1907                 .pat = V4L2_STD_DK,
1908                 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1909         },
1910 };
1911
1912 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1913 {
1914         char buf[40];
1915         unsigned int bcnt;
1916         v4l2_std_id std1,std2,std3;
1917
1918         std1 = get_default_standard(hdw);
1919         std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1920
1921         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1922         pvr2_trace(PVR2_TRACE_STD,
1923                    "Supported video standard(s) reported available"
1924                    " in hardware: %.*s",
1925                    bcnt,buf);
1926
1927         hdw->std_mask_avail = hdw->std_mask_eeprom;
1928
1929         std2 = (std1|std3) & ~hdw->std_mask_avail;
1930         if (std2) {
1931                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1932                 pvr2_trace(PVR2_TRACE_STD,
1933                            "Expanding supported video standards"
1934                            " to include: %.*s",
1935                            bcnt,buf);
1936                 hdw->std_mask_avail |= std2;
1937         }
1938
1939         pvr2_hdw_internal_set_std_avail(hdw);
1940
1941         if (std1) {
1942                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1943                 pvr2_trace(PVR2_TRACE_STD,
1944                            "Initial video standard forced to %.*s",
1945                            bcnt,buf);
1946                 hdw->std_mask_cur = std1;
1947                 hdw->std_dirty = !0;
1948                 pvr2_hdw_internal_find_stdenum(hdw);
1949                 return;
1950         }
1951         if (std3) {
1952                 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1953                 pvr2_trace(PVR2_TRACE_STD,
1954                            "Initial video standard"
1955                            " (determined by device type): %.*s",bcnt,buf);
1956                 hdw->std_mask_cur = std3;
1957                 hdw->std_dirty = !0;
1958                 pvr2_hdw_internal_find_stdenum(hdw);
1959                 return;
1960         }
1961
1962         {
1963                 unsigned int idx;
1964                 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1965                         if (std_eeprom_maps[idx].msk ?
1966                             ((std_eeprom_maps[idx].pat ^
1967                              hdw->std_mask_eeprom) &
1968                              std_eeprom_maps[idx].msk) :
1969                             (std_eeprom_maps[idx].pat !=
1970                              hdw->std_mask_eeprom)) continue;
1971                         bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1972                                                   std_eeprom_maps[idx].std);
1973                         pvr2_trace(PVR2_TRACE_STD,
1974                                    "Initial video standard guessed as %.*s",
1975                                    bcnt,buf);
1976                         hdw->std_mask_cur = std_eeprom_maps[idx].std;
1977                         hdw->std_dirty = !0;
1978                         pvr2_hdw_internal_find_stdenum(hdw);
1979                         return;
1980                 }
1981         }
1982
1983         if (hdw->std_enum_cnt > 1) {
1984                 // Autoselect the first listed standard
1985                 hdw->std_enum_cur = 1;
1986                 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1987                 hdw->std_dirty = !0;
1988                 pvr2_trace(PVR2_TRACE_STD,
1989                            "Initial video standard auto-selected to %s",
1990                            hdw->std_defs[hdw->std_enum_cur-1].name);
1991                 return;
1992         }
1993
1994         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1995                    "Unable to select a viable initial video standard");
1996 }
1997
1998
1999 static unsigned int pvr2_copy_i2c_addr_list(
2000         unsigned short *dst, const unsigned char *src,
2001         unsigned int dst_max)
2002 {
2003         unsigned int cnt = 0;
2004         if (!src) return 0;
2005         while (src[cnt] && (cnt + 1) < dst_max) {
2006                 dst[cnt] = src[cnt];
2007                 cnt++;
2008         }
2009         dst[cnt] = I2C_CLIENT_END;
2010         return cnt;
2011 }
2012
2013
2014 static void pvr2_hdw_cx25840_vbi_hack(struct pvr2_hdw *hdw)
2015 {
2016         /*
2017           Mike Isely <isely@pobox.com> 19-Nov-2006 - This bit of nuttiness
2018           for cx25840 causes that module to correctly set up its video
2019           scaling.  This is really a problem in the cx25840 module itself,
2020           but we work around it here.  The problem has not been seen in
2021           ivtv because there VBI is supported and set up.  We don't do VBI
2022           here (at least not yet) and thus we never attempted to even set
2023           it up.
2024         */
2025         struct v4l2_format fmt;
2026         if (hdw->decoder_client_id != PVR2_CLIENT_ID_CX25840) {
2027                 /* We're not using a cx25840 so don't enable the hack */
2028                 return;
2029         }
2030
2031         pvr2_trace(PVR2_TRACE_INIT,
2032                    "Module ID %u:"
2033                    " Executing cx25840 VBI hack",
2034                    hdw->decoder_client_id);
2035         memset(&fmt, 0, sizeof(fmt));
2036         fmt.type = V4L2_BUF_TYPE_SLICED_VBI_CAPTURE;
2037         fmt.fmt.sliced.service_lines[0][21] = V4L2_SLICED_CAPTION_525;
2038         fmt.fmt.sliced.service_lines[1][21] = V4L2_SLICED_CAPTION_525;
2039         v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
2040                              vbi, s_sliced_fmt, &fmt.fmt.sliced);
2041 }
2042
2043
2044 static int pvr2_hdw_load_subdev(struct pvr2_hdw *hdw,
2045                                 const struct pvr2_device_client_desc *cd)
2046 {
2047         const char *fname;
2048         unsigned char mid;
2049         struct v4l2_subdev *sd;
2050         unsigned int i2ccnt;
2051         const unsigned char *p;
2052         /* Arbitrary count - max # i2c addresses we will probe */
2053         unsigned short i2caddr[25];
2054
2055         mid = cd->module_id;
2056         fname = (mid < ARRAY_SIZE(module_names)) ? module_names[mid] : NULL;
2057         if (!fname) {
2058                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2059                            "Module ID %u for device %s has no name?"
2060                            "  The driver might have a configuration problem.",
2061                            mid,
2062                            hdw->hdw_desc->description);
2063                 return -EINVAL;
2064         }
2065         pvr2_trace(PVR2_TRACE_INIT,
2066                    "Module ID %u (%s) for device %s being loaded...",
2067                    mid, fname,
2068                    hdw->hdw_desc->description);
2069
2070         i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, cd->i2c_address_list,
2071                                          ARRAY_SIZE(i2caddr));
2072         if (!i2ccnt && ((p = (mid < ARRAY_SIZE(module_i2c_addresses)) ?
2073                          module_i2c_addresses[mid] : NULL) != NULL)) {
2074                 /* Second chance: Try default i2c address list */
2075                 i2ccnt = pvr2_copy_i2c_addr_list(i2caddr, p,
2076                                                  ARRAY_SIZE(i2caddr));
2077                 if (i2ccnt) {
2078                         pvr2_trace(PVR2_TRACE_INIT,
2079                                    "Module ID %u:"
2080                                    " Using default i2c address list",
2081                                    mid);
2082                 }
2083         }
2084
2085         if (!i2ccnt) {
2086                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2087                            "Module ID %u (%s) for device %s:"
2088                            " No i2c addresses."
2089                            "  The driver might have a configuration problem.",
2090                            mid, fname, hdw->hdw_desc->description);
2091                 return -EINVAL;
2092         }
2093
2094         if (i2ccnt == 1) {
2095                 pvr2_trace(PVR2_TRACE_INIT,
2096                            "Module ID %u:"
2097                            " Setting up with specified i2c address 0x%x",
2098                            mid, i2caddr[0]);
2099                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2100                                          fname, i2caddr[0], NULL);
2101         } else {
2102                 pvr2_trace(PVR2_TRACE_INIT,
2103                            "Module ID %u:"
2104                            " Setting up with address probe list",
2105                            mid);
2106                 sd = v4l2_i2c_new_subdev(&hdw->v4l2_dev, &hdw->i2c_adap,
2107                                          fname, 0, i2caddr);
2108         }
2109
2110         if (!sd) {
2111                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2112                            "Module ID %u (%s) for device %s failed to load."
2113                            "  Possible missing sub-device kernel module or"
2114                            " initialization failure within module.",
2115                            mid, fname, hdw->hdw_desc->description);
2116                 return -EIO;
2117         }
2118
2119         /* Tag this sub-device instance with the module ID we know about.
2120            In other places we'll use that tag to determine if the instance
2121            requires special handling. */
2122         sd->grp_id = mid;
2123
2124         pvr2_trace(PVR2_TRACE_INFO, "Attached sub-driver %s", fname);
2125
2126
2127         /* client-specific setup... */
2128         switch (mid) {
2129         case PVR2_CLIENT_ID_CX25840:
2130         case PVR2_CLIENT_ID_SAA7115:
2131                 hdw->decoder_client_id = mid;
2132                 break;
2133         default: break;
2134         }
2135
2136         return 0;
2137 }
2138
2139
2140 static void pvr2_hdw_load_modules(struct pvr2_hdw *hdw)
2141 {
2142         unsigned int idx;
2143         const struct pvr2_string_table *cm;
2144         const struct pvr2_device_client_table *ct;
2145         int okFl = !0;
2146
2147         cm = &hdw->hdw_desc->client_modules;
2148         for (idx = 0; idx < cm->cnt; idx++) {
2149                 request_module(cm->lst[idx]);
2150         }
2151
2152         ct = &hdw->hdw_desc->client_table;
2153         for (idx = 0; idx < ct->cnt; idx++) {
2154                 if (pvr2_hdw_load_subdev(hdw, &ct->lst[idx]) < 0) okFl = 0;
2155         }
2156         if (!okFl) {
2157                 hdw->flag_modulefail = !0;
2158                 pvr2_hdw_render_useless(hdw);
2159         }
2160 }
2161
2162
2163 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
2164 {
2165         int ret;
2166         unsigned int idx;
2167         struct pvr2_ctrl *cptr;
2168         int reloadFl = 0;
2169         if (hdw->hdw_desc->fx2_firmware.cnt) {
2170                 if (!reloadFl) {
2171                         reloadFl =
2172                                 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
2173                                  == 0);
2174                         if (reloadFl) {
2175                                 pvr2_trace(PVR2_TRACE_INIT,
2176                                            "USB endpoint config looks strange"
2177                                            "; possibly firmware needs to be"
2178                                            " loaded");
2179                         }
2180                 }
2181                 if (!reloadFl) {
2182                         reloadFl = !pvr2_hdw_check_firmware(hdw);
2183                         if (reloadFl) {
2184                                 pvr2_trace(PVR2_TRACE_INIT,
2185                                            "Check for FX2 firmware failed"
2186                                            "; possibly firmware needs to be"
2187                                            " loaded");
2188                         }
2189                 }
2190                 if (reloadFl) {
2191                         if (pvr2_upload_firmware1(hdw) != 0) {
2192                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2193                                            "Failure uploading firmware1");
2194                         }
2195                         return;
2196                 }
2197         }
2198         hdw->fw1_state = FW1_STATE_OK;
2199
2200         if (!pvr2_hdw_dev_ok(hdw)) return;
2201
2202         hdw->force_dirty = !0;
2203
2204         if (!hdw->hdw_desc->flag_no_powerup) {
2205                 pvr2_hdw_cmd_powerup(hdw);
2206                 if (!pvr2_hdw_dev_ok(hdw)) return;
2207         }
2208
2209         /* Take the IR chip out of reset, if appropriate */
2210         if (hdw->ir_scheme_active == PVR2_IR_SCHEME_ZILOG) {
2211                 pvr2_issue_simple_cmd(hdw,
2212                                       FX2CMD_HCW_ZILOG_RESET |
2213                                       (1 << 8) |
2214                                       ((0) << 16));
2215         }
2216
2217         // This step MUST happen after the earlier powerup step.
2218         pvr2_i2c_core_init(hdw);
2219         if (!pvr2_hdw_dev_ok(hdw)) return;
2220
2221         pvr2_hdw_load_modules(hdw);
2222         if (!pvr2_hdw_dev_ok(hdw)) return;
2223
2224         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, load_fw);
2225
2226         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2227                 cptr = hdw->controls + idx;
2228                 if (cptr->info->skip_init) continue;
2229                 if (!cptr->info->set_value) continue;
2230                 cptr->info->set_value(cptr,~0,cptr->info->default_value);
2231         }
2232
2233         pvr2_hdw_cx25840_vbi_hack(hdw);
2234
2235         /* Set up special default values for the television and radio
2236            frequencies here.  It's not really important what these defaults
2237            are, but I set them to something usable in the Chicago area just
2238            to make driver testing a little easier. */
2239
2240         hdw->freqValTelevision = default_tv_freq;
2241         hdw->freqValRadio = default_radio_freq;
2242
2243         // Do not use pvr2_reset_ctl_endpoints() here.  It is not
2244         // thread-safe against the normal pvr2_send_request() mechanism.
2245         // (We should make it thread safe).
2246
2247         if (hdw->hdw_desc->flag_has_hauppauge_rom) {
2248                 ret = pvr2_hdw_get_eeprom_addr(hdw);
2249                 if (!pvr2_hdw_dev_ok(hdw)) return;
2250                 if (ret < 0) {
2251                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2252                                    "Unable to determine location of eeprom,"
2253                                    " skipping");
2254                 } else {
2255                         hdw->eeprom_addr = ret;
2256                         pvr2_eeprom_analyze(hdw);
2257                         if (!pvr2_hdw_dev_ok(hdw)) return;
2258                 }
2259         } else {
2260                 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
2261                 hdw->tuner_updated = !0;
2262                 hdw->std_mask_eeprom = V4L2_STD_ALL;
2263         }
2264
2265         if (hdw->serial_number) {
2266                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2267                                 "sn-%lu", hdw->serial_number);
2268         } else if (hdw->unit_number >= 0) {
2269                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2270                                 "unit-%c",
2271                                 hdw->unit_number + 'a');
2272         } else {
2273                 idx = scnprintf(hdw->identifier, sizeof(hdw->identifier) - 1,
2274                                 "unit-??");
2275         }
2276         hdw->identifier[idx] = 0;
2277
2278         pvr2_hdw_setup_std(hdw);
2279
2280         if (!get_default_tuner_type(hdw)) {
2281                 pvr2_trace(PVR2_TRACE_INIT,
2282                            "pvr2_hdw_setup: Tuner type overridden to %d",
2283                            hdw->tuner_type);
2284         }
2285
2286
2287         if (!pvr2_hdw_dev_ok(hdw)) return;
2288
2289         if (hdw->hdw_desc->signal_routing_scheme ==
2290             PVR2_ROUTING_SCHEME_GOTVIEW) {
2291                 /* Ensure that GPIO 11 is set to output for GOTVIEW
2292                    hardware. */
2293                 pvr2_hdw_gpio_chg_dir(hdw,(1 << 11),~0);
2294         }
2295
2296         pvr2_hdw_commit_setup(hdw);
2297
2298         hdw->vid_stream = pvr2_stream_create();
2299         if (!pvr2_hdw_dev_ok(hdw)) return;
2300         pvr2_trace(PVR2_TRACE_INIT,
2301                    "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
2302         if (hdw->vid_stream) {
2303                 idx = get_default_error_tolerance(hdw);
2304                 if (idx) {
2305                         pvr2_trace(PVR2_TRACE_INIT,
2306                                    "pvr2_hdw_setup: video stream %p"
2307                                    " setting tolerance %u",
2308                                    hdw->vid_stream,idx);
2309                 }
2310                 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
2311                                   PVR2_VID_ENDPOINT,idx);
2312         }
2313
2314         if (!pvr2_hdw_dev_ok(hdw)) return;
2315
2316         hdw->flag_init_ok = !0;
2317
2318         pvr2_hdw_state_sched(hdw);
2319 }
2320
2321
2322 /* Set up the structure and attempt to put the device into a usable state.
2323    This can be a time-consuming operation, which is why it is not done
2324    internally as part of the create() step. */
2325 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
2326 {
2327         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
2328         do {
2329                 pvr2_hdw_setup_low(hdw);
2330                 pvr2_trace(PVR2_TRACE_INIT,
2331                            "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
2332                            hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
2333                 if (pvr2_hdw_dev_ok(hdw)) {
2334                         if (hdw->flag_init_ok) {
2335                                 pvr2_trace(
2336                                         PVR2_TRACE_INFO,
2337                                         "Device initialization"
2338                                         " completed successfully.");
2339                                 break;
2340                         }
2341                         if (hdw->fw1_state == FW1_STATE_RELOAD) {
2342                                 pvr2_trace(
2343                                         PVR2_TRACE_INFO,
2344                                         "Device microcontroller firmware"
2345                                         " (re)loaded; it should now reset"
2346                                         " and reconnect.");
2347                                 break;
2348                         }
2349                         pvr2_trace(
2350                                 PVR2_TRACE_ERROR_LEGS,
2351                                 "Device initialization was not successful.");
2352                         if (hdw->fw1_state == FW1_STATE_MISSING) {
2353                                 pvr2_trace(
2354                                         PVR2_TRACE_ERROR_LEGS,
2355                                         "Giving up since device"
2356                                         " microcontroller firmware"
2357                                         " appears to be missing.");
2358                                 break;
2359                         }
2360                 }
2361                 if (hdw->flag_modulefail) {
2362                         pvr2_trace(
2363                                 PVR2_TRACE_ERROR_LEGS,
2364                                 "***WARNING*** pvrusb2 driver initialization"
2365                                 " failed due to the failure of one or more"
2366                                 " sub-device kernel modules.");
2367                         pvr2_trace(
2368                                 PVR2_TRACE_ERROR_LEGS,
2369                                 "You need to resolve the failing condition"
2370                                 " before this driver can function.  There"
2371                                 " should be some earlier messages giving more"
2372                                 " information about the problem.");
2373                         break;
2374                 }
2375                 if (procreload) {
2376                         pvr2_trace(
2377                                 PVR2_TRACE_ERROR_LEGS,
2378                                 "Attempting pvrusb2 recovery by reloading"
2379                                 " primary firmware.");
2380                         pvr2_trace(
2381                                 PVR2_TRACE_ERROR_LEGS,
2382                                 "If this works, device should disconnect"
2383                                 " and reconnect in a sane state.");
2384                         hdw->fw1_state = FW1_STATE_UNKNOWN;
2385                         pvr2_upload_firmware1(hdw);
2386                 } else {
2387                         pvr2_trace(
2388                                 PVR2_TRACE_ERROR_LEGS,
2389                                 "***WARNING*** pvrusb2 device hardware"
2390                                 " appears to be jammed"
2391                                 " and I can't clear it.");
2392                         pvr2_trace(
2393                                 PVR2_TRACE_ERROR_LEGS,
2394                                 "You might need to power cycle"
2395                                 " the pvrusb2 device"
2396                                 " in order to recover.");
2397                 }
2398         } while (0);
2399         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
2400 }
2401
2402
2403 /* Perform second stage initialization.  Set callback pointer first so that
2404    we can avoid a possible initialization race (if the kernel thread runs
2405    before the callback has been set). */
2406 int pvr2_hdw_initialize(struct pvr2_hdw *hdw,
2407                         void (*callback_func)(void *),
2408                         void *callback_data)
2409 {
2410         LOCK_TAKE(hdw->big_lock); do {
2411                 if (hdw->flag_disconnected) {
2412                         /* Handle a race here: If we're already
2413                            disconnected by this point, then give up.  If we
2414                            get past this then we'll remain connected for
2415                            the duration of initialization since the entire
2416                            initialization sequence is now protected by the
2417                            big_lock. */
2418                         break;
2419                 }
2420                 hdw->state_data = callback_data;
2421                 hdw->state_func = callback_func;
2422                 pvr2_hdw_setup(hdw);
2423         } while (0); LOCK_GIVE(hdw->big_lock);
2424         return hdw->flag_init_ok;
2425 }
2426
2427
2428 /* Create, set up, and return a structure for interacting with the
2429    underlying hardware.  */
2430 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
2431                                  const struct usb_device_id *devid)
2432 {
2433         unsigned int idx,cnt1,cnt2,m;
2434         struct pvr2_hdw *hdw = NULL;
2435         int valid_std_mask;
2436         struct pvr2_ctrl *cptr;
2437         struct usb_device *usb_dev;
2438         const struct pvr2_device_desc *hdw_desc;
2439         __u8 ifnum;
2440         struct v4l2_queryctrl qctrl;
2441         struct pvr2_ctl_info *ciptr;
2442
2443         usb_dev = interface_to_usbdev(intf);
2444
2445         hdw_desc = (const struct pvr2_device_desc *)(devid->driver_info);
2446
2447         if (hdw_desc == NULL) {
2448                 pvr2_trace(PVR2_TRACE_INIT, "pvr2_hdw_create:"
2449                            " No device description pointer,"
2450                            " unable to continue.");
2451                 pvr2_trace(PVR2_TRACE_INIT, "If you have a new device type,"
2452                            " please contact Mike Isely <isely@pobox.com>"
2453                            " to get it included in the driver\n");
2454                 goto fail;
2455         }
2456
2457         hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
2458         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
2459                    hdw,hdw_desc->description);
2460         pvr2_trace(PVR2_TRACE_INFO, "Hardware description: %s",
2461                 hdw_desc->description);
2462         if (hdw_desc->flag_is_experimental) {
2463                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2464                 pvr2_trace(PVR2_TRACE_INFO,
2465                            "WARNING: Support for this device (%s) is"
2466                            " experimental.", hdw_desc->description);
2467                 pvr2_trace(PVR2_TRACE_INFO,
2468                            "Important functionality might not be"
2469                            " entirely working.");
2470                 pvr2_trace(PVR2_TRACE_INFO,
2471                            "Please consider contacting the driver author to"
2472                            " help with further stabilization of the driver.");
2473                 pvr2_trace(PVR2_TRACE_INFO, "**********");
2474         }
2475         if (!hdw) goto fail;
2476
2477         init_timer(&hdw->quiescent_timer);
2478         hdw->quiescent_timer.data = (unsigned long)hdw;
2479         hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
2480
2481         init_timer(&hdw->decoder_stabilization_timer);
2482         hdw->decoder_stabilization_timer.data = (unsigned long)hdw;
2483         hdw->decoder_stabilization_timer.function =
2484                 pvr2_hdw_decoder_stabilization_timeout;
2485
2486         init_timer(&hdw->encoder_wait_timer);
2487         hdw->encoder_wait_timer.data = (unsigned long)hdw;
2488         hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
2489
2490         init_timer(&hdw->encoder_run_timer);
2491         hdw->encoder_run_timer.data = (unsigned long)hdw;
2492         hdw->encoder_run_timer.function = pvr2_hdw_encoder_run_timeout;
2493
2494         hdw->master_state = PVR2_STATE_DEAD;
2495
2496         init_waitqueue_head(&hdw->state_wait_data);
2497
2498         hdw->tuner_signal_stale = !0;
2499         cx2341x_fill_defaults(&hdw->enc_ctl_state);
2500
2501         /* Calculate which inputs are OK */
2502         m = 0;
2503         if (hdw_desc->flag_has_analogtuner) m |= 1 << PVR2_CVAL_INPUT_TV;
2504         if (hdw_desc->digital_control_scheme != PVR2_DIGITAL_SCHEME_NONE) {
2505                 m |= 1 << PVR2_CVAL_INPUT_DTV;
2506         }
2507         if (hdw_desc->flag_has_svideo) m |= 1 << PVR2_CVAL_INPUT_SVIDEO;
2508         if (hdw_desc->flag_has_composite) m |= 1 << PVR2_CVAL_INPUT_COMPOSITE;
2509         if (hdw_desc->flag_has_fmradio) m |= 1 << PVR2_CVAL_INPUT_RADIO;
2510         hdw->input_avail_mask = m;
2511         hdw->input_allowed_mask = hdw->input_avail_mask;
2512
2513         /* If not a hybrid device, pathway_state never changes.  So
2514            initialize it here to what it should forever be. */
2515         if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_DTV))) {
2516                 hdw->pathway_state = PVR2_PATHWAY_ANALOG;
2517         } else if (!(hdw->input_avail_mask & (1 << PVR2_CVAL_INPUT_TV))) {
2518                 hdw->pathway_state = PVR2_PATHWAY_DIGITAL;
2519         }
2520
2521         hdw->control_cnt = CTRLDEF_COUNT;
2522         hdw->control_cnt += MPEGDEF_COUNT;
2523         hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
2524                                 GFP_KERNEL);
2525         if (!hdw->controls) goto fail;
2526         hdw->hdw_desc = hdw_desc;
2527         hdw->ir_scheme_active = hdw->hdw_desc->ir_scheme;
2528         for (idx = 0; idx < hdw->control_cnt; idx++) {
2529                 cptr = hdw->controls + idx;
2530                 cptr->hdw = hdw;
2531         }
2532         for (idx = 0; idx < 32; idx++) {
2533                 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
2534         }
2535         for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
2536                 cptr = hdw->controls + idx;
2537                 cptr->info = control_defs+idx;
2538         }
2539
2540         /* Ensure that default input choice is a valid one. */
2541         m = hdw->input_avail_mask;
2542         if (m) for (idx = 0; idx < (sizeof(m) << 3); idx++) {
2543                 if (!((1 << idx) & m)) continue;
2544                 hdw->input_val = idx;
2545                 break;
2546         }
2547
2548         /* Define and configure additional controls from cx2341x module. */
2549         hdw->mpeg_ctrl_info = kcalloc(MPEGDEF_COUNT,
2550                                       sizeof(*(hdw->mpeg_ctrl_info)),
2551                                       GFP_KERNEL);
2552         if (!hdw->mpeg_ctrl_info) goto fail;
2553         for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
2554                 cptr = hdw->controls + idx + CTRLDEF_COUNT;
2555                 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
2556                 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
2557                 ciptr->name = mpeg_ids[idx].strid;
2558                 ciptr->v4l_id = mpeg_ids[idx].id;
2559                 ciptr->skip_init = !0;
2560                 ciptr->get_value = ctrl_cx2341x_get;
2561                 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
2562                 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
2563                 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
2564                 qctrl.id = ciptr->v4l_id;
2565                 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
2566                 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
2567                         ciptr->set_value = ctrl_cx2341x_set;
2568                 }
2569                 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
2570                         PVR2_CTLD_INFO_DESC_SIZE);
2571                 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
2572                 ciptr->default_value = qctrl.default_value;
2573                 switch (qctrl.type) {
2574                 default:
2575                 case V4L2_CTRL_TYPE_INTEGER:
2576                         ciptr->type = pvr2_ctl_int;
2577                         ciptr->def.type_int.min_value = qctrl.minimum;
2578                         ciptr->def.type_int.max_value = qctrl.maximum;
2579                         break;
2580                 case V4L2_CTRL_TYPE_BOOLEAN:
2581                         ciptr->type = pvr2_ctl_bool;
2582                         break;
2583                 case V4L2_CTRL_TYPE_MENU:
2584                         ciptr->type = pvr2_ctl_enum;
2585                         ciptr->def.type_enum.value_names =
2586                                 cx2341x_ctrl_get_menu(&hdw->enc_ctl_state,
2587                                                                 ciptr->v4l_id);
2588                         for (cnt1 = 0;
2589                              ciptr->def.type_enum.value_names[cnt1] != NULL;
2590                              cnt1++) { }
2591                         ciptr->def.type_enum.count = cnt1;
2592                         break;
2593                 }
2594                 cptr->info = ciptr;
2595         }
2596
2597         // Initialize video standard enum dynamic control
2598         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
2599         if (cptr) {
2600                 memcpy(&hdw->std_info_enum,cptr->info,
2601                        sizeof(hdw->std_info_enum));
2602                 cptr->info = &hdw->std_info_enum;
2603
2604         }
2605         // Initialize control data regarding video standard masks
2606         valid_std_mask = pvr2_std_get_usable();
2607         for (idx = 0; idx < 32; idx++) {
2608                 if (!(valid_std_mask & (1 << idx))) continue;
2609                 cnt1 = pvr2_std_id_to_str(
2610                         hdw->std_mask_names[idx],
2611                         sizeof(hdw->std_mask_names[idx])-1,
2612                         1 << idx);
2613                 hdw->std_mask_names[idx][cnt1] = 0;
2614         }
2615         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
2616         if (cptr) {
2617                 memcpy(&hdw->std_info_avail,cptr->info,
2618                        sizeof(hdw->std_info_avail));
2619                 cptr->info = &hdw->std_info_avail;
2620                 hdw->std_info_avail.def.type_bitmask.bit_names =
2621                         hdw->std_mask_ptrs;
2622                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2623                         valid_std_mask;
2624         }
2625         cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
2626         if (cptr) {
2627                 memcpy(&hdw->std_info_cur,cptr->info,
2628                        sizeof(hdw->std_info_cur));
2629                 cptr->info = &hdw->std_info_cur;
2630                 hdw->std_info_cur.def.type_bitmask.bit_names =
2631                         hdw->std_mask_ptrs;
2632                 hdw->std_info_avail.def.type_bitmask.valid_bits =
2633                         valid_std_mask;
2634         }
2635
2636         hdw->cropcap_stale = !0;
2637         hdw->eeprom_addr = -1;
2638         hdw->unit_number = -1;
2639         hdw->v4l_minor_number_video = -1;
2640         hdw->v4l_minor_number_vbi = -1;
2641         hdw->v4l_minor_number_radio = -1;
2642         hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2643         if (!hdw->ctl_write_buffer) goto fail;
2644         hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
2645         if (!hdw->ctl_read_buffer) goto fail;
2646         hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
2647         if (!hdw->ctl_write_urb) goto fail;
2648         hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
2649         if (!hdw->ctl_read_urb) goto fail;
2650
2651         if (v4l2_device_register(&intf->dev, &hdw->v4l2_dev) != 0) {
2652                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2653                            "Error registering with v4l core, giving up");
2654                 goto fail;
2655         }
2656         mutex_lock(&pvr2_unit_mtx); do {
2657                 for (idx = 0; idx < PVR_NUM; idx++) {
2658                         if (unit_pointers[idx]) continue;
2659                         hdw->unit_number = idx;
2660                         unit_pointers[idx] = hdw;
2661                         break;
2662                 }
2663         } while (0); mutex_unlock(&pvr2_unit_mtx);
2664
2665         cnt1 = 0;
2666         cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
2667         cnt1 += cnt2;
2668         if (hdw->unit_number >= 0) {
2669                 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
2670                                  ('a' + hdw->unit_number));
2671                 cnt1 += cnt2;
2672         }
2673         if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
2674         hdw->name[cnt1] = 0;
2675
2676         hdw->workqueue = create_singlethread_workqueue(hdw->name);
2677         INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
2678
2679         pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
2680                    hdw->unit_number,hdw->name);
2681
2682         hdw->tuner_type = -1;
2683         hdw->flag_ok = !0;
2684
2685         hdw->usb_intf = intf;
2686         hdw->usb_dev = usb_dev;
2687
2688         usb_make_path(hdw->usb_dev, hdw->bus_info, sizeof(hdw->bus_info));
2689
2690         ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2691         usb_set_interface(hdw->usb_dev,ifnum,0);
2692
2693         mutex_init(&hdw->ctl_lock_mutex);
2694         mutex_init(&hdw->big_lock_mutex);
2695
2696         return hdw;
2697  fail:
2698         if (hdw) {
2699                 del_timer_sync(&hdw->quiescent_timer);
2700                 del_timer_sync(&hdw->decoder_stabilization_timer);
2701                 del_timer_sync(&hdw->encoder_run_timer);
2702                 del_timer_sync(&hdw->encoder_wait_timer);
2703                 if (hdw->workqueue) {
2704                         flush_workqueue(hdw->workqueue);
2705                         destroy_workqueue(hdw->workqueue);
2706                         hdw->workqueue = NULL;
2707                 }
2708                 usb_free_urb(hdw->ctl_read_urb);
2709                 usb_free_urb(hdw->ctl_write_urb);
2710                 kfree(hdw->ctl_read_buffer);
2711                 kfree(hdw->ctl_write_buffer);
2712                 kfree(hdw->controls);
2713                 kfree(hdw->mpeg_ctrl_info);
2714                 kfree(hdw->std_defs);
2715                 kfree(hdw->std_enum_names);
2716                 kfree(hdw);
2717         }
2718         return NULL;
2719 }
2720
2721
2722 /* Remove _all_ associations between this driver and the underlying USB
2723    layer. */
2724 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2725 {
2726         if (hdw->flag_disconnected) return;
2727         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2728         if (hdw->ctl_read_urb) {
2729                 usb_kill_urb(hdw->ctl_read_urb);
2730                 usb_free_urb(hdw->ctl_read_urb);
2731                 hdw->ctl_read_urb = NULL;
2732         }
2733         if (hdw->ctl_write_urb) {
2734                 usb_kill_urb(hdw->ctl_write_urb);
2735                 usb_free_urb(hdw->ctl_write_urb);
2736                 hdw->ctl_write_urb = NULL;
2737         }
2738         if (hdw->ctl_read_buffer) {
2739                 kfree(hdw->ctl_read_buffer);
2740                 hdw->ctl_read_buffer = NULL;
2741         }
2742         if (hdw->ctl_write_buffer) {
2743                 kfree(hdw->ctl_write_buffer);
2744                 hdw->ctl_write_buffer = NULL;
2745         }
2746         hdw->flag_disconnected = !0;
2747         /* If we don't do this, then there will be a dangling struct device
2748            reference to our disappearing device persisting inside the V4L
2749            core... */
2750         v4l2_device_disconnect(&hdw->v4l2_dev);
2751         hdw->usb_dev = NULL;
2752         hdw->usb_intf = NULL;
2753         pvr2_hdw_render_useless(hdw);
2754 }
2755
2756
2757 /* Destroy hardware interaction structure */
2758 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2759 {
2760         if (!hdw) return;
2761         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2762         if (hdw->workqueue) {
2763                 flush_workqueue(hdw->workqueue);
2764                 destroy_workqueue(hdw->workqueue);
2765                 hdw->workqueue = NULL;
2766         }
2767         del_timer_sync(&hdw->quiescent_timer);
2768         del_timer_sync(&hdw->decoder_stabilization_timer);
2769         del_timer_sync(&hdw->encoder_run_timer);
2770         del_timer_sync(&hdw->encoder_wait_timer);
2771         if (hdw->fw_buffer) {
2772                 kfree(hdw->fw_buffer);
2773                 hdw->fw_buffer = NULL;
2774         }
2775         if (hdw->vid_stream) {
2776                 pvr2_stream_destroy(hdw->vid_stream);
2777                 hdw->vid_stream = NULL;
2778         }
2779         pvr2_i2c_core_done(hdw);
2780         v4l2_device_unregister(&hdw->v4l2_dev);
2781         pvr2_hdw_remove_usb_stuff(hdw);
2782         mutex_lock(&pvr2_unit_mtx); do {
2783                 if ((hdw->unit_number >= 0) &&
2784                     (hdw->unit_number < PVR_NUM) &&
2785                     (unit_pointers[hdw->unit_number] == hdw)) {
2786                         unit_pointers[hdw->unit_number] = NULL;
2787                 }
2788         } while (0); mutex_unlock(&pvr2_unit_mtx);
2789         kfree(hdw->controls);
2790         kfree(hdw->mpeg_ctrl_info);
2791         kfree(hdw->std_defs);
2792         kfree(hdw->std_enum_names);
2793         kfree(hdw);
2794 }
2795
2796
2797 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2798 {
2799         return (hdw && hdw->flag_ok);
2800 }
2801
2802
2803 /* Called when hardware has been unplugged */
2804 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2805 {
2806         pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2807         LOCK_TAKE(hdw->big_lock);
2808         LOCK_TAKE(hdw->ctl_lock);
2809         pvr2_hdw_remove_usb_stuff(hdw);
2810         LOCK_GIVE(hdw->ctl_lock);
2811         LOCK_GIVE(hdw->big_lock);
2812 }
2813
2814
2815 // Attempt to autoselect an appropriate value for std_enum_cur given
2816 // whatever is currently in std_mask_cur
2817 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2818 {
2819         unsigned int idx;
2820         for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2821                 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2822                         hdw->std_enum_cur = idx;
2823                         return;
2824                 }
2825         }
2826         hdw->std_enum_cur = 0;
2827 }
2828
2829
2830 // Calculate correct set of enumerated standards based on currently known
2831 // set of available standards bits.
2832 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2833 {
2834         struct v4l2_standard *newstd;
2835         unsigned int std_cnt;
2836         unsigned int idx;
2837
2838         newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2839
2840         if (hdw->std_defs) {
2841                 kfree(hdw->std_defs);
2842                 hdw->std_defs = NULL;
2843         }
2844         hdw->std_enum_cnt = 0;
2845         if (hdw->std_enum_names) {
2846                 kfree(hdw->std_enum_names);
2847                 hdw->std_enum_names = NULL;
2848         }
2849
2850         if (!std_cnt) {
2851                 pvr2_trace(
2852                         PVR2_TRACE_ERROR_LEGS,
2853                         "WARNING: Failed to identify any viable standards");
2854         }
2855
2856         /* Set up the dynamic control for this standard */
2857         hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2858         if (hdw->std_enum_names) {
2859                 hdw->std_enum_names[0] = "none";
2860                 for (idx = 0; idx < std_cnt; idx++)
2861                         hdw->std_enum_names[idx+1] = newstd[idx].name;
2862                 hdw->std_info_enum.def.type_enum.value_names =
2863                                                 hdw->std_enum_names;
2864                 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2865         } else {
2866                 pvr2_trace(
2867                         PVR2_TRACE_ERROR_LEGS,
2868                         "WARNING: Failed to alloc memory for names");
2869                 hdw->std_info_enum.def.type_enum.value_names = NULL;
2870                 hdw->std_info_enum.def.type_enum.count = 0;
2871         }
2872         hdw->std_defs = newstd;
2873         hdw->std_enum_cnt = std_cnt+1;
2874         hdw->std_enum_cur = 0;
2875         hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2876 }
2877
2878
2879 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2880                                struct v4l2_standard *std,
2881                                unsigned int idx)
2882 {
2883         int ret = -EINVAL;
2884         if (!idx) return ret;
2885         LOCK_TAKE(hdw->big_lock); do {
2886                 if (idx >= hdw->std_enum_cnt) break;
2887                 idx--;
2888                 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2889                 ret = 0;
2890         } while (0); LOCK_GIVE(hdw->big_lock);
2891         return ret;
2892 }
2893
2894
2895 /* Get the number of defined controls */
2896 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2897 {
2898         return hdw->control_cnt;
2899 }
2900
2901
2902 /* Retrieve a control handle given its index (0..count-1) */
2903 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2904                                              unsigned int idx)
2905 {
2906         if (idx >= hdw->control_cnt) return NULL;
2907         return hdw->controls + idx;
2908 }
2909
2910
2911 /* Retrieve a control handle given its index (0..count-1) */
2912 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2913                                           unsigned int ctl_id)
2914 {
2915         struct pvr2_ctrl *cptr;
2916         unsigned int idx;
2917         int i;
2918
2919         /* This could be made a lot more efficient, but for now... */
2920         for (idx = 0; idx < hdw->control_cnt; idx++) {
2921                 cptr = hdw->controls + idx;
2922                 i = cptr->info->internal_id;
2923                 if (i && (i == ctl_id)) return cptr;
2924         }
2925         return NULL;
2926 }
2927
2928
2929 /* Given a V4L ID, retrieve the control structure associated with it. */
2930 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2931 {
2932         struct pvr2_ctrl *cptr;
2933         unsigned int idx;
2934         int i;
2935
2936         /* This could be made a lot more efficient, but for now... */
2937         for (idx = 0; idx < hdw->control_cnt; idx++) {
2938                 cptr = hdw->controls + idx;
2939                 i = cptr->info->v4l_id;
2940                 if (i && (i == ctl_id)) return cptr;
2941         }
2942         return NULL;
2943 }
2944
2945
2946 /* Given a V4L ID for its immediate predecessor, retrieve the control
2947    structure associated with it. */
2948 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2949                                             unsigned int ctl_id)
2950 {
2951         struct pvr2_ctrl *cptr,*cp2;
2952         unsigned int idx;
2953         int i;
2954
2955         /* This could be made a lot more efficient, but for now... */
2956         cp2 = NULL;
2957         for (idx = 0; idx < hdw->control_cnt; idx++) {
2958                 cptr = hdw->controls + idx;
2959                 i = cptr->info->v4l_id;
2960                 if (!i) continue;
2961                 if (i <= ctl_id) continue;
2962                 if (cp2 && (cp2->info->v4l_id < i)) continue;
2963                 cp2 = cptr;
2964         }
2965         return cp2;
2966         return NULL;
2967 }
2968
2969
2970 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2971 {
2972         switch (tp) {
2973         case pvr2_ctl_int: return "integer";
2974         case pvr2_ctl_enum: return "enum";
2975         case pvr2_ctl_bool: return "boolean";
2976         case pvr2_ctl_bitmask: return "bitmask";
2977         }
2978         return "";
2979 }
2980
2981
2982 static void pvr2_subdev_set_control(struct pvr2_hdw *hdw, int id,
2983                                     const char *name, int val)
2984 {
2985         struct v4l2_control ctrl;
2986         pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 %s=%d", name, val);
2987         memset(&ctrl, 0, sizeof(ctrl));
2988         ctrl.id = id;
2989         ctrl.value = val;
2990         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, s_ctrl, &ctrl);
2991 }
2992
2993 #define PVR2_SUBDEV_SET_CONTROL(hdw, id, lab) \
2994         if ((hdw)->lab##_dirty || (hdw)->force_dirty) {         \
2995                 pvr2_subdev_set_control(hdw, id, #lab, (hdw)->lab##_val); \
2996         }
2997
2998 int pvr2_hdw_get_detected_std(struct pvr2_hdw *hdw, v4l2_std_id *std)
2999 {
3000         v4l2_device_call_all(&hdw->v4l2_dev, 0,
3001                              video, querystd, std);
3002         return 0;
3003 }
3004
3005 /* Execute whatever commands are required to update the state of all the
3006    sub-devices so that they match our current control values. */
3007 static void pvr2_subdev_update(struct pvr2_hdw *hdw)
3008 {
3009         struct v4l2_subdev *sd;
3010         unsigned int id;
3011         pvr2_subdev_update_func fp;
3012
3013         pvr2_trace(PVR2_TRACE_CHIPS, "subdev update...");
3014
3015         if (hdw->tuner_updated || hdw->force_dirty) {
3016                 struct tuner_setup setup;
3017                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev tuner set_type(%d)",
3018                            hdw->tuner_type);
3019                 if (((int)(hdw->tuner_type)) >= 0) {
3020                         memset(&setup, 0, sizeof(setup));
3021                         setup.addr = ADDR_UNSET;
3022                         setup.type = hdw->tuner_type;
3023                         setup.mode_mask = T_RADIO | T_ANALOG_TV;
3024                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
3025                                              tuner, s_type_addr, &setup);
3026                 }
3027         }
3028
3029         if (hdw->input_dirty || hdw->std_dirty || hdw->force_dirty) {
3030                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_standard");
3031                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3032                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
3033                                              tuner, s_radio);
3034                 } else {
3035                         v4l2_std_id vs;
3036                         vs = hdw->std_mask_cur;
3037                         v4l2_device_call_all(&hdw->v4l2_dev, 0,
3038                                              core, s_std, vs);
3039                         pvr2_hdw_cx25840_vbi_hack(hdw);
3040                 }
3041                 hdw->tuner_signal_stale = !0;
3042                 hdw->cropcap_stale = !0;
3043         }
3044
3045         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_BRIGHTNESS, brightness);
3046         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_CONTRAST, contrast);
3047         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_SATURATION, saturation);
3048         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_HUE, hue);
3049         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_MUTE, mute);
3050         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_VOLUME, volume);
3051         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BALANCE, balance);
3052         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_BASS, bass);
3053         PVR2_SUBDEV_SET_CONTROL(hdw, V4L2_CID_AUDIO_TREBLE, treble);
3054
3055         if (hdw->input_dirty || hdw->audiomode_dirty || hdw->force_dirty) {
3056                 struct v4l2_tuner vt;
3057                 memset(&vt, 0, sizeof(vt));
3058                 vt.type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
3059                         V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
3060                 vt.audmode = hdw->audiomode_val;
3061                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, s_tuner, &vt);
3062         }
3063
3064         if (hdw->freqDirty || hdw->force_dirty) {
3065                 unsigned long fv;
3066                 struct v4l2_frequency freq;
3067                 fv = pvr2_hdw_get_cur_freq(hdw);
3068                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_freq(%lu)", fv);
3069                 if (hdw->tuner_signal_stale) pvr2_hdw_status_poll(hdw);
3070                 memset(&freq, 0, sizeof(freq));
3071                 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
3072                         /* ((fv * 1000) / 62500) */
3073                         freq.frequency = (fv * 2) / 125;
3074                 } else {
3075                         freq.frequency = fv / 62500;
3076                 }
3077                 /* tuner-core currently doesn't seem to care about this, but
3078                    let's set it anyway for completeness. */
3079                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3080                         freq.type = V4L2_TUNER_RADIO;
3081                 } else {
3082                         freq.type = V4L2_TUNER_ANALOG_TV;
3083                 }
3084                 freq.tuner = 0;
3085                 v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner,
3086                                      s_frequency, &freq);
3087         }
3088
3089         if (hdw->res_hor_dirty || hdw->res_ver_dirty || hdw->force_dirty) {
3090                 struct v4l2_mbus_framefmt fmt;
3091                 memset(&fmt, 0, sizeof(fmt));
3092                 fmt.width = hdw->res_hor_val;
3093                 fmt.height = hdw->res_ver_val;
3094                 fmt.code = V4L2_MBUS_FMT_FIXED;
3095                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_size(%dx%d)",
3096                            fmt.width, fmt.height);
3097                 v4l2_device_call_all(&hdw->v4l2_dev, 0, video, s_mbus_fmt, &fmt);
3098         }
3099
3100         if (hdw->srate_dirty || hdw->force_dirty) {
3101                 u32 val;
3102                 pvr2_trace(PVR2_TRACE_CHIPS, "subdev v4l2 set_audio %d",
3103                            hdw->srate_val);
3104                 switch (hdw->srate_val) {
3105                 default:
3106                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000:
3107                         val = 48000;
3108                         break;
3109                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100:
3110                         val = 44100;
3111                         break;
3112                 case V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000:
3113                         val = 32000;
3114                         break;
3115                 }
3116                 v4l2_device_call_all(&hdw->v4l2_dev, 0,
3117                                      audio, s_clock_freq, val);
3118         }
3119
3120         /* Unable to set crop parameters; there is apparently no equivalent
3121            for VIDIOC_S_CROP */
3122
3123         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
3124                 id = sd->grp_id;
3125                 if (id >= ARRAY_SIZE(pvr2_module_update_functions)) continue;
3126                 fp = pvr2_module_update_functions[id];
3127                 if (!fp) continue;
3128                 (*fp)(hdw, sd);
3129         }
3130
3131         if (hdw->tuner_signal_stale || hdw->cropcap_stale) {
3132                 pvr2_hdw_status_poll(hdw);
3133         }
3134 }
3135
3136
3137 /* Figure out if we need to commit control changes.  If so, mark internal
3138    state flags to indicate this fact and return true.  Otherwise do nothing
3139    else and return false. */
3140 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
3141 {
3142         unsigned int idx;
3143         struct pvr2_ctrl *cptr;
3144         int value;
3145         int commit_flag = hdw->force_dirty;
3146         char buf[100];
3147         unsigned int bcnt,ccnt;
3148
3149         for (idx = 0; idx < hdw->control_cnt; idx++) {
3150                 cptr = hdw->controls + idx;
3151                 if (!cptr->info->is_dirty) continue;
3152                 if (!cptr->info->is_dirty(cptr)) continue;
3153                 commit_flag = !0;
3154
3155                 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
3156                 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
3157                                  cptr->info->name);
3158                 value = 0;
3159                 cptr->info->get_value(cptr,&value);
3160                 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
3161                                                 buf+bcnt,
3162                                                 sizeof(buf)-bcnt,&ccnt);
3163                 bcnt += ccnt;
3164                 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
3165                                   get_ctrl_typename(cptr->info->type));
3166                 pvr2_trace(PVR2_TRACE_CTL,
3167                            "/*--TRACE_COMMIT--*/ %.*s",
3168                            bcnt,buf);
3169         }
3170
3171         if (!commit_flag) {
3172                 /* Nothing has changed */
3173                 return 0;
3174         }
3175
3176         hdw->state_pipeline_config = 0;
3177         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3178         pvr2_hdw_state_sched(hdw);
3179
3180         return !0;
3181 }
3182
3183
3184 /* Perform all operations needed to commit all control changes.  This must
3185    be performed in synchronization with the pipeline state and is thus
3186    expected to be called as part of the driver's worker thread.  Return
3187    true if commit successful, otherwise return false to indicate that
3188    commit isn't possible at this time. */
3189 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
3190 {
3191         unsigned int idx;
3192         struct pvr2_ctrl *cptr;
3193         int disruptive_change;
3194
3195         if (hdw->input_dirty && hdw->state_pathway_ok &&
3196             (((hdw->input_val == PVR2_CVAL_INPUT_DTV) ?
3197               PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG) !=
3198              hdw->pathway_state)) {
3199                 /* Change of mode being asked for... */
3200                 hdw->state_pathway_ok = 0;
3201                 trace_stbit("state_pathway_ok", hdw->state_pathway_ok);
3202         }
3203         if (!hdw->state_pathway_ok) {
3204                 /* Can't commit anything until pathway is ok. */
3205                 return 0;
3206         }
3207
3208         /* Handle some required side effects when the video standard is
3209            changed.... */
3210         if (hdw->std_dirty) {
3211                 int nvres;
3212                 int gop_size;
3213                 if (hdw->std_mask_cur & V4L2_STD_525_60) {
3214                         nvres = 480;
3215                         gop_size = 15;
3216                 } else {
3217                         nvres = 576;
3218                         gop_size = 12;
3219                 }
3220                 /* Rewrite the vertical resolution to be appropriate to the
3221                    video standard that has been selected. */
3222                 if (nvres != hdw->res_ver_val) {
3223                         hdw->res_ver_val = nvres;
3224                         hdw->res_ver_dirty = !0;
3225                 }
3226                 /* Rewrite the GOP size to be appropriate to the video
3227                    standard that has been selected. */
3228                 if (gop_size != hdw->enc_ctl_state.video_gop_size) {
3229                         struct v4l2_ext_controls cs;
3230                         struct v4l2_ext_control c1;
3231                         memset(&cs, 0, sizeof(cs));
3232                         memset(&c1, 0, sizeof(c1));
3233                         cs.controls = &c1;
3234                         cs.count = 1;
3235                         c1.id = V4L2_CID_MPEG_VIDEO_GOP_SIZE;
3236                         c1.value = gop_size;
3237                         cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,
3238                                           VIDIOC_S_EXT_CTRLS);
3239                 }
3240         }
3241
3242         /* The broadcast decoder can only scale down, so if
3243          * res_*_dirty && crop window < output format ==> enlarge crop.
3244          *
3245          * The mpeg encoder receives fields of res_hor_val dots and
3246          * res_ver_val halflines.  Limits: hor<=720, ver<=576.
3247          */
3248         if (hdw->res_hor_dirty && hdw->cropw_val < hdw->res_hor_val) {
3249                 hdw->cropw_val = hdw->res_hor_val;
3250                 hdw->cropw_dirty = !0;
3251         } else if (hdw->cropw_dirty) {
3252                 hdw->res_hor_dirty = !0;           /* must rescale */
3253                 hdw->res_hor_val = min(720, hdw->cropw_val);
3254         }
3255         if (hdw->res_ver_dirty && hdw->croph_val < hdw->res_ver_val) {
3256                 hdw->croph_val = hdw->res_ver_val;
3257                 hdw->croph_dirty = !0;
3258         } else if (hdw->croph_dirty) {
3259                 int nvres = hdw->std_mask_cur & V4L2_STD_525_60 ? 480 : 576;
3260                 hdw->res_ver_dirty = !0;
3261                 hdw->res_ver_val = min(nvres, hdw->croph_val);
3262         }
3263
3264         /* If any of the below has changed, then we can't do the update
3265            while the pipeline is running.  Pipeline must be paused first
3266            and decoder -> encoder connection be made quiescent before we
3267            can proceed. */
3268         disruptive_change =
3269                 (hdw->std_dirty ||
3270                  hdw->enc_unsafe_stale ||
3271                  hdw->srate_dirty ||
3272                  hdw->res_ver_dirty ||
3273                  hdw->res_hor_dirty ||
3274                  hdw->cropw_dirty ||
3275                  hdw->croph_dirty ||
3276                  hdw->input_dirty ||
3277                  (hdw->active_stream_type != hdw->desired_stream_type));
3278         if (disruptive_change && !hdw->state_pipeline_idle) {
3279                 /* Pipeline is not idle; we can't proceed.  Arrange to
3280                    cause pipeline to stop so that we can try this again
3281                    later.... */
3282                 hdw->state_pipeline_pause = !0;
3283                 return 0;
3284         }
3285
3286         if (hdw->srate_dirty) {
3287                 /* Write new sample rate into control structure since
3288                  * the master copy is stale.  We must track srate
3289                  * separate from the mpeg control structure because
3290                  * other logic also uses this value. */
3291                 struct v4l2_ext_controls cs;
3292                 struct v4l2_ext_control c1;
3293                 memset(&cs,0,sizeof(cs));
3294                 memset(&c1,0,sizeof(c1));
3295                 cs.controls = &c1;
3296                 cs.count = 1;
3297                 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
3298                 c1.value = hdw->srate_val;
3299                 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
3300         }
3301
3302         if (hdw->active_stream_type != hdw->desired_stream_type) {
3303                 /* Handle any side effects of stream config here */
3304                 hdw->active_stream_type = hdw->desired_stream_type;
3305         }
3306
3307         if (hdw->hdw_desc->signal_routing_scheme ==
3308             PVR2_ROUTING_SCHEME_GOTVIEW) {
3309                 u32 b;
3310                 /* Handle GOTVIEW audio switching */
3311                 pvr2_hdw_gpio_get_out(hdw,&b);
3312                 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
3313                         /* Set GPIO 11 */
3314                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),~0);
3315                 } else {
3316                         /* Clear GPIO 11 */
3317                         pvr2_hdw_gpio_chg_out(hdw,(1 << 11),0);
3318                 }
3319         }
3320
3321         /* Check and update state for all sub-devices. */
3322         pvr2_subdev_update(hdw);
3323
3324         hdw->tuner_updated = 0;
3325         hdw->force_dirty = 0;
3326         for (idx = 0; idx < hdw->control_cnt; idx++) {
3327                 cptr = hdw->controls + idx;
3328                 if (!cptr->info->clear_dirty) continue;
3329                 cptr->info->clear_dirty(cptr);
3330         }
3331
3332         if ((hdw->pathway_state == PVR2_PATHWAY_ANALOG) &&
3333             hdw->state_encoder_run) {
3334                 /* If encoder isn't running or it can't be touched, then
3335                    this will get worked out later when we start the
3336                    encoder. */
3337                 if (pvr2_encoder_adjust(hdw) < 0) return !0;
3338         }
3339
3340         hdw->state_pipeline_config = !0;
3341         /* Hardware state may have changed in a way to cause the cropping
3342            capabilities to have changed.  So mark it stale, which will
3343            cause a later re-fetch. */
3344         trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
3345         return !0;
3346 }
3347
3348
3349 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
3350 {
3351         int fl;
3352         LOCK_TAKE(hdw->big_lock);
3353         fl = pvr2_hdw_commit_setup(hdw);
3354         LOCK_GIVE(hdw->big_lock);
3355         if (!fl) return 0;
3356         return pvr2_hdw_wait(hdw,0);
3357 }
3358
3359
3360 static void pvr2_hdw_worker_poll(struct work_struct *work)
3361 {
3362         int fl = 0;
3363         struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
3364         LOCK_TAKE(hdw->big_lock); do {
3365                 fl = pvr2_hdw_state_eval(hdw);
3366         } while (0); LOCK_GIVE(hdw->big_lock);
3367         if (fl && hdw->state_func) {
3368                 hdw->state_func(hdw->state_data);
3369         }
3370 }
3371
3372
3373 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
3374 {
3375         return wait_event_interruptible(
3376                 hdw->state_wait_data,
3377                 (hdw->state_stale == 0) &&
3378                 (!state || (hdw->master_state != state)));
3379 }
3380
3381
3382 /* Return name for this driver instance */
3383 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
3384 {
3385         return hdw->name;
3386 }
3387
3388
3389 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
3390 {
3391         return hdw->hdw_desc->description;
3392 }
3393
3394
3395 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
3396 {
3397         return hdw->hdw_desc->shortname;
3398 }
3399
3400
3401 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
3402 {
3403         int result;
3404         LOCK_TAKE(hdw->ctl_lock); do {
3405                 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
3406                 result = pvr2_send_request(hdw,
3407                                            hdw->cmd_buffer,1,
3408                                            hdw->cmd_buffer,1);
3409                 if (result < 0) break;
3410                 result = (hdw->cmd_buffer[0] != 0);
3411         } while(0); LOCK_GIVE(hdw->ctl_lock);
3412         return result;
3413 }
3414
3415
3416 /* Execute poll of tuner status */
3417 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
3418 {
3419         LOCK_TAKE(hdw->big_lock); do {
3420                 pvr2_hdw_status_poll(hdw);
3421         } while (0); LOCK_GIVE(hdw->big_lock);
3422 }
3423
3424
3425 static int pvr2_hdw_check_cropcap(struct pvr2_hdw *hdw)
3426 {
3427         if (!hdw->cropcap_stale) {
3428                 return 0;
3429         }
3430         pvr2_hdw_status_poll(hdw);
3431         if (hdw->cropcap_stale) {
3432                 return -EIO;
3433         }
3434         return 0;
3435 }
3436
3437
3438 /* Return information about cropping capabilities */
3439 int pvr2_hdw_get_cropcap(struct pvr2_hdw *hdw, struct v4l2_cropcap *pp)
3440 {
3441         int stat = 0;
3442         LOCK_TAKE(hdw->big_lock);
3443         stat = pvr2_hdw_check_cropcap(hdw);
3444         if (!stat) {
3445                 memcpy(pp, &hdw->cropcap_info, sizeof(hdw->cropcap_info));
3446         }
3447         LOCK_GIVE(hdw->big_lock);
3448         return stat;
3449 }
3450
3451
3452 /* Return information about the tuner */
3453 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
3454 {
3455         LOCK_TAKE(hdw->big_lock); do {
3456                 if (hdw->tuner_signal_stale) {
3457                         pvr2_hdw_status_poll(hdw);
3458                 }
3459                 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
3460         } while (0); LOCK_GIVE(hdw->big_lock);
3461         return 0;
3462 }
3463
3464
3465 /* Get handle to video output stream */
3466 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
3467 {
3468         return hp->vid_stream;
3469 }
3470
3471
3472 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
3473 {
3474         int nr = pvr2_hdw_get_unit_number(hdw);
3475         LOCK_TAKE(hdw->big_lock); do {
3476                 printk(KERN_INFO "pvrusb2: =================  START STATUS CARD #%d  =================\n", nr);
3477                 v4l2_device_call_all(&hdw->v4l2_dev, 0, core, log_status);
3478                 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
3479                 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
3480                 pvr2_hdw_state_log_state(hdw);
3481                 printk(KERN_INFO "pvrusb2: ==================  END STATUS CARD #%d  ==================\n", nr);
3482         } while (0); LOCK_GIVE(hdw->big_lock);
3483 }
3484
3485
3486 /* Grab EEPROM contents, needed for direct method. */
3487 #define EEPROM_SIZE 8192
3488 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
3489 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
3490 {
3491         struct i2c_msg msg[2];
3492         u8 *eeprom;
3493         u8 iadd[2];
3494         u8 addr;
3495         u16 eepromSize;
3496         unsigned int offs;
3497         int ret;
3498         int mode16 = 0;
3499         unsigned pcnt,tcnt;
3500         eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
3501         if (!eeprom) {
3502                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3503                            "Failed to allocate memory"
3504                            " required to read eeprom");
3505                 return NULL;
3506         }
3507
3508         trace_eeprom("Value for eeprom addr from controller was 0x%x",
3509                      hdw->eeprom_addr);
3510         addr = hdw->eeprom_addr;
3511         /* Seems that if the high bit is set, then the *real* eeprom
3512            address is shifted right now bit position (noticed this in
3513            newer PVR USB2 hardware) */
3514         if (addr & 0x80) addr >>= 1;
3515
3516         /* FX2 documentation states that a 16bit-addressed eeprom is
3517            expected if the I2C address is an odd number (yeah, this is
3518            strange but it's what they do) */
3519         mode16 = (addr & 1);
3520         eepromSize = (mode16 ? EEPROM_SIZE : 256);
3521         trace_eeprom("Examining %d byte eeprom at location 0x%x"
3522                      " using %d bit addressing",eepromSize,addr,
3523                      mode16 ? 16 : 8);
3524
3525         msg[0].addr = addr;
3526         msg[0].flags = 0;
3527         msg[0].len = mode16 ? 2 : 1;
3528         msg[0].buf = iadd;
3529         msg[1].addr = addr;
3530         msg[1].flags = I2C_M_RD;
3531
3532         /* We have to do the actual eeprom data fetch ourselves, because
3533            (1) we're only fetching part of the eeprom, and (2) if we were
3534            getting the whole thing our I2C driver can't grab it in one
3535            pass - which is what tveeprom is otherwise going to attempt */
3536         memset(eeprom,0,EEPROM_SIZE);
3537         for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
3538                 pcnt = 16;
3539                 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
3540                 offs = tcnt + (eepromSize - EEPROM_SIZE);
3541                 if (mode16) {
3542                         iadd[0] = offs >> 8;
3543                         iadd[1] = offs;
3544                 } else {
3545                         iadd[0] = offs;
3546                 }
3547                 msg[1].len = pcnt;
3548                 msg[1].buf = eeprom+tcnt;
3549                 if ((ret = i2c_transfer(&hdw->i2c_adap,
3550                                         msg,ARRAY_SIZE(msg))) != 2) {
3551                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3552                                    "eeprom fetch set offs err=%d",ret);
3553                         kfree(eeprom);
3554                         return NULL;
3555                 }
3556         }
3557         return eeprom;
3558 }
3559
3560
3561 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
3562                                 int mode,
3563                                 int enable_flag)
3564 {
3565         int ret;
3566         u16 address;
3567         unsigned int pipe;
3568         LOCK_TAKE(hdw->big_lock); do {
3569                 if ((hdw->fw_buffer == NULL) == !enable_flag) break;
3570
3571                 if (!enable_flag) {
3572                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3573                                    "Cleaning up after CPU firmware fetch");
3574                         kfree(hdw->fw_buffer);
3575                         hdw->fw_buffer = NULL;
3576                         hdw->fw_size = 0;
3577                         if (hdw->fw_cpu_flag) {
3578                                 /* Now release the CPU.  It will disconnect
3579                                    and reconnect later. */
3580                                 pvr2_hdw_cpureset_assert(hdw,0);
3581                         }
3582                         break;
3583                 }
3584
3585                 hdw->fw_cpu_flag = (mode != 2);
3586                 if (hdw->fw_cpu_flag) {
3587                         hdw->fw_size = (mode == 1) ? 0x4000 : 0x2000;
3588                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3589                                    "Preparing to suck out CPU firmware"
3590                                    " (size=%u)", hdw->fw_size);
3591                         hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
3592                         if (!hdw->fw_buffer) {
3593                                 hdw->fw_size = 0;
3594                                 break;
3595                         }
3596
3597                         /* We have to hold the CPU during firmware upload. */
3598                         pvr2_hdw_cpureset_assert(hdw,1);
3599
3600                         /* download the firmware from address 0000-1fff in 2048
3601                            (=0x800) bytes chunk. */
3602
3603                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3604                                    "Grabbing CPU firmware");
3605                         pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
3606                         for(address = 0; address < hdw->fw_size;
3607                             address += 0x800) {
3608                                 ret = usb_control_msg(hdw->usb_dev,pipe,
3609                                                       0xa0,0xc0,
3610                                                       address,0,
3611                                                       hdw->fw_buffer+address,
3612                                                       0x800,HZ);
3613                                 if (ret < 0) break;
3614                         }
3615
3616                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3617                                    "Done grabbing CPU firmware");
3618                 } else {
3619                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3620                                    "Sucking down EEPROM contents");
3621                         hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
3622                         if (!hdw->fw_buffer) {
3623                                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3624                                            "EEPROM content suck failed.");
3625                                 break;
3626                         }
3627                         hdw->fw_size = EEPROM_SIZE;
3628                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3629                                    "Done sucking down EEPROM contents");
3630                 }
3631
3632         } while (0); LOCK_GIVE(hdw->big_lock);
3633 }
3634
3635
3636 /* Return true if we're in a mode for retrieval CPU firmware */
3637 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
3638 {
3639         return hdw->fw_buffer != NULL;
3640 }
3641
3642
3643 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
3644                        char *buf,unsigned int cnt)
3645 {
3646         int ret = -EINVAL;
3647         LOCK_TAKE(hdw->big_lock); do {
3648                 if (!buf) break;
3649                 if (!cnt) break;
3650
3651                 if (!hdw->fw_buffer) {
3652                         ret = -EIO;
3653                         break;
3654                 }
3655
3656                 if (offs >= hdw->fw_size) {
3657                         pvr2_trace(PVR2_TRACE_FIRMWARE,
3658                                    "Read firmware data offs=%d EOF",
3659                                    offs);
3660                         ret = 0;
3661                         break;
3662                 }
3663
3664                 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
3665
3666                 memcpy(buf,hdw->fw_buffer+offs,cnt);
3667
3668                 pvr2_trace(PVR2_TRACE_FIRMWARE,
3669                            "Read firmware data offs=%d cnt=%d",
3670                            offs,cnt);
3671                 ret = cnt;
3672         } while (0); LOCK_GIVE(hdw->big_lock);
3673
3674         return ret;
3675 }
3676
3677
3678 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
3679                                   enum pvr2_v4l_type index)
3680 {
3681         switch (index) {
3682         case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
3683         case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
3684         case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
3685         default: return -1;
3686         }
3687 }
3688
3689
3690 /* Store a v4l minor device number */
3691 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
3692                                      enum pvr2_v4l_type index,int v)
3693 {
3694         switch (index) {
3695         case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
3696         case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
3697         case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
3698         default: break;
3699         }
3700 }
3701
3702
3703 static void pvr2_ctl_write_complete(struct urb *urb)
3704 {
3705         struct pvr2_hdw *hdw = urb->context;
3706         hdw->ctl_write_pend_flag = 0;
3707         if (hdw->ctl_read_pend_flag) return;
3708         complete(&hdw->ctl_done);
3709 }
3710
3711
3712 static void pvr2_ctl_read_complete(struct urb *urb)
3713 {
3714         struct pvr2_hdw *hdw = urb->context;
3715         hdw->ctl_read_pend_flag = 0;
3716         if (hdw->ctl_write_pend_flag) return;
3717         complete(&hdw->ctl_done);
3718 }
3719
3720
3721 static void pvr2_ctl_timeout(unsigned long data)
3722 {
3723         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3724         if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3725                 hdw->ctl_timeout_flag = !0;
3726                 if (hdw->ctl_write_pend_flag)
3727                         usb_unlink_urb(hdw->ctl_write_urb);
3728                 if (hdw->ctl_read_pend_flag)
3729                         usb_unlink_urb(hdw->ctl_read_urb);
3730         }
3731 }
3732
3733
3734 /* Issue a command and get a response from the device.  This extended
3735    version includes a probe flag (which if set means that device errors
3736    should not be logged or treated as fatal) and a timeout in jiffies.
3737    This can be used to non-lethally probe the health of endpoint 1. */
3738 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
3739                                 unsigned int timeout,int probe_fl,
3740                                 void *write_data,unsigned int write_len,
3741                                 void *read_data,unsigned int read_len)
3742 {
3743         unsigned int idx;
3744         int status = 0;
3745         struct timer_list timer;
3746         if (!hdw->ctl_lock_held) {
3747                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3748                            "Attempted to execute control transfer"
3749                            " without lock!!");
3750                 return -EDEADLK;
3751         }
3752         if (!hdw->flag_ok && !probe_fl) {
3753                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3754                            "Attempted to execute control transfer"
3755                            " when device not ok");
3756                 return -EIO;
3757         }
3758         if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
3759                 if (!probe_fl) {
3760                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3761                                    "Attempted to execute control transfer"
3762                                    " when USB is disconnected");
3763                 }
3764                 return -ENOTTY;
3765         }
3766
3767         /* Ensure that we have sane parameters */
3768         if (!write_data) write_len = 0;
3769         if (!read_data) read_len = 0;
3770         if (write_len > PVR2_CTL_BUFFSIZE) {
3771                 pvr2_trace(
3772                         PVR2_TRACE_ERROR_LEGS,
3773                         "Attempted to execute %d byte"
3774                         " control-write transfer (limit=%d)",
3775                         write_len,PVR2_CTL_BUFFSIZE);
3776                 return -EINVAL;
3777         }
3778         if (read_len > PVR2_CTL_BUFFSIZE) {
3779                 pvr2_trace(
3780                         PVR2_TRACE_ERROR_LEGS,
3781                         "Attempted to execute %d byte"
3782                         " control-read transfer (limit=%d)",
3783                         write_len,PVR2_CTL_BUFFSIZE);
3784                 return -EINVAL;
3785         }
3786         if ((!write_len) && (!read_len)) {
3787                 pvr2_trace(
3788                         PVR2_TRACE_ERROR_LEGS,
3789                         "Attempted to execute null control transfer?");
3790                 return -EINVAL;
3791         }
3792
3793
3794         hdw->cmd_debug_state = 1;
3795         if (write_len) {
3796                 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
3797         } else {
3798                 hdw->cmd_debug_code = 0;
3799         }
3800         hdw->cmd_debug_write_len = write_len;
3801         hdw->cmd_debug_read_len = read_len;
3802
3803         /* Initialize common stuff */
3804         init_completion(&hdw->ctl_done);
3805         hdw->ctl_timeout_flag = 0;
3806         hdw->ctl_write_pend_flag = 0;
3807         hdw->ctl_read_pend_flag = 0;
3808         init_timer(&timer);
3809         timer.expires = jiffies + timeout;
3810         timer.data = (unsigned long)hdw;
3811         timer.function = pvr2_ctl_timeout;
3812
3813         if (write_len) {
3814                 hdw->cmd_debug_state = 2;
3815                 /* Transfer write data to internal buffer */
3816                 for (idx = 0; idx < write_len; idx++) {
3817                         hdw->ctl_write_buffer[idx] =
3818                                 ((unsigned char *)write_data)[idx];
3819                 }
3820                 /* Initiate a write request */
3821                 usb_fill_bulk_urb(hdw->ctl_write_urb,
3822                                   hdw->usb_dev,
3823                                   usb_sndbulkpipe(hdw->usb_dev,
3824                                                   PVR2_CTL_WRITE_ENDPOINT),
3825                                   hdw->ctl_write_buffer,
3826                                   write_len,
3827                                   pvr2_ctl_write_complete,
3828                                   hdw);
3829                 hdw->ctl_write_urb->actual_length = 0;
3830                 hdw->ctl_write_pend_flag = !0;
3831                 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
3832                 if (status < 0) {
3833                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3834                                    "Failed to submit write-control"
3835                                    " URB status=%d",status);
3836                         hdw->ctl_write_pend_flag = 0;
3837                         goto done;
3838                 }
3839         }
3840
3841         if (read_len) {
3842                 hdw->cmd_debug_state = 3;
3843                 memset(hdw->ctl_read_buffer,0x43,read_len);
3844                 /* Initiate a read request */
3845                 usb_fill_bulk_urb(hdw->ctl_read_urb,
3846                                   hdw->usb_dev,
3847                                   usb_rcvbulkpipe(hdw->usb_dev,
3848                                                   PVR2_CTL_READ_ENDPOINT),
3849                                   hdw->ctl_read_buffer,
3850                                   read_len,
3851                                   pvr2_ctl_read_complete,
3852                                   hdw);
3853                 hdw->ctl_read_urb->actual_length = 0;
3854                 hdw->ctl_read_pend_flag = !0;
3855                 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
3856                 if (status < 0) {
3857                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3858                                    "Failed to submit read-control"
3859                                    " URB status=%d",status);
3860                         hdw->ctl_read_pend_flag = 0;
3861                         goto done;
3862                 }
3863         }
3864
3865         /* Start timer */
3866         add_timer(&timer);
3867
3868         /* Now wait for all I/O to complete */
3869         hdw->cmd_debug_state = 4;
3870         while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
3871                 wait_for_completion(&hdw->ctl_done);
3872         }
3873         hdw->cmd_debug_state = 5;
3874
3875         /* Stop timer */
3876         del_timer_sync(&timer);
3877
3878         hdw->cmd_debug_state = 6;
3879         status = 0;
3880
3881         if (hdw->ctl_timeout_flag) {
3882                 status = -ETIMEDOUT;
3883                 if (!probe_fl) {
3884                         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3885                                    "Timed out control-write");
3886                 }
3887                 goto done;
3888         }
3889
3890         if (write_len) {
3891                 /* Validate results of write request */
3892                 if ((hdw->ctl_write_urb->status != 0) &&
3893                     (hdw->ctl_write_urb->status != -ENOENT) &&
3894                     (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
3895                     (hdw->ctl_write_urb->status != -ECONNRESET)) {
3896                         /* USB subsystem is reporting some kind of failure
3897                            on the write */
3898                         status = hdw->ctl_write_urb->status;
3899                         if (!probe_fl) {
3900                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3901                                            "control-write URB failure,"
3902                                            " status=%d",
3903                                            status);
3904                         }
3905                         goto done;
3906                 }
3907                 if (hdw->ctl_write_urb->actual_length < write_len) {
3908                         /* Failed to write enough data */
3909                         status = -EIO;
3910                         if (!probe_fl) {
3911                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3912                                            "control-write URB short,"
3913                                            " expected=%d got=%d",
3914                                            write_len,
3915                                            hdw->ctl_write_urb->actual_length);
3916                         }
3917                         goto done;
3918                 }
3919         }
3920         if (read_len) {
3921                 /* Validate results of read request */
3922                 if ((hdw->ctl_read_urb->status != 0) &&
3923                     (hdw->ctl_read_urb->status != -ENOENT) &&
3924                     (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3925                     (hdw->ctl_read_urb->status != -ECONNRESET)) {
3926                         /* USB subsystem is reporting some kind of failure
3927                            on the read */
3928                         status = hdw->ctl_read_urb->status;
3929                         if (!probe_fl) {
3930                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3931                                            "control-read URB failure,"
3932                                            " status=%d",
3933                                            status);
3934                         }
3935                         goto done;
3936                 }
3937                 if (hdw->ctl_read_urb->actual_length < read_len) {
3938                         /* Failed to read enough data */
3939                         status = -EIO;
3940                         if (!probe_fl) {
3941                                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3942                                            "control-read URB short,"
3943                                            " expected=%d got=%d",
3944                                            read_len,
3945                                            hdw->ctl_read_urb->actual_length);
3946                         }
3947                         goto done;
3948                 }
3949                 /* Transfer retrieved data out from internal buffer */
3950                 for (idx = 0; idx < read_len; idx++) {
3951                         ((unsigned char *)read_data)[idx] =
3952                                 hdw->ctl_read_buffer[idx];
3953                 }
3954         }
3955
3956  done:
3957
3958         hdw->cmd_debug_state = 0;
3959         if ((status < 0) && (!probe_fl)) {
3960                 pvr2_hdw_render_useless(hdw);
3961         }
3962         return status;
3963 }
3964
3965
3966 int pvr2_send_request(struct pvr2_hdw *hdw,
3967                       void *write_data,unsigned int write_len,
3968                       void *read_data,unsigned int read_len)
3969 {
3970         return pvr2_send_request_ex(hdw,HZ*4,0,
3971                                     write_data,write_len,
3972                                     read_data,read_len);
3973 }
3974
3975
3976 static int pvr2_issue_simple_cmd(struct pvr2_hdw *hdw,u32 cmdcode)
3977 {
3978         int ret;
3979         unsigned int cnt = 1;
3980         unsigned int args = 0;
3981         LOCK_TAKE(hdw->ctl_lock);
3982         hdw->cmd_buffer[0] = cmdcode & 0xffu;
3983         args = (cmdcode >> 8) & 0xffu;
3984         args = (args > 2) ? 2 : args;
3985         if (args) {
3986                 cnt += args;
3987                 hdw->cmd_buffer[1] = (cmdcode >> 16) & 0xffu;
3988                 if (args > 1) {
3989                         hdw->cmd_buffer[2] = (cmdcode >> 24) & 0xffu;
3990                 }
3991         }
3992         if (pvrusb2_debug & PVR2_TRACE_INIT) {
3993                 unsigned int idx;
3994                 unsigned int ccnt,bcnt;
3995                 char tbuf[50];
3996                 cmdcode &= 0xffu;
3997                 bcnt = 0;
3998                 ccnt = scnprintf(tbuf+bcnt,
3999                                  sizeof(tbuf)-bcnt,
4000                                  "Sending FX2 command 0x%x",cmdcode);
4001                 bcnt += ccnt;
4002                 for (idx = 0; idx < ARRAY_SIZE(pvr2_fx2cmd_desc); idx++) {
4003                         if (pvr2_fx2cmd_desc[idx].id == cmdcode) {
4004                                 ccnt = scnprintf(tbuf+bcnt,
4005                                                  sizeof(tbuf)-bcnt,
4006                                                  " \"%s\"",
4007                                                  pvr2_fx2cmd_desc[idx].desc);
4008                                 bcnt += ccnt;
4009                                 break;
4010                         }
4011                 }
4012                 if (args) {
4013                         ccnt = scnprintf(tbuf+bcnt,
4014                                          sizeof(tbuf)-bcnt,
4015                                          " (%u",hdw->cmd_buffer[1]);
4016                         bcnt += ccnt;
4017                         if (args > 1) {
4018                                 ccnt = scnprintf(tbuf+bcnt,
4019                                                  sizeof(tbuf)-bcnt,
4020                                                  ",%u",hdw->cmd_buffer[2]);
4021                                 bcnt += ccnt;
4022                         }
4023                         ccnt = scnprintf(tbuf+bcnt,
4024                                          sizeof(tbuf)-bcnt,
4025                                          ")");
4026                         bcnt += ccnt;
4027                 }
4028                 pvr2_trace(PVR2_TRACE_INIT,"%.*s",bcnt,tbuf);
4029         }
4030         ret = pvr2_send_request(hdw,hdw->cmd_buffer,cnt,NULL,0);
4031         LOCK_GIVE(hdw->ctl_lock);
4032         return ret;
4033 }
4034
4035
4036 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
4037 {
4038         int ret;
4039
4040         LOCK_TAKE(hdw->ctl_lock);
4041
4042         hdw->cmd_buffer[0] = FX2CMD_REG_WRITE;  /* write register prefix */
4043         PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
4044         hdw->cmd_buffer[5] = 0;
4045         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4046         hdw->cmd_buffer[7] = reg & 0xff;
4047
4048
4049         ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
4050
4051         LOCK_GIVE(hdw->ctl_lock);
4052
4053         return ret;
4054 }
4055
4056
4057 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
4058 {
4059         int ret = 0;
4060
4061         LOCK_TAKE(hdw->ctl_lock);
4062
4063         hdw->cmd_buffer[0] = FX2CMD_REG_READ;  /* read register prefix */
4064         hdw->cmd_buffer[1] = 0;
4065         hdw->cmd_buffer[2] = 0;
4066         hdw->cmd_buffer[3] = 0;
4067         hdw->cmd_buffer[4] = 0;
4068         hdw->cmd_buffer[5] = 0;
4069         hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
4070         hdw->cmd_buffer[7] = reg & 0xff;
4071
4072         ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
4073         *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
4074
4075         LOCK_GIVE(hdw->ctl_lock);
4076
4077         return ret;
4078 }
4079
4080
4081 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
4082 {
4083         if (!hdw->flag_ok) return;
4084         pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4085                    "Device being rendered inoperable");
4086         if (hdw->vid_stream) {
4087                 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
4088         }
4089         hdw->flag_ok = 0;
4090         trace_stbit("flag_ok",hdw->flag_ok);
4091         pvr2_hdw_state_sched(hdw);
4092 }
4093
4094
4095 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
4096 {
4097         int ret;
4098         pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
4099         ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
4100         if (ret == 0) {
4101                 ret = usb_reset_device(hdw->usb_dev);
4102                 usb_unlock_device(hdw->usb_dev);
4103         } else {
4104                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4105                            "Failed to lock USB device ret=%d",ret);
4106         }
4107         if (init_pause_msec) {
4108                 pvr2_trace(PVR2_TRACE_INFO,
4109                            "Waiting %u msec for hardware to settle",
4110                            init_pause_msec);
4111                 msleep(init_pause_msec);
4112         }
4113
4114 }
4115
4116
4117 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
4118 {
4119         char *da;
4120         unsigned int pipe;
4121         int ret;
4122
4123         if (!hdw->usb_dev) return;
4124
4125         da = kmalloc(16, GFP_KERNEL);
4126
4127         if (da == NULL) {
4128                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4129                            "Unable to allocate memory to control CPU reset");
4130                 return;
4131         }
4132
4133         pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
4134
4135         da[0] = val ? 0x01 : 0x00;
4136
4137         /* Write the CPUCS register on the 8051.  The lsb of the register
4138            is the reset bit; a 1 asserts reset while a 0 clears it. */
4139         pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
4140         ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
4141         if (ret < 0) {
4142                 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
4143                            "cpureset_assert(%d) error=%d",val,ret);
4144                 pvr2_hdw_render_useless(hdw);
4145         }
4146
4147         kfree(da);
4148 }
4149
4150
4151 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
4152 {
4153         return pvr2_issue_simple_cmd(hdw,FX2CMD_DEEP_RESET);
4154 }
4155
4156
4157 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
4158 {
4159         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_ON);
4160 }
4161
4162
4163 int pvr2_hdw_cmd_powerdown(struct pvr2_hdw *hdw)
4164 {
4165         return pvr2_issue_simple_cmd(hdw,FX2CMD_POWER_OFF);
4166 }
4167
4168
4169 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
4170 {
4171         pvr2_trace(PVR2_TRACE_INIT,
4172                    "Requesting decoder reset");
4173         if (hdw->decoder_client_id) {
4174                 v4l2_device_call_all(&hdw->v4l2_dev, hdw->decoder_client_id,
4175                                      core, reset, 0);
4176                 pvr2_hdw_cx25840_vbi_hack(hdw);
4177                 return 0;
4178         }
4179         pvr2_trace(PVR2_TRACE_INIT,
4180                    "Unable to reset decoder: nothing attached");
4181         return -ENOTTY;
4182 }
4183
4184
4185 static int pvr2_hdw_cmd_hcw_demod_reset(struct pvr2_hdw *hdw, int onoff)
4186 {
4187         hdw->flag_ok = !0;
4188         return pvr2_issue_simple_cmd(hdw,
4189                                      FX2CMD_HCW_DEMOD_RESETIN |
4190                                      (1 << 8) |
4191                                      ((onoff ? 1 : 0) << 16));
4192 }
4193
4194
4195 static int pvr2_hdw_cmd_onair_fe_power_ctrl(struct pvr2_hdw *hdw, int onoff)
4196 {
4197         hdw->flag_ok = !0;
4198         return pvr2_issue_simple_cmd(hdw,(onoff ?
4199                                           FX2CMD_ONAIR_DTV_POWER_ON :
4200                                           FX2CMD_ONAIR_DTV_POWER_OFF));
4201 }
4202
4203
4204 static int pvr2_hdw_cmd_onair_digital_path_ctrl(struct pvr2_hdw *hdw,
4205                                                 int onoff)
4206 {
4207         return pvr2_issue_simple_cmd(hdw,(onoff ?
4208                                           FX2CMD_ONAIR_DTV_STREAMING_ON :
4209                                           FX2CMD_ONAIR_DTV_STREAMING_OFF));
4210 }
4211
4212
4213 static void pvr2_hdw_cmd_modeswitch(struct pvr2_hdw *hdw,int digitalFl)
4214 {
4215         int cmode;
4216         /* Compare digital/analog desired setting with current setting.  If
4217            they don't match, fix it... */
4218         cmode = (digitalFl ? PVR2_PATHWAY_DIGITAL : PVR2_PATHWAY_ANALOG);
4219         if (cmode == hdw->pathway_state) {
4220                 /* They match; nothing to do */
4221                 return;
4222         }
4223
4224         switch (hdw->hdw_desc->digital_control_scheme) {
4225         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4226                 pvr2_hdw_cmd_hcw_demod_reset(hdw,digitalFl);
4227                 if (cmode == PVR2_PATHWAY_ANALOG) {
4228                         /* If moving to analog mode, also force the decoder
4229                            to reset.  If no decoder is attached, then it's
4230                            ok to ignore this because if/when the decoder
4231                            attaches, it will reset itself at that time. */
4232                         pvr2_hdw_cmd_decoder_reset(hdw);
4233                 }
4234                 break;
4235         case PVR2_DIGITAL_SCHEME_ONAIR:
4236                 /* Supposedly we should always have the power on whether in
4237                    digital or analog mode.  But for now do what appears to
4238                    work... */
4239                 pvr2_hdw_cmd_onair_fe_power_ctrl(hdw,digitalFl);
4240                 break;
4241         default: break;
4242         }
4243
4244         pvr2_hdw_untrip_unlocked(hdw);
4245         hdw->pathway_state = cmode;
4246 }
4247
4248
4249 static void pvr2_led_ctrl_hauppauge(struct pvr2_hdw *hdw, int onoff)
4250 {
4251         /* change some GPIO data
4252          *
4253          * note: bit d7 of dir appears to control the LED,
4254          * so we shut it off here.
4255          *
4256          */
4257         if (onoff) {
4258                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000481);
4259         } else {
4260                 pvr2_hdw_gpio_chg_dir(hdw, 0xffffffff, 0x00000401);
4261         }
4262         pvr2_hdw_gpio_chg_out(hdw, 0xffffffff, 0x00000000);
4263 }
4264
4265
4266 typedef void (*led_method_func)(struct pvr2_hdw *,int);
4267
4268 static led_method_func led_methods[] = {
4269         [PVR2_LED_SCHEME_HAUPPAUGE] = pvr2_led_ctrl_hauppauge,
4270 };
4271
4272
4273 /* Toggle LED */
4274 static void pvr2_led_ctrl(struct pvr2_hdw *hdw,int onoff)
4275 {
4276         unsigned int scheme_id;
4277         led_method_func fp;
4278
4279         if ((!onoff) == (!hdw->led_on)) return;
4280
4281         hdw->led_on = onoff != 0;
4282
4283         scheme_id = hdw->hdw_desc->led_scheme;
4284         if (scheme_id < ARRAY_SIZE(led_methods)) {
4285                 fp = led_methods[scheme_id];
4286         } else {
4287                 fp = NULL;
4288         }
4289
4290         if (fp) (*fp)(hdw,onoff);
4291 }
4292
4293
4294 /* Stop / start video stream transport */
4295 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
4296 {
4297         int ret;
4298
4299         /* If we're in analog mode, then just issue the usual analog
4300            command. */
4301         if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4302                 return pvr2_issue_simple_cmd(hdw,
4303                                              (runFl ?
4304                                               FX2CMD_STREAMING_ON :
4305                                               FX2CMD_STREAMING_OFF));
4306                 /*Note: Not reached */
4307         }
4308
4309         if (hdw->pathway_state != PVR2_PATHWAY_DIGITAL) {
4310                 /* Whoops, we don't know what mode we're in... */
4311                 return -EINVAL;
4312         }
4313
4314         /* To get here we have to be in digital mode.  The mechanism here
4315            is unfortunately different for different vendors.  So we switch
4316            on the device's digital scheme attribute in order to figure out
4317            what to do. */
4318         switch (hdw->hdw_desc->digital_control_scheme) {
4319         case PVR2_DIGITAL_SCHEME_HAUPPAUGE:
4320                 return pvr2_issue_simple_cmd(hdw,
4321                                              (runFl ?
4322                                               FX2CMD_HCW_DTV_STREAMING_ON :
4323                                               FX2CMD_HCW_DTV_STREAMING_OFF));
4324         case PVR2_DIGITAL_SCHEME_ONAIR:
4325                 ret = pvr2_issue_simple_cmd(hdw,
4326                                             (runFl ?
4327                                              FX2CMD_STREAMING_ON :
4328                                              FX2CMD_STREAMING_OFF));
4329                 if (ret) return ret;
4330                 return pvr2_hdw_cmd_onair_digital_path_ctrl(hdw,runFl);
4331         default:
4332                 return -EINVAL;
4333         }
4334 }
4335
4336
4337 /* Evaluate whether or not state_pathway_ok can change */
4338 static int state_eval_pathway_ok(struct pvr2_hdw *hdw)
4339 {
4340         if (hdw->state_pathway_ok) {
4341                 /* Nothing to do if pathway is already ok */
4342                 return 0;
4343         }
4344         if (!hdw->state_pipeline_idle) {
4345                 /* Not allowed to change anything if pipeline is not idle */
4346                 return 0;
4347         }
4348         pvr2_hdw_cmd_modeswitch(hdw,hdw->input_val == PVR2_CVAL_INPUT_DTV);
4349         hdw->state_pathway_ok = !0;
4350         trace_stbit("state_pathway_ok",hdw->state_pathway_ok);
4351         return !0;
4352 }
4353
4354
4355 /* Evaluate whether or not state_encoder_ok can change */
4356 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
4357 {
4358         if (hdw->state_encoder_ok) return 0;
4359         if (hdw->flag_tripped) return 0;
4360         if (hdw->state_encoder_run) return 0;
4361         if (hdw->state_encoder_config) return 0;
4362         if (hdw->state_decoder_run) return 0;
4363         if (hdw->state_usbstream_run) return 0;
4364         if (hdw->pathway_state == PVR2_PATHWAY_DIGITAL) {
4365                 if (!hdw->hdw_desc->flag_digital_requires_cx23416) return 0;
4366         } else if (hdw->pathway_state != PVR2_PATHWAY_ANALOG) {
4367                 return 0;
4368         }
4369
4370         if (pvr2_upload_firmware2(hdw) < 0) {
4371                 hdw->flag_tripped = !0;
4372                 trace_stbit("flag_tripped",hdw->flag_tripped);
4373                 return !0;
4374         }
4375         hdw->state_encoder_ok = !0;
4376         trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
4377         return !0;
4378 }
4379
4380
4381 /* Evaluate whether or not state_encoder_config can change */
4382 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
4383 {
4384         if (hdw->state_encoder_config) {
4385                 if (hdw->state_encoder_ok) {
4386                         if (hdw->state_pipeline_req &&
4387                             !hdw->state_pipeline_pause) return 0;
4388                 }
4389                 hdw->state_encoder_config = 0;
4390                 hdw->state_encoder_waitok = 0;
4391                 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4392                 /* paranoia - solve race if timer just completed */
4393                 del_timer_sync(&hdw->encoder_wait_timer);
4394         } else {
4395                 if (!hdw->state_pathway_ok ||
4396                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4397                     !hdw->state_encoder_ok ||
4398                     !hdw->state_pipeline_idle ||
4399                     hdw->state_pipeline_pause ||
4400                     !hdw->state_pipeline_req ||
4401                     !hdw->state_pipeline_config) {
4402                         /* We must reset the enforced wait interval if
4403                            anything has happened that might have disturbed
4404                            the encoder.  This should be a rare case. */
4405                         if (timer_pending(&hdw->encoder_wait_timer)) {
4406                                 del_timer_sync(&hdw->encoder_wait_timer);
4407                         }
4408                         if (hdw->state_encoder_waitok) {
4409                                 /* Must clear the state - therefore we did
4410                                    something to a state bit and must also
4411                                    return true. */
4412                                 hdw->state_encoder_waitok = 0;
4413                                 trace_stbit("state_encoder_waitok",
4414                                             hdw->state_encoder_waitok);
4415                                 return !0;
4416                         }
4417                         return 0;
4418                 }
4419                 if (!hdw->state_encoder_waitok) {
4420                         if (!timer_pending(&hdw->encoder_wait_timer)) {
4421                                 /* waitok flag wasn't set and timer isn't
4422                                    running.  Check flag once more to avoid
4423                                    a race then start the timer.  This is
4424                                    the point when we measure out a minimal
4425                                    quiet interval before doing something to
4426                                    the encoder. */
4427                                 if (!hdw->state_encoder_waitok) {
4428                                         hdw->encoder_wait_timer.expires =
4429                                                 jiffies +
4430                                                 (HZ * TIME_MSEC_ENCODER_WAIT
4431                                                  / 1000);
4432                                         add_timer(&hdw->encoder_wait_timer);
4433                                 }
4434                         }
4435                         /* We can't continue until we know we have been
4436                            quiet for the interval measured by this
4437                            timer. */
4438                         return 0;
4439                 }
4440                 pvr2_encoder_configure(hdw);
4441                 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
4442         }
4443         trace_stbit("state_encoder_config",hdw->state_encoder_config);
4444         return !0;
4445 }
4446
4447
4448 /* Return true if the encoder should not be running. */
4449 static int state_check_disable_encoder_run(struct pvr2_hdw *hdw)
4450 {
4451         if (!hdw->state_encoder_ok) {
4452                 /* Encoder isn't healthy at the moment, so stop it. */
4453                 return !0;
4454         }
4455         if (!hdw->state_pathway_ok) {
4456                 /* Mode is not understood at the moment (i.e. it wants to
4457                    change), so encoder must be stopped. */
4458                 return !0;
4459         }
4460
4461         switch (hdw->pathway_state) {
4462         case PVR2_PATHWAY_ANALOG:
4463                 if (!hdw->state_decoder_run) {
4464                         /* We're in analog mode and the decoder is not
4465                            running; thus the encoder should be stopped as
4466                            well. */
4467                         return !0;
4468                 }
4469                 break;
4470         case PVR2_PATHWAY_DIGITAL:
4471                 if (hdw->state_encoder_runok) {
4472                         /* This is a funny case.  We're in digital mode so
4473                            really the encoder should be stopped.  However
4474                            if it really is running, only kill it after
4475                            runok has been set.  This gives a chance for the
4476                            onair quirk to function (encoder must run
4477                            briefly first, at least once, before onair
4478                            digital streaming can work). */
4479                         return !0;
4480                 }
4481                 break;
4482         default:
4483                 /* Unknown mode; so encoder should be stopped. */
4484                 return !0;
4485         }
4486
4487         /* If we get here, we haven't found a reason to stop the
4488            encoder. */
4489         return 0;
4490 }
4491
4492
4493 /* Return true if the encoder should be running. */
4494 static int state_check_enable_encoder_run(struct pvr2_hdw *hdw)
4495 {
4496         if (!hdw->state_encoder_ok) {
4497                 /* Don't run the encoder if it isn't healthy... */
4498                 return 0;
4499         }
4500         if (!hdw->state_pathway_ok) {
4501                 /* Don't run the encoder if we don't (yet) know what mode
4502                    we need to be in... */
4503                 return 0;
4504         }
4505
4506         switch (hdw->pathway_state) {
4507         case PVR2_PATHWAY_ANALOG:
4508                 if (hdw->state_decoder_run && hdw->state_decoder_ready) {
4509                         /* In analog mode, if the decoder is running, then
4510                            run the encoder. */
4511                         return !0;
4512                 }
4513                 break;
4514         case PVR2_PATHWAY_DIGITAL:
4515                 if ((hdw->hdw_desc->digital_control_scheme ==
4516                      PVR2_DIGITAL_SCHEME_ONAIR) &&
4517                     !hdw->state_encoder_runok) {
4518                         /* This is a quirk.  OnAir hardware won't stream
4519                            digital until the encoder has been run at least
4520                            once, for a minimal period of time (empiricially
4521                            measured to be 1/4 second).  So if we're on
4522                            OnAir hardware and the encoder has never been
4523                            run at all, then start the encoder.  Normal
4524                            state machine logic in the driver will
4525                            automatically handle the remaining bits. */
4526                         return !0;
4527                 }
4528                 break;
4529         default:
4530                 /* For completeness (unknown mode; encoder won't run ever) */
4531                 break;
4532         }
4533         /* If we get here, then we haven't found any reason to run the
4534            encoder, so don't run it. */
4535         return 0;
4536 }
4537
4538
4539 /* Evaluate whether or not state_encoder_run can change */
4540 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
4541 {
4542         if (hdw->state_encoder_run) {
4543                 if (!state_check_disable_encoder_run(hdw)) return 0;
4544                 if (hdw->state_encoder_ok) {
4545                         del_timer_sync(&hdw->encoder_run_timer);
4546                         if (pvr2_encoder_stop(hdw) < 0) return !0;
4547                 }
4548                 hdw->state_encoder_run = 0;
4549         } else {
4550                 if (!state_check_enable_encoder_run(hdw)) return 0;
4551                 if (pvr2_encoder_start(hdw) < 0) return !0;
4552                 hdw->state_encoder_run = !0;
4553                 if (!hdw->state_encoder_runok) {
4554                         hdw->encoder_run_timer.expires =
4555                                 jiffies + (HZ * TIME_MSEC_ENCODER_OK / 1000);
4556                         add_timer(&hdw->encoder_run_timer);
4557                 }
4558         }
4559         trace_stbit("state_encoder_run",hdw->state_encoder_run);
4560         return !0;
4561 }
4562
4563
4564 /* Timeout function for quiescent timer. */
4565 static void pvr2_hdw_quiescent_timeout(unsigned long data)
4566 {
4567         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4568         hdw->state_decoder_quiescent = !0;
4569         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4570         hdw->state_stale = !0;
4571         queue_work(hdw->workqueue,&hdw->workpoll);
4572 }
4573
4574
4575 /* Timeout function for decoder stabilization timer. */
4576 static void pvr2_hdw_decoder_stabilization_timeout(unsigned long data)
4577 {
4578         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4579         hdw->state_decoder_ready = !0;
4580         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4581         hdw->state_stale = !0;
4582         queue_work(hdw->workqueue, &hdw->workpoll);
4583 }
4584
4585
4586 /* Timeout function for encoder wait timer. */
4587 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
4588 {
4589         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4590         hdw->state_encoder_waitok = !0;
4591         trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
4592         hdw->state_stale = !0;
4593         queue_work(hdw->workqueue,&hdw->workpoll);
4594 }
4595
4596
4597 /* Timeout function for encoder run timer. */
4598 static void pvr2_hdw_encoder_run_timeout(unsigned long data)
4599 {
4600         struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
4601         if (!hdw->state_encoder_runok) {
4602                 hdw->state_encoder_runok = !0;
4603                 trace_stbit("state_encoder_runok",hdw->state_encoder_runok);
4604                 hdw->state_stale = !0;
4605                 queue_work(hdw->workqueue,&hdw->workpoll);
4606         }
4607 }
4608
4609
4610 /* Evaluate whether or not state_decoder_run can change */
4611 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
4612 {
4613         if (hdw->state_decoder_run) {
4614                 if (hdw->state_encoder_ok) {
4615                         if (hdw->state_pipeline_req &&
4616                             !hdw->state_pipeline_pause &&
4617                             hdw->state_pathway_ok) return 0;
4618                 }
4619                 if (!hdw->flag_decoder_missed) {
4620                         pvr2_decoder_enable(hdw,0);
4621                 }
4622                 hdw->state_decoder_quiescent = 0;
4623                 hdw->state_decoder_run = 0;
4624                 /* paranoia - solve race if timer(s) just completed */
4625                 del_timer_sync(&hdw->quiescent_timer);
4626                 /* Kill the stabilization timer, in case we're killing the
4627                    encoder before the previous stabilization interval has
4628                    been properly timed. */
4629                 del_timer_sync(&hdw->decoder_stabilization_timer);
4630                 hdw->state_decoder_ready = 0;
4631         } else {
4632                 if (!hdw->state_decoder_quiescent) {
4633                         if (!timer_pending(&hdw->quiescent_timer)) {
4634                                 /* We don't do something about the
4635                                    quiescent timer until right here because
4636                                    we also want to catch cases where the
4637                                    decoder was already not running (like
4638                                    after initialization) as opposed to
4639                                    knowing that we had just stopped it.
4640                                    The second flag check is here to cover a
4641                                    race - the timer could have run and set
4642                                    this flag just after the previous check
4643                                    but before we did the pending check. */
4644                                 if (!hdw->state_decoder_quiescent) {
4645                                         hdw->quiescent_timer.expires =
4646                                                 jiffies +
4647                                                 (HZ * TIME_MSEC_DECODER_WAIT
4648                                                  / 1000);
4649                                         add_timer(&hdw->quiescent_timer);
4650                                 }
4651                         }
4652                         /* Don't allow decoder to start again until it has
4653                            been quiesced first.  This little detail should
4654                            hopefully further stabilize the encoder. */
4655                         return 0;
4656                 }
4657                 if (!hdw->state_pathway_ok ||
4658                     (hdw->pathway_state != PVR2_PATHWAY_ANALOG) ||
4659                     !hdw->state_pipeline_req ||
4660                     hdw->state_pipeline_pause ||
4661                     !hdw->state_pipeline_config ||
4662                     !hdw->state_encoder_config ||
4663                     !hdw->state_encoder_ok) return 0;
4664                 del_timer_sync(&hdw->quiescent_timer);
4665                 if (hdw->flag_decoder_missed) return 0;
4666                 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
4667                 hdw->state_decoder_quiescent = 0;
4668                 hdw->state_decoder_ready = 0;
4669                 hdw->state_decoder_run = !0;
4670                 if (hdw->decoder_client_id == PVR2_CLIENT_ID_SAA7115) {
4671                         hdw->decoder_stabilization_timer.expires =
4672                                 jiffies +
4673                                 (HZ * TIME_MSEC_DECODER_STABILIZATION_WAIT /
4674                                  1000);
4675                         add_timer(&hdw->decoder_stabilization_timer);
4676                 } else {
4677                         hdw->state_decoder_ready = !0;
4678                 }
4679         }
4680         trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
4681         trace_stbit("state_decoder_run",hdw->state_decoder_run);
4682         trace_stbit("state_decoder_ready", hdw->state_decoder_ready);
4683         return !0;
4684 }
4685
4686
4687 /* Evaluate whether or not state_usbstream_run can change */
4688 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
4689 {
4690         if (hdw->state_usbstream_run) {
4691                 int fl = !0;
4692                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4693                         fl = (hdw->state_encoder_ok &&
4694                               hdw->state_encoder_run);
4695                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4696                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4697                         fl = hdw->state_encoder_ok;
4698                 }
4699                 if (fl &&
4700                     hdw->state_pipeline_req &&
4701                     !hdw->state_pipeline_pause &&
4702                     hdw->state_pathway_ok) {
4703                         return 0;
4704                 }
4705                 pvr2_hdw_cmd_usbstream(hdw,0);
4706                 hdw->state_usbstream_run = 0;
4707         } else {
4708                 if (!hdw->state_pipeline_req ||
4709                     hdw->state_pipeline_pause ||
4710                     !hdw->state_pathway_ok) return 0;
4711                 if (hdw->pathway_state == PVR2_PATHWAY_ANALOG) {
4712                         if (!hdw->state_encoder_ok ||
4713                             !hdw->state_encoder_run) return 0;
4714                 } else if ((hdw->pathway_state == PVR2_PATHWAY_DIGITAL) &&
4715                            (hdw->hdw_desc->flag_digital_requires_cx23416)) {
4716                         if (!hdw->state_encoder_ok) return 0;
4717                         if (hdw->state_encoder_run) return 0;
4718                         if (hdw->hdw_desc->digital_control_scheme ==
4719                             PVR2_DIGITAL_SCHEME_ONAIR) {
4720                                 /* OnAir digital receivers won't stream
4721                                    unless the analog encoder has run first.
4722                                    Why?  I have no idea.  But don't even
4723                                    try until we know the analog side is
4724                                    known to have run. */
4725                                 if (!hdw->state_encoder_runok) return 0;
4726                         }
4727                 }
4728                 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
4729                 hdw->state_usbstream_run = !0;
4730         }
4731         trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
4732         return !0;
4733 }
4734
4735
4736 /* Attempt to configure pipeline, if needed */
4737 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
4738 {
4739         if (hdw->state_pipeline_config ||
4740             hdw->state_pipeline_pause) return 0;
4741         pvr2_hdw_commit_execute(hdw);
4742         return !0;
4743 }
4744
4745
4746 /* Update pipeline idle and pipeline pause tracking states based on other
4747    inputs.  This must be called whenever the other relevant inputs have
4748    changed. */
4749 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
4750 {
4751         unsigned int st;
4752         int updatedFl = 0;
4753         /* Update pipeline state */
4754         st = !(hdw->state_encoder_run ||
4755                hdw->state_decoder_run ||
4756                hdw->state_usbstream_run ||
4757                (!hdw->state_decoder_quiescent));
4758         if (!st != !hdw->state_pipeline_idle) {
4759                 hdw->state_pipeline_idle = st;
4760                 updatedFl = !0;
4761         }
4762         if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
4763                 hdw->state_pipeline_pause = 0;
4764                 updatedFl = !0;
4765         }
4766         return updatedFl;
4767 }
4768
4769
4770 typedef int (*state_eval_func)(struct pvr2_hdw *);
4771
4772 /* Set of functions to be run to evaluate various states in the driver. */
4773 static const state_eval_func eval_funcs[] = {
4774         state_eval_pathway_ok,
4775         state_eval_pipeline_config,
4776         state_eval_encoder_ok,
4777         state_eval_encoder_config,
4778         state_eval_decoder_run,
4779         state_eval_encoder_run,
4780         state_eval_usbstream_run,
4781 };
4782
4783
4784 /* Process various states and return true if we did anything interesting. */
4785 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
4786 {
4787         unsigned int i;
4788         int state_updated = 0;
4789         int check_flag;
4790
4791         if (!hdw->state_stale) return 0;
4792         if ((hdw->fw1_state != FW1_STATE_OK) ||
4793             !hdw->flag_ok) {
4794                 hdw->state_stale = 0;
4795                 return !0;
4796         }
4797         /* This loop is the heart of the entire driver.  It keeps trying to
4798            evaluate various bits of driver state until nothing changes for
4799            one full iteration.  Each "bit of state" tracks some global
4800            aspect of the driver, e.g. whether decoder should run, if
4801            pipeline is configured, usb streaming is on, etc.  We separately
4802            evaluate each of those questions based on other driver state to
4803            arrive at the correct running configuration. */
4804         do {
4805                 check_flag = 0;
4806                 state_update_pipeline_state(hdw);
4807                 /* Iterate over each bit of state */
4808                 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
4809                         if ((*eval_funcs[i])(hdw)) {
4810                                 check_flag = !0;
4811                                 state_updated = !0;
4812                                 state_update_pipeline_state(hdw);
4813                         }
4814                 }
4815         } while (check_flag && hdw->flag_ok);
4816         hdw->state_stale = 0;
4817         trace_stbit("state_stale",hdw->state_stale);
4818         return state_updated;
4819 }
4820
4821
4822 static unsigned int print_input_mask(unsigned int msk,
4823                                      char *buf,unsigned int acnt)
4824 {
4825         unsigned int idx,ccnt;
4826         unsigned int tcnt = 0;
4827         for (idx = 0; idx < ARRAY_SIZE(control_values_input); idx++) {
4828                 if (!((1 << idx) & msk)) continue;
4829                 ccnt = scnprintf(buf+tcnt,
4830                                  acnt-tcnt,
4831                                  "%s%s",
4832                                  (tcnt ? ", " : ""),
4833                                  control_values_input[idx]);
4834                 tcnt += ccnt;
4835         }
4836         return tcnt;
4837 }
4838
4839
4840 static const char *pvr2_pathway_state_name(int id)
4841 {
4842         switch (id) {
4843         case PVR2_PATHWAY_ANALOG: return "analog";
4844         case PVR2_PATHWAY_DIGITAL: return "digital";
4845         default: return "unknown";
4846         }
4847 }
4848
4849
4850 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
4851                                              char *buf,unsigned int acnt)
4852 {
4853         switch (which) {
4854         case 0:
4855                 return scnprintf(
4856                         buf,acnt,
4857                         "driver:%s%s%s%s%s <mode=%s>",
4858                         (hdw->flag_ok ? " <ok>" : " <fail>"),
4859                         (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
4860                         (hdw->flag_disconnected ? " <disconnected>" :
4861                          " <connected>"),
4862                         (hdw->flag_tripped ? " <tripped>" : ""),
4863                         (hdw->flag_decoder_missed ? " <no decoder>" : ""),
4864                         pvr2_pathway_state_name(hdw->pathway_state));
4865
4866         case 1:
4867                 return scnprintf(
4868                         buf,acnt,
4869                         "pipeline:%s%s%s%s",
4870                         (hdw->state_pipeline_idle ? " <idle>" : ""),
4871                         (hdw->state_pipeline_config ?
4872                          " <configok>" : " <stale>"),
4873                         (hdw->state_pipeline_req ? " <req>" : ""),
4874                         (hdw->state_pipeline_pause ? " <pause>" : ""));
4875         case 2:
4876                 return scnprintf(
4877                         buf,acnt,
4878                         "worker:%s%s%s%s%s%s%s",
4879                         (hdw->state_decoder_run ?
4880                          (hdw->state_decoder_ready ?
4881                           "<decode:run>" : " <decode:start>") :
4882                          (hdw->state_decoder_quiescent ?
4883                           "" : " <decode:stop>")),
4884                         (hdw->state_decoder_quiescent ?
4885                          " <decode:quiescent>" : ""),
4886                         (hdw->state_encoder_ok ?
4887                          "" : " <encode:init>"),
4888                         (hdw->state_encoder_run ?
4889                          (hdw->state_encoder_runok ?
4890                           " <encode:run>" :
4891                           " <encode:firstrun>") :
4892                          (hdw->state_encoder_runok ?
4893                           " <encode:stop>" :
4894                           " <encode:virgin>")),
4895                         (hdw->state_encoder_config ?
4896                          " <encode:configok>" :
4897                          (hdw->state_encoder_waitok ?
4898                           "" : " <encode:waitok>")),
4899                         (hdw->state_usbstream_run ?
4900                          " <usb:run>" : " <usb:stop>"),
4901                         (hdw->state_pathway_ok ?
4902                          " <pathway:ok>" : ""));
4903         case 3:
4904                 return scnprintf(
4905                         buf,acnt,
4906                         "state: %s",
4907                         pvr2_get_state_name(hdw->master_state));
4908         case 4: {
4909                 unsigned int tcnt = 0;
4910                 unsigned int ccnt;
4911
4912                 ccnt = scnprintf(buf,
4913                                  acnt,
4914                                  "Hardware supported inputs: ");
4915                 tcnt += ccnt;
4916                 tcnt += print_input_mask(hdw->input_avail_mask,
4917                                          buf+tcnt,
4918                                          acnt-tcnt);
4919                 if (hdw->input_avail_mask != hdw->input_allowed_mask) {
4920                         ccnt = scnprintf(buf+tcnt,
4921                                          acnt-tcnt,
4922                                          "; allowed inputs: ");
4923                         tcnt += ccnt;
4924                         tcnt += print_input_mask(hdw->input_allowed_mask,
4925                                                  buf+tcnt,
4926                                                  acnt-tcnt);
4927                 }
4928                 return tcnt;
4929         }
4930         case 5: {
4931                 struct pvr2_stream_stats stats;
4932                 if (!hdw->vid_stream) break;
4933                 pvr2_stream_get_stats(hdw->vid_stream,
4934                                       &stats,
4935                                       0);
4936                 return scnprintf(
4937                         buf,acnt,
4938                         "Bytes streamed=%u"
4939                         " URBs: queued=%u idle=%u ready=%u"
4940                         " processed=%u failed=%u",
4941                         stats.bytes_processed,
4942                         stats.buffers_in_queue,
4943                         stats.buffers_in_idle,
4944                         stats.buffers_in_ready,
4945                         stats.buffers_processed,
4946                         stats.buffers_failed);
4947         }
4948         case 6: {
4949                 unsigned int id = hdw->ir_scheme_active;
4950                 return scnprintf(buf, acnt, "ir scheme: id=%d %s", id,
4951                                  (id >= ARRAY_SIZE(ir_scheme_names) ?
4952                                   "?" : ir_scheme_names[id]));
4953         }
4954         default: break;
4955         }
4956         return 0;
4957 }
4958
4959
4960 /* Generate report containing info about attached sub-devices and attached
4961    i2c clients, including an indication of which attached i2c clients are
4962    actually sub-devices. */
4963 static unsigned int pvr2_hdw_report_clients(struct pvr2_hdw *hdw,
4964                                             char *buf, unsigned int acnt)
4965 {
4966         struct v4l2_subdev *sd;
4967         unsigned int tcnt = 0;
4968         unsigned int ccnt;
4969         struct i2c_client *client;
4970         const char *p;
4971         unsigned int id;
4972
4973         ccnt = scnprintf(buf, acnt, "Associated v4l2-subdev drivers and I2C clients:\n");
4974         tcnt += ccnt;
4975         v4l2_device_for_each_subdev(sd, &hdw->v4l2_dev) {
4976                 id = sd->grp_id;
4977                 p = NULL;
4978                 if (id < ARRAY_SIZE(module_names)) p = module_names[id];
4979                 if (p) {
4980                         ccnt = scnprintf(buf + tcnt, acnt - tcnt, "  %s:", p);
4981                         tcnt += ccnt;
4982                 } else {
4983                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4984                                          "  (unknown id=%u):", id);
4985                         tcnt += ccnt;
4986                 }
4987                 client = v4l2_get_subdevdata(sd);
4988                 if (client) {
4989                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4990                                          " %s @ %02x\n", client->name,
4991                                          client->addr);
4992                         tcnt += ccnt;
4993                 } else {
4994                         ccnt = scnprintf(buf + tcnt, acnt - tcnt,
4995                                          " no i2c client\n");
4996                         tcnt += ccnt;
4997                 }
4998         }
4999         return tcnt;
5000 }
5001
5002
5003 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
5004                                    char *buf,unsigned int acnt)
5005 {
5006         unsigned int bcnt,ccnt,idx;
5007         bcnt = 0;
5008         LOCK_TAKE(hdw->big_lock);
5009         for (idx = 0; ; idx++) {
5010                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
5011                 if (!ccnt) break;
5012                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5013                 if (!acnt) break;
5014                 buf[0] = '\n'; ccnt = 1;
5015                 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5016         }
5017         ccnt = pvr2_hdw_report_clients(hdw, buf, acnt);
5018         bcnt += ccnt; acnt -= ccnt; buf += ccnt;
5019         LOCK_GIVE(hdw->big_lock);
5020         return bcnt;
5021 }
5022
5023
5024 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
5025 {
5026         char buf[256];
5027         unsigned int idx, ccnt;
5028         unsigned int lcnt, ucnt;
5029
5030         for (idx = 0; ; idx++) {
5031                 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
5032                 if (!ccnt) break;
5033                 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
5034         }
5035         ccnt = pvr2_hdw_report_clients(hdw, buf, sizeof(buf));
5036         ucnt = 0;
5037         while (ucnt < ccnt) {
5038                 lcnt = 0;
5039                 while ((lcnt + ucnt < ccnt) && (buf[lcnt + ucnt] != '\n')) {
5040                         lcnt++;
5041                 }
5042                 printk(KERN_INFO "%s %.*s\n", hdw->name, lcnt, buf + ucnt);
5043                 ucnt += lcnt + 1;
5044         }
5045 }
5046
5047
5048 /* Evaluate and update the driver's current state, taking various actions
5049    as appropriate for the update. */
5050 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
5051 {
5052         unsigned int st;
5053         int state_updated = 0;
5054         int callback_flag = 0;
5055         int analog_mode;
5056
5057         pvr2_trace(PVR2_TRACE_STBITS,
5058                    "Drive state check START");
5059         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5060                 pvr2_hdw_state_log_state(hdw);
5061         }
5062
5063         /* Process all state and get back over disposition */
5064         state_updated = pvr2_hdw_state_update(hdw);
5065
5066         analog_mode = (hdw->pathway_state != PVR2_PATHWAY_DIGITAL);
5067
5068         /* Update master state based upon all other states. */
5069         if (!hdw->flag_ok) {
5070                 st = PVR2_STATE_DEAD;
5071         } else if (hdw->fw1_state != FW1_STATE_OK) {
5072                 st = PVR2_STATE_COLD;
5073         } else if ((analog_mode ||
5074                     hdw->hdw_desc->flag_digital_requires_cx23416) &&
5075                    !hdw->state_encoder_ok) {
5076                 st = PVR2_STATE_WARM;
5077         } else if (hdw->flag_tripped ||
5078                    (analog_mode && hdw->flag_decoder_missed)) {
5079                 st = PVR2_STATE_ERROR;
5080         } else if (hdw->state_usbstream_run &&
5081                    (!analog_mode ||
5082                     (hdw->state_encoder_run && hdw->state_decoder_run))) {
5083                 st = PVR2_STATE_RUN;
5084         } else {
5085                 st = PVR2_STATE_READY;
5086         }
5087         if (hdw->master_state != st) {
5088                 pvr2_trace(PVR2_TRACE_STATE,
5089                            "Device state change from %s to %s",
5090                            pvr2_get_state_name(hdw->master_state),
5091                            pvr2_get_state_name(st));
5092                 pvr2_led_ctrl(hdw,st == PVR2_STATE_RUN);
5093                 hdw->master_state = st;
5094                 state_updated = !0;
5095                 callback_flag = !0;
5096         }
5097         if (state_updated) {
5098                 /* Trigger anyone waiting on any state changes here. */
5099                 wake_up(&hdw->state_wait_data);
5100         }
5101
5102         if (pvrusb2_debug & PVR2_TRACE_STBITS) {
5103                 pvr2_hdw_state_log_state(hdw);
5104         }
5105         pvr2_trace(PVR2_TRACE_STBITS,
5106                    "Drive state check DONE callback=%d",callback_flag);
5107
5108         return callback_flag;
5109 }
5110
5111
5112 /* Cause kernel thread to check / update driver state */
5113 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
5114 {
5115         if (hdw->state_stale) return;
5116         hdw->state_stale = !0;
5117         trace_stbit("state_stale",hdw->state_stale);
5118         queue_work(hdw->workqueue,&hdw->workpoll);
5119 }
5120
5121
5122 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
5123 {
5124         return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
5125 }
5126
5127
5128 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
5129 {
5130         return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
5131 }
5132
5133
5134 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
5135 {
5136         return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
5137 }
5138
5139
5140 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
5141 {
5142         u32 cval,nval;
5143         int ret;
5144         if (~msk) {
5145                 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
5146                 if (ret) return ret;
5147                 nval = (cval & ~msk) | (val & msk);
5148                 pvr2_trace(PVR2_TRACE_GPIO,
5149                            "GPIO direction changing 0x%x:0x%x"
5150                            " from 0x%x to 0x%x",
5151                            msk,val,cval,nval);
5152         } else {
5153                 nval = val;
5154                 pvr2_trace(PVR2_TRACE_GPIO,
5155                            "GPIO direction changing to 0x%x",nval);
5156         }
5157         return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
5158 }
5159
5160
5161 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
5162 {
5163         u32 cval,nval;
5164         int ret;
5165         if (~msk) {
5166                 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
5167                 if (ret) return ret;
5168                 nval = (cval & ~msk) | (val & msk);
5169                 pvr2_trace(PVR2_TRACE_GPIO,
5170                            "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
5171                            msk,val,cval,nval);
5172         } else {
5173                 nval = val;
5174                 pvr2_trace(PVR2_TRACE_GPIO,
5175                            "GPIO output changing to 0x%x",nval);
5176         }
5177         return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
5178 }
5179
5180
5181 void pvr2_hdw_status_poll(struct pvr2_hdw *hdw)
5182 {
5183         struct v4l2_tuner *vtp = &hdw->tuner_signal_info;
5184         memset(vtp, 0, sizeof(*vtp));
5185         vtp->type = (hdw->input_val == PVR2_CVAL_INPUT_RADIO) ?
5186                 V4L2_TUNER_RADIO : V4L2_TUNER_ANALOG_TV;
5187         hdw->tuner_signal_stale = 0;
5188         /* Note: There apparently is no replacement for VIDIOC_CROPCAP
5189            using v4l2-subdev - therefore we can't support that AT ALL right
5190            now.  (Of course, no sub-drivers seem to implement it either.
5191            But now it's a a chicken and egg problem...) */
5192         v4l2_device_call_all(&hdw->v4l2_dev, 0, tuner, g_tuner, vtp);
5193         pvr2_trace(PVR2_TRACE_CHIPS, "subdev status poll"
5194                    " type=%u strength=%u audio=0x%x cap=0x%x"
5195                    " low=%u hi=%u",
5196                    vtp->type,
5197                    vtp->signal, vtp->rxsubchans, vtp->capability,
5198                    vtp->rangelow, vtp->rangehigh);
5199
5200         /* We have to do this to avoid getting into constant polling if
5201            there's nobody to answer a poll of cropcap info. */
5202         hdw->cropcap_stale = 0;
5203 }
5204
5205
5206 unsigned int pvr2_hdw_get_input_available(struct pvr2_hdw *hdw)
5207 {
5208         return hdw->input_avail_mask;
5209 }
5210
5211
5212 unsigned int pvr2_hdw_get_input_allowed(struct pvr2_hdw *hdw)
5213 {
5214         return hdw->input_allowed_mask;
5215 }
5216
5217
5218 static int pvr2_hdw_set_input(struct pvr2_hdw *hdw,int v)
5219 {
5220         if (hdw->input_val != v) {
5221                 hdw->input_val = v;
5222                 hdw->input_dirty = !0;
5223         }
5224
5225         /* Handle side effects - if we switch to a mode that needs the RF
5226            tuner, then select the right frequency choice as well and mark
5227            it dirty. */
5228         if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
5229                 hdw->freqSelector = 0;
5230                 hdw->freqDirty = !0;
5231         } else if ((hdw->input_val == PVR2_CVAL_INPUT_TV) ||
5232                    (hdw->input_val == PVR2_CVAL_INPUT_DTV)) {
5233                 hdw->freqSelector = 1;
5234                 hdw->freqDirty = !0;
5235         }
5236         return 0;
5237 }
5238
5239
5240 int pvr2_hdw_set_input_allowed(struct pvr2_hdw *hdw,
5241                                unsigned int change_mask,
5242                                unsigned int change_val)
5243 {
5244         int ret = 0;
5245         unsigned int nv,m,idx;
5246         LOCK_TAKE(hdw->big_lock);
5247         do {
5248                 nv = hdw->input_allowed_mask & ~change_mask;
5249                 nv |= (change_val & change_mask);
5250                 nv &= hdw->input_avail_mask;
5251                 if (!nv) {
5252                         /* No legal modes left; return error instead. */
5253                         ret = -EPERM;
5254                         break;
5255                 }
5256                 hdw->input_allowed_mask = nv;
5257                 if ((1 << hdw->input_val) & hdw->input_allowed_mask) {
5258                         /* Current mode is still in the allowed mask, so
5259                            we're done. */
5260                         break;
5261                 }
5262                 /* Select and switch to a mode that is still in the allowed
5263                    mask */
5264                 if (!hdw->input_allowed_mask) {
5265                         /* Nothing legal; give up */
5266                         break;
5267                 }
5268                 m = hdw->input_allowed_mask;
5269                 for (idx = 0; idx < (sizeof(m) << 3); idx++) {
5270                         if (!((1 << idx) & m)) continue;
5271                         pvr2_hdw_set_input(hdw,idx);
5272                         break;
5273                 }
5274         } while (0);
5275         LOCK_GIVE(hdw->big_lock);
5276         return ret;
5277 }
5278
5279
5280 /* Find I2C address of eeprom */
5281 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
5282 {
5283         int result;
5284         LOCK_TAKE(hdw->ctl_lock); do {
5285                 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
5286                 result = pvr2_send_request(hdw,
5287                                            hdw->cmd_buffer,1,
5288                                            hdw->cmd_buffer,1);
5289                 if (result < 0) break;
5290                 result = hdw->cmd_buffer[0];
5291         } while(0); LOCK_GIVE(hdw->ctl_lock);
5292         return result;
5293 }
5294
5295
5296 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
5297                              struct v4l2_dbg_match *match, u64 reg_id,
5298                              int setFl, u64 *val_ptr)
5299 {
5300 #ifdef CONFIG_VIDEO_ADV_DEBUG
5301         struct v4l2_dbg_register req;
5302         int stat = 0;
5303         int okFl = 0;
5304
5305         if (!capable(CAP_SYS_ADMIN)) return -EPERM;
5306
5307         req.match = *match;
5308         req.reg = reg_id;
5309         if (setFl) req.val = *val_ptr;
5310         /* It would be nice to know if a sub-device answered the request */
5311         v4l2_device_call_all(&hdw->v4l2_dev, 0, core, g_register, &req);
5312         if (!setFl) *val_ptr = req.val;
5313         if (okFl) {
5314                 return stat;
5315         }
5316         return -EINVAL;
5317 #else
5318         return -ENOSYS;
5319 #endif
5320 }
5321
5322
5323 /*
5324   Stuff for Emacs to see, in order to encourage consistent editing style:
5325   *** Local Variables: ***
5326   *** mode: c ***
5327   *** fill-column: 75 ***
5328   *** tab-width: 8 ***
5329   *** c-basic-offset: 8 ***
5330   *** End: ***
5331   */