drivers/media/platform/ti/omap3isp/ispcsi2.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ispcsi2.c
   4  *
   5  * TI OMAP3 ISP - CSI2 module
   6  *
   7  * Copyright (C) 2010 Nokia Corporation
   8  * Copyright (C) 2009 Texas Instruments, Inc.
   9  *
  10  * Contacts: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  11  *           Sakari Ailus <sakari.ailus@iki.fi>
  12  */
  13 #include <linux/delay.h>
  14 #include <media/v4l2-common.h>
  15 #include <linux/v4l2-mediabus.h>
  16 #include <linux/mm.h>
  17
  18 #include "isp.h"
  19 #include "ispreg.h"
  20 #include "ispcsi2.h"
  21
  22 /*
  23  * csi2_if_enable - Enable CSI2 Receiver interface.
  24  * @enable: enable flag
  25  *
  26  */
  27 static void csi2_if_enable(struct isp_device *isp,
  28                            struct isp_csi2_device *csi2, u8 enable)
  29 {
  30         struct isp_csi2_ctrl_cfg *currctrl = &csi2->ctrl;
  31
  32         isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_CTRL, ISPCSI2_CTRL_IF_EN,
  33                         enable ? ISPCSI2_CTRL_IF_EN : 0);
  34
  35         currctrl->if_enable = enable;
  36 }
  37
  38 /*
  39  * csi2_recv_config - CSI2 receiver module configuration.
  40  * @currctrl: isp_csi2_ctrl_cfg structure
  41  *
  42  */
  43 static void csi2_recv_config(struct isp_device *isp,
  44                              struct isp_csi2_device *csi2,
  45                              struct isp_csi2_ctrl_cfg *currctrl)
  46 {
  47         u32 reg;
  48
  49         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTRL);
  50
  51         if (currctrl->frame_mode)
  52                 reg |= ISPCSI2_CTRL_FRAME;
  53         else
  54                 reg &= ~ISPCSI2_CTRL_FRAME;
  55
  56         if (currctrl->vp_clk_enable)
  57                 reg |= ISPCSI2_CTRL_VP_CLK_EN;
  58         else
  59                 reg &= ~ISPCSI2_CTRL_VP_CLK_EN;
  60
  61         if (currctrl->vp_only_enable)
  62                 reg |= ISPCSI2_CTRL_VP_ONLY_EN;
  63         else
  64                 reg &= ~ISPCSI2_CTRL_VP_ONLY_EN;
  65
  66         reg &= ~ISPCSI2_CTRL_VP_OUT_CTRL_MASK;
  67         reg |= currctrl->vp_out_ctrl << ISPCSI2_CTRL_VP_OUT_CTRL_SHIFT;
  68
  69         if (currctrl->ecc_enable)
  70                 reg |= ISPCSI2_CTRL_ECC_EN;
  71         else
  72                 reg &= ~ISPCSI2_CTRL_ECC_EN;
  73
  74         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTRL);
  75 }
  76
  77 static const unsigned int csi2_input_fmts[] = {
  78         MEDIA_BUS_FMT_SGRBG10_1X10,
  79         MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8,
  80         MEDIA_BUS_FMT_SRGGB10_1X10,
  81         MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8,
  82         MEDIA_BUS_FMT_SBGGR10_1X10,
  83         MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8,
  84         MEDIA_BUS_FMT_SGBRG10_1X10,
  85         MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8,
  86         MEDIA_BUS_FMT_YUYV8_2X8,
  87 };
  88
  89 /* To set the format on the CSI2 requires a mapping function that takes
  90  * the following inputs:
  91  * - 3 different formats (at this time)
  92  * - 2 destinations (mem, vp+mem) (vp only handled separately)
  93  * - 2 decompression options (on, off)
  94  * - 2 isp revisions (certain format must be handled differently on OMAP3630)
  95  * Output should be CSI2 frame format code
  96  * Array indices as follows: [format][dest][decompr][is_3630]
  97  * Not all combinations are valid. 0 means invalid.
  98  */
  99 static const u16 __csi2_fmt_map[3][2][2][2] = {
 100         /* RAW10 formats */
 101         {
 102                 /* Output to memory */
 103                 {
 104                         /* No DPCM decompression */
 105                         { CSI2_PIX_FMT_RAW10_EXP16, CSI2_PIX_FMT_RAW10_EXP16 },
 106                         /* DPCM decompression */
 107                         { 0, 0 },
 108                 },
 109                 /* Output to both */
 110                 {
 111                         /* No DPCM decompression */
 112                         { CSI2_PIX_FMT_RAW10_EXP16_VP,
 113                           CSI2_PIX_FMT_RAW10_EXP16_VP },
 114                         /* DPCM decompression */
 115                         { 0, 0 },
 116                 },
 117         },
 118         /* RAW10 DPCM8 formats */
 119         {
 120                 /* Output to memory */
 121                 {
 122                         /* No DPCM decompression */
 123                         { CSI2_PIX_FMT_RAW8, CSI2_USERDEF_8BIT_DATA1 },
 124                         /* DPCM decompression */
 125                         { CSI2_PIX_FMT_RAW8_DPCM10_EXP16,
 126                           CSI2_USERDEF_8BIT_DATA1_DPCM10 },
 127                 },
 128                 /* Output to both */
 129                 {
 130                         /* No DPCM decompression */
 131                         { CSI2_PIX_FMT_RAW8_VP,
 132                           CSI2_PIX_FMT_RAW8_VP },
 133                         /* DPCM decompression */
 134                         { CSI2_PIX_FMT_RAW8_DPCM10_VP,
 135                           CSI2_USERDEF_8BIT_DATA1_DPCM10_VP },
 136                 },
 137         },
 138         /* YUYV8 2X8 formats */
 139         {
 140                 /* Output to memory */
 141                 {
 142                         /* No DPCM decompression */
 143                         { CSI2_PIX_FMT_YUV422_8BIT,
 144                           CSI2_PIX_FMT_YUV422_8BIT },
 145                         /* DPCM decompression */
 146                         { 0, 0 },
 147                 },
 148                 /* Output to both */
 149                 {
 150                         /* No DPCM decompression */
 151                         { CSI2_PIX_FMT_YUV422_8BIT_VP,
 152                           CSI2_PIX_FMT_YUV422_8BIT_VP },
 153                         /* DPCM decompression */
 154                         { 0, 0 },
 155                 },
 156         },
 157 };
 158
 159 /*
 160  * csi2_ctx_map_format - Map CSI2 sink media bus format to CSI2 format ID
 161  * @csi2: ISP CSI2 device
 162  *
 163  * Returns CSI2 physical format id
 164  */
 165 static u16 csi2_ctx_map_format(struct isp_csi2_device *csi2)
 166 {
 167         const struct v4l2_mbus_framefmt *fmt = &csi2->formats[CSI2_PAD_SINK];
 168         int fmtidx, destidx, is_3630;
 169
 170         switch (fmt->code) {
 171         case MEDIA_BUS_FMT_SGRBG10_1X10:
 172         case MEDIA_BUS_FMT_SRGGB10_1X10:
 173         case MEDIA_BUS_FMT_SBGGR10_1X10:
 174         case MEDIA_BUS_FMT_SGBRG10_1X10:
 175                 fmtidx = 0;
 176                 break;
 177         case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
 178         case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
 179         case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
 180         case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
 181                 fmtidx = 1;
 182                 break;
 183         case MEDIA_BUS_FMT_YUYV8_2X8:
 184                 fmtidx = 2;
 185                 break;
 186         default:
 187                 WARN(1, KERN_ERR "CSI2: pixel format %08x unsupported!\n",
 188                      fmt->code);
 189                 return 0;
 190         }
 191
 192         if (!(csi2->output & CSI2_OUTPUT_CCDC) &&
 193             !(csi2->output & CSI2_OUTPUT_MEMORY)) {
 194                 /* Neither output enabled is a valid combination */
 195                 return CSI2_PIX_FMT_OTHERS;
 196         }
 197
 198         /* If we need to skip frames at the beginning of the stream disable the
 199          * video port to avoid sending the skipped frames to the CCDC.
 200          */
 201         destidx = csi2->frame_skip ? 0 : !!(csi2->output & CSI2_OUTPUT_CCDC);
 202         is_3630 = csi2->isp->revision == ISP_REVISION_15_0;
 203
 204         return __csi2_fmt_map[fmtidx][destidx][csi2->dpcm_decompress][is_3630];
 205 }
 206
 207 /*
 208  * csi2_set_outaddr - Set memory address to save output image
 209  * @csi2: Pointer to ISP CSI2a device.
 210  * @addr: ISP MMU Mapped 32-bit memory address aligned on 32 byte boundary.
 211  *
 212  * Sets the memory address where the output will be saved.
 213  *
 214  * Returns 0 if successful, or -EINVAL if the address is not in the 32 byte
 215  * boundary.
 216  */
 217 static void csi2_set_outaddr(struct isp_csi2_device *csi2, u32 addr)
 218 {
 219         struct isp_device *isp = csi2->isp;
 220         struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[0];
 221
 222         ctx->ping_addr = addr;
 223         ctx->pong_addr = addr;
 224         isp_reg_writel(isp, ctx->ping_addr,
 225                        csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
 226         isp_reg_writel(isp, ctx->pong_addr,
 227                        csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
 228 }
 229
 230 /*
 231  * is_usr_def_mapping - Checks whether USER_DEF_MAPPING should
 232  *                      be enabled by CSI2.
 233  * @format_id: mapped format id
 234  *
 235  */
 236 static inline int is_usr_def_mapping(u32 format_id)
 237 {
 238         return (format_id & 0x40) ? 1 : 0;
 239 }
 240
 241 /*
 242  * csi2_ctx_enable - Enable specified CSI2 context
 243  * @ctxnum: Context number, valid between 0 and 7 values.
 244  * @enable: enable
 245  *
 246  */
 247 static void csi2_ctx_enable(struct isp_device *isp,
 248                             struct isp_csi2_device *csi2, u8 ctxnum, u8 enable)
 249 {
 250         struct isp_csi2_ctx_cfg *ctx = &csi2->contexts[ctxnum];
 251         unsigned int skip = 0;
 252         u32 reg;
 253
 254         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
 255
 256         if (enable) {
 257                 if (csi2->frame_skip)
 258                         skip = csi2->frame_skip;
 259                 else if (csi2->output & CSI2_OUTPUT_MEMORY)
 260                         skip = 1;
 261
 262                 reg &= ~ISPCSI2_CTX_CTRL1_COUNT_MASK;
 263                 reg |= ISPCSI2_CTX_CTRL1_COUNT_UNLOCK
 264                     |  (skip << ISPCSI2_CTX_CTRL1_COUNT_SHIFT)
 265                     |  ISPCSI2_CTX_CTRL1_CTX_EN;
 266         } else {
 267                 reg &= ~ISPCSI2_CTX_CTRL1_CTX_EN;
 268         }
 269
 270         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctxnum));
 271         ctx->enabled = enable;
 272 }
 273
 274 /*
 275  * csi2_ctx_config - CSI2 context configuration.
 276  * @ctx: context configuration
 277  *
 278  */
 279 static void csi2_ctx_config(struct isp_device *isp,
 280                             struct isp_csi2_device *csi2,
 281                             struct isp_csi2_ctx_cfg *ctx)
 282 {
 283         u32 reg;
 284
 285         /* Set up CSI2_CTx_CTRL1 */
 286         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
 287
 288         if (ctx->eof_enabled)
 289                 reg |= ISPCSI2_CTX_CTRL1_EOF_EN;
 290         else
 291                 reg &= ~ISPCSI2_CTX_CTRL1_EOF_EN;
 292
 293         if (ctx->eol_enabled)
 294                 reg |= ISPCSI2_CTX_CTRL1_EOL_EN;
 295         else
 296                 reg &= ~ISPCSI2_CTX_CTRL1_EOL_EN;
 297
 298         if (ctx->checksum_enabled)
 299                 reg |= ISPCSI2_CTX_CTRL1_CS_EN;
 300         else
 301                 reg &= ~ISPCSI2_CTX_CTRL1_CS_EN;
 302
 303         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL1(ctx->ctxnum));
 304
 305         /* Set up CSI2_CTx_CTRL2 */
 306         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
 307
 308         reg &= ~(ISPCSI2_CTX_CTRL2_VIRTUAL_ID_MASK);
 309         reg |= ctx->virtual_id << ISPCSI2_CTX_CTRL2_VIRTUAL_ID_SHIFT;
 310
 311         reg &= ~(ISPCSI2_CTX_CTRL2_FORMAT_MASK);
 312         reg |= ctx->format_id << ISPCSI2_CTX_CTRL2_FORMAT_SHIFT;
 313
 314         if (ctx->dpcm_decompress) {
 315                 if (ctx->dpcm_predictor)
 316                         reg |= ISPCSI2_CTX_CTRL2_DPCM_PRED;
 317                 else
 318                         reg &= ~ISPCSI2_CTX_CTRL2_DPCM_PRED;
 319         }
 320
 321         if (is_usr_def_mapping(ctx->format_id)) {
 322                 reg &= ~ISPCSI2_CTX_CTRL2_USER_DEF_MAP_MASK;
 323                 reg |= 2 << ISPCSI2_CTX_CTRL2_USER_DEF_MAP_SHIFT;
 324         }
 325
 326         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL2(ctx->ctxnum));
 327
 328         /* Set up CSI2_CTx_CTRL3 */
 329         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
 330         reg &= ~(ISPCSI2_CTX_CTRL3_ALPHA_MASK);
 331         reg |= (ctx->alpha << ISPCSI2_CTX_CTRL3_ALPHA_SHIFT);
 332
 333         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_CTX_CTRL3(ctx->ctxnum));
 334
 335         /* Set up CSI2_CTx_DAT_OFST */
 336         reg = isp_reg_readl(isp, csi2->regs1,
 337                             ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
 338         reg &= ~ISPCSI2_CTX_DAT_OFST_OFST_MASK;
 339         reg |= ctx->data_offset << ISPCSI2_CTX_DAT_OFST_OFST_SHIFT;
 340         isp_reg_writel(isp, reg, csi2->regs1,
 341                        ISPCSI2_CTX_DAT_OFST(ctx->ctxnum));
 342
 343         isp_reg_writel(isp, ctx->ping_addr,
 344                        csi2->regs1, ISPCSI2_CTX_DAT_PING_ADDR(ctx->ctxnum));
 345
 346         isp_reg_writel(isp, ctx->pong_addr,
 347                        csi2->regs1, ISPCSI2_CTX_DAT_PONG_ADDR(ctx->ctxnum));
 348 }
 349
 350 /*
 351  * csi2_timing_config - CSI2 timing configuration.
 352  * @timing: csi2_timing_cfg structure
 353  */
 354 static void csi2_timing_config(struct isp_device *isp,
 355                                struct isp_csi2_device *csi2,
 356                                struct isp_csi2_timing_cfg *timing)
 357 {
 358         u32 reg;
 359
 360         reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_TIMING);
 361
 362         if (timing->force_rx_mode)
 363                 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
 364         else
 365                 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum);
 366
 367         if (timing->stop_state_16x)
 368                 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
 369         else
 370                 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum);
 371
 372         if (timing->stop_state_4x)
 373                 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
 374         else
 375                 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum);
 376
 377         reg &= ~ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_MASK(timing->ionum);
 378         reg |= timing->stop_state_counter <<
 379                ISPCSI2_TIMING_STOP_STATE_COUNTER_IO_SHIFT(timing->ionum);
 380
 381         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_TIMING);
 382 }
 383
 384 /*
 385  * csi2_irq_ctx_set - Enables CSI2 Context IRQs.
 386  * @enable: Enable/disable CSI2 Context interrupts
 387  */
 388 static void csi2_irq_ctx_set(struct isp_device *isp,
 389                              struct isp_csi2_device *csi2, int enable)
 390 {
 391         int i;
 392
 393         for (i = 0; i < 8; i++) {
 394                 isp_reg_writel(isp, ISPCSI2_CTX_IRQSTATUS_FE_IRQ, csi2->regs1,
 395                                ISPCSI2_CTX_IRQSTATUS(i));
 396                 if (enable)
 397                         isp_reg_set(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
 398                                     ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
 399                 else
 400                         isp_reg_clr(isp, csi2->regs1, ISPCSI2_CTX_IRQENABLE(i),
 401                                     ISPCSI2_CTX_IRQSTATUS_FE_IRQ);
 402         }
 403 }
 404
 405 /*
 406  * csi2_irq_complexio1_set - Enables CSI2 ComplexIO IRQs.
 407  * @enable: Enable/disable CSI2 ComplexIO #1 interrupts
 408  */
 409 static void csi2_irq_complexio1_set(struct isp_device *isp,
 410                                     struct isp_csi2_device *csi2, int enable)
 411 {
 412         u32 reg;
 413         reg = ISPCSI2_PHY_IRQENABLE_STATEALLULPMEXIT |
 414                 ISPCSI2_PHY_IRQENABLE_STATEALLULPMENTER |
 415                 ISPCSI2_PHY_IRQENABLE_STATEULPM5 |
 416                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL5 |
 417                 ISPCSI2_PHY_IRQENABLE_ERRESC5 |
 418                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS5 |
 419                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS5 |
 420                 ISPCSI2_PHY_IRQENABLE_STATEULPM4 |
 421                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL4 |
 422                 ISPCSI2_PHY_IRQENABLE_ERRESC4 |
 423                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS4 |
 424                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS4 |
 425                 ISPCSI2_PHY_IRQENABLE_STATEULPM3 |
 426                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL3 |
 427                 ISPCSI2_PHY_IRQENABLE_ERRESC3 |
 428                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS3 |
 429                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS3 |
 430                 ISPCSI2_PHY_IRQENABLE_STATEULPM2 |
 431                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL2 |
 432                 ISPCSI2_PHY_IRQENABLE_ERRESC2 |
 433                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS2 |
 434                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS2 |
 435                 ISPCSI2_PHY_IRQENABLE_STATEULPM1 |
 436                 ISPCSI2_PHY_IRQENABLE_ERRCONTROL1 |
 437                 ISPCSI2_PHY_IRQENABLE_ERRESC1 |
 438                 ISPCSI2_PHY_IRQENABLE_ERRSOTSYNCHS1 |
 439                 ISPCSI2_PHY_IRQENABLE_ERRSOTHS1;
 440         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
 441         if (enable)
 442                 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
 443         else
 444                 reg = 0;
 445         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_PHY_IRQENABLE);
 446 }
 447
 448 /*
 449  * csi2_irq_status_set - Enables CSI2 Status IRQs.
 450  * @enable: Enable/disable CSI2 Status interrupts
 451  */
 452 static void csi2_irq_status_set(struct isp_device *isp,
 453                                 struct isp_csi2_device *csi2, int enable)
 454 {
 455         u32 reg;
 456         reg = ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
 457                 ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
 458                 ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ |
 459                 ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
 460                 ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
 461                 ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ |
 462                 ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ |
 463                 ISPCSI2_IRQSTATUS_CONTEXT(0);
 464         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQSTATUS);
 465         if (enable)
 466                 reg |= isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQENABLE);
 467         else
 468                 reg = 0;
 469
 470         isp_reg_writel(isp, reg, csi2->regs1, ISPCSI2_IRQENABLE);
 471 }
 472
 473 /*
 474  * omap3isp_csi2_reset - Resets the CSI2 module.
 475  *
 476  * Must be called with the phy lock held.
 477  *
 478  * Returns 0 if successful, or -EBUSY if power command didn't respond.
 479  */
 480 int omap3isp_csi2_reset(struct isp_csi2_device *csi2)
 481 {
 482         struct isp_device *isp = csi2->isp;
 483         u8 soft_reset_retries = 0;
 484         u32 reg;
 485         int i;
 486
 487         if (!csi2->available)
 488                 return -ENODEV;
 489
 490         if (csi2->phy->entity)
 491                 return -EBUSY;
 492
 493         isp_reg_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
 494                     ISPCSI2_SYSCONFIG_SOFT_RESET);
 495
 496         do {
 497                 reg = isp_reg_readl(isp, csi2->regs1, ISPCSI2_SYSSTATUS) &
 498                                     ISPCSI2_SYSSTATUS_RESET_DONE;
 499                 if (reg == ISPCSI2_SYSSTATUS_RESET_DONE)
 500                         break;
 501                 soft_reset_retries++;
 502                 if (soft_reset_retries < 5)
 503                         udelay(100);
 504         } while (soft_reset_retries < 5);
 505
 506         if (soft_reset_retries == 5) {
 507                 dev_err(isp->dev, "CSI2: Soft reset try count exceeded!\n");
 508                 return -EBUSY;
 509         }
 510
 511         if (isp->revision == ISP_REVISION_15_0)
 512                 isp_reg_set(isp, csi2->regs1, ISPCSI2_PHY_CFG,
 513                             ISPCSI2_PHY_CFG_RESET_CTRL);
 514
 515         i = 100;
 516         do {
 517                 reg = isp_reg_readl(isp, csi2->phy->phy_regs, ISPCSIPHY_REG1)
 518                     & ISPCSIPHY_REG1_RESET_DONE_CTRLCLK;
 519                 if (reg == ISPCSIPHY_REG1_RESET_DONE_CTRLCLK)
 520                         break;
 521                 udelay(100);
 522         } while (--i > 0);
 523
 524         if (i == 0) {
 525                 dev_err(isp->dev,
 526                         "CSI2: Reset for CSI2_96M_FCLK domain Failed!\n");
 527                 return -EBUSY;
 528         }
 529
 530         if (isp->autoidle)
 531                 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
 532                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 533                                 ISPCSI2_SYSCONFIG_AUTO_IDLE,
 534                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_SMART |
 535                                 ((isp->revision == ISP_REVISION_15_0) ?
 536                                  ISPCSI2_SYSCONFIG_AUTO_IDLE : 0));
 537         else
 538                 isp_reg_clr_set(isp, csi2->regs1, ISPCSI2_SYSCONFIG,
 539                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_MASK |
 540                                 ISPCSI2_SYSCONFIG_AUTO_IDLE,
 541                                 ISPCSI2_SYSCONFIG_MSTANDBY_MODE_NO);
 542
 543         return 0;
 544 }
 545
 546 static int csi2_configure(struct isp_csi2_device *csi2)
 547 {
 548         struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
 549         const struct isp_bus_cfg *buscfg;
 550         struct isp_device *isp = csi2->isp;
 551         struct isp_csi2_timing_cfg *timing = &csi2->timing[0];
 552         struct v4l2_subdev *sensor;
 553         struct media_pad *pad;
 554
 555         /*
 556          * CSI2 fields that can be updated while the context has
 557          * been enabled or the interface has been enabled are not
 558          * updated dynamically currently. So we do not allow to
 559          * reconfigure if either has been enabled
 560          */
 561         if (csi2->contexts[0].enabled || csi2->ctrl.if_enable)
 562                 return -EBUSY;
 563
 564         pad = media_pad_remote_pad_first(&csi2->pads[CSI2_PAD_SINK]);
 565         sensor = media_entity_to_v4l2_subdev(pad->entity);
 566         buscfg = v4l2_subdev_to_bus_cfg(pipe->external);
 567         if (WARN_ON(!buscfg))
 568                 return -EPIPE;
 569
 570         csi2->frame_skip = 0;
 571         v4l2_subdev_call(sensor, sensor, g_skip_frames, &csi2->frame_skip);
 572
 573         csi2->ctrl.vp_out_ctrl =
 574                 clamp_t(unsigned int, pipe->l3_ick / pipe->external_rate - 1,
 575                         1, 3);
 576         dev_dbg(isp->dev, "%s: l3_ick %lu, external_rate %u, vp_out_ctrl %u\n",
 577                 __func__, pipe->l3_ick,  pipe->external_rate,
 578                 csi2->ctrl.vp_out_ctrl);
 579         csi2->ctrl.frame_mode = ISP_CSI2_FRAME_IMMEDIATE;
 580         csi2->ctrl.ecc_enable = buscfg->bus.csi2.crc;
 581
 582         timing->ionum = 1;
 583         timing->force_rx_mode = 1;
 584         timing->stop_state_16x = 1;
 585         timing->stop_state_4x = 1;
 586         timing->stop_state_counter = 0x1FF;
 587
 588         /*
 589          * The CSI2 receiver can't do any format conversion except DPCM
 590          * decompression, so every set_format call configures both pads
 591          * and enables DPCM decompression as a special case:
 592          */
 593         if (csi2->formats[CSI2_PAD_SINK].code !=
 594             csi2->formats[CSI2_PAD_SOURCE].code)
 595                 csi2->dpcm_decompress = true;
 596         else
 597                 csi2->dpcm_decompress = false;
 598
 599         csi2->contexts[0].format_id = csi2_ctx_map_format(csi2);
 600
 601         if (csi2->video_out.bpl_padding == 0)
 602                 csi2->contexts[0].data_offset = 0;
 603         else
 604                 csi2->contexts[0].data_offset = csi2->video_out.bpl_value;
 605
 606         /*
 607          * Enable end of frame and end of line signals generation for
 608          * context 0. These signals are generated from CSI2 receiver to
 609          * qualify the last pixel of a frame and the last pixel of a line.
 610          * Without enabling the signals CSI2 receiver writes data to memory
 611          * beyond buffer size and/or data line offset is not handled correctly.
 612          */
 613         csi2->contexts[0].eof_enabled = 1;
 614         csi2->contexts[0].eol_enabled = 1;
 615
 616         csi2_irq_complexio1_set(isp, csi2, 1);
 617         csi2_irq_ctx_set(isp, csi2, 1);
 618         csi2_irq_status_set(isp, csi2, 1);
 619
 620         /* Set configuration (timings, format and links) */
 621         csi2_timing_config(isp, csi2, timing);
 622         csi2_recv_config(isp, csi2, &csi2->ctrl);
 623         csi2_ctx_config(isp, csi2, &csi2->contexts[0]);
 624
 625         return 0;
 626 }
 627
 628 /*
 629  * csi2_print_status - Prints CSI2 debug information.
 630  */
 631 #define CSI2_PRINT_REGISTER(isp, regs, name)\
 632         dev_dbg(isp->dev, "###CSI2 " #name "=0x%08x\n", \
 633                 isp_reg_readl(isp, regs, ISPCSI2_##name))
 634
 635 static void csi2_print_status(struct isp_csi2_device *csi2)
 636 {
 637         struct isp_device *isp = csi2->isp;
 638
 639         if (!csi2->available)
 640                 return;
 641
 642         dev_dbg(isp->dev, "-------------CSI2 Register dump-------------\n");
 643
 644         CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSCONFIG);
 645         CSI2_PRINT_REGISTER(isp, csi2->regs1, SYSSTATUS);
 646         CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQENABLE);
 647         CSI2_PRINT_REGISTER(isp, csi2->regs1, IRQSTATUS);
 648         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTRL);
 649         CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_H);
 650         CSI2_PRINT_REGISTER(isp, csi2->regs1, GNQ);
 651         CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_CFG);
 652         CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQSTATUS);
 653         CSI2_PRINT_REGISTER(isp, csi2->regs1, SHORT_PACKET);
 654         CSI2_PRINT_REGISTER(isp, csi2->regs1, PHY_IRQENABLE);
 655         CSI2_PRINT_REGISTER(isp, csi2->regs1, DBG_P);
 656         CSI2_PRINT_REGISTER(isp, csi2->regs1, TIMING);
 657         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL1(0));
 658         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL2(0));
 659         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_OFST(0));
 660         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PING_ADDR(0));
 661         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_DAT_PONG_ADDR(0));
 662         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQENABLE(0));
 663         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_IRQSTATUS(0));
 664         CSI2_PRINT_REGISTER(isp, csi2->regs1, CTX_CTRL3(0));
 665
 666         dev_dbg(isp->dev, "--------------------------------------------\n");
 667 }
 668
 669 /* -----------------------------------------------------------------------------
 670  * Interrupt handling
 671  */
 672
 673 /*
 674  * csi2_isr_buffer - Does buffer handling at end-of-frame
 675  * when writing to memory.
 676  */
 677 static void csi2_isr_buffer(struct isp_csi2_device *csi2)
 678 {
 679         struct isp_device *isp = csi2->isp;
 680         struct isp_buffer *buffer;
 681
 682         csi2_ctx_enable(isp, csi2, 0, 0);
 683
 684         buffer = omap3isp_video_buffer_next(&csi2->video_out);
 685
 686         /*
 687          * Let video queue operation restart engine if there is an underrun
 688          * condition.
 689          */
 690         if (buffer == NULL)
 691                 return;
 692
 693         csi2_set_outaddr(csi2, buffer->dma);
 694         csi2_ctx_enable(isp, csi2, 0, 1);
 695 }
 696
 697 static void csi2_isr_ctx(struct isp_csi2_device *csi2,
 698                          struct isp_csi2_ctx_cfg *ctx)
 699 {
 700         struct isp_device *isp = csi2->isp;
 701         unsigned int n = ctx->ctxnum;
 702         u32 status;
 703
 704         status = isp_reg_readl(isp, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
 705         isp_reg_writel(isp, status, csi2->regs1, ISPCSI2_CTX_IRQSTATUS(n));
 706
 707         if (!(status & ISPCSI2_CTX_IRQSTATUS_FE_IRQ))
 708                 return;
 709
 710         /* Skip interrupts until we reach the frame skip count. The CSI2 will be
 711          * automatically disabled, as the frame skip count has been programmed
 712          * in the CSI2_CTx_CTRL1::COUNT field, so re-enable it.
 713          *
 714          * It would have been nice to rely on the FRAME_NUMBER interrupt instead
 715          * but it turned out that the interrupt is only generated when the CSI2
 716          * writes to memory (the CSI2_CTx_CTRL1::COUNT field is decreased
 717          * correctly and reaches 0 when data is forwarded to the video port only
 718          * but no interrupt arrives). Maybe a CSI2 hardware bug.
 719          */
 720         if (csi2->frame_skip) {
 721                 csi2->frame_skip--;
 722                 if (csi2->frame_skip == 0) {
 723                         ctx->format_id = csi2_ctx_map_format(csi2);
 724                         csi2_ctx_config(isp, csi2, ctx);
 725                         csi2_ctx_enable(isp, csi2, n, 1);
 726                 }
 727                 return;
 728         }
 729
 730         if (csi2->output & CSI2_OUTPUT_MEMORY)
 731                 csi2_isr_buffer(csi2);
 732 }
 733
 734 /*
 735  * omap3isp_csi2_isr - CSI2 interrupt handling.
 736  */
 737 void omap3isp_csi2_isr(struct isp_csi2_device *csi2)
 738 {
 739         struct isp_pipeline *pipe = to_isp_pipeline(&csi2->subdev.entity);
 740         u32 csi2_irqstatus, cpxio1_irqstatus;
 741         struct isp_device *isp = csi2->isp;
 742
 743         if (!csi2->available)
 744                 return;
 745
 746         csi2_irqstatus = isp_reg_readl(isp, csi2->regs1, ISPCSI2_IRQSTATUS);
 747         isp_reg_writel(isp, csi2_irqstatus, csi2->regs1, ISPCSI2_IRQSTATUS);
 748
 749         /* Failure Cases */
 750         if (csi2_irqstatus & ISPCSI2_IRQSTATUS_COMPLEXIO1_ERR_IRQ) {
 751                 cpxio1_irqstatus = isp_reg_readl(isp, csi2->regs1,
 752                                                  ISPCSI2_PHY_IRQSTATUS);
 753                 isp_reg_writel(isp, cpxio1_irqstatus,
 754                                csi2->regs1, ISPCSI2_PHY_IRQSTATUS);
 755                 dev_dbg(isp->dev, "CSI2: ComplexIO Error IRQ %x\n",
 756                         cpxio1_irqstatus);
 757                 pipe->error = true;
 758         }
 759
 760         if (csi2_irqstatus & (ISPCSI2_IRQSTATUS_OCP_ERR_IRQ |
 761                               ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ |
 762                               ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ |
 763                               ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ |
 764                               ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ)) {
 765                 dev_dbg(isp->dev,
 766                         "CSI2 Err: OCP:%d, Short_pack:%d, ECC:%d, CPXIO2:%d, FIFO_OVF:%d,\n",
 767                         (csi2_irqstatus &
 768                          ISPCSI2_IRQSTATUS_OCP_ERR_IRQ) ? 1 : 0,
 769                         (csi2_irqstatus &
 770                          ISPCSI2_IRQSTATUS_SHORT_PACKET_IRQ) ? 1 : 0,
 771                         (csi2_irqstatus &
 772                          ISPCSI2_IRQSTATUS_ECC_NO_CORRECTION_IRQ) ? 1 : 0,
 773                         (csi2_irqstatus &
 774                          ISPCSI2_IRQSTATUS_COMPLEXIO2_ERR_IRQ) ? 1 : 0,
 775                         (csi2_irqstatus &
 776                          ISPCSI2_IRQSTATUS_FIFO_OVF_IRQ) ? 1 : 0);
 777                 pipe->error = true;
 778         }
 779
 780         if (omap3isp_module_sync_is_stopping(&csi2->wait, &csi2->stopping))
 781                 return;
 782
 783         /* Successful cases */
 784         if (csi2_irqstatus & ISPCSI2_IRQSTATUS_CONTEXT(0))
 785                 csi2_isr_ctx(csi2, &csi2->contexts[0]);
 786
 787         if (csi2_irqstatus & ISPCSI2_IRQSTATUS_ECC_CORRECTION_IRQ)
 788                 dev_dbg(isp->dev, "CSI2: ECC correction done\n");
 789 }
 790
 791 /* -----------------------------------------------------------------------------
 792  * ISP video operations
 793  */
 794
 795 /*
 796  * csi2_queue - Queues the first buffer when using memory output
 797  * @video: The video node
 798  * @buffer: buffer to queue
 799  */
 800 static int csi2_queue(struct isp_video *video, struct isp_buffer *buffer)
 801 {
 802         struct isp_device *isp = video->isp;
 803         struct isp_csi2_device *csi2 = &isp->isp_csi2a;
 804
 805         csi2_set_outaddr(csi2, buffer->dma);
 806
 807         /*
 808          * If streaming was enabled before there was a buffer queued
 809          * or underrun happened in the ISR, the hardware was not enabled
 810          * and DMA queue flag ISP_VIDEO_DMAQUEUE_UNDERRUN is still set.
 811          * Enable it now.
 812          */
 813         if (csi2->video_out.dmaqueue_flags & ISP_VIDEO_DMAQUEUE_UNDERRUN) {
 814                 /* Enable / disable context 0 and IRQs */
 815                 csi2_if_enable(isp, csi2, 1);
 816                 csi2_ctx_enable(isp, csi2, 0, 1);
 817                 isp_video_dmaqueue_flags_clr(&csi2->video_out);
 818         }
 819
 820         return 0;
 821 }
 822
 823 static const struct isp_video_operations csi2_ispvideo_ops = {
 824         .queue = csi2_queue,
 825 };
 826
 827 /* -----------------------------------------------------------------------------
 828  * V4L2 subdev operations
 829  */
 830
 831 static struct v4l2_mbus_framefmt *
 832 __csi2_get_format(struct isp_csi2_device *csi2,
 833                   struct v4l2_subdev_state *sd_state,
 834                   unsigned int pad, enum v4l2_subdev_format_whence which)
 835 {
 836         if (which == V4L2_SUBDEV_FORMAT_TRY)
 837                 return v4l2_subdev_get_try_format(&csi2->subdev, sd_state,
 838                                                   pad);
 839         else
 840                 return &csi2->formats[pad];
 841 }
 842
 843 static void
 844 csi2_try_format(struct isp_csi2_device *csi2,
 845                 struct v4l2_subdev_state *sd_state,
 846                 unsigned int pad, struct v4l2_mbus_framefmt *fmt,
 847                 enum v4l2_subdev_format_whence which)
 848 {
 849         u32 pixelcode;
 850         struct v4l2_mbus_framefmt *format;
 851         const struct isp_format_info *info;
 852         unsigned int i;
 853
 854         switch (pad) {
 855         case CSI2_PAD_SINK:
 856                 /* Clamp the width and height to valid range (1-8191). */
 857                 for (i = 0; i < ARRAY_SIZE(csi2_input_fmts); i++) {
 858                         if (fmt->code == csi2_input_fmts[i])
 859                                 break;
 860                 }
 861
 862                 /* If not found, use SGRBG10 as default */
 863                 if (i >= ARRAY_SIZE(csi2_input_fmts))
 864                         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 865
 866                 fmt->width = clamp_t(u32, fmt->width, 1, 8191);
 867                 fmt->height = clamp_t(u32, fmt->height, 1, 8191);
 868                 break;
 869
 870         case CSI2_PAD_SOURCE:
 871                 /* Source format same as sink format, except for DPCM
 872                  * compression.
 873                  */
 874                 pixelcode = fmt->code;
 875                 format = __csi2_get_format(csi2, sd_state, CSI2_PAD_SINK,
 876                                            which);
 877                 memcpy(fmt, format, sizeof(*fmt));
 878
 879                 /*
 880                  * Only Allow DPCM decompression, and check that the
 881                  * pattern is preserved
 882                  */
 883                 info = omap3isp_video_format_info(fmt->code);
 884                 if (info->uncompressed == pixelcode)
 885                         fmt->code = pixelcode;
 886                 break;
 887         }
 888
 889         /* RGB, non-interlaced */
 890         fmt->colorspace = V4L2_COLORSPACE_SRGB;
 891         fmt->field = V4L2_FIELD_NONE;
 892 }
 893
 894 /*
 895  * csi2_enum_mbus_code - Handle pixel format enumeration
 896  * @sd     : pointer to v4l2 subdev structure
 897  * @cfg: V4L2 subdev pad configuration
 898  * @code   : pointer to v4l2_subdev_mbus_code_enum structure
 899  * return -EINVAL or zero on success
 900  */
 901 static int csi2_enum_mbus_code(struct v4l2_subdev *sd,
 902                                struct v4l2_subdev_state *sd_state,
 903                                struct v4l2_subdev_mbus_code_enum *code)
 904 {
 905         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 906         struct v4l2_mbus_framefmt *format;
 907         const struct isp_format_info *info;
 908
 909         if (code->pad == CSI2_PAD_SINK) {
 910                 if (code->index >= ARRAY_SIZE(csi2_input_fmts))
 911                         return -EINVAL;
 912
 913                 code->code = csi2_input_fmts[code->index];
 914         } else {
 915                 format = __csi2_get_format(csi2, sd_state, CSI2_PAD_SINK,
 916                                            code->which);
 917                 switch (code->index) {
 918                 case 0:
 919                         /* Passthrough sink pad code */
 920                         code->code = format->code;
 921                         break;
 922                 case 1:
 923                         /* Uncompressed code */
 924                         info = omap3isp_video_format_info(format->code);
 925                         if (info->uncompressed == format->code)
 926                                 return -EINVAL;
 927
 928                         code->code = info->uncompressed;
 929                         break;
 930                 default:
 931                         return -EINVAL;
 932                 }
 933         }
 934
 935         return 0;
 936 }
 937
 938 static int csi2_enum_frame_size(struct v4l2_subdev *sd,
 939                                 struct v4l2_subdev_state *sd_state,
 940                                 struct v4l2_subdev_frame_size_enum *fse)
 941 {
 942         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 943         struct v4l2_mbus_framefmt format;
 944
 945         if (fse->index != 0)
 946                 return -EINVAL;
 947
 948         format.code = fse->code;
 949         format.width = 1;
 950         format.height = 1;
 951         csi2_try_format(csi2, sd_state, fse->pad, &format, fse->which);
 952         fse->min_width = format.width;
 953         fse->min_height = format.height;
 954
 955         if (format.code != fse->code)
 956                 return -EINVAL;
 957
 958         format.code = fse->code;
 959         format.width = -1;
 960         format.height = -1;
 961         csi2_try_format(csi2, sd_state, fse->pad, &format, fse->which);
 962         fse->max_width = format.width;
 963         fse->max_height = format.height;
 964
 965         return 0;
 966 }
 967
 968 /*
 969  * csi2_get_format - Handle get format by pads subdev method
 970  * @sd : pointer to v4l2 subdev structure
 971  * @cfg: V4L2 subdev pad configuration
 972  * @fmt: pointer to v4l2 subdev format structure
 973  * return -EINVAL or zero on success
 974  */
 975 static int csi2_get_format(struct v4l2_subdev *sd,
 976                            struct v4l2_subdev_state *sd_state,
 977                            struct v4l2_subdev_format *fmt)
 978 {
 979         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
 980         struct v4l2_mbus_framefmt *format;
 981
 982         format = __csi2_get_format(csi2, sd_state, fmt->pad, fmt->which);
 983         if (format == NULL)
 984                 return -EINVAL;
 985
 986         fmt->format = *format;
 987         return 0;
 988 }
 989
 990 /*
 991  * csi2_set_format - Handle set format by pads subdev method
 992  * @sd : pointer to v4l2 subdev structure
 993  * @cfg: V4L2 subdev pad configuration
 994  * @fmt: pointer to v4l2 subdev format structure
 995  * return -EINVAL or zero on success
 996  */
 997 static int csi2_set_format(struct v4l2_subdev *sd,
 998                            struct v4l2_subdev_state *sd_state,
 999                            struct v4l2_subdev_format *fmt)
1000 {
1001         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1002         struct v4l2_mbus_framefmt *format;
1003
1004         format = __csi2_get_format(csi2, sd_state, fmt->pad, fmt->which);
1005         if (format == NULL)
1006                 return -EINVAL;
1007
1008         csi2_try_format(csi2, sd_state, fmt->pad, &fmt->format, fmt->which);
1009         *format = fmt->format;
1010
1011         /* Propagate the format from sink to source */
1012         if (fmt->pad == CSI2_PAD_SINK) {
1013                 format = __csi2_get_format(csi2, sd_state, CSI2_PAD_SOURCE,
1014                                            fmt->which);
1015                 *format = fmt->format;
1016                 csi2_try_format(csi2, sd_state, CSI2_PAD_SOURCE, format,
1017                                 fmt->which);
1018         }
1019
1020         return 0;
1021 }
1022
1023 /*
1024  * csi2_init_formats - Initialize formats on all pads
1025  * @sd: ISP CSI2 V4L2 subdevice
1026  * @fh: V4L2 subdev file handle
1027  *
1028  * Initialize all pad formats with default values. If fh is not NULL, try
1029  * formats are initialized on the file handle. Otherwise active formats are
1030  * initialized on the device.
1031  */
1032 static int csi2_init_formats(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
1033 {
1034         struct v4l2_subdev_format format;
1035
1036         memset(&format, 0, sizeof(format));
1037         format.pad = CSI2_PAD_SINK;
1038         format.which = fh ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
1039         format.format.code = MEDIA_BUS_FMT_SGRBG10_1X10;
1040         format.format.width = 4096;
1041         format.format.height = 4096;
1042         csi2_set_format(sd, fh ? fh->state : NULL, &format);
1043
1044         return 0;
1045 }
1046
1047 /*
1048  * csi2_set_stream - Enable/Disable streaming on the CSI2 module
1049  * @sd: ISP CSI2 V4L2 subdevice
1050  * @enable: ISP pipeline stream state
1051  *
1052  * Return 0 on success or a negative error code otherwise.
1053  */
1054 static int csi2_set_stream(struct v4l2_subdev *sd, int enable)
1055 {
1056         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1057         struct isp_device *isp = csi2->isp;
1058         struct isp_video *video_out = &csi2->video_out;
1059
1060         switch (enable) {
1061         case ISP_PIPELINE_STREAM_CONTINUOUS:
1062                 if (omap3isp_csiphy_acquire(csi2->phy, &sd->entity) < 0)
1063                         return -ENODEV;
1064                 if (csi2->output & CSI2_OUTPUT_MEMORY)
1065                         omap3isp_sbl_enable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1066                 csi2_configure(csi2);
1067                 csi2_print_status(csi2);
1068
1069                 /*
1070                  * When outputting to memory with no buffer available, let the
1071                  * buffer queue handler start the hardware. A DMA queue flag
1072                  * ISP_VIDEO_DMAQUEUE_QUEUED will be set as soon as there is
1073                  * a buffer available.
1074                  */
1075                 if (csi2->output & CSI2_OUTPUT_MEMORY &&
1076                     !(video_out->dmaqueue_flags & ISP_VIDEO_DMAQUEUE_QUEUED))
1077                         break;
1078                 /* Enable context 0 and IRQs */
1079                 atomic_set(&csi2->stopping, 0);
1080                 csi2_ctx_enable(isp, csi2, 0, 1);
1081                 csi2_if_enable(isp, csi2, 1);
1082                 isp_video_dmaqueue_flags_clr(video_out);
1083                 break;
1084
1085         case ISP_PIPELINE_STREAM_STOPPED:
1086                 if (csi2->state == ISP_PIPELINE_STREAM_STOPPED)
1087                         return 0;
1088                 if (omap3isp_module_sync_idle(&sd->entity, &csi2->wait,
1089                                               &csi2->stopping))
1090                         dev_dbg(isp->dev, "%s: module stop timeout.\n",
1091                                 sd->name);
1092                 csi2_ctx_enable(isp, csi2, 0, 0);
1093                 csi2_if_enable(isp, csi2, 0);
1094                 csi2_irq_ctx_set(isp, csi2, 0);
1095                 omap3isp_csiphy_release(csi2->phy);
1096                 isp_video_dmaqueue_flags_clr(video_out);
1097                 omap3isp_sbl_disable(isp, OMAP3_ISP_SBL_CSI2A_WRITE);
1098                 break;
1099         }
1100
1101         csi2->state = enable;
1102         return 0;
1103 }
1104
1105 /* subdev video operations */
1106 static const struct v4l2_subdev_video_ops csi2_video_ops = {
1107         .s_stream = csi2_set_stream,
1108 };
1109
1110 /* subdev pad operations */
1111 static const struct v4l2_subdev_pad_ops csi2_pad_ops = {
1112         .enum_mbus_code = csi2_enum_mbus_code,
1113         .enum_frame_size = csi2_enum_frame_size,
1114         .get_fmt = csi2_get_format,
1115         .set_fmt = csi2_set_format,
1116 };
1117
1118 /* subdev operations */
1119 static const struct v4l2_subdev_ops csi2_ops = {
1120         .video = &csi2_video_ops,
1121         .pad = &csi2_pad_ops,
1122 };
1123
1124 /* subdev internal operations */
1125 static const struct v4l2_subdev_internal_ops csi2_internal_ops = {
1126         .open = csi2_init_formats,
1127 };
1128
1129 /* -----------------------------------------------------------------------------
1130  * Media entity operations
1131  */
1132
1133 /*
1134  * csi2_link_setup - Setup CSI2 connections.
1135  * @entity : Pointer to media entity structure
1136  * @local  : Pointer to local pad array
1137  * @remote : Pointer to remote pad array
1138  * @flags  : Link flags
1139  * return -EINVAL or zero on success
1140  */
1141 static int csi2_link_setup(struct media_entity *entity,
1142                            const struct media_pad *local,
1143                            const struct media_pad *remote, u32 flags)
1144 {
1145         struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1146         struct isp_csi2_device *csi2 = v4l2_get_subdevdata(sd);
1147         struct isp_csi2_ctrl_cfg *ctrl = &csi2->ctrl;
1148         unsigned int index = local->index;
1149
1150         /*
1151          * The ISP core doesn't support pipelines with multiple video outputs.
1152          * Revisit this when it will be implemented, and return -EBUSY for now.
1153          */
1154
1155         /* FIXME: this is actually a hack! */
1156         if (is_media_entity_v4l2_subdev(remote->entity))
1157                 index |= 2 << 16;
1158
1159         switch (index) {
1160         case CSI2_PAD_SOURCE:
1161                 if (flags & MEDIA_LNK_FL_ENABLED) {
1162                         if (csi2->output & ~CSI2_OUTPUT_MEMORY)
1163                                 return -EBUSY;
1164                         csi2->output |= CSI2_OUTPUT_MEMORY;
1165                 } else {
1166                         csi2->output &= ~CSI2_OUTPUT_MEMORY;
1167                 }
1168                 break;
1169
1170         case CSI2_PAD_SOURCE | 2 << 16:
1171                 if (flags & MEDIA_LNK_FL_ENABLED) {
1172                         if (csi2->output & ~CSI2_OUTPUT_CCDC)
1173                                 return -EBUSY;
1174                         csi2->output |= CSI2_OUTPUT_CCDC;
1175                 } else {
1176                         csi2->output &= ~CSI2_OUTPUT_CCDC;
1177                 }
1178                 break;
1179
1180         default:
1181                 /* Link from camera to CSI2 is fixed... */
1182                 return -EINVAL;
1183         }
1184
1185         ctrl->vp_only_enable =
1186                 (csi2->output & CSI2_OUTPUT_MEMORY) ? false : true;
1187         ctrl->vp_clk_enable = !!(csi2->output & CSI2_OUTPUT_CCDC);
1188
1189         return 0;
1190 }
1191
1192 /* media operations */
1193 static const struct media_entity_operations csi2_media_ops = {
1194         .link_setup = csi2_link_setup,
1195         .link_validate = v4l2_subdev_link_validate,
1196 };
1197
1198 void omap3isp_csi2_unregister_entities(struct isp_csi2_device *csi2)
1199 {
1200         v4l2_device_unregister_subdev(&csi2->subdev);
1201         omap3isp_video_unregister(&csi2->video_out);
1202 }
1203
1204 int omap3isp_csi2_register_entities(struct isp_csi2_device *csi2,
1205                                     struct v4l2_device *vdev)
1206 {
1207         int ret;
1208
1209         /* Register the subdev and video nodes. */
1210         csi2->subdev.dev = vdev->mdev->dev;
1211         ret = v4l2_device_register_subdev(vdev, &csi2->subdev);
1212         if (ret < 0)
1213                 goto error;
1214
1215         ret = omap3isp_video_register(&csi2->video_out, vdev);
1216         if (ret < 0)
1217                 goto error;
1218
1219         return 0;
1220
1221 error:
1222         omap3isp_csi2_unregister_entities(csi2);
1223         return ret;
1224 }
1225
1226 /* -----------------------------------------------------------------------------
1227  * ISP CSI2 initialisation and cleanup
1228  */
1229
1230 /*
1231  * csi2_init_entities - Initialize subdev and media entity.
1232  * @csi2: Pointer to csi2 structure.
1233  * return -ENOMEM or zero on success
1234  */
1235 static int csi2_init_entities(struct isp_csi2_device *csi2)
1236 {
1237         struct v4l2_subdev *sd = &csi2->subdev;
1238         struct media_pad *pads = csi2->pads;
1239         struct media_entity *me = &sd->entity;
1240         int ret;
1241
1242         v4l2_subdev_init(sd, &csi2_ops);
1243         sd->internal_ops = &csi2_internal_ops;
1244         strscpy(sd->name, "OMAP3 ISP CSI2a", sizeof(sd->name));
1245
1246         sd->grp_id = 1 << 16;   /* group ID for isp subdevs */
1247         v4l2_set_subdevdata(sd, csi2);
1248         sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1249
1250         pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1251         pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1252                                     | MEDIA_PAD_FL_MUST_CONNECT;
1253
1254         me->ops = &csi2_media_ops;
1255         ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads);
1256         if (ret < 0)
1257                 return ret;
1258
1259         csi2_init_formats(sd, NULL);
1260
1261         /* Video device node */
1262         csi2->video_out.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1263         csi2->video_out.ops = &csi2_ispvideo_ops;
1264         csi2->video_out.bpl_alignment = 32;
1265         csi2->video_out.bpl_zero_padding = 1;
1266         csi2->video_out.bpl_max = 0x1ffe0;
1267         csi2->video_out.isp = csi2->isp;
1268         csi2->video_out.capture_mem = PAGE_ALIGN(4096 * 4096) * 3;
1269
1270         ret = omap3isp_video_init(&csi2->video_out, "CSI2a");
1271         if (ret < 0)
1272                 goto error_video;
1273
1274         return 0;
1275
1276 error_video:
1277         media_entity_cleanup(&csi2->subdev.entity);
1278         return ret;
1279 }
1280
1281 /*
1282  * omap3isp_csi2_init - Routine for module driver init
1283  */
1284 int omap3isp_csi2_init(struct isp_device *isp)
1285 {
1286         struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1287         struct isp_csi2_device *csi2c = &isp->isp_csi2c;
1288         int ret;
1289
1290         csi2a->isp = isp;
1291         csi2a->available = 1;
1292         csi2a->regs1 = OMAP3_ISP_IOMEM_CSI2A_REGS1;
1293         csi2a->regs2 = OMAP3_ISP_IOMEM_CSI2A_REGS2;
1294         csi2a->phy = &isp->isp_csiphy2;
1295         csi2a->state = ISP_PIPELINE_STREAM_STOPPED;
1296         init_waitqueue_head(&csi2a->wait);
1297
1298         ret = csi2_init_entities(csi2a);
1299         if (ret < 0)
1300                 return ret;
1301
1302         if (isp->revision == ISP_REVISION_15_0) {
1303                 csi2c->isp = isp;
1304                 csi2c->available = 1;
1305                 csi2c->regs1 = OMAP3_ISP_IOMEM_CSI2C_REGS1;
1306                 csi2c->regs2 = OMAP3_ISP_IOMEM_CSI2C_REGS2;
1307                 csi2c->phy = &isp->isp_csiphy1;
1308                 csi2c->state = ISP_PIPELINE_STREAM_STOPPED;
1309                 init_waitqueue_head(&csi2c->wait);
1310         }
1311
1312         return 0;
1313 }
1314
1315 /*
1316  * omap3isp_csi2_cleanup - Routine for module driver cleanup
1317  */
1318 void omap3isp_csi2_cleanup(struct isp_device *isp)
1319 {
1320         struct isp_csi2_device *csi2a = &isp->isp_csi2a;
1321
1322         omap3isp_video_cleanup(&csi2a->video_out);
1323         media_entity_cleanup(&csi2a->subdev.entity);
1324 }