1 /* SPDX-License-Identifier: GPL-2.0 */
3 * c8sectpfe-core.h - C8SECTPFE STi DVB driver
5 * Copyright (c) STMicroelectronics 2015
7 * Author:Peter Bennett <peter.bennett@st.com>
8 * Peter Griffin <peter.griffin@linaro.org>
11 #ifndef _C8SECTPFE_CORE_H_
12 #define _C8SECTPFE_CORE_H_
14 #define C8SECTPFEI_MAXCHANNEL 16
15 #define C8SECTPFEI_MAXADAPTER 3
17 #define C8SECTPFE_MAX_TSIN_CHAN 8
25 bool serial_not_parallel;
30 struct gpio_desc *rst_gpio;
32 struct i2c_adapter *i2c_adapter;
33 struct i2c_adapter *tuner_i2c;
34 struct i2c_adapter *lnb_i2c;
35 struct i2c_client *i2c_client;
36 struct dvb_frontend *frontend;
38 struct pinctrl_state *pstate;
43 void *back_buffer_start;
44 void *back_buffer_aligned;
45 dma_addr_t back_buffer_busaddr;
47 void *pid_buffer_start;
48 void *pid_buffer_aligned;
49 dma_addr_t pid_buffer_busaddr;
53 struct completion idle_completion;
54 struct tasklet_struct tsklet;
56 struct c8sectpfei *fei;
74 struct pinctrl *pinctrl;
77 struct debugfs_regset32 *regset;
78 struct completion fw_ack;
83 struct c8sectpfe_hw hw_stats;
85 struct c8sectpfe *c8sectpfe[C8SECTPFEI_MAXADAPTER];
87 int mapping[C8SECTPFEI_MAXCHANNEL];
91 struct timer_list timer; /* timer interrupts for outputs */
96 unsigned long sram_size;
98 struct channel_info *channel_data[C8SECTPFE_MAX_TSIN_CHAN];
100 struct clk *c8sectpfeclk;
107 int global_feed_count;
110 /* C8SECTPFE SYS Regs list */
112 #define SYS_INPUT_ERR_STATUS 0x0
113 #define SYS_OTHER_ERR_STATUS 0x8
114 #define SYS_INPUT_ERR_MASK 0x10
115 #define SYS_OTHER_ERR_MASK 0x18
116 #define SYS_DMA_ROUTE 0x20
117 #define SYS_INPUT_CLKEN 0x30
118 #define IBENABLE_MASK 0x7F
120 #define SYS_OTHER_CLKEN 0x38
121 #define TSDMAENABLE BIT(1)
122 #define MEMDMAENABLE BIT(0)
124 #define SYS_CFG_NUM_IB 0x200
125 #define SYS_CFG_NUM_MIB 0x204
126 #define SYS_CFG_NUM_SWTS 0x208
127 #define SYS_CFG_NUM_TSOUT 0x20C
128 #define SYS_CFG_NUM_CCSC 0x210
129 #define SYS_CFG_NUM_RAM 0x214
130 #define SYS_CFG_NUM_TP 0x218
132 /* Input Block Regs */
134 #define C8SECTPFE_INPUTBLK_OFFSET 0x1000
135 #define C8SECTPFE_CHANNEL_OFFSET(x) ((x*0x40) + C8SECTPFE_INPUTBLK_OFFSET)
137 #define C8SECTPFE_IB_IP_FMT_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x00)
138 #define C8SECTPFE_IGNORE_ERR_AT_SOP BIT(7)
139 #define C8SECTPFE_IGNORE_ERR_IN_PKT BIT(6)
140 #define C8SECTPFE_IGNORE_ERR_IN_BYTE BIT(5)
141 #define C8SECTPFE_INVERT_TSCLK BIT(4)
142 #define C8SECTPFE_ALIGN_BYTE_SOP BIT(3)
143 #define C8SECTPFE_ASYNC_NOT_SYNC BIT(2)
144 #define C8SECTPFE_BYTE_ENDIANNESS_MSB BIT(1)
145 #define C8SECTPFE_SERIAL_NOT_PARALLEL BIT(0)
147 #define C8SECTPFE_IB_SYNCLCKDRP_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x04)
148 #define C8SECTPFE_SYNC(x) (x & 0xf)
149 #define C8SECTPFE_DROP(x) ((x<<4) & 0xf)
150 #define C8SECTPFE_TOKEN(x) ((x<<8) & 0xff00)
151 #define C8SECTPFE_SLDENDIANNESS BIT(16)
153 #define C8SECTPFE_IB_TAGBYTES_CFG(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x08)
154 #define C8SECTPFE_TAG_HEADER(x) (x << 16)
155 #define C8SECTPFE_TAG_COUNTER(x) ((x<<1) & 0x7fff)
156 #define C8SECTPFE_TAG_ENABLE BIT(0)
158 #define C8SECTPFE_IB_PID_SET(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x0C)
159 #define C8SECTPFE_PID_OFFSET(x) (x & 0x3f)
160 #define C8SECTPFE_PID_NUMBITS(x) ((x << 6) & 0xfff)
161 #define C8SECTPFE_PID_ENABLE BIT(31)
163 #define C8SECTPFE_IB_PKT_LEN(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x10)
165 #define C8SECTPFE_IB_BUFF_STRT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x14)
166 #define C8SECTPFE_IB_BUFF_END(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x18)
167 #define C8SECTPFE_IB_READ_PNT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x1C)
168 #define C8SECTPFE_IB_WRT_PNT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x20)
170 #define C8SECTPFE_IB_PRI_THRLD(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x24)
171 #define C8SECTPFE_PRI_VALUE(x) (x & 0x7fffff)
172 #define C8SECTPFE_PRI_LOWPRI(x) ((x & 0xf) << 24)
173 #define C8SECTPFE_PRI_HIGHPRI(x) ((x & 0xf) << 28)
175 #define C8SECTPFE_IB_STAT(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x28)
176 #define C8SECTPFE_STAT_FIFO_OVERFLOW(x) (x & 0x1)
177 #define C8SECTPFE_STAT_BUFFER_OVERFLOW(x) (x & 0x2)
178 #define C8SECTPFE_STAT_OUTOFORDERRP(x) (x & 0x4)
179 #define C8SECTPFE_STAT_PID_OVERFLOW(x) (x & 0x8)
180 #define C8SECTPFE_STAT_PKT_OVERFLOW(x) (x & 0x10)
181 #define C8SECTPFE_STAT_ERROR_PACKETS(x) ((x >> 8) & 0xf)
182 #define C8SECTPFE_STAT_SHORT_PACKETS(x) ((x >> 12) & 0xf)
184 #define C8SECTPFE_IB_MASK(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x2C)
185 #define C8SECTPFE_MASK_FIFO_OVERFLOW BIT(0)
186 #define C8SECTPFE_MASK_BUFFER_OVERFLOW BIT(1)
187 #define C8SECTPFE_MASK_OUTOFORDERRP(x) BIT(2)
188 #define C8SECTPFE_MASK_PID_OVERFLOW(x) BIT(3)
189 #define C8SECTPFE_MASK_PKT_OVERFLOW(x) BIT(4)
190 #define C8SECTPFE_MASK_ERROR_PACKETS(x) ((x & 0xf) << 8)
191 #define C8SECTPFE_MASK_SHORT_PACKETS(x) ((x & 0xf) >> 12)
193 #define C8SECTPFE_IB_SYS(x) (C8SECTPFE_CHANNEL_OFFSET(x) + 0x30)
194 #define C8SECTPFE_SYS_RESET BIT(1)
195 #define C8SECTPFE_SYS_ENABLE BIT(0)
198 * Pointer record data structure required for each input block
199 * see Table 82 on page 167 of functional specification.
202 #define DMA_PRDS_MEMBASE 0x0 /* Internal sram base address */
203 #define DMA_PRDS_MEMTOP 0x4 /* Internal sram top address */
206 * TS packet size, including tag bytes added by input block,
207 * rounded up to the next multiple of 8 bytes. The packet size,
208 * including any tagging bytes and rounded up to the nearest
209 * multiple of 8 bytes must be less than 255 bytes.
211 #define DMA_PRDS_PKTSIZE 0x8
212 #define DMA_PRDS_TPENABLE 0xc
214 #define TP0_OFFSET 0x10
215 #define DMA_PRDS_BUSBASE_TP(x) ((0x10*x) + TP0_OFFSET)
216 #define DMA_PRDS_BUSTOP_TP(x) ((0x10*x) + TP0_OFFSET + 0x4)
217 #define DMA_PRDS_BUSWP_TP(x) ((0x10*x) + TP0_OFFSET + 0x8)
218 #define DMA_PRDS_BUSRP_TP(x) ((0x10*x) + TP0_OFFSET + 0xc)
220 #define DMA_PRDS_SIZE (0x20)
222 #define DMA_MEMDMA_OFFSET 0x4000
223 #define DMA_IMEM_OFFSET 0x0
224 #define DMA_DMEM_OFFSET 0x4000
225 #define DMA_CPU 0x8000
226 #define DMA_PER_OFFSET 0xb000
228 #define DMA_MEMDMA_DMEM (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET)
229 #define DMA_MEMDMA_IMEM (DMA_MEMDMA_OFFSET + DMA_IMEM_OFFSET)
231 /* XP70 Slim core regs */
232 #define DMA_CPU_ID (DMA_MEMDMA_OFFSET + DMA_CPU + 0x0)
233 #define DMA_CPU_VCR (DMA_MEMDMA_OFFSET + DMA_CPU + 0x4)
234 #define DMA_CPU_RUN (DMA_MEMDMA_OFFSET + DMA_CPU + 0x8)
235 #define DMA_CPU_CLOCKGATE (DMA_MEMDMA_OFFSET + DMA_CPU + 0xc)
236 #define DMA_CPU_PC (DMA_MEMDMA_OFFSET + DMA_CPU + 0x20)
238 /* Enable Interrupt for a IB */
239 #define DMA_PER_TPn_DREQ_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd00)
240 /* Ack interrupt by setting corresponding bit */
241 #define DMA_PER_TPn_DACK_SET (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xd80)
242 #define DMA_PER_TPn_DREQ (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe00)
243 #define DMA_PER_TPn_DACK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xe80)
244 #define DMA_PER_DREQ_MODE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf80)
245 #define DMA_PER_STBUS_SYNC (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf88)
246 #define DMA_PER_STBUS_ACCESS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf8c)
247 #define DMA_PER_STBUS_ADDRESS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xf90)
248 #define DMA_PER_IDLE_INT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfa8)
249 #define DMA_PER_PRIORITY (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfac)
250 #define DMA_PER_MAX_OPCODE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb0)
251 #define DMA_PER_MAX_CHUNK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfb4)
252 #define DMA_PER_PAGE_SIZE (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfbc)
253 #define DMA_PER_MBOX_STATUS (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc0)
254 #define DMA_PER_MBOX_SET (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfc8)
255 #define DMA_PER_MBOX_CLEAR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd0)
256 #define DMA_PER_MBOX_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfd8)
257 #define DMA_PER_INJECT_PKT_SRC (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe0)
258 #define DMA_PER_INJECT_PKT_DEST (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe4)
259 #define DMA_PER_INJECT_PKT_ADDR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfe8)
260 #define DMA_PER_INJECT_PKT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xfec)
261 #define DMA_PER_PAT_PTR_INIT (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff0)
262 #define DMA_PER_PAT_PTR (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff4)
263 #define DMA_PER_SLEEP_MASK (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xff8)
264 #define DMA_PER_SLEEP_COUNTER (DMA_MEMDMA_OFFSET + DMA_PER_OFFSET + 0xffc)
265 /* #define DMA_RF_CPUREGn DMA_RFBASEADDR n=0 to 15) slim regsa */
267 /* The following are from DMA_DMEM_BaseAddress */
268 #define DMA_FIRMWARE_VERSION (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x0)
269 #define DMA_PTRREC_BASE (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x4)
270 #define DMA_PTRREC_INPUT_OFFSET (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x8)
271 #define DMA_ERRREC_BASE (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0xc)
272 #define DMA_ERROR_RECORD(n) ((n*4) + DMA_ERRREC_BASE + 0x4)
273 #define DMA_IDLE_REQ (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x10)
274 #define IDLEREQ BIT(31)
276 #define DMA_FIRMWARE_CONFIG (DMA_MEMDMA_OFFSET + DMA_DMEM_OFFSET + 0x14)
278 /* Regs for PID Filter */
280 #define PIDF_OFFSET 0x2800
281 #define PIDF_BASE(n) ((n*4) + PIDF_OFFSET)
282 #define PIDF_LEAK_ENABLE (PIDF_OFFSET + 0x100)
283 #define PIDF_LEAK_STATUS (PIDF_OFFSET + 0x108)
284 #define PIDF_LEAK_COUNT_RESET (PIDF_OFFSET + 0x110)
285 #define PIDF_LEAK_COUNTER (PIDF_OFFSET + 0x114)
287 #endif /* _C8SECTPFE_CORE_H_ */