drivers/media/platform/qcom/venus/hfi_venus_io.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2017 Linaro Ltd.
   5  */
   6 #ifndef __VENUS_HFI_VENUS_IO_H__
   7 #define __VENUS_HFI_VENUS_IO_H__
   8
   9 #define VBIF_BASE                               0x80000
  10
  11 #define VBIF_AXI_HALT_CTRL0                     (VBIF_BASE + 0x208)
  12 #define VBIF_AXI_HALT_CTRL1                     (VBIF_BASE + 0x20c)
  13
  14 #define VBIF_AXI_HALT_CTRL0_HALT_REQ            BIT(0)
  15 #define VBIF_AXI_HALT_CTRL1_HALT_ACK            BIT(0)
  16 #define VBIF_AXI_HALT_ACK_TIMEOUT_US            500000
  17
  18 #define CPU_BASE                                0xc0000
  19 #define CPU_CS_BASE                             (CPU_BASE + 0x12000)
  20 #define CPU_IC_BASE                             (CPU_BASE + 0x1f000)
  21
  22 #define CPU_CS_A2HSOFTINTCLR                    (CPU_CS_BASE + 0x1c)
  23
  24 #define VIDC_CTRL_INIT                          (CPU_CS_BASE + 0x48)
  25 #define VIDC_CTRL_INIT_RESERVED_BITS31_1_MASK   0xfffffffe
  26 #define VIDC_CTRL_INIT_RESERVED_BITS31_1_SHIFT  1
  27 #define VIDC_CTRL_INIT_CTRL_MASK                0x1
  28 #define VIDC_CTRL_INIT_CTRL_SHIFT               0
  29
  30 /* HFI control status */
  31 #define CPU_CS_SCIACMDARG0                      (CPU_CS_BASE + 0x4c)
  32 #define CPU_CS_SCIACMDARG0_MASK                 0xff
  33 #define CPU_CS_SCIACMDARG0_SHIFT                0x0
  34 #define CPU_CS_SCIACMDARG0_ERROR_STATUS_MASK    0xfe
  35 #define CPU_CS_SCIACMDARG0_ERROR_STATUS_SHIFT   0x1
  36 #define CPU_CS_SCIACMDARG0_INIT_STATUS_MASK     0x1
  37 #define CPU_CS_SCIACMDARG0_INIT_STATUS_SHIFT    0x0
  38 #define CPU_CS_SCIACMDARG0_PC_READY             BIT(8)
  39 #define CPU_CS_SCIACMDARG0_INIT_IDLE_MSG_MASK   BIT(30)
  40
  41 /* HFI queue table info */
  42 #define CPU_CS_SCIACMDARG1                      (CPU_CS_BASE + 0x50)
  43
  44 /* HFI queue table address */
  45 #define CPU_CS_SCIACMDARG2                      (CPU_CS_BASE + 0x54)
  46
  47 /* Venus cpu */
  48 #define CPU_CS_SCIACMDARG3                      (CPU_CS_BASE + 0x58)
  49
  50 #define SFR_ADDR                                (CPU_CS_BASE + 0x5c)
  51 #define MMAP_ADDR                               (CPU_CS_BASE + 0x60)
  52 #define UC_REGION_ADDR                          (CPU_CS_BASE + 0x64)
  53 #define UC_REGION_SIZE                          (CPU_CS_BASE + 0x68)
  54
  55 #define CPU_IC_SOFTINT                          (CPU_IC_BASE + 0x18)
  56 #define CPU_IC_SOFTINT_H2A_MASK                 0x8000
  57 #define CPU_IC_SOFTINT_H2A_SHIFT                0xf
  58
  59 /* Venus wrapper */
  60 #define WRAPPER_BASE                            0x000e0000
  61
  62 #define WRAPPER_HW_VERSION                      (WRAPPER_BASE + 0x00)
  63 #define WRAPPER_HW_VERSION_MAJOR_VERSION_MASK   0x78000000
  64 #define WRAPPER_HW_VERSION_MAJOR_VERSION_SHIFT  28
  65 #define WRAPPER_HW_VERSION_MINOR_VERSION_MASK   0xfff0000
  66 #define WRAPPER_HW_VERSION_MINOR_VERSION_SHIFT  16
  67 #define WRAPPER_HW_VERSION_STEP_VERSION_MASK    0xffff
  68
  69 #define WRAPPER_CLOCK_CONFIG                    (WRAPPER_BASE + 0x04)
  70
  71 #define WRAPPER_INTR_STATUS                     (WRAPPER_BASE + 0x0c)
  72 #define WRAPPER_INTR_STATUS_A2HWD_MASK          0x10
  73 #define WRAPPER_INTR_STATUS_A2HWD_SHIFT         0x4
  74 #define WRAPPER_INTR_STATUS_A2H_MASK            0x4
  75 #define WRAPPER_INTR_STATUS_A2H_SHIFT           0x2
  76
  77 #define WRAPPER_INTR_MASK                       (WRAPPER_BASE + 0x10)
  78 #define WRAPPER_INTR_MASK_A2HWD_BASK            0x10
  79 #define WRAPPER_INTR_MASK_A2HWD_SHIFT           0x4
  80 #define WRAPPER_INTR_MASK_A2HVCODEC_MASK        0x8
  81 #define WRAPPER_INTR_MASK_A2HVCODEC_SHIFT       0x3
  82 #define WRAPPER_INTR_MASK_A2HCPU_MASK           0x4
  83 #define WRAPPER_INTR_MASK_A2HCPU_SHIFT          0x2
  84
  85 #define WRAPPER_INTR_CLEAR                      (WRAPPER_BASE + 0x14)
  86 #define WRAPPER_INTR_CLEAR_A2HWD_MASK           0x10
  87 #define WRAPPER_INTR_CLEAR_A2HWD_SHIFT          0x4
  88 #define WRAPPER_INTR_CLEAR_A2H_MASK             0x4
  89 #define WRAPPER_INTR_CLEAR_A2H_SHIFT            0x2
  90
  91 #define WRAPPER_POWER_STATUS                    (WRAPPER_BASE + 0x44)
  92 #define WRAPPER_VDEC_VCODEC_POWER_CONTROL       (WRAPPER_BASE + 0x48)
  93 #define WRAPPER_VENC_VCODEC_POWER_CONTROL       (WRAPPER_BASE + 0x4c)
  94 #define WRAPPER_VDEC_VENC_AHB_BRIDGE_SYNC_RESET (WRAPPER_BASE + 0x64)
  95
  96 #define WRAPPER_CPU_CLOCK_CONFIG                (WRAPPER_BASE + 0x2000)
  97 #define WRAPPER_CPU_AXI_HALT                    (WRAPPER_BASE + 0x2008)
  98 #define WRAPPER_CPU_AXI_HALT_HALT               BIT(16)
  99 #define WRAPPER_CPU_AXI_HALT_STATUS             (WRAPPER_BASE + 0x200c)
 100 #define WRAPPER_CPU_AXI_HALT_STATUS_IDLE        BIT(24)
 101
 102 #define WRAPPER_CPU_CGC_DIS                     (WRAPPER_BASE + 0x2010)
 103 #define WRAPPER_CPU_STATUS                      (WRAPPER_BASE + 0x2014)
 104 #define WRAPPER_CPU_STATUS_WFI                  BIT(0)
 105 #define WRAPPER_SW_RESET                        (WRAPPER_BASE + 0x3000)
 106 #define WRAPPER_CPA_START_ADDR                  (WRAPPER_BASE + 0x1020)
 107 #define WRAPPER_CPA_END_ADDR                    (WRAPPER_BASE + 0x1024)
 108 #define WRAPPER_FW_START_ADDR                   (WRAPPER_BASE + 0x1028)
 109 #define WRAPPER_FW_END_ADDR                     (WRAPPER_BASE + 0x102C)
 110 #define WRAPPER_NONPIX_START_ADDR               (WRAPPER_BASE + 0x1030)
 111 #define WRAPPER_NONPIX_END_ADDR                 (WRAPPER_BASE + 0x1034)
 112 #define WRAPPER_A9SS_SW_RESET                   (WRAPPER_BASE + 0x3000)
 113 #define WRAPPER_A9SS_SW_RESET_BIT               BIT(4)
 114
 115 /* Venus 4xx */
 116 #define WRAPPER_VCODEC0_MMCC_POWER_STATUS       (WRAPPER_BASE + 0x90)
 117 #define WRAPPER_VCODEC0_MMCC_POWER_CONTROL      (WRAPPER_BASE + 0x94)
 118
 119 #define WRAPPER_VCODEC1_MMCC_POWER_STATUS       (WRAPPER_BASE + 0x110)
 120 #define WRAPPER_VCODEC1_MMCC_POWER_CONTROL      (WRAPPER_BASE + 0x114)
 121
 122 #endif