drivers/media/platform/mediatek/vcodec/decoder/vdec/vdec_hevc_req_multi_if.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2023 MediaTek Inc.
   4  * Author: Yunfei Dong <yunfei.dong@mediatek.com>
   5  */
   6
   7 #include <linux/module.h>
   8 #include <linux/slab.h>
   9 #include <media/videobuf2-dma-contig.h>
  10
  11 #include "../mtk_vcodec_dec.h"
  12 #include "../../common/mtk_vcodec_intr.h"
  13 #include "../vdec_drv_base.h"
  14 #include "../vdec_drv_if.h"
  15 #include "../vdec_vpu_if.h"
  16
  17 /* the size used to store hevc wrap information */
  18 #define VDEC_HEVC_WRAP_SZ (532 * SZ_1K)
  19
  20 #define HEVC_MAX_MV_NUM 32
  21
  22 /* get used parameters for sps/pps */
  23 #define GET_HEVC_VDEC_FLAG(cond, flag) \
  24         { dst_param->cond = ((src_param->flags & (flag)) ? (1) : (0)); }
  25 #define GET_HEVC_VDEC_PARAM(param) \
  26         { dst_param->param = src_param->param; }
  27
  28 /**
  29  * enum vdec_hevc_core_dec_err_type  - core decode error type
  30  *
  31  * @TRANS_BUFFER_FULL: trans buffer is full
  32  * @SLICE_HEADER_FULL: slice header buffer is full
  33  */
  34 enum vdec_hevc_core_dec_err_type {
  35         TRANS_BUFFER_FULL = 1,
  36         SLICE_HEADER_FULL,
  37 };
  38
  39 /**
  40  * struct mtk_hevc_dpb_info  - hevc dpb information
  41  *
  42  * @y_dma_addr:     Y plane physical address
  43  * @c_dma_addr:     CbCr plane physical address
  44  * @reference_flag: reference picture flag (short/long term reference picture)
  45  * @field:          field picture flag
  46  */
  47 struct mtk_hevc_dpb_info {
  48         dma_addr_t y_dma_addr;
  49         dma_addr_t c_dma_addr;
  50         int reference_flag;
  51         int field;
  52 };
  53
  54 /*
  55  * struct mtk_hevc_sps_param  - parameters for sps
  56  */
  57 struct mtk_hevc_sps_param {
  58         unsigned char video_parameter_set_id;
  59         unsigned char seq_parameter_set_id;
  60         unsigned short pic_width_in_luma_samples;
  61         unsigned short pic_height_in_luma_samples;
  62         unsigned char bit_depth_luma_minus8;
  63         unsigned char bit_depth_chroma_minus8;
  64         unsigned char log2_max_pic_order_cnt_lsb_minus4;
  65         unsigned char sps_max_dec_pic_buffering_minus1;
  66         unsigned char sps_max_num_reorder_pics;
  67         unsigned char sps_max_latency_increase_plus1;
  68         unsigned char log2_min_luma_coding_block_size_minus3;
  69         unsigned char log2_diff_max_min_luma_coding_block_size;
  70         unsigned char log2_min_luma_transform_block_size_minus2;
  71         unsigned char log2_diff_max_min_luma_transform_block_size;
  72         unsigned char max_transform_hierarchy_depth_inter;
  73         unsigned char max_transform_hierarchy_depth_intra;
  74         unsigned char pcm_sample_bit_depth_luma_minus1;
  75         unsigned char pcm_sample_bit_depth_chroma_minus1;
  76         unsigned char log2_min_pcm_luma_coding_block_size_minus3;
  77         unsigned char log2_diff_max_min_pcm_luma_coding_block_size;
  78         unsigned char num_short_term_ref_pic_sets;
  79         unsigned char num_long_term_ref_pics_sps;
  80         unsigned char chroma_format_idc;
  81         unsigned char sps_max_sub_layers_minus1;
  82         unsigned char separate_colour_plane;
  83         unsigned char scaling_list_enabled;
  84         unsigned char amp_enabled;
  85         unsigned char sample_adaptive_offset;
  86         unsigned char pcm_enabled;
  87         unsigned char pcm_loop_filter_disabled;
  88         unsigned char long_term_ref_pics_enabled;
  89         unsigned char sps_temporal_mvp_enabled;
  90         unsigned char strong_intra_smoothing_enabled;
  91         unsigned char reserved[5];
  92 };
  93
  94 /*
  95  * struct mtk_hevc_pps_param  - parameters for pps
  96  */
  97 struct mtk_hevc_pps_param {
  98         unsigned char pic_parameter_set_id;
  99         unsigned char num_extra_slice_header_bits;
 100         unsigned char num_ref_idx_l0_default_active_minus1;
 101         unsigned char num_ref_idx_l1_default_active_minus1;
 102         char init_qp_minus26;
 103         unsigned char diff_cu_qp_delta_depth;
 104         char pps_cb_qp_offset;
 105         char pps_cr_qp_offset;
 106         unsigned char num_tile_columns_minus1;
 107         unsigned char num_tile_rows_minus1;
 108         unsigned char column_width_minus1[20];
 109         unsigned char row_height_minus1[22];
 110         char pps_beta_offset_div2;
 111         char pps_tc_offset_div2;
 112         unsigned char log2_parallel_merge_level_minus2;
 113         char dependent_slice_segment_enabled;
 114         char output_flag_present;
 115         char sign_data_hiding_enabled;
 116         char cabac_init_present;
 117         char constrained_intra_pred;
 118         char transform_skip_enabled;
 119         char cu_qp_delta_enabled;
 120         char pps_slice_chroma_qp_offsets_present;
 121         char weighted_pred;
 122         char weighted_bipred;
 123         char transquant_bypass_enabled;
 124         char pps_flag_tiles_enabled;
 125         char entropy_coding_sync_enabled;
 126         char loop_filter_across_tiles_enabled;
 127         char pps_loop_filter_across_slices_enabled;
 128         char deblocking_filter_override_enabled;
 129         char pps_disable_deflocking_filter;
 130         char lists_modification_present;
 131         char slice_segment_header_extersion_present;
 132         char deblocking_filter_control_present;
 133         char uniform_spacing;
 134         char reserved[6];
 135 };
 136
 137 /*
 138  * struct mtk_hevc_slice_header_param  - parameters for slice header
 139  */
 140 struct mtk_hevc_slice_header_param {
 141         unsigned int    slice_type;
 142         unsigned int    num_active_ref_layer_pics;
 143         int             slice_qp;
 144         int             slice_qp_delta_cb;
 145         int             slice_qp_delta_cr;
 146         int             num_ref_idx[3];
 147         unsigned int    col_ref_idx;
 148         unsigned int    five_minus_max_num_merge_cand;
 149         int             slice_deblocking_filter_beta_offset_div2;
 150         int             slice_deblocking_filter_tc_offset_div2;
 151         unsigned char   sao_enable_flag;
 152         unsigned char   sao_enable_flag_chroma;
 153         unsigned char   cabac_init_flag;
 154         unsigned char   slice_tmvp_flags_present;
 155         unsigned char   col_from_l0_flag;
 156         unsigned char   mvd_l1_zero_flag;
 157         unsigned char   slice_loop_filter_across_slices_enabled_flag;
 158         unsigned char   deblocking_filter_disable_flag;
 159         unsigned int    slice_reg0;
 160         unsigned int    slice_reg1;
 161         unsigned int    slice_reg2;
 162         unsigned int    num_rps_curr_temp_list;
 163         unsigned int    ref_list_mode;
 164         int             str_num_delta_pocs;
 165         int             str_num_negtive_pos_pics;
 166         int             num_long_term;
 167         int             num_long_term_sps;
 168         unsigned int    max_cu_width;
 169         unsigned int    max_cu_height;
 170         unsigned int    num_entry_point_offsets;
 171         unsigned int    last_lcu_x_in_tile[17];
 172         unsigned int    last_lcu_y_in_tile[17];
 173         unsigned char   nal_unit_type;
 174 };
 175
 176 /*
 177  * struct slice_api_hevc_scaling_matrix  - parameters for scaling list
 178  */
 179 struct slice_api_hevc_scaling_matrix {
 180         unsigned char scaling_list_4x4[6][16];
 181         unsigned char scaling_list_8x8[6][64];
 182         unsigned char scaling_list_16x16[6][64];
 183         unsigned char scaling_list_32x32[2][64];
 184         unsigned char scaling_list_dc_coef_16x16[6];
 185         unsigned char scaling_list_dc_coef_32x32[2];
 186 };
 187
 188 /*
 189  * struct slice_hevc_dpb_entry  - each dpb information
 190  */
 191 struct slice_hevc_dpb_entry {
 192         u64 timestamp;
 193         unsigned char flags;
 194         unsigned char field_pic;
 195         int pic_order_cnt_val;
 196 };
 197
 198 /*
 199  * struct slice_api_hevc_decode_param - parameters for decode.
 200  */
 201 struct slice_api_hevc_decode_param {
 202         struct slice_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 203         int pic_order_cnt_val;
 204         unsigned short short_term_ref_pic_set_size;
 205         unsigned short long_term_ref_pic_set_size;
 206         unsigned char num_active_dpb_entries;
 207         unsigned char num_poc_st_curr_before;
 208         unsigned char num_poc_st_curr_after;
 209         unsigned char num_poc_lt_curr;
 210         unsigned char poc_st_curr_before[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 211         unsigned char poc_st_curr_after[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 212         unsigned char poc_lt_curr[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 213         unsigned char num_delta_pocs_of_ref_rps_idx;
 214         int flags;
 215 };
 216
 217 /**
 218  * struct hevc_fb - hevc decode frame buffer information
 219  *
 220  * @vdec_fb_va: virtual address of struct vdec_fb
 221  * @y_fb_dma:   dma address of Y frame buffer (luma)
 222  * @c_fb_dma:   dma address of C frame buffer (chroma)
 223  * @poc:        picture order count of frame buffer
 224  * @reserved:   for 8 bytes alignment
 225  */
 226 struct hevc_fb {
 227         u64 vdec_fb_va;
 228         u64 y_fb_dma;
 229         u64 c_fb_dma;
 230         s32 poc;
 231         u32 reserved;
 232 };
 233
 234 /**
 235  * struct vdec_hevc_slice_lat_dec_param  - parameters for decode current frame
 236  *
 237  * @sps:            hevc sps syntax parameters
 238  * @pps:            hevc pps syntax parameters
 239  * @slice_header:   hevc slice header syntax parameters
 240  * @scaling_matrix: hevc scaling list parameters
 241  * @decode_params:  decoder parameters of each frame used for hardware decode
 242  * @hevc_dpb_info:  dpb reference list
 243  */
 244 struct vdec_hevc_slice_lat_dec_param {
 245         struct mtk_hevc_sps_param sps;
 246         struct mtk_hevc_pps_param pps;
 247         struct mtk_hevc_slice_header_param slice_header;
 248         struct slice_api_hevc_scaling_matrix scaling_matrix;
 249         struct slice_api_hevc_decode_param decode_params;
 250         struct mtk_hevc_dpb_info hevc_dpb_info[V4L2_HEVC_DPB_ENTRIES_NUM_MAX];
 251 };
 252
 253 /**
 254  * struct vdec_hevc_slice_info - decode information
 255  *
 256  * @wdma_end_addr_offset: wdma end address offset
 257  * @timeout:              Decode timeout: 1 timeout, 0 no timeount
 258  * @vdec_fb_va:           VDEC frame buffer struct virtual address
 259  * @crc:                  Used to check whether hardware's status is right
 260  */
 261 struct vdec_hevc_slice_info {
 262         u64 wdma_end_addr_offset;
 263         u64 timeout;
 264         u64 vdec_fb_va;
 265         u32 crc[8];
 266 };
 267
 268 /*
 269  * struct vdec_hevc_slice_mem - memory address and size
 270  */
 271 struct vdec_hevc_slice_mem {
 272         union {
 273                 u64 buf;
 274                 dma_addr_t dma_addr;
 275         };
 276         union {
 277                 size_t size;
 278                 dma_addr_t dma_addr_end;
 279                 u64 padding;
 280         };
 281 };
 282
 283 /**
 284  * struct vdec_hevc_slice_fb - frame buffer for decoding
 285  * @y:  current y buffer address info
 286  * @c:  current c buffer address info
 287  */
 288 struct vdec_hevc_slice_fb {
 289         struct vdec_hevc_slice_mem y;
 290         struct vdec_hevc_slice_mem c;
 291 };
 292
 293 /**
 294  * struct vdec_hevc_slice_vsi - shared memory for decode information exchange
 295  *        between SCP and Host.
 296  *
 297  * @bs:                input buffer info
 298  *
 299  * @ube:               ube buffer
 300  * @trans:             transcoded buffer
 301  * @err_map:           err map buffer
 302  * @slice_bc:          slice bc buffer
 303  * @wrap:              temp buffer
 304  *
 305  * @fb:                current y/c buffer
 306  * @mv_buf_dma:        HW working motion vector buffer
 307  * @dec:               decode information (AP-R, VPU-W)
 308  * @hevc_slice_params: decode parameters for hw used
 309  */
 310 struct vdec_hevc_slice_vsi {
 311         /* used in LAT stage */
 312         struct vdec_hevc_slice_mem bs;
 313
 314         struct vdec_hevc_slice_mem ube;
 315         struct vdec_hevc_slice_mem trans;
 316         struct vdec_hevc_slice_mem err_map;
 317         struct vdec_hevc_slice_mem slice_bc;
 318         struct vdec_hevc_slice_mem wrap;
 319
 320         struct vdec_hevc_slice_fb fb;
 321         struct vdec_hevc_slice_mem mv_buf_dma[HEVC_MAX_MV_NUM];
 322         struct vdec_hevc_slice_info dec;
 323         struct vdec_hevc_slice_lat_dec_param hevc_slice_params;
 324 };
 325
 326 /**
 327  * struct vdec_hevc_slice_share_info - shared information used to exchange
 328  *                                     message between lat and core
 329  *
 330  * @sps:               sequence header information from user space
 331  * @dec_params:        decoder params from user space
 332  * @hevc_slice_params: decoder params used for hardware
 333  * @trans:             trans buffer dma address
 334  */
 335 struct vdec_hevc_slice_share_info {
 336         struct v4l2_ctrl_hevc_sps sps;
 337         struct v4l2_ctrl_hevc_decode_params dec_params;
 338         struct vdec_hevc_slice_lat_dec_param hevc_slice_params;
 339         struct vdec_hevc_slice_mem trans;
 340 };
 341
 342 /**
 343  * struct vdec_hevc_slice_inst - hevc decoder instance
 344  *
 345  * @slice_dec_num:      how many picture be decoded
 346  * @ctx:                point to mtk_vcodec_dec_ctx
 347  * @mv_buf:             HW working motion vector buffer
 348  * @vpu:                VPU instance
 349  * @vsi:                vsi used for lat
 350  * @vsi_core:           vsi used for core
 351  * @wrap_addr:          wrap address used for hevc
 352  *
 353  * @hevc_slice_param:   the parameters that hardware use to decode
 354  *
 355  * @resolution_changed: resolution changed
 356  * @realloc_mv_buf:     reallocate mv buffer
 357  * @cap_num_planes:     number of capture queue plane
 358  */
 359 struct vdec_hevc_slice_inst {
 360         unsigned int slice_dec_num;
 361         struct mtk_vcodec_dec_ctx *ctx;
 362         struct mtk_vcodec_mem mv_buf[HEVC_MAX_MV_NUM];
 363         struct vdec_vpu_inst vpu;
 364         struct vdec_hevc_slice_vsi *vsi;
 365         struct vdec_hevc_slice_vsi *vsi_core;
 366         struct mtk_vcodec_mem wrap_addr;
 367
 368         struct vdec_hevc_slice_lat_dec_param hevc_slice_param;
 369
 370         unsigned int resolution_changed;
 371         unsigned int realloc_mv_buf;
 372         unsigned int cap_num_planes;
 373 };
 374
 375 static unsigned int vdec_hevc_get_mv_buf_size(unsigned int width, unsigned int height)
 376 {
 377         const unsigned int unit_size = (width / 16) * (height / 16) + 8;
 378
 379         return 64 * unit_size;
 380 }
 381
 382 static void *vdec_hevc_get_ctrl_ptr(struct mtk_vcodec_dec_ctx *ctx, int id)
 383 {
 384         struct v4l2_ctrl *ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, id);
 385
 386         if (!ctrl)
 387                 return ERR_PTR(-EINVAL);
 388
 389         return ctrl->p_cur.p;
 390 }
 391
 392 static void vdec_hevc_fill_dpb_info(struct mtk_vcodec_dec_ctx *ctx,
 393                                     struct slice_api_hevc_decode_param *decode_params,
 394                                     struct mtk_hevc_dpb_info *hevc_dpb_info)
 395 {
 396         const struct slice_hevc_dpb_entry *dpb;
 397         struct vb2_queue *vq;
 398         struct vb2_buffer *vb;
 399         int index;
 400
 401         vq = v4l2_m2m_get_vq(ctx->m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
 402         for (index = 0; index < V4L2_HEVC_DPB_ENTRIES_NUM_MAX; index++) {
 403                 dpb = &decode_params->dpb[index];
 404                 if (index >= decode_params->num_active_dpb_entries)
 405                         continue;
 406
 407                 vb = vb2_find_buffer(vq, dpb->timestamp);
 408                 if (!vb) {
 409                         dev_err(&ctx->dev->plat_dev->dev,
 410                                 "Reference invalid: dpb_index(%d) timestamp(%lld)",
 411                                 index, dpb->timestamp);
 412                         continue;
 413                 }
 414
 415                 hevc_dpb_info[index].field = dpb->field_pic;
 416
 417                 hevc_dpb_info[index].y_dma_addr = vb2_dma_contig_plane_dma_addr(vb, 0);
 418                 if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 2)
 419                         hevc_dpb_info[index].c_dma_addr = vb2_dma_contig_plane_dma_addr(vb, 1);
 420                 else
 421                         hevc_dpb_info[index].c_dma_addr =
 422                                 hevc_dpb_info[index].y_dma_addr + ctx->picinfo.fb_sz[0];
 423         }
 424 }
 425
 426 static void vdec_hevc_copy_sps_params(struct mtk_hevc_sps_param *dst_param,
 427                                       const struct v4l2_ctrl_hevc_sps *src_param)
 428 {
 429         GET_HEVC_VDEC_PARAM(video_parameter_set_id);
 430         GET_HEVC_VDEC_PARAM(seq_parameter_set_id);
 431         GET_HEVC_VDEC_PARAM(pic_width_in_luma_samples);
 432         GET_HEVC_VDEC_PARAM(pic_height_in_luma_samples);
 433         GET_HEVC_VDEC_PARAM(bit_depth_luma_minus8);
 434         GET_HEVC_VDEC_PARAM(bit_depth_chroma_minus8);
 435         GET_HEVC_VDEC_PARAM(log2_max_pic_order_cnt_lsb_minus4);
 436         GET_HEVC_VDEC_PARAM(sps_max_dec_pic_buffering_minus1);
 437         GET_HEVC_VDEC_PARAM(sps_max_num_reorder_pics);
 438         GET_HEVC_VDEC_PARAM(sps_max_latency_increase_plus1);
 439         GET_HEVC_VDEC_PARAM(log2_min_luma_coding_block_size_minus3);
 440         GET_HEVC_VDEC_PARAM(log2_diff_max_min_luma_coding_block_size);
 441         GET_HEVC_VDEC_PARAM(log2_min_luma_transform_block_size_minus2);
 442         GET_HEVC_VDEC_PARAM(log2_diff_max_min_luma_transform_block_size);
 443         GET_HEVC_VDEC_PARAM(max_transform_hierarchy_depth_inter);
 444         GET_HEVC_VDEC_PARAM(max_transform_hierarchy_depth_intra);
 445         GET_HEVC_VDEC_PARAM(pcm_sample_bit_depth_luma_minus1);
 446         GET_HEVC_VDEC_PARAM(pcm_sample_bit_depth_chroma_minus1);
 447         GET_HEVC_VDEC_PARAM(log2_min_pcm_luma_coding_block_size_minus3);
 448         GET_HEVC_VDEC_PARAM(log2_diff_max_min_pcm_luma_coding_block_size);
 449         GET_HEVC_VDEC_PARAM(num_short_term_ref_pic_sets);
 450         GET_HEVC_VDEC_PARAM(num_long_term_ref_pics_sps);
 451         GET_HEVC_VDEC_PARAM(chroma_format_idc);
 452         GET_HEVC_VDEC_PARAM(sps_max_sub_layers_minus1);
 453
 454         GET_HEVC_VDEC_FLAG(separate_colour_plane,
 455                            V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE);
 456         GET_HEVC_VDEC_FLAG(scaling_list_enabled,
 457                            V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED);
 458         GET_HEVC_VDEC_FLAG(amp_enabled,
 459                            V4L2_HEVC_SPS_FLAG_AMP_ENABLED);
 460         GET_HEVC_VDEC_FLAG(sample_adaptive_offset,
 461                            V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET);
 462         GET_HEVC_VDEC_FLAG(pcm_enabled,
 463                            V4L2_HEVC_SPS_FLAG_PCM_ENABLED);
 464         GET_HEVC_VDEC_FLAG(pcm_loop_filter_disabled,
 465                            V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED);
 466         GET_HEVC_VDEC_FLAG(long_term_ref_pics_enabled,
 467                            V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT);
 468         GET_HEVC_VDEC_FLAG(sps_temporal_mvp_enabled,
 469                            V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED);
 470         GET_HEVC_VDEC_FLAG(strong_intra_smoothing_enabled,
 471                            V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED);
 472 }
 473
 474 static void vdec_hevc_copy_pps_params(struct mtk_hevc_pps_param *dst_param,
 475                                       const struct v4l2_ctrl_hevc_pps *src_param)
 476 {
 477         int i;
 478
 479         GET_HEVC_VDEC_PARAM(pic_parameter_set_id);
 480         GET_HEVC_VDEC_PARAM(num_extra_slice_header_bits);
 481         GET_HEVC_VDEC_PARAM(num_ref_idx_l0_default_active_minus1);
 482         GET_HEVC_VDEC_PARAM(num_ref_idx_l1_default_active_minus1);
 483         GET_HEVC_VDEC_PARAM(init_qp_minus26);
 484         GET_HEVC_VDEC_PARAM(diff_cu_qp_delta_depth);
 485         GET_HEVC_VDEC_PARAM(pps_cb_qp_offset);
 486         GET_HEVC_VDEC_PARAM(pps_cr_qp_offset);
 487         GET_HEVC_VDEC_PARAM(num_tile_columns_minus1);
 488         GET_HEVC_VDEC_PARAM(num_tile_rows_minus1);
 489         GET_HEVC_VDEC_PARAM(init_qp_minus26);
 490         GET_HEVC_VDEC_PARAM(diff_cu_qp_delta_depth);
 491         GET_HEVC_VDEC_PARAM(pic_parameter_set_id);
 492         GET_HEVC_VDEC_PARAM(num_extra_slice_header_bits);
 493         GET_HEVC_VDEC_PARAM(num_ref_idx_l0_default_active_minus1);
 494         GET_HEVC_VDEC_PARAM(num_ref_idx_l1_default_active_minus1);
 495         GET_HEVC_VDEC_PARAM(pps_beta_offset_div2);
 496         GET_HEVC_VDEC_PARAM(pps_tc_offset_div2);
 497         GET_HEVC_VDEC_PARAM(log2_parallel_merge_level_minus2);
 498
 499         for (i = 0; i < ARRAY_SIZE(src_param->column_width_minus1); i++)
 500                 GET_HEVC_VDEC_PARAM(column_width_minus1[i]);
 501         for (i = 0; i < ARRAY_SIZE(src_param->row_height_minus1); i++)
 502                 GET_HEVC_VDEC_PARAM(row_height_minus1[i]);
 503
 504         GET_HEVC_VDEC_FLAG(dependent_slice_segment_enabled,
 505                            V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED);
 506         GET_HEVC_VDEC_FLAG(output_flag_present,
 507                            V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT);
 508         GET_HEVC_VDEC_FLAG(sign_data_hiding_enabled,
 509                            V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED);
 510         GET_HEVC_VDEC_FLAG(cabac_init_present,
 511                            V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT);
 512         GET_HEVC_VDEC_FLAG(constrained_intra_pred,
 513                            V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED);
 514         GET_HEVC_VDEC_FLAG(transform_skip_enabled,
 515                            V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED);
 516         GET_HEVC_VDEC_FLAG(cu_qp_delta_enabled,
 517                            V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED);
 518         GET_HEVC_VDEC_FLAG(pps_slice_chroma_qp_offsets_present,
 519                            V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT);
 520         GET_HEVC_VDEC_FLAG(weighted_pred,
 521                            V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED);
 522         GET_HEVC_VDEC_FLAG(weighted_bipred,
 523                            V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED);
 524         GET_HEVC_VDEC_FLAG(transquant_bypass_enabled,
 525                            V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED);
 526         GET_HEVC_VDEC_FLAG(pps_flag_tiles_enabled,
 527                            V4L2_HEVC_PPS_FLAG_TILES_ENABLED);
 528         GET_HEVC_VDEC_FLAG(entropy_coding_sync_enabled,
 529                            V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED);
 530         GET_HEVC_VDEC_FLAG(loop_filter_across_tiles_enabled,
 531                            V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED);
 532         GET_HEVC_VDEC_FLAG(pps_loop_filter_across_slices_enabled,
 533                            V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED);
 534         GET_HEVC_VDEC_FLAG(deblocking_filter_override_enabled,
 535                            V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED);
 536         GET_HEVC_VDEC_FLAG(pps_disable_deflocking_filter,
 537                            V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER);
 538         GET_HEVC_VDEC_FLAG(lists_modification_present,
 539                            V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT);
 540         GET_HEVC_VDEC_FLAG(slice_segment_header_extersion_present,
 541                            V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT);
 542         GET_HEVC_VDEC_FLAG(deblocking_filter_control_present,
 543                            V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT);
 544         GET_HEVC_VDEC_FLAG(uniform_spacing,
 545                            V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);
 546 }
 547
 548 static void vdec_hevc_copy_scaling_matrix(struct slice_api_hevc_scaling_matrix *dst_matrix,
 549                                           const struct v4l2_ctrl_hevc_scaling_matrix *src_matrix)
 550 {
 551         memcpy(dst_matrix, src_matrix, sizeof(*src_matrix));
 552 }
 553
 554 static void
 555 vdec_hevc_copy_decode_params(struct slice_api_hevc_decode_param *dst_param,
 556                              const struct v4l2_ctrl_hevc_decode_params *src_param,
 557                              const struct v4l2_hevc_dpb_entry dpb[V4L2_HEVC_DPB_ENTRIES_NUM_MAX])
 558 {
 559         struct slice_hevc_dpb_entry *dst_entry;
 560         const struct v4l2_hevc_dpb_entry *src_entry;
 561         int i;
 562
 563         for (i = 0; i < ARRAY_SIZE(dst_param->dpb); i++) {
 564                 dst_entry = &dst_param->dpb[i];
 565                 src_entry = &dpb[i];
 566
 567                 dst_entry->timestamp = src_entry->timestamp;
 568                 dst_entry->flags = src_entry->flags;
 569                 dst_entry->field_pic = src_entry->field_pic;
 570                 dst_entry->pic_order_cnt_val = src_entry->pic_order_cnt_val;
 571
 572                 GET_HEVC_VDEC_PARAM(poc_st_curr_before[i]);
 573                 GET_HEVC_VDEC_PARAM(poc_st_curr_after[i]);
 574                 GET_HEVC_VDEC_PARAM(poc_lt_curr[i]);
 575         }
 576
 577         GET_HEVC_VDEC_PARAM(pic_order_cnt_val);
 578         GET_HEVC_VDEC_PARAM(short_term_ref_pic_set_size);
 579         GET_HEVC_VDEC_PARAM(long_term_ref_pic_set_size);
 580         GET_HEVC_VDEC_PARAM(num_active_dpb_entries);
 581         GET_HEVC_VDEC_PARAM(num_poc_st_curr_before);
 582         GET_HEVC_VDEC_PARAM(num_poc_st_curr_after);
 583         GET_HEVC_VDEC_PARAM(num_delta_pocs_of_ref_rps_idx);
 584         GET_HEVC_VDEC_PARAM(num_poc_lt_curr);
 585         GET_HEVC_VDEC_PARAM(flags);
 586 }
 587
 588 static int vdec_hevc_slice_fill_decode_parameters(struct vdec_hevc_slice_inst *inst,
 589                                                   struct vdec_hevc_slice_share_info *share_info)
 590 {
 591         struct vdec_hevc_slice_lat_dec_param *slice_param = &inst->vsi->hevc_slice_params;
 592         const struct v4l2_ctrl_hevc_decode_params *dec_params;
 593         const struct v4l2_ctrl_hevc_scaling_matrix *src_matrix;
 594         const struct v4l2_ctrl_hevc_sps *sps;
 595         const struct v4l2_ctrl_hevc_pps *pps;
 596
 597         dec_params =
 598                 vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
 599         if (IS_ERR(dec_params))
 600                 return PTR_ERR(dec_params);
 601
 602         src_matrix =
 603                 vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
 604         if (IS_ERR(src_matrix))
 605                 return PTR_ERR(src_matrix);
 606
 607         sps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_SPS);
 608         if (IS_ERR(sps))
 609                 return PTR_ERR(sps);
 610
 611         pps = vdec_hevc_get_ctrl_ptr(inst->ctx, V4L2_CID_STATELESS_HEVC_PPS);
 612         if (IS_ERR(pps))
 613                 return PTR_ERR(pps);
 614
 615         vdec_hevc_copy_sps_params(&slice_param->sps, sps);
 616         vdec_hevc_copy_pps_params(&slice_param->pps, pps);
 617         vdec_hevc_copy_scaling_matrix(&slice_param->scaling_matrix, src_matrix);
 618
 619         memcpy(&share_info->sps, sps, sizeof(*sps));
 620         memcpy(&share_info->dec_params, dec_params, sizeof(*dec_params));
 621
 622         slice_param->decode_params.num_poc_st_curr_before = dec_params->num_poc_st_curr_before;
 623         slice_param->decode_params.num_poc_st_curr_after = dec_params->num_poc_st_curr_after;
 624         slice_param->decode_params.num_poc_lt_curr = dec_params->num_poc_lt_curr;
 625         slice_param->decode_params.num_delta_pocs_of_ref_rps_idx =
 626                 dec_params->num_delta_pocs_of_ref_rps_idx;
 627
 628         return 0;
 629 }
 630
 631 static void vdec_hevc_slice_fill_decode_reflist(struct vdec_hevc_slice_inst *inst,
 632                                                 struct vdec_hevc_slice_lat_dec_param *slice_param,
 633                                                 struct vdec_hevc_slice_share_info *share_info)
 634 {
 635         struct v4l2_ctrl_hevc_decode_params *dec_params = &share_info->dec_params;
 636
 637         vdec_hevc_copy_decode_params(&slice_param->decode_params, dec_params,
 638                                      share_info->dec_params.dpb);
 639
 640         vdec_hevc_fill_dpb_info(inst->ctx, &slice_param->decode_params,
 641                                 slice_param->hevc_dpb_info);
 642 }
 643
 644 static int vdec_hevc_slice_alloc_mv_buf(struct vdec_hevc_slice_inst *inst,
 645                                         struct vdec_pic_info *pic)
 646 {
 647         unsigned int buf_sz = vdec_hevc_get_mv_buf_size(pic->buf_w, pic->buf_h);
 648         struct mtk_vcodec_mem *mem;
 649         int i, err;
 650
 651         mtk_v4l2_vdec_dbg(3, inst->ctx, "allocate mv buffer size = 0x%x", buf_sz);
 652         for (i = 0; i < HEVC_MAX_MV_NUM; i++) {
 653                 mem = &inst->mv_buf[i];
 654                 if (mem->va)
 655                         mtk_vcodec_mem_free(inst->ctx, mem);
 656                 mem->size = buf_sz;
 657                 err = mtk_vcodec_mem_alloc(inst->ctx, mem);
 658                 if (err) {
 659                         mtk_vdec_err(inst->ctx, "failed to allocate mv buf");
 660                         return err;
 661                 }
 662         }
 663
 664         return 0;
 665 }
 666
 667 static void vdec_hevc_slice_free_mv_buf(struct vdec_hevc_slice_inst *inst)
 668 {
 669         int i;
 670         struct mtk_vcodec_mem *mem;
 671
 672         for (i = 0; i < HEVC_MAX_MV_NUM; i++) {
 673                 mem = &inst->mv_buf[i];
 674                 if (mem->va)
 675                         mtk_vcodec_mem_free(inst->ctx, mem);
 676         }
 677 }
 678
 679 static void vdec_hevc_slice_get_pic_info(struct vdec_hevc_slice_inst *inst)
 680 {
 681         struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
 682         u32 data[3];
 683
 684         data[0] = ctx->picinfo.pic_w;
 685         data[1] = ctx->picinfo.pic_h;
 686         data[2] = ctx->capture_fourcc;
 687         vpu_dec_get_param(&inst->vpu, data, 3, GET_PARAM_PIC_INFO);
 688
 689         ctx->picinfo.buf_w = ALIGN(ctx->picinfo.pic_w, VCODEC_DEC_ALIGNED_64);
 690         ctx->picinfo.buf_h = ALIGN(ctx->picinfo.pic_h, VCODEC_DEC_ALIGNED_64);
 691         ctx->picinfo.fb_sz[0] = inst->vpu.fb_sz[0];
 692         ctx->picinfo.fb_sz[1] = inst->vpu.fb_sz[1];
 693         inst->cap_num_planes =
 694                 ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes;
 695
 696         mtk_vdec_debug(ctx, "pic(%d, %d), buf(%d, %d)",
 697                        ctx->picinfo.pic_w, ctx->picinfo.pic_h,
 698                        ctx->picinfo.buf_w, ctx->picinfo.buf_h);
 699         mtk_vdec_debug(ctx, "Y/C(%d, %d)", ctx->picinfo.fb_sz[0],
 700                        ctx->picinfo.fb_sz[1]);
 701
 702         if (ctx->last_decoded_picinfo.pic_w != ctx->picinfo.pic_w ||
 703             ctx->last_decoded_picinfo.pic_h != ctx->picinfo.pic_h) {
 704                 inst->resolution_changed = true;
 705                 if (ctx->last_decoded_picinfo.buf_w != ctx->picinfo.buf_w ||
 706                     ctx->last_decoded_picinfo.buf_h != ctx->picinfo.buf_h)
 707                         inst->realloc_mv_buf = true;
 708
 709                 mtk_v4l2_vdec_dbg(1, inst->ctx, "resChg: (%d %d) : old(%d, %d) -> new(%d, %d)",
 710                                   inst->resolution_changed,
 711                                   inst->realloc_mv_buf,
 712                                   ctx->last_decoded_picinfo.pic_w,
 713                                   ctx->last_decoded_picinfo.pic_h,
 714                                   ctx->picinfo.pic_w, ctx->picinfo.pic_h);
 715         }
 716 }
 717
 718 static void vdec_hevc_slice_get_crop_info(struct vdec_hevc_slice_inst *inst,
 719                                           struct v4l2_rect *cr)
 720 {
 721         cr->left = 0;
 722         cr->top = 0;
 723         cr->width = inst->ctx->picinfo.pic_w;
 724         cr->height = inst->ctx->picinfo.pic_h;
 725
 726         mtk_vdec_debug(inst->ctx, "l=%d, t=%d, w=%d, h=%d",
 727                        cr->left, cr->top, cr->width, cr->height);
 728 }
 729
 730 static int vdec_hevc_slice_setup_lat_buffer(struct vdec_hevc_slice_inst *inst,
 731                                             struct mtk_vcodec_mem *bs,
 732                                             struct vdec_lat_buf *lat_buf,
 733                                             bool *res_chg)
 734 {
 735         struct mtk_vcodec_mem *mem;
 736         struct mtk_video_dec_buf *src_buf_info;
 737         struct vdec_hevc_slice_share_info *share_info;
 738         int i, err;
 739
 740         inst->vsi->bs.dma_addr = (u64)bs->dma_addr;
 741         inst->vsi->bs.size = bs->size;
 742
 743         src_buf_info = container_of(bs, struct mtk_video_dec_buf, bs_buffer);
 744         lat_buf->src_buf_req = src_buf_info->m2m_buf.vb.vb2_buf.req_obj.req;
 745         v4l2_m2m_buf_copy_metadata(&src_buf_info->m2m_buf.vb, &lat_buf->ts_info, true);
 746
 747         *res_chg = inst->resolution_changed;
 748         if (inst->resolution_changed) {
 749                 mtk_vdec_debug(inst->ctx, "- resolution changed -");
 750                 if (inst->realloc_mv_buf) {
 751                         err = vdec_hevc_slice_alloc_mv_buf(inst, &inst->ctx->picinfo);
 752                         inst->realloc_mv_buf = false;
 753                         if (err)
 754                                 return err;
 755                 }
 756                 inst->resolution_changed = false;
 757         }
 758
 759         for (i = 0; i < HEVC_MAX_MV_NUM; i++) {
 760                 mem = &inst->mv_buf[i];
 761                 inst->vsi->mv_buf_dma[i].dma_addr = mem->dma_addr;
 762                 inst->vsi->mv_buf_dma[i].size = mem->size;
 763         }
 764
 765         inst->vsi->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
 766         inst->vsi->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size;
 767
 768         inst->vsi->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr;
 769         inst->vsi->err_map.size = lat_buf->wdma_err_addr.size;
 770
 771         inst->vsi->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr;
 772         inst->vsi->slice_bc.size = lat_buf->slice_bc_addr.size;
 773
 774         inst->vsi->trans.dma_addr_end = inst->ctx->msg_queue.wdma_rptr_addr;
 775         inst->vsi->trans.dma_addr = inst->ctx->msg_queue.wdma_wptr_addr;
 776
 777         share_info = lat_buf->private_data;
 778         share_info->trans.dma_addr = inst->vsi->trans.dma_addr;
 779         share_info->trans.dma_addr_end = inst->vsi->trans.dma_addr_end;
 780
 781         mtk_vdec_debug(inst->ctx, "lat: ube addr/size(0x%llx 0x%llx) err:0x%llx",
 782                        inst->vsi->ube.buf,
 783                        inst->vsi->ube.padding,
 784                        inst->vsi->err_map.buf);
 785
 786         mtk_vdec_debug(inst->ctx, "slice addr/size(0x%llx 0x%llx) trans start/end((0x%llx 0x%llx))",
 787                        inst->vsi->slice_bc.buf,
 788                        inst->vsi->slice_bc.padding,
 789                        inst->vsi->trans.buf,
 790                        inst->vsi->trans.padding);
 791
 792         return 0;
 793 }
 794
 795 static int vdec_hevc_slice_setup_core_buffer(struct vdec_hevc_slice_inst *inst,
 796                                              struct vdec_hevc_slice_share_info *share_info,
 797                                              struct vdec_lat_buf *lat_buf)
 798 {
 799         struct mtk_vcodec_mem *mem;
 800         struct mtk_vcodec_dec_ctx *ctx = inst->ctx;
 801         struct vb2_v4l2_buffer *vb2_v4l2;
 802         struct vdec_fb *fb;
 803         u64 y_fb_dma, c_fb_dma;
 804         int i;
 805
 806         fb = ctx->dev->vdec_pdata->get_cap_buffer(ctx);
 807         if (!fb) {
 808                 mtk_vdec_err(inst->ctx, "fb buffer is NULL");
 809                 return -EBUSY;
 810         }
 811
 812         y_fb_dma = (u64)fb->base_y.dma_addr;
 813         if (ctx->q_data[MTK_Q_DATA_DST].fmt->num_planes == 1)
 814                 c_fb_dma =
 815                         y_fb_dma + inst->ctx->picinfo.buf_w * inst->ctx->picinfo.buf_h;
 816         else
 817                 c_fb_dma = (u64)fb->base_c.dma_addr;
 818
 819         mtk_vdec_debug(inst->ctx, "[hevc-core] y/c addr = 0x%llx 0x%llx", y_fb_dma, c_fb_dma);
 820
 821         inst->vsi_core->fb.y.dma_addr = y_fb_dma;
 822         inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[0];
 823         inst->vsi_core->fb.c.dma_addr = c_fb_dma;
 824         inst->vsi_core->fb.y.size = ctx->picinfo.fb_sz[1];
 825
 826         inst->vsi_core->dec.vdec_fb_va = (unsigned long)fb;
 827
 828         inst->vsi_core->ube.dma_addr = lat_buf->ctx->msg_queue.wdma_addr.dma_addr;
 829         inst->vsi_core->ube.size = lat_buf->ctx->msg_queue.wdma_addr.size;
 830
 831         inst->vsi_core->err_map.dma_addr = lat_buf->wdma_err_addr.dma_addr;
 832         inst->vsi_core->err_map.size = lat_buf->wdma_err_addr.size;
 833
 834         inst->vsi_core->slice_bc.dma_addr = lat_buf->slice_bc_addr.dma_addr;
 835         inst->vsi_core->slice_bc.size = lat_buf->slice_bc_addr.size;
 836
 837         inst->vsi_core->trans.dma_addr = share_info->trans.dma_addr;
 838         inst->vsi_core->trans.dma_addr_end = share_info->trans.dma_addr_end;
 839
 840         inst->vsi_core->wrap.dma_addr = inst->wrap_addr.dma_addr;
 841         inst->vsi_core->wrap.size = inst->wrap_addr.size;
 842
 843         for (i = 0; i < HEVC_MAX_MV_NUM; i++) {
 844                 mem = &inst->mv_buf[i];
 845                 inst->vsi_core->mv_buf_dma[i].dma_addr = mem->dma_addr;
 846                 inst->vsi_core->mv_buf_dma[i].size = mem->size;
 847         }
 848
 849         vb2_v4l2 = v4l2_m2m_next_dst_buf(ctx->m2m_ctx);
 850         v4l2_m2m_buf_copy_metadata(&lat_buf->ts_info, vb2_v4l2, true);
 851
 852         return 0;
 853 }
 854
 855 static int vdec_hevc_slice_init(struct mtk_vcodec_dec_ctx *ctx)
 856 {
 857         struct vdec_hevc_slice_inst *inst;
 858         int err, vsi_size;
 859
 860         inst = kzalloc(sizeof(*inst), GFP_KERNEL);
 861         if (!inst)
 862                 return -ENOMEM;
 863
 864         inst->ctx = ctx;
 865
 866         inst->vpu.id = SCP_IPI_VDEC_LAT;
 867         inst->vpu.core_id = SCP_IPI_VDEC_CORE;
 868         inst->vpu.ctx = ctx;
 869         inst->vpu.codec_type = ctx->current_codec;
 870         inst->vpu.capture_type = ctx->capture_fourcc;
 871
 872         ctx->drv_handle = inst;
 873         err = vpu_dec_init(&inst->vpu);
 874         if (err) {
 875                 mtk_vdec_err(ctx, "vdec_hevc init err=%d", err);
 876                 goto error_free_inst;
 877         }
 878
 879         vsi_size = round_up(sizeof(struct vdec_hevc_slice_vsi), VCODEC_DEC_ALIGNED_64);
 880         inst->vsi = inst->vpu.vsi;
 881         inst->vsi_core =
 882                 (struct vdec_hevc_slice_vsi *)(((char *)inst->vpu.vsi) + vsi_size);
 883
 884         inst->resolution_changed = true;
 885         inst->realloc_mv_buf = true;
 886
 887         inst->wrap_addr.size = VDEC_HEVC_WRAP_SZ;
 888         err = mtk_vcodec_mem_alloc(ctx, &inst->wrap_addr);
 889         if (err)
 890                 goto error_free_inst;
 891
 892         mtk_vdec_debug(ctx, "lat struct size = %d,%d,%d,%d vsi: %d\n",
 893                        (int)sizeof(struct mtk_hevc_sps_param),
 894                        (int)sizeof(struct mtk_hevc_pps_param),
 895                        (int)sizeof(struct vdec_hevc_slice_lat_dec_param),
 896                        (int)sizeof(struct mtk_hevc_dpb_info),
 897                          vsi_size);
 898         mtk_vdec_debug(ctx, "lat hevc instance >> %p, codec_type = 0x%x",
 899                        inst, inst->vpu.codec_type);
 900
 901         return 0;
 902 error_free_inst:
 903         kfree(inst);
 904         return err;
 905 }
 906
 907 static void vdec_hevc_slice_deinit(void *h_vdec)
 908 {
 909         struct vdec_hevc_slice_inst *inst = h_vdec;
 910         struct mtk_vcodec_mem *mem;
 911
 912         vpu_dec_deinit(&inst->vpu);
 913         vdec_hevc_slice_free_mv_buf(inst);
 914
 915         mem = &inst->wrap_addr;
 916         if (mem->va)
 917                 mtk_vcodec_mem_free(inst->ctx, mem);
 918
 919         vdec_msg_queue_deinit(&inst->ctx->msg_queue, inst->ctx);
 920         kfree(inst);
 921 }
 922
 923 static int vdec_hevc_slice_core_decode(struct vdec_lat_buf *lat_buf)
 924 {
 925         int err, timeout;
 926         struct mtk_vcodec_dec_ctx *ctx = lat_buf->ctx;
 927         struct vdec_hevc_slice_inst *inst = ctx->drv_handle;
 928         struct vdec_hevc_slice_share_info *share_info = lat_buf->private_data;
 929         struct vdec_vpu_inst *vpu = &inst->vpu;
 930
 931         mtk_vdec_debug(ctx, "[hevc-core] vdec_hevc core decode");
 932         memcpy(&inst->vsi_core->hevc_slice_params, &share_info->hevc_slice_params,
 933                sizeof(share_info->hevc_slice_params));
 934
 935         err = vdec_hevc_slice_setup_core_buffer(inst, share_info, lat_buf);
 936         if (err)
 937                 goto vdec_dec_end;
 938
 939         vdec_hevc_slice_fill_decode_reflist(inst, &inst->vsi_core->hevc_slice_params,
 940                                             share_info);
 941         err = vpu_dec_core(vpu);
 942         if (err) {
 943                 mtk_vdec_err(ctx, "core decode err=%d", err);
 944                 goto vdec_dec_end;
 945         }
 946
 947         /* wait decoder done interrupt */
 948         timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
 949                                                WAIT_INTR_TIMEOUT_MS, MTK_VDEC_CORE);
 950         if (timeout)
 951                 mtk_vdec_err(ctx, "core decode timeout: pic_%d", ctx->decoded_frame_cnt);
 952         inst->vsi_core->dec.timeout = !!timeout;
 953
 954         vpu_dec_core_end(vpu);
 955         mtk_vdec_debug(ctx, "pic[%d] crc: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
 956                        ctx->decoded_frame_cnt,
 957                        inst->vsi_core->dec.crc[0], inst->vsi_core->dec.crc[1],
 958                        inst->vsi_core->dec.crc[2], inst->vsi_core->dec.crc[3],
 959                        inst->vsi_core->dec.crc[4], inst->vsi_core->dec.crc[5],
 960                        inst->vsi_core->dec.crc[6], inst->vsi_core->dec.crc[7]);
 961
 962 vdec_dec_end:
 963         vdec_msg_queue_update_ube_rptr(&lat_buf->ctx->msg_queue, share_info->trans.dma_addr_end);
 964         ctx->dev->vdec_pdata->cap_to_disp(ctx, !!err, lat_buf->src_buf_req);
 965         mtk_vdec_debug(ctx, "core decode done err=%d", err);
 966         ctx->decoded_frame_cnt++;
 967         return 0;
 968 }
 969
 970 static int vdec_hevc_slice_lat_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
 971                                       struct vdec_fb *fb, bool *res_chg)
 972 {
 973         struct vdec_hevc_slice_inst *inst = h_vdec;
 974         struct vdec_vpu_inst *vpu = &inst->vpu;
 975         int err, timeout = 0;
 976         unsigned int data[2];
 977         struct vdec_lat_buf *lat_buf;
 978         struct vdec_hevc_slice_share_info *share_info;
 979
 980         if (vdec_msg_queue_init(&inst->ctx->msg_queue, inst->ctx,
 981                                 vdec_hevc_slice_core_decode,
 982                                 sizeof(*share_info)))
 983                 return -ENOMEM;
 984
 985         /* bs NULL means flush decoder */
 986         if (!bs) {
 987                 vdec_msg_queue_wait_lat_buf_full(&inst->ctx->msg_queue);
 988                 return vpu_dec_reset(vpu);
 989         }
 990
 991         lat_buf = vdec_msg_queue_dqbuf(&inst->ctx->msg_queue.lat_ctx);
 992         if (!lat_buf) {
 993                 mtk_vdec_debug(inst->ctx, "failed to get lat buffer");
 994                 return -EAGAIN;
 995         }
 996
 997         share_info = lat_buf->private_data;
 998         err = vdec_hevc_slice_fill_decode_parameters(inst, share_info);
 999         if (err)
1000                 goto err_free_fb_out;
1001
1002         err = vdec_hevc_slice_setup_lat_buffer(inst, bs, lat_buf, res_chg);
1003         if (err)
1004                 goto err_free_fb_out;
1005
1006         err = vpu_dec_start(vpu, data, 2);
1007         if (err) {
1008                 mtk_vdec_debug(inst->ctx, "lat decode err: %d", err);
1009                 goto err_free_fb_out;
1010         }
1011
1012         if (IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
1013                 memcpy(&share_info->hevc_slice_params, &inst->vsi->hevc_slice_params,
1014                        sizeof(share_info->hevc_slice_params));
1015                 vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
1016         }
1017
1018         /* wait decoder done interrupt */
1019         timeout = mtk_vcodec_wait_for_done_ctx(inst->ctx, MTK_INST_IRQ_RECEIVED,
1020                                                WAIT_INTR_TIMEOUT_MS, MTK_VDEC_LAT0);
1021         if (timeout)
1022                 mtk_vdec_err(inst->ctx, "lat decode timeout: pic_%d", inst->slice_dec_num);
1023         inst->vsi->dec.timeout = !!timeout;
1024
1025         err = vpu_dec_end(vpu);
1026         if (err == SLICE_HEADER_FULL || err == TRANS_BUFFER_FULL) {
1027                 if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability))
1028                         vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
1029                 inst->slice_dec_num++;
1030                 mtk_vdec_err(inst->ctx, "lat dec fail: pic_%d err:%d", inst->slice_dec_num, err);
1031                 return -EINVAL;
1032         }
1033
1034         share_info->trans.dma_addr_end = inst->ctx->msg_queue.wdma_addr.dma_addr +
1035                 inst->vsi->dec.wdma_end_addr_offset;
1036         vdec_msg_queue_update_ube_wptr(&lat_buf->ctx->msg_queue, share_info->trans.dma_addr_end);
1037
1038         if (!IS_VDEC_INNER_RACING(inst->ctx->dev->dec_capability)) {
1039                 memcpy(&share_info->hevc_slice_params, &inst->vsi->hevc_slice_params,
1040                        sizeof(share_info->hevc_slice_params));
1041                 vdec_msg_queue_qbuf(&inst->ctx->msg_queue.core_ctx, lat_buf);
1042         }
1043         mtk_vdec_debug(inst->ctx, "dec num: %d lat crc: 0x%x 0x%x 0x%x", inst->slice_dec_num,
1044                        inst->vsi->dec.crc[0], inst->vsi->dec.crc[1], inst->vsi->dec.crc[2]);
1045
1046         inst->slice_dec_num++;
1047         return 0;
1048 err_free_fb_out:
1049         vdec_msg_queue_qbuf(&inst->ctx->msg_queue.lat_ctx, lat_buf);
1050         mtk_vdec_err(inst->ctx, "slice dec number: %d err: %d", inst->slice_dec_num, err);
1051         return err;
1052 }
1053
1054 static int vdec_hevc_slice_decode(void *h_vdec, struct mtk_vcodec_mem *bs,
1055                                   struct vdec_fb *unused, bool *res_chg)
1056 {
1057         struct vdec_hevc_slice_inst *inst = h_vdec;
1058
1059         if (!h_vdec || inst->ctx->dev->vdec_pdata->hw_arch == MTK_VDEC_PURE_SINGLE_CORE)
1060                 return -EINVAL;
1061
1062         return vdec_hevc_slice_lat_decode(h_vdec, bs, unused, res_chg);
1063 }
1064
1065 static int vdec_hevc_slice_get_param(void *h_vdec, enum vdec_get_param_type type,
1066                                      void *out)
1067 {
1068         struct vdec_hevc_slice_inst *inst = h_vdec;
1069
1070         switch (type) {
1071         case GET_PARAM_PIC_INFO:
1072                 vdec_hevc_slice_get_pic_info(inst);
1073                 break;
1074         case GET_PARAM_DPB_SIZE:
1075                 *(unsigned int *)out = 6;
1076                 break;
1077         case GET_PARAM_CROP_INFO:
1078                 vdec_hevc_slice_get_crop_info(inst, out);
1079                 break;
1080         default:
1081                 mtk_vdec_err(inst->ctx, "invalid get parameter type=%d", type);
1082                 return -EINVAL;
1083         }
1084         return 0;
1085 }
1086
1087 const struct vdec_common_if vdec_hevc_slice_multi_if = {
1088         .init           = vdec_hevc_slice_init,
1089         .decode         = vdec_hevc_slice_decode,
1090         .get_param      = vdec_hevc_slice_get_param,
1091         .deinit         = vdec_hevc_slice_deinit,
1092 };