2 * The Marvell camera core. This device appears in a number of settings,
3 * so it needs platform-specific support outside of the core.
5 * Copyright 2011 Jonathan Corbet corbet@lwn.net
7 #include <linux/kernel.h>
8 #include <linux/module.h>
11 #include <linux/i2c.h>
12 #include <linux/interrupt.h>
13 #include <linux/spinlock.h>
14 #include <linux/slab.h>
15 #include <linux/device.h>
16 #include <linux/wait.h>
17 #include <linux/list.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/delay.h>
20 #include <linux/vmalloc.h>
22 #include <linux/clk.h>
23 #include <linux/videodev2.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-ioctl.h>
26 #include <media/v4l2-ctrls.h>
27 #include <media/v4l2-event.h>
28 #include <media/i2c/ov7670.h>
29 #include <media/videobuf2-vmalloc.h>
30 #include <media/videobuf2-dma-contig.h>
31 #include <media/videobuf2-dma-sg.h>
33 #include "mcam-core.h"
35 #ifdef MCAM_MODE_VMALLOC
37 * Internal DMA buffer management. Since the controller cannot do S/G I/O,
38 * we must have physically contiguous buffers to bring frames into.
39 * These parameters control how many buffers we use, whether we
40 * allocate them at load time (better chance of success, but nails down
41 * memory) or when somebody tries to use the camera (riskier), and,
42 * for load-time allocation, how big they should be.
44 * The controller can cycle through three buffers. We could use
45 * more by flipping pointers around, but it probably makes little
49 static bool alloc_bufs_at_read;
50 module_param(alloc_bufs_at_read, bool, 0444);
51 MODULE_PARM_DESC(alloc_bufs_at_read,
52 "Non-zero value causes DMA buffers to be allocated when the video capture device is read, rather than at module load time. This saves memory, but decreases the chances of successfully getting those buffers. This parameter is only used in the vmalloc buffer mode");
54 static int n_dma_bufs = 3;
55 module_param(n_dma_bufs, uint, 0644);
56 MODULE_PARM_DESC(n_dma_bufs,
57 "The number of DMA buffers to allocate. Can be either two (saves memory, makes timing tighter) or three.");
59 static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
60 module_param(dma_buf_size, uint, 0444);
61 MODULE_PARM_DESC(dma_buf_size,
62 "The size of the allocated DMA buffers. If actual operating parameters require larger buffers, an attempt to reallocate will be made.");
63 #else /* MCAM_MODE_VMALLOC */
64 static const bool alloc_bufs_at_read;
65 static const int n_dma_bufs = 3; /* Used by S/G_PARM */
66 #endif /* MCAM_MODE_VMALLOC */
69 module_param(flip, bool, 0444);
70 MODULE_PARM_DESC(flip,
71 "If set, the sensor will be instructed to flip the image vertically.");
73 static int buffer_mode = -1;
74 module_param(buffer_mode, int, 0444);
75 MODULE_PARM_DESC(buffer_mode,
76 "Set the buffer mode to be used; default is to go with what the platform driver asks for. Set to 0 for vmalloc, 1 for DMA contiguous.");
79 * Status flags. Always manipulated with bit operations.
81 #define CF_BUF0_VALID 0 /* Buffers valid - first three */
82 #define CF_BUF1_VALID 1
83 #define CF_BUF2_VALID 2
84 #define CF_DMA_ACTIVE 3 /* A frame is incoming */
85 #define CF_CONFIG_NEEDED 4 /* Must configure hardware */
86 #define CF_SINGLE_BUFFER 5 /* Running with a single buffer */
87 #define CF_SG_RESTART 6 /* SG restart needed */
88 #define CF_FRAME_SOF0 7 /* Frame 0 started */
89 #define CF_FRAME_SOF1 8
90 #define CF_FRAME_SOF2 9
92 #define sensor_call(cam, o, f, args...) \
93 v4l2_subdev_call(cam->sensor, o, f, ##args)
95 static struct mcam_format_struct {
98 int bpp; /* Bytes per pixel */
103 .desc = "YUYV 4:2:2",
104 .pixelformat = V4L2_PIX_FMT_YUYV,
105 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
110 .desc = "YVYU 4:2:2",
111 .pixelformat = V4L2_PIX_FMT_YVYU,
112 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
117 .desc = "YUV 4:2:0 PLANAR",
118 .pixelformat = V4L2_PIX_FMT_YUV420,
119 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
124 .desc = "YVU 4:2:0 PLANAR",
125 .pixelformat = V4L2_PIX_FMT_YVU420,
126 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
132 .pixelformat = V4L2_PIX_FMT_XRGB444,
133 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
139 .pixelformat = V4L2_PIX_FMT_RGB565,
140 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
145 .desc = "Raw RGB Bayer",
146 .pixelformat = V4L2_PIX_FMT_SBGGR8,
147 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
152 #define N_MCAM_FMTS ARRAY_SIZE(mcam_formats)
154 static struct mcam_format_struct *mcam_find_format(u32 pixelformat)
158 for (i = 0; i < N_MCAM_FMTS; i++)
159 if (mcam_formats[i].pixelformat == pixelformat)
160 return mcam_formats + i;
161 /* Not found? Then return the first format. */
166 * The default format we use until somebody says otherwise.
168 static const struct v4l2_pix_format mcam_def_pix_format = {
170 .height = VGA_HEIGHT,
171 .pixelformat = V4L2_PIX_FMT_YUYV,
172 .field = V4L2_FIELD_NONE,
173 .bytesperline = VGA_WIDTH*2,
174 .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
175 .colorspace = V4L2_COLORSPACE_SRGB,
178 static const u32 mcam_def_mbus_code = MEDIA_BUS_FMT_YUYV8_2X8;
182 * The two-word DMA descriptor format used by the Armada 610 and like. There
183 * Is a three-word format as well (set C1_DESC_3WORD) where the third
184 * word is a pointer to the next descriptor, but we don't use it. Two-word
185 * descriptors have to be contiguous in memory.
187 struct mcam_dma_desc {
193 * Our buffer type for working with videobuf2. Note that the vb2
194 * developers have decreed that struct vb2_v4l2_buffer must be at the
195 * beginning of this structure.
197 struct mcam_vb_buffer {
198 struct vb2_v4l2_buffer vb_buf;
199 struct list_head queue;
200 struct mcam_dma_desc *dma_desc; /* Descriptor virtual address */
201 dma_addr_t dma_desc_pa; /* Descriptor physical address */
202 int dma_desc_nent; /* Number of mapped descriptors */
205 static inline struct mcam_vb_buffer *vb_to_mvb(struct vb2_v4l2_buffer *vb)
207 return container_of(vb, struct mcam_vb_buffer, vb_buf);
211 * Hand a completed buffer back to user space.
213 static void mcam_buffer_done(struct mcam_camera *cam, int frame,
214 struct vb2_v4l2_buffer *vbuf)
216 vbuf->vb2_buf.planes[0].bytesused = cam->pix_format.sizeimage;
217 vbuf->sequence = cam->buf_seq[frame];
218 vbuf->field = V4L2_FIELD_NONE;
219 vbuf->vb2_buf.timestamp = ktime_get_ns();
220 vb2_set_plane_payload(&vbuf->vb2_buf, 0, cam->pix_format.sizeimage);
221 vb2_buffer_done(&vbuf->vb2_buf, VB2_BUF_STATE_DONE);
227 * Debugging and related.
229 #define cam_err(cam, fmt, arg...) \
230 dev_err((cam)->dev, fmt, ##arg);
231 #define cam_warn(cam, fmt, arg...) \
232 dev_warn((cam)->dev, fmt, ##arg);
233 #define cam_dbg(cam, fmt, arg...) \
234 dev_dbg((cam)->dev, fmt, ##arg);
238 * Flag manipulation helpers
240 static void mcam_reset_buffers(struct mcam_camera *cam)
245 for (i = 0; i < cam->nbufs; i++) {
246 clear_bit(i, &cam->flags);
247 clear_bit(CF_FRAME_SOF0 + i, &cam->flags);
251 static inline int mcam_needs_config(struct mcam_camera *cam)
253 return test_bit(CF_CONFIG_NEEDED, &cam->flags);
256 static void mcam_set_config_needed(struct mcam_camera *cam, int needed)
259 set_bit(CF_CONFIG_NEEDED, &cam->flags);
261 clear_bit(CF_CONFIG_NEEDED, &cam->flags);
264 /* ------------------------------------------------------------------- */
266 * Make the controller start grabbing images. Everything must
267 * be set up before doing this.
269 static void mcam_ctlr_start(struct mcam_camera *cam)
271 /* set_bit performs a read, so no other barrier should be
273 mcam_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
276 static void mcam_ctlr_stop(struct mcam_camera *cam)
278 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
281 static void mcam_enable_mipi(struct mcam_camera *mcam)
283 /* Using MIPI mode and enable MIPI */
284 cam_dbg(mcam, "camera: DPHY3=0x%x, DPHY5=0x%x, DPHY6=0x%x\n",
285 mcam->dphy[0], mcam->dphy[1], mcam->dphy[2]);
286 mcam_reg_write(mcam, REG_CSI2_DPHY3, mcam->dphy[0]);
287 mcam_reg_write(mcam, REG_CSI2_DPHY5, mcam->dphy[1]);
288 mcam_reg_write(mcam, REG_CSI2_DPHY6, mcam->dphy[2]);
290 if (!mcam->mipi_enabled) {
291 if (mcam->lane > 4 || mcam->lane <= 0) {
292 cam_warn(mcam, "lane number error\n");
293 mcam->lane = 1; /* set the default value */
296 * 0x41 actives 1 lane
297 * 0x43 actives 2 lanes
298 * 0x45 actives 3 lanes (never happen)
299 * 0x47 actives 4 lanes
301 mcam_reg_write(mcam, REG_CSI2_CTRL0,
302 CSI2_C0_MIPI_EN | CSI2_C0_ACT_LANE(mcam->lane));
303 mcam_reg_write(mcam, REG_CLKCTRL,
304 (mcam->mclk_src << 29) | mcam->mclk_div);
306 mcam->mipi_enabled = true;
310 static void mcam_disable_mipi(struct mcam_camera *mcam)
312 /* Using Parallel mode or disable MIPI */
313 mcam_reg_write(mcam, REG_CSI2_CTRL0, 0x0);
314 mcam_reg_write(mcam, REG_CSI2_DPHY3, 0x0);
315 mcam_reg_write(mcam, REG_CSI2_DPHY5, 0x0);
316 mcam_reg_write(mcam, REG_CSI2_DPHY6, 0x0);
317 mcam->mipi_enabled = false;
320 static bool mcam_fmt_is_planar(__u32 pfmt)
322 struct mcam_format_struct *f;
324 f = mcam_find_format(pfmt);
328 static void mcam_write_yuv_bases(struct mcam_camera *cam,
329 unsigned frame, dma_addr_t base)
331 struct v4l2_pix_format *fmt = &cam->pix_format;
332 u32 pixel_count = fmt->width * fmt->height;
333 dma_addr_t y, u = 0, v = 0;
337 switch (fmt->pixelformat) {
338 case V4L2_PIX_FMT_YUV420:
340 v = u + pixel_count / 4;
342 case V4L2_PIX_FMT_YVU420:
344 u = v + pixel_count / 4;
350 mcam_reg_write(cam, REG_Y0BAR + frame * 4, y);
351 if (mcam_fmt_is_planar(fmt->pixelformat)) {
352 mcam_reg_write(cam, REG_U0BAR + frame * 4, u);
353 mcam_reg_write(cam, REG_V0BAR + frame * 4, v);
357 /* ------------------------------------------------------------------- */
359 #ifdef MCAM_MODE_VMALLOC
361 * Code specific to the vmalloc buffer mode.
365 * Allocate in-kernel DMA buffers for vmalloc mode.
367 static int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
371 mcam_set_config_needed(cam, 1);
373 cam->dma_buf_size = dma_buf_size;
375 cam->dma_buf_size = cam->pix_format.sizeimage;
380 for (i = 0; i < n_dma_bufs; i++) {
381 cam->dma_bufs[i] = dma_alloc_coherent(cam->dev,
382 cam->dma_buf_size, cam->dma_handles + i,
384 if (cam->dma_bufs[i] == NULL) {
385 cam_warn(cam, "Failed to allocate DMA buffer\n");
391 switch (cam->nbufs) {
393 dma_free_coherent(cam->dev, cam->dma_buf_size,
394 cam->dma_bufs[0], cam->dma_handles[0]);
398 cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
403 cam_warn(cam, "Will limp along with only 2 buffers\n");
409 static void mcam_free_dma_bufs(struct mcam_camera *cam)
413 for (i = 0; i < cam->nbufs; i++) {
414 dma_free_coherent(cam->dev, cam->dma_buf_size,
415 cam->dma_bufs[i], cam->dma_handles[i]);
416 cam->dma_bufs[i] = NULL;
423 * Set up DMA buffers when operating in vmalloc mode
425 static void mcam_ctlr_dma_vmalloc(struct mcam_camera *cam)
428 * Store the first two YUV buffers. Then either
429 * set the third if it exists, or tell the controller
432 mcam_write_yuv_bases(cam, 0, cam->dma_handles[0]);
433 mcam_write_yuv_bases(cam, 1, cam->dma_handles[1]);
434 if (cam->nbufs > 2) {
435 mcam_write_yuv_bases(cam, 2, cam->dma_handles[2]);
436 mcam_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
438 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
439 if (cam->chip_id == MCAM_CAFE)
440 mcam_reg_write(cam, REG_UBAR, 0); /* 32 bits only */
444 * Copy data out to user space in the vmalloc case
446 static void mcam_frame_tasklet(unsigned long data)
448 struct mcam_camera *cam = (struct mcam_camera *) data;
451 struct mcam_vb_buffer *buf;
453 spin_lock_irqsave(&cam->dev_lock, flags);
454 for (i = 0; i < cam->nbufs; i++) {
455 int bufno = cam->next_buf;
457 if (cam->state != S_STREAMING || bufno < 0)
458 break; /* I/O got stopped */
459 if (++(cam->next_buf) >= cam->nbufs)
461 if (!test_bit(bufno, &cam->flags))
463 if (list_empty(&cam->buffers)) {
464 cam->frame_state.singles++;
465 break; /* Leave it valid, hope for better later */
467 cam->frame_state.delivered++;
468 clear_bit(bufno, &cam->flags);
469 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
471 list_del_init(&buf->queue);
473 * Drop the lock during the big copy. This *should* be safe...
475 spin_unlock_irqrestore(&cam->dev_lock, flags);
476 memcpy(vb2_plane_vaddr(&buf->vb_buf.vb2_buf, 0),
477 cam->dma_bufs[bufno],
478 cam->pix_format.sizeimage);
479 mcam_buffer_done(cam, bufno, &buf->vb_buf);
480 spin_lock_irqsave(&cam->dev_lock, flags);
482 spin_unlock_irqrestore(&cam->dev_lock, flags);
487 * Make sure our allocated buffers are up to the task.
489 static int mcam_check_dma_buffers(struct mcam_camera *cam)
491 if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
492 mcam_free_dma_bufs(cam);
494 return mcam_alloc_dma_bufs(cam, 0);
498 static void mcam_vmalloc_done(struct mcam_camera *cam, int frame)
500 tasklet_schedule(&cam->s_tasklet);
503 #else /* MCAM_MODE_VMALLOC */
505 static inline int mcam_alloc_dma_bufs(struct mcam_camera *cam, int loadtime)
510 static inline void mcam_free_dma_bufs(struct mcam_camera *cam)
515 static inline int mcam_check_dma_buffers(struct mcam_camera *cam)
522 #endif /* MCAM_MODE_VMALLOC */
525 #ifdef MCAM_MODE_DMA_CONTIG
526 /* ---------------------------------------------------------------------- */
528 * DMA-contiguous code.
532 * Set up a contiguous buffer for the given frame. Here also is where
533 * the underrun strategy is set: if there is no buffer available, reuse
534 * the buffer from the other BAR and set the CF_SINGLE_BUFFER flag to
535 * keep the interrupt handler from giving that buffer back to user
536 * space. In this way, we always have a buffer to DMA to and don't
537 * have to try to play games stopping and restarting the controller.
539 static void mcam_set_contig_buffer(struct mcam_camera *cam, int frame)
541 struct mcam_vb_buffer *buf;
542 dma_addr_t dma_handle;
543 struct vb2_v4l2_buffer *vb;
546 * If there are no available buffers, go into single mode
548 if (list_empty(&cam->buffers)) {
549 buf = cam->vb_bufs[frame ^ 0x1];
550 set_bit(CF_SINGLE_BUFFER, &cam->flags);
551 cam->frame_state.singles++;
554 * OK, we have a buffer we can use.
556 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer,
558 list_del_init(&buf->queue);
559 clear_bit(CF_SINGLE_BUFFER, &cam->flags);
562 cam->vb_bufs[frame] = buf;
565 dma_handle = vb2_dma_contig_plane_dma_addr(&vb->vb2_buf, 0);
566 mcam_write_yuv_bases(cam, frame, dma_handle);
570 * Initial B_DMA_contig setup.
572 static void mcam_ctlr_dma_contig(struct mcam_camera *cam)
574 mcam_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
576 mcam_set_contig_buffer(cam, 0);
577 mcam_set_contig_buffer(cam, 1);
581 * Frame completion handling.
583 static void mcam_dma_contig_done(struct mcam_camera *cam, int frame)
585 struct mcam_vb_buffer *buf = cam->vb_bufs[frame];
587 if (!test_bit(CF_SINGLE_BUFFER, &cam->flags)) {
588 cam->frame_state.delivered++;
589 cam->vb_bufs[frame] = NULL;
590 mcam_buffer_done(cam, frame, &buf->vb_buf);
592 mcam_set_contig_buffer(cam, frame);
595 #endif /* MCAM_MODE_DMA_CONTIG */
597 #ifdef MCAM_MODE_DMA_SG
598 /* ---------------------------------------------------------------------- */
600 * Scatter/gather-specific code.
604 * Set up the next buffer for S/G I/O; caller should be sure that
605 * the controller is stopped and a buffer is available.
607 static void mcam_sg_next_buffer(struct mcam_camera *cam)
609 struct mcam_vb_buffer *buf;
611 buf = list_first_entry(&cam->buffers, struct mcam_vb_buffer, queue);
612 list_del_init(&buf->queue);
614 * Very Bad Not Good Things happen if you don't clear
615 * C1_DESC_ENA before making any descriptor changes.
617 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_ENA);
618 mcam_reg_write(cam, REG_DMA_DESC_Y, buf->dma_desc_pa);
619 mcam_reg_write(cam, REG_DESC_LEN_Y,
620 buf->dma_desc_nent*sizeof(struct mcam_dma_desc));
621 mcam_reg_write(cam, REG_DESC_LEN_U, 0);
622 mcam_reg_write(cam, REG_DESC_LEN_V, 0);
623 mcam_reg_set_bit(cam, REG_CTRL1, C1_DESC_ENA);
624 cam->vb_bufs[0] = buf;
628 * Initial B_DMA_sg setup
630 static void mcam_ctlr_dma_sg(struct mcam_camera *cam)
633 * The list-empty condition can hit us at resume time
634 * if the buffer list was empty when the system was suspended.
636 if (list_empty(&cam->buffers)) {
637 set_bit(CF_SG_RESTART, &cam->flags);
641 mcam_reg_clear_bit(cam, REG_CTRL1, C1_DESC_3WORD);
642 mcam_sg_next_buffer(cam);
648 * Frame completion with S/G is trickier. We can't muck with
649 * a descriptor chain on the fly, since the controller buffers it
650 * internally. So we have to actually stop and restart; Marvell
651 * says this is the way to do it.
653 * Of course, stopping is easier said than done; experience shows
654 * that the controller can start a frame *after* C0_ENABLE has been
655 * cleared. So when running in S/G mode, the controller is "stopped"
656 * on receipt of the start-of-frame interrupt. That means we can
657 * safely change the DMA descriptor array here and restart things
658 * (assuming there's another buffer waiting to go).
660 static void mcam_dma_sg_done(struct mcam_camera *cam, int frame)
662 struct mcam_vb_buffer *buf = cam->vb_bufs[0];
665 * If we're no longer supposed to be streaming, don't do anything.
667 if (cam->state != S_STREAMING)
670 * If we have another buffer available, put it in and
671 * restart the engine.
673 if (!list_empty(&cam->buffers)) {
674 mcam_sg_next_buffer(cam);
675 mcam_ctlr_start(cam);
677 * Otherwise set CF_SG_RESTART and the controller will
678 * be restarted once another buffer shows up.
681 set_bit(CF_SG_RESTART, &cam->flags);
682 cam->frame_state.singles++;
683 cam->vb_bufs[0] = NULL;
686 * Now we can give the completed frame back to user space.
688 cam->frame_state.delivered++;
689 mcam_buffer_done(cam, frame, &buf->vb_buf);
694 * Scatter/gather mode requires stopping the controller between
695 * frames so we can put in a new DMA descriptor array. If no new
696 * buffer exists at frame completion, the controller is left stopped;
697 * this function is charged with gettig things going again.
699 static void mcam_sg_restart(struct mcam_camera *cam)
701 mcam_ctlr_dma_sg(cam);
702 mcam_ctlr_start(cam);
703 clear_bit(CF_SG_RESTART, &cam->flags);
706 #else /* MCAM_MODE_DMA_SG */
708 static inline void mcam_sg_restart(struct mcam_camera *cam)
713 #endif /* MCAM_MODE_DMA_SG */
715 /* ---------------------------------------------------------------------- */
717 * Buffer-mode-independent controller code.
723 static void mcam_ctlr_image(struct mcam_camera *cam)
725 struct v4l2_pix_format *fmt = &cam->pix_format;
726 u32 widthy = 0, widthuv = 0, imgsz_h, imgsz_w;
728 cam_dbg(cam, "camera: bytesperline = %d; height = %d\n",
729 fmt->bytesperline, fmt->sizeimage / fmt->bytesperline);
730 imgsz_h = (fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK;
731 imgsz_w = (fmt->width * 2) & IMGSZ_H_MASK;
733 switch (fmt->pixelformat) {
734 case V4L2_PIX_FMT_YUYV:
735 case V4L2_PIX_FMT_YVYU:
736 widthy = fmt->width * 2;
739 case V4L2_PIX_FMT_YUV420:
740 case V4L2_PIX_FMT_YVU420:
742 widthuv = fmt->width / 2;
745 widthy = fmt->bytesperline;
750 mcam_reg_write_mask(cam, REG_IMGPITCH, widthuv << 16 | widthy,
751 IMGP_YP_MASK | IMGP_UVP_MASK);
752 mcam_reg_write(cam, REG_IMGSIZE, imgsz_h | imgsz_w);
753 mcam_reg_write(cam, REG_IMGOFFSET, 0x0);
756 * Tell the controller about the image format we are using.
758 switch (fmt->pixelformat) {
759 case V4L2_PIX_FMT_YUV420:
760 case V4L2_PIX_FMT_YVU420:
761 mcam_reg_write_mask(cam, REG_CTRL0,
762 C0_DF_YUV | C0_YUV_420PL | C0_YUVE_VYUY, C0_DF_MASK);
764 case V4L2_PIX_FMT_YUYV:
765 mcam_reg_write_mask(cam, REG_CTRL0,
766 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_NOSWAP, C0_DF_MASK);
768 case V4L2_PIX_FMT_YVYU:
769 mcam_reg_write_mask(cam, REG_CTRL0,
770 C0_DF_YUV | C0_YUV_PACKED | C0_YUVE_SWAP24, C0_DF_MASK);
772 case V4L2_PIX_FMT_XRGB444:
773 mcam_reg_write_mask(cam, REG_CTRL0,
774 C0_DF_RGB | C0_RGBF_444 | C0_RGB4_XBGR, C0_DF_MASK);
776 case V4L2_PIX_FMT_RGB565:
777 mcam_reg_write_mask(cam, REG_CTRL0,
778 C0_DF_RGB | C0_RGBF_565 | C0_RGB5_BGGR, C0_DF_MASK);
780 case V4L2_PIX_FMT_SBGGR8:
781 mcam_reg_write_mask(cam, REG_CTRL0,
782 C0_DF_RGB | C0_RGB5_GRBG, C0_DF_MASK);
785 cam_err(cam, "camera: unknown format: %#x\n", fmt->pixelformat);
790 * Make sure it knows we want to use hsync/vsync.
792 mcam_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC, C0_SIFM_MASK);
794 * This field controls the generation of EOF(DVP only)
796 if (cam->bus_type != V4L2_MBUS_CSI2)
797 mcam_reg_set_bit(cam, REG_CTRL0,
798 C0_EOF_VSYNC | C0_VEDGE_CTRL);
803 * Configure the controller for operation; caller holds the
806 static int mcam_ctlr_configure(struct mcam_camera *cam)
810 spin_lock_irqsave(&cam->dev_lock, flags);
811 clear_bit(CF_SG_RESTART, &cam->flags);
813 mcam_ctlr_image(cam);
814 mcam_set_config_needed(cam, 0);
815 spin_unlock_irqrestore(&cam->dev_lock, flags);
819 static void mcam_ctlr_irq_enable(struct mcam_camera *cam)
822 * Clear any pending interrupts, since we do not
823 * expect to have I/O active prior to enabling.
825 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
826 mcam_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
829 static void mcam_ctlr_irq_disable(struct mcam_camera *cam)
831 mcam_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
836 static void mcam_ctlr_init(struct mcam_camera *cam)
840 spin_lock_irqsave(&cam->dev_lock, flags);
842 * Make sure it's not powered down.
844 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
846 * Turn off the enable bit. It sure should be off anyway,
847 * but it's good to be sure.
849 mcam_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
851 * Clock the sensor appropriately. Controller clock should
852 * be 48MHz, sensor "typical" value is half that.
854 mcam_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
855 spin_unlock_irqrestore(&cam->dev_lock, flags);
860 * Stop the controller, and don't return until we're really sure that no
861 * further DMA is going on.
863 static void mcam_ctlr_stop_dma(struct mcam_camera *cam)
868 * Theory: stop the camera controller (whether it is operating
869 * or not). Delay briefly just in case we race with the SOF
870 * interrupt, then wait until no DMA is active.
872 spin_lock_irqsave(&cam->dev_lock, flags);
873 clear_bit(CF_SG_RESTART, &cam->flags);
876 spin_unlock_irqrestore(&cam->dev_lock, flags);
878 * This is a brutally long sleep, but experience shows that
879 * it can take the controller a while to get the message that
880 * it needs to stop grabbing frames. In particular, we can
881 * sometimes (on mmp) get a frame at the end WITHOUT the
882 * start-of-frame indication.
885 if (test_bit(CF_DMA_ACTIVE, &cam->flags))
886 cam_err(cam, "Timeout waiting for DMA to end\n");
887 /* This would be bad news - what now? */
888 spin_lock_irqsave(&cam->dev_lock, flags);
889 mcam_ctlr_irq_disable(cam);
890 spin_unlock_irqrestore(&cam->dev_lock, flags);
896 static int mcam_ctlr_power_up(struct mcam_camera *cam)
901 spin_lock_irqsave(&cam->dev_lock, flags);
902 ret = cam->plat_power_up(cam);
904 spin_unlock_irqrestore(&cam->dev_lock, flags);
907 mcam_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
908 spin_unlock_irqrestore(&cam->dev_lock, flags);
909 msleep(5); /* Just to be sure */
913 static void mcam_ctlr_power_down(struct mcam_camera *cam)
917 spin_lock_irqsave(&cam->dev_lock, flags);
919 * School of hard knocks department: be sure we do any register
920 * twiddling on the controller *before* calling the platform
921 * power down routine.
923 mcam_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
924 cam->plat_power_down(cam);
925 spin_unlock_irqrestore(&cam->dev_lock, flags);
928 /* -------------------------------------------------------------------- */
930 * Communications with the sensor.
933 static int __mcam_cam_reset(struct mcam_camera *cam)
935 return sensor_call(cam, core, reset, 0);
939 * We have found the sensor on the i2c. Let's try to have a
942 static int mcam_cam_init(struct mcam_camera *cam)
946 if (cam->state != S_NOTREADY)
947 cam_warn(cam, "Cam init with device in funky state %d",
949 ret = __mcam_cam_reset(cam);
950 /* Get/set parameters? */
952 mcam_ctlr_power_down(cam);
957 * Configure the sensor to match the parameters we have. Caller should
960 static int mcam_cam_set_flip(struct mcam_camera *cam)
962 struct v4l2_control ctrl;
964 memset(&ctrl, 0, sizeof(ctrl));
965 ctrl.id = V4L2_CID_VFLIP;
967 return v4l2_s_ctrl(NULL, cam->sensor->ctrl_handler, &ctrl);
971 static int mcam_cam_configure(struct mcam_camera *cam)
973 struct v4l2_subdev_format format = {
974 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
978 v4l2_fill_mbus_format(&format.format, &cam->pix_format, cam->mbus_code);
979 ret = sensor_call(cam, core, init, 0);
981 ret = sensor_call(cam, pad, set_fmt, NULL, &format);
983 * OV7670 does weird things if flip is set *before* format...
985 ret += mcam_cam_set_flip(cam);
990 * Get everything ready, and start grabbing frames.
992 static int mcam_read_setup(struct mcam_camera *cam)
998 * Configuration. If we still don't have DMA buffers,
999 * make one last, desperate attempt.
1001 if (cam->buffer_mode == B_vmalloc && cam->nbufs == 0 &&
1002 mcam_alloc_dma_bufs(cam, 0))
1005 if (mcam_needs_config(cam)) {
1006 mcam_cam_configure(cam);
1007 ret = mcam_ctlr_configure(cam);
1015 spin_lock_irqsave(&cam->dev_lock, flags);
1016 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1017 mcam_reset_buffers(cam);
1019 * Update CSI2_DPHY value
1022 cam->calc_dphy(cam);
1023 cam_dbg(cam, "camera: DPHY sets: dphy3=0x%x, dphy5=0x%x, dphy6=0x%x\n",
1024 cam->dphy[0], cam->dphy[1], cam->dphy[2]);
1025 if (cam->bus_type == V4L2_MBUS_CSI2)
1026 mcam_enable_mipi(cam);
1028 mcam_disable_mipi(cam);
1029 mcam_ctlr_irq_enable(cam);
1030 cam->state = S_STREAMING;
1031 if (!test_bit(CF_SG_RESTART, &cam->flags))
1032 mcam_ctlr_start(cam);
1033 spin_unlock_irqrestore(&cam->dev_lock, flags);
1037 /* ----------------------------------------------------------------------- */
1039 * Videobuf2 interface code.
1042 static int mcam_vb_queue_setup(struct vb2_queue *vq,
1043 unsigned int *nbufs,
1044 unsigned int *num_planes, unsigned int sizes[],
1045 struct device *alloc_devs[])
1047 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1048 int minbufs = (cam->buffer_mode == B_DMA_contig) ? 3 : 2;
1049 unsigned size = cam->pix_format.sizeimage;
1051 if (*nbufs < minbufs)
1055 return sizes[0] < size ? -EINVAL : 0;
1057 *num_planes = 1; /* Someday we have to support planar formats... */
1062 static void mcam_vb_buf_queue(struct vb2_buffer *vb)
1064 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1065 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1066 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1067 unsigned long flags;
1070 spin_lock_irqsave(&cam->dev_lock, flags);
1071 start = (cam->state == S_BUFWAIT) && !list_empty(&cam->buffers);
1072 list_add(&mvb->queue, &cam->buffers);
1073 if (cam->state == S_STREAMING && test_bit(CF_SG_RESTART, &cam->flags))
1074 mcam_sg_restart(cam);
1075 spin_unlock_irqrestore(&cam->dev_lock, flags);
1077 mcam_read_setup(cam);
1080 static void mcam_vb_requeue_bufs(struct vb2_queue *vq,
1081 enum vb2_buffer_state state)
1083 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1084 struct mcam_vb_buffer *buf, *node;
1085 unsigned long flags;
1088 spin_lock_irqsave(&cam->dev_lock, flags);
1089 list_for_each_entry_safe(buf, node, &cam->buffers, queue) {
1090 vb2_buffer_done(&buf->vb_buf.vb2_buf, state);
1091 list_del(&buf->queue);
1093 for (i = 0; i < MAX_DMA_BUFS; i++) {
1094 buf = cam->vb_bufs[i];
1097 vb2_buffer_done(&buf->vb_buf.vb2_buf, state);
1098 cam->vb_bufs[i] = NULL;
1101 spin_unlock_irqrestore(&cam->dev_lock, flags);
1105 * These need to be called with the mutex held from vb2
1107 static int mcam_vb_start_streaming(struct vb2_queue *vq, unsigned int count)
1109 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1113 if (cam->state != S_IDLE) {
1114 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1117 cam->frame_state.frames = 0;
1118 cam->frame_state.singles = 0;
1119 cam->frame_state.delivered = 0;
1122 * Videobuf2 sneakily hoards all the buffers and won't
1123 * give them to us until *after* streaming starts. But
1124 * we can't actually start streaming until we have a
1125 * destination. So go into a wait state and hope they
1126 * give us buffers soon.
1128 if (cam->buffer_mode != B_vmalloc && list_empty(&cam->buffers)) {
1129 cam->state = S_BUFWAIT;
1134 * Ensure clear the left over frame flags
1135 * before every really start streaming
1137 for (frame = 0; frame < cam->nbufs; frame++)
1138 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1140 ret = mcam_read_setup(cam);
1142 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_QUEUED);
1146 static void mcam_vb_stop_streaming(struct vb2_queue *vq)
1148 struct mcam_camera *cam = vb2_get_drv_priv(vq);
1150 cam_dbg(cam, "stop_streaming: %d frames, %d singles, %d delivered\n",
1151 cam->frame_state.frames, cam->frame_state.singles,
1152 cam->frame_state.delivered);
1153 if (cam->state == S_BUFWAIT) {
1154 /* They never gave us buffers */
1155 cam->state = S_IDLE;
1158 if (cam->state != S_STREAMING)
1160 mcam_ctlr_stop_dma(cam);
1162 * Reset the CCIC PHY after stopping streaming,
1163 * otherwise, the CCIC may be unstable.
1165 if (cam->ctlr_reset)
1166 cam->ctlr_reset(cam);
1168 * VB2 reclaims the buffers, so we need to forget
1171 mcam_vb_requeue_bufs(vq, VB2_BUF_STATE_ERROR);
1175 static const struct vb2_ops mcam_vb2_ops = {
1176 .queue_setup = mcam_vb_queue_setup,
1177 .buf_queue = mcam_vb_buf_queue,
1178 .start_streaming = mcam_vb_start_streaming,
1179 .stop_streaming = mcam_vb_stop_streaming,
1180 .wait_prepare = vb2_ops_wait_prepare,
1181 .wait_finish = vb2_ops_wait_finish,
1185 #ifdef MCAM_MODE_DMA_SG
1187 * Scatter/gather mode uses all of the above functions plus a
1188 * few extras to deal with DMA mapping.
1190 static int mcam_vb_sg_buf_init(struct vb2_buffer *vb)
1192 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1193 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1194 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1195 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1197 mvb->dma_desc = dma_alloc_coherent(cam->dev,
1198 ndesc * sizeof(struct mcam_dma_desc),
1199 &mvb->dma_desc_pa, GFP_KERNEL);
1200 if (mvb->dma_desc == NULL) {
1201 cam_err(cam, "Unable to get DMA descriptor array\n");
1207 static int mcam_vb_sg_buf_prepare(struct vb2_buffer *vb)
1209 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1210 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1211 struct sg_table *sg_table = vb2_dma_sg_plane_desc(vb, 0);
1212 struct mcam_dma_desc *desc = mvb->dma_desc;
1213 struct scatterlist *sg;
1216 for_each_sg(sg_table->sgl, sg, sg_table->nents, i) {
1217 desc->dma_addr = sg_dma_address(sg);
1218 desc->segment_len = sg_dma_len(sg);
1224 static void mcam_vb_sg_buf_cleanup(struct vb2_buffer *vb)
1226 struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
1227 struct mcam_camera *cam = vb2_get_drv_priv(vb->vb2_queue);
1228 struct mcam_vb_buffer *mvb = vb_to_mvb(vbuf);
1229 int ndesc = cam->pix_format.sizeimage/PAGE_SIZE + 1;
1231 dma_free_coherent(cam->dev, ndesc * sizeof(struct mcam_dma_desc),
1232 mvb->dma_desc, mvb->dma_desc_pa);
1236 static const struct vb2_ops mcam_vb2_sg_ops = {
1237 .queue_setup = mcam_vb_queue_setup,
1238 .buf_init = mcam_vb_sg_buf_init,
1239 .buf_prepare = mcam_vb_sg_buf_prepare,
1240 .buf_queue = mcam_vb_buf_queue,
1241 .buf_cleanup = mcam_vb_sg_buf_cleanup,
1242 .start_streaming = mcam_vb_start_streaming,
1243 .stop_streaming = mcam_vb_stop_streaming,
1244 .wait_prepare = vb2_ops_wait_prepare,
1245 .wait_finish = vb2_ops_wait_finish,
1248 #endif /* MCAM_MODE_DMA_SG */
1250 static int mcam_setup_vb2(struct mcam_camera *cam)
1252 struct vb2_queue *vq = &cam->vb_queue;
1254 memset(vq, 0, sizeof(*vq));
1255 vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
1257 vq->lock = &cam->s_mutex;
1258 vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1259 vq->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF | VB2_READ;
1260 vq->buf_struct_size = sizeof(struct mcam_vb_buffer);
1262 INIT_LIST_HEAD(&cam->buffers);
1263 switch (cam->buffer_mode) {
1265 #ifdef MCAM_MODE_DMA_CONTIG
1266 vq->ops = &mcam_vb2_ops;
1267 vq->mem_ops = &vb2_dma_contig_memops;
1268 cam->dma_setup = mcam_ctlr_dma_contig;
1269 cam->frame_complete = mcam_dma_contig_done;
1273 #ifdef MCAM_MODE_DMA_SG
1274 vq->ops = &mcam_vb2_sg_ops;
1275 vq->mem_ops = &vb2_dma_sg_memops;
1276 cam->dma_setup = mcam_ctlr_dma_sg;
1277 cam->frame_complete = mcam_dma_sg_done;
1281 #ifdef MCAM_MODE_VMALLOC
1282 tasklet_init(&cam->s_tasklet, mcam_frame_tasklet,
1283 (unsigned long) cam);
1284 vq->ops = &mcam_vb2_ops;
1285 vq->mem_ops = &vb2_vmalloc_memops;
1286 cam->dma_setup = mcam_ctlr_dma_vmalloc;
1287 cam->frame_complete = mcam_vmalloc_done;
1291 return vb2_queue_init(vq);
1295 /* ---------------------------------------------------------------------- */
1297 * The long list of V4L2 ioctl() operations.
1300 static int mcam_vidioc_querycap(struct file *file, void *priv,
1301 struct v4l2_capability *cap)
1303 struct mcam_camera *cam = video_drvdata(file);
1305 strcpy(cap->driver, "marvell_ccic");
1306 strcpy(cap->card, "marvell_ccic");
1307 strlcpy(cap->bus_info, cam->bus_info, sizeof(cap->bus_info));
1308 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE |
1309 V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
1310 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1315 static int mcam_vidioc_enum_fmt_vid_cap(struct file *filp,
1316 void *priv, struct v4l2_fmtdesc *fmt)
1318 if (fmt->index >= N_MCAM_FMTS)
1320 strlcpy(fmt->description, mcam_formats[fmt->index].desc,
1321 sizeof(fmt->description));
1322 fmt->pixelformat = mcam_formats[fmt->index].pixelformat;
1326 static int mcam_vidioc_try_fmt_vid_cap(struct file *filp, void *priv,
1327 struct v4l2_format *fmt)
1329 struct mcam_camera *cam = video_drvdata(filp);
1330 struct mcam_format_struct *f;
1331 struct v4l2_pix_format *pix = &fmt->fmt.pix;
1332 struct v4l2_subdev_pad_config pad_cfg;
1333 struct v4l2_subdev_format format = {
1334 .which = V4L2_SUBDEV_FORMAT_TRY,
1338 f = mcam_find_format(pix->pixelformat);
1339 pix->pixelformat = f->pixelformat;
1340 v4l2_fill_mbus_format(&format.format, pix, f->mbus_code);
1341 ret = sensor_call(cam, pad, set_fmt, &pad_cfg, &format);
1342 v4l2_fill_pix_format(pix, &format.format);
1343 pix->bytesperline = pix->width * f->bpp;
1344 switch (f->pixelformat) {
1345 case V4L2_PIX_FMT_YUV420:
1346 case V4L2_PIX_FMT_YVU420:
1347 pix->sizeimage = pix->height * pix->bytesperline * 3 / 2;
1350 pix->sizeimage = pix->height * pix->bytesperline;
1353 pix->colorspace = V4L2_COLORSPACE_SRGB;
1357 static int mcam_vidioc_s_fmt_vid_cap(struct file *filp, void *priv,
1358 struct v4l2_format *fmt)
1360 struct mcam_camera *cam = video_drvdata(filp);
1361 struct mcam_format_struct *f;
1365 * Can't do anything if the device is not idle
1366 * Also can't if there are streaming buffers in place.
1368 if (cam->state != S_IDLE || vb2_is_busy(&cam->vb_queue))
1371 f = mcam_find_format(fmt->fmt.pix.pixelformat);
1374 * See if the formatting works in principle.
1376 ret = mcam_vidioc_try_fmt_vid_cap(filp, priv, fmt);
1380 * Now we start to change things for real, so let's do it
1383 cam->pix_format = fmt->fmt.pix;
1384 cam->mbus_code = f->mbus_code;
1387 * Make sure we have appropriate DMA buffers.
1389 if (cam->buffer_mode == B_vmalloc) {
1390 ret = mcam_check_dma_buffers(cam);
1394 mcam_set_config_needed(cam, 1);
1400 * Return our stored notion of how the camera is/should be configured.
1401 * The V4l2 spec wants us to be smarter, and actually get this from
1402 * the camera (and not mess with it at open time). Someday.
1404 static int mcam_vidioc_g_fmt_vid_cap(struct file *filp, void *priv,
1405 struct v4l2_format *f)
1407 struct mcam_camera *cam = video_drvdata(filp);
1409 f->fmt.pix = cam->pix_format;
1414 * We only have one input - the sensor - so minimize the nonsense here.
1416 static int mcam_vidioc_enum_input(struct file *filp, void *priv,
1417 struct v4l2_input *input)
1419 if (input->index != 0)
1422 input->type = V4L2_INPUT_TYPE_CAMERA;
1423 strcpy(input->name, "Camera");
1427 static int mcam_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
1433 static int mcam_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
1441 * G/S_PARM. Most of this is done by the sensor, but we are
1442 * the level which controls the number of read buffers.
1444 static int mcam_vidioc_g_parm(struct file *filp, void *priv,
1445 struct v4l2_streamparm *parms)
1447 struct mcam_camera *cam = video_drvdata(filp);
1450 ret = sensor_call(cam, video, g_parm, parms);
1451 parms->parm.capture.readbuffers = n_dma_bufs;
1455 static int mcam_vidioc_s_parm(struct file *filp, void *priv,
1456 struct v4l2_streamparm *parms)
1458 struct mcam_camera *cam = video_drvdata(filp);
1461 ret = sensor_call(cam, video, s_parm, parms);
1462 parms->parm.capture.readbuffers = n_dma_bufs;
1466 static int mcam_vidioc_enum_framesizes(struct file *filp, void *priv,
1467 struct v4l2_frmsizeenum *sizes)
1469 struct mcam_camera *cam = video_drvdata(filp);
1470 struct mcam_format_struct *f;
1471 struct v4l2_subdev_frame_size_enum fse = {
1472 .index = sizes->index,
1473 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1477 f = mcam_find_format(sizes->pixel_format);
1478 if (f->pixelformat != sizes->pixel_format)
1480 fse.code = f->mbus_code;
1481 ret = sensor_call(cam, pad, enum_frame_size, NULL, &fse);
1484 if (fse.min_width == fse.max_width &&
1485 fse.min_height == fse.max_height) {
1486 sizes->type = V4L2_FRMSIZE_TYPE_DISCRETE;
1487 sizes->discrete.width = fse.min_width;
1488 sizes->discrete.height = fse.min_height;
1491 sizes->type = V4L2_FRMSIZE_TYPE_CONTINUOUS;
1492 sizes->stepwise.min_width = fse.min_width;
1493 sizes->stepwise.max_width = fse.max_width;
1494 sizes->stepwise.min_height = fse.min_height;
1495 sizes->stepwise.max_height = fse.max_height;
1496 sizes->stepwise.step_width = 1;
1497 sizes->stepwise.step_height = 1;
1501 static int mcam_vidioc_enum_frameintervals(struct file *filp, void *priv,
1502 struct v4l2_frmivalenum *interval)
1504 struct mcam_camera *cam = video_drvdata(filp);
1505 struct mcam_format_struct *f;
1506 struct v4l2_subdev_frame_interval_enum fie = {
1507 .index = interval->index,
1508 .width = interval->width,
1509 .height = interval->height,
1510 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1514 f = mcam_find_format(interval->pixel_format);
1515 if (f->pixelformat != interval->pixel_format)
1517 fie.code = f->mbus_code;
1518 ret = sensor_call(cam, pad, enum_frame_interval, NULL, &fie);
1521 interval->type = V4L2_FRMIVAL_TYPE_DISCRETE;
1522 interval->discrete = fie.interval;
1526 #ifdef CONFIG_VIDEO_ADV_DEBUG
1527 static int mcam_vidioc_g_register(struct file *file, void *priv,
1528 struct v4l2_dbg_register *reg)
1530 struct mcam_camera *cam = video_drvdata(file);
1532 if (reg->reg > cam->regs_size - 4)
1534 reg->val = mcam_reg_read(cam, reg->reg);
1539 static int mcam_vidioc_s_register(struct file *file, void *priv,
1540 const struct v4l2_dbg_register *reg)
1542 struct mcam_camera *cam = video_drvdata(file);
1544 if (reg->reg > cam->regs_size - 4)
1546 mcam_reg_write(cam, reg->reg, reg->val);
1551 static const struct v4l2_ioctl_ops mcam_v4l_ioctl_ops = {
1552 .vidioc_querycap = mcam_vidioc_querycap,
1553 .vidioc_enum_fmt_vid_cap = mcam_vidioc_enum_fmt_vid_cap,
1554 .vidioc_try_fmt_vid_cap = mcam_vidioc_try_fmt_vid_cap,
1555 .vidioc_s_fmt_vid_cap = mcam_vidioc_s_fmt_vid_cap,
1556 .vidioc_g_fmt_vid_cap = mcam_vidioc_g_fmt_vid_cap,
1557 .vidioc_enum_input = mcam_vidioc_enum_input,
1558 .vidioc_g_input = mcam_vidioc_g_input,
1559 .vidioc_s_input = mcam_vidioc_s_input,
1560 .vidioc_reqbufs = vb2_ioctl_reqbufs,
1561 .vidioc_create_bufs = vb2_ioctl_create_bufs,
1562 .vidioc_querybuf = vb2_ioctl_querybuf,
1563 .vidioc_qbuf = vb2_ioctl_qbuf,
1564 .vidioc_dqbuf = vb2_ioctl_dqbuf,
1565 .vidioc_expbuf = vb2_ioctl_expbuf,
1566 .vidioc_streamon = vb2_ioctl_streamon,
1567 .vidioc_streamoff = vb2_ioctl_streamoff,
1568 .vidioc_g_parm = mcam_vidioc_g_parm,
1569 .vidioc_s_parm = mcam_vidioc_s_parm,
1570 .vidioc_enum_framesizes = mcam_vidioc_enum_framesizes,
1571 .vidioc_enum_frameintervals = mcam_vidioc_enum_frameintervals,
1572 .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
1573 .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1574 #ifdef CONFIG_VIDEO_ADV_DEBUG
1575 .vidioc_g_register = mcam_vidioc_g_register,
1576 .vidioc_s_register = mcam_vidioc_s_register,
1580 /* ---------------------------------------------------------------------- */
1582 * Our various file operations.
1584 static int mcam_v4l_open(struct file *filp)
1586 struct mcam_camera *cam = video_drvdata(filp);
1589 mutex_lock(&cam->s_mutex);
1590 ret = v4l2_fh_open(filp);
1593 if (v4l2_fh_is_singular_file(filp)) {
1594 ret = mcam_ctlr_power_up(cam);
1597 __mcam_cam_reset(cam);
1598 mcam_set_config_needed(cam, 1);
1601 mutex_unlock(&cam->s_mutex);
1603 v4l2_fh_release(filp);
1608 static int mcam_v4l_release(struct file *filp)
1610 struct mcam_camera *cam = video_drvdata(filp);
1613 mutex_lock(&cam->s_mutex);
1614 last_open = v4l2_fh_is_singular_file(filp);
1615 _vb2_fop_release(filp, NULL);
1617 mcam_disable_mipi(cam);
1618 mcam_ctlr_power_down(cam);
1619 if (cam->buffer_mode == B_vmalloc && alloc_bufs_at_read)
1620 mcam_free_dma_bufs(cam);
1623 mutex_unlock(&cam->s_mutex);
1627 static const struct v4l2_file_operations mcam_v4l_fops = {
1628 .owner = THIS_MODULE,
1629 .open = mcam_v4l_open,
1630 .release = mcam_v4l_release,
1631 .read = vb2_fop_read,
1632 .poll = vb2_fop_poll,
1633 .mmap = vb2_fop_mmap,
1634 .unlocked_ioctl = video_ioctl2,
1639 * This template device holds all of those v4l2 methods; we
1640 * clone it for specific real devices.
1642 static const struct video_device mcam_v4l_template = {
1644 .fops = &mcam_v4l_fops,
1645 .ioctl_ops = &mcam_v4l_ioctl_ops,
1646 .release = video_device_release_empty,
1649 /* ---------------------------------------------------------------------- */
1651 * Interrupt handler stuff
1653 static void mcam_frame_complete(struct mcam_camera *cam, int frame)
1656 * Basic frame housekeeping.
1658 set_bit(frame, &cam->flags);
1659 clear_bit(CF_DMA_ACTIVE, &cam->flags);
1660 cam->next_buf = frame;
1661 cam->buf_seq[frame] = cam->sequence++;
1662 cam->frame_state.frames++;
1664 * "This should never happen"
1666 if (cam->state != S_STREAMING)
1669 * Process the frame and set up the next one.
1671 cam->frame_complete(cam, frame);
1676 * The interrupt handler; this needs to be called from the
1677 * platform irq handler with the lock held.
1679 int mccic_irq(struct mcam_camera *cam, unsigned int irqs)
1681 unsigned int frame, handled = 0;
1683 mcam_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
1685 * Handle any frame completions. There really should
1686 * not be more than one of these, or we have fallen
1689 * When running in S/G mode, the frame number lacks any
1690 * real meaning - there's only one descriptor array - but
1691 * the controller still picks a different one to signal
1694 for (frame = 0; frame < cam->nbufs; frame++)
1695 if (irqs & (IRQ_EOF0 << frame) &&
1696 test_bit(CF_FRAME_SOF0 + frame, &cam->flags)) {
1697 mcam_frame_complete(cam, frame);
1699 clear_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1700 if (cam->buffer_mode == B_DMA_sg)
1704 * If a frame starts, note that we have DMA active. This
1705 * code assumes that we won't get multiple frame interrupts
1706 * at once; may want to rethink that.
1708 for (frame = 0; frame < cam->nbufs; frame++) {
1709 if (irqs & (IRQ_SOF0 << frame)) {
1710 set_bit(CF_FRAME_SOF0 + frame, &cam->flags);
1711 handled = IRQ_HANDLED;
1715 if (handled == IRQ_HANDLED) {
1716 set_bit(CF_DMA_ACTIVE, &cam->flags);
1717 if (cam->buffer_mode == B_DMA_sg)
1718 mcam_ctlr_stop(cam);
1723 /* ---------------------------------------------------------------------- */
1725 * Registration and such.
1727 static struct ov7670_config sensor_cfg = {
1729 * Exclude QCIF mode, because it only captures a tiny portion
1737 int mccic_register(struct mcam_camera *cam)
1739 struct i2c_board_info ov7670_info = {
1742 .platform_data = &sensor_cfg,
1747 * Validate the requested buffer mode.
1749 if (buffer_mode >= 0)
1750 cam->buffer_mode = buffer_mode;
1751 if (cam->buffer_mode == B_DMA_sg &&
1752 cam->chip_id == MCAM_CAFE) {
1753 printk(KERN_ERR "marvell-cam: Cafe can't do S/G I/O, attempting vmalloc mode instead\n");
1754 cam->buffer_mode = B_vmalloc;
1756 if (!mcam_buffer_mode_supported(cam->buffer_mode)) {
1757 printk(KERN_ERR "marvell-cam: buffer mode %d unsupported\n",
1764 ret = v4l2_device_register(cam->dev, &cam->v4l2_dev);
1768 mutex_init(&cam->s_mutex);
1769 cam->state = S_NOTREADY;
1770 mcam_set_config_needed(cam, 1);
1771 cam->pix_format = mcam_def_pix_format;
1772 cam->mbus_code = mcam_def_mbus_code;
1773 mcam_ctlr_init(cam);
1776 * Get the v4l2 setup done.
1778 ret = v4l2_ctrl_handler_init(&cam->ctrl_handler, 10);
1780 goto out_unregister;
1781 cam->v4l2_dev.ctrl_handler = &cam->ctrl_handler;
1784 * Try to find the sensor.
1786 sensor_cfg.clock_speed = cam->clock_speed;
1787 sensor_cfg.use_smbus = cam->use_smbus;
1788 cam->sensor_addr = ov7670_info.addr;
1789 cam->sensor = v4l2_i2c_new_subdev_board(&cam->v4l2_dev,
1790 cam->i2c_adapter, &ov7670_info, NULL);
1791 if (cam->sensor == NULL) {
1793 goto out_unregister;
1796 ret = mcam_cam_init(cam);
1798 goto out_unregister;
1800 ret = mcam_setup_vb2(cam);
1802 goto out_unregister;
1804 mutex_lock(&cam->s_mutex);
1805 cam->vdev = mcam_v4l_template;
1806 cam->vdev.v4l2_dev = &cam->v4l2_dev;
1807 cam->vdev.lock = &cam->s_mutex;
1808 cam->vdev.queue = &cam->vb_queue;
1809 video_set_drvdata(&cam->vdev, cam);
1810 ret = video_register_device(&cam->vdev, VFL_TYPE_GRABBER, -1);
1812 mutex_unlock(&cam->s_mutex);
1813 goto out_unregister;
1817 * If so requested, try to get our DMA buffers now.
1819 if (cam->buffer_mode == B_vmalloc && !alloc_bufs_at_read) {
1820 if (mcam_alloc_dma_bufs(cam, 1))
1821 cam_warn(cam, "Unable to alloc DMA buffers at load will try again later.");
1824 mutex_unlock(&cam->s_mutex);
1828 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1829 v4l2_device_unregister(&cam->v4l2_dev);
1834 void mccic_shutdown(struct mcam_camera *cam)
1837 * If we have no users (and we really, really should have no
1838 * users) the device will already be powered down. Trying to
1839 * take it down again will wedge the machine, which is frowned
1842 if (!list_empty(&cam->vdev.fh_list)) {
1843 cam_warn(cam, "Removing a device with users!\n");
1844 mcam_ctlr_power_down(cam);
1846 if (cam->buffer_mode == B_vmalloc)
1847 mcam_free_dma_bufs(cam);
1848 video_unregister_device(&cam->vdev);
1849 v4l2_ctrl_handler_free(&cam->ctrl_handler);
1850 v4l2_device_unregister(&cam->v4l2_dev);
1858 void mccic_suspend(struct mcam_camera *cam)
1860 mutex_lock(&cam->s_mutex);
1861 if (!list_empty(&cam->vdev.fh_list)) {
1862 enum mcam_state cstate = cam->state;
1864 mcam_ctlr_stop_dma(cam);
1865 mcam_ctlr_power_down(cam);
1866 cam->state = cstate;
1868 mutex_unlock(&cam->s_mutex);
1871 int mccic_resume(struct mcam_camera *cam)
1875 mutex_lock(&cam->s_mutex);
1876 if (!list_empty(&cam->vdev.fh_list)) {
1877 ret = mcam_ctlr_power_up(cam);
1879 mutex_unlock(&cam->s_mutex);
1882 __mcam_cam_reset(cam);
1884 mcam_ctlr_power_down(cam);
1886 mutex_unlock(&cam->s_mutex);
1888 set_bit(CF_CONFIG_NEEDED, &cam->flags);
1889 if (cam->state == S_STREAMING) {
1891 * If there was a buffer in the DMA engine at suspend
1892 * time, put it back on the queue or we'll forget about it.
1894 if (cam->buffer_mode == B_DMA_sg && cam->vb_bufs[0])
1895 list_add(&cam->vb_bufs[0]->queue, &cam->buffers);
1896 ret = mcam_read_setup(cam);
1900 #endif /* CONFIG_PM */