drivers/media/i2c/ov2740.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2020 Intel Corporation.
   3
   4 #include <asm/unaligned.h>
   5 #include <linux/acpi.h>
   6 #include <linux/delay.h>
   7 #include <linux/i2c.h>
   8 #include <linux/module.h>
   9 #include <linux/pm_runtime.h>
  10 #include <linux/nvmem-provider.h>
  11 #include <linux/regmap.h>
  12 #include <media/v4l2-ctrls.h>
  13 #include <media/v4l2-device.h>
  14 #include <media/v4l2-fwnode.h>
  15
  16 #define OV2740_LINK_FREQ_360MHZ         360000000ULL
  17 #define OV2740_SCLK                     72000000LL
  18 #define OV2740_MCLK                     19200000
  19 #define OV2740_DATA_LANES               2
  20 #define OV2740_RGB_DEPTH                10
  21
  22 #define OV2740_REG_CHIP_ID              0x300a
  23 #define OV2740_CHIP_ID                  0x2740
  24
  25 #define OV2740_REG_MODE_SELECT          0x0100
  26 #define OV2740_MODE_STANDBY             0x00
  27 #define OV2740_MODE_STREAMING           0x01
  28
  29 /* vertical-timings from sensor */
  30 #define OV2740_REG_VTS                  0x380e
  31 #define OV2740_VTS_DEF                  0x088a
  32 #define OV2740_VTS_MIN                  0x0460
  33 #define OV2740_VTS_MAX                  0x7fff
  34
  35 /* horizontal-timings from sensor */
  36 #define OV2740_REG_HTS                  0x380c
  37
  38 /* Exposure controls from sensor */
  39 #define OV2740_REG_EXPOSURE             0x3500
  40 #define OV2740_EXPOSURE_MIN             4
  41 #define OV2740_EXPOSURE_MAX_MARGIN      8
  42 #define OV2740_EXPOSURE_STEP            1
  43
  44 /* Analog gain controls from sensor */
  45 #define OV2740_REG_ANALOG_GAIN          0x3508
  46 #define OV2740_ANAL_GAIN_MIN            128
  47 #define OV2740_ANAL_GAIN_MAX            1983
  48 #define OV2740_ANAL_GAIN_STEP           1
  49
  50 /* Digital gain controls from sensor */
  51 #define OV2740_REG_MWB_R_GAIN           0x500a
  52 #define OV2740_REG_MWB_G_GAIN           0x500c
  53 #define OV2740_REG_MWB_B_GAIN           0x500e
  54 #define OV2740_DGTL_GAIN_MIN            1024
  55 #define OV2740_DGTL_GAIN_MAX            4095
  56 #define OV2740_DGTL_GAIN_STEP           1
  57 #define OV2740_DGTL_GAIN_DEFAULT        1024
  58
  59 /* Test Pattern Control */
  60 #define OV2740_REG_TEST_PATTERN         0x5040
  61 #define OV2740_TEST_PATTERN_ENABLE      BIT(7)
  62 #define OV2740_TEST_PATTERN_BAR_SHIFT   2
  63
  64 /* Group Access */
  65 #define OV2740_REG_GROUP_ACCESS         0x3208
  66 #define OV2740_GROUP_HOLD_START         0x0
  67 #define OV2740_GROUP_HOLD_END           0x10
  68 #define OV2740_GROUP_HOLD_LAUNCH        0xa0
  69
  70 /* ISP CTRL00 */
  71 #define OV2740_REG_ISP_CTRL00           0x5000
  72 /* ISP CTRL01 */
  73 #define OV2740_REG_ISP_CTRL01           0x5001
  74 /* Customer Addresses: 0x7010 - 0x710F */
  75 #define CUSTOMER_USE_OTP_SIZE           0x100
  76 /* OTP registers from sensor */
  77 #define OV2740_REG_OTP_CUSTOMER         0x7010
  78
  79 struct nvm_data {
  80         struct nvmem_device *nvmem;
  81         struct regmap *regmap;
  82         char *nvm_buffer;
  83 };
  84
  85 enum {
  86         OV2740_LINK_FREQ_360MHZ_INDEX,
  87 };
  88
  89 struct ov2740_reg {
  90         u16 address;
  91         u8 val;
  92 };
  93
  94 struct ov2740_reg_list {
  95         u32 num_of_regs;
  96         const struct ov2740_reg *regs;
  97 };
  98
  99 struct ov2740_link_freq_config {
 100         const struct ov2740_reg_list reg_list;
 101 };
 102
 103 struct ov2740_mode {
 104         /* Frame width in pixels */
 105         u32 width;
 106
 107         /* Frame height in pixels */
 108         u32 height;
 109
 110         /* Horizontal timining size */
 111         u32 hts;
 112
 113         /* Default vertical timining size */
 114         u32 vts_def;
 115
 116         /* Min vertical timining size */
 117         u32 vts_min;
 118
 119         /* Link frequency needed for this resolution */
 120         u32 link_freq_index;
 121
 122         /* Sensor register settings for this resolution */
 123         const struct ov2740_reg_list reg_list;
 124 };
 125
 126 static const struct ov2740_reg mipi_data_rate_720mbps[] = {
 127         {0x0103, 0x01},
 128         {0x0302, 0x4b},
 129         {0x030d, 0x4b},
 130         {0x030e, 0x02},
 131         {0x030a, 0x01},
 132         {0x0312, 0x11},
 133 };
 134
 135 static const struct ov2740_reg mode_1932x1092_regs[] = {
 136         {0x3000, 0x00},
 137         {0x3018, 0x32},
 138         {0x3031, 0x0a},
 139         {0x3080, 0x08},
 140         {0x3083, 0xB4},
 141         {0x3103, 0x00},
 142         {0x3104, 0x01},
 143         {0x3106, 0x01},
 144         {0x3500, 0x00},
 145         {0x3501, 0x44},
 146         {0x3502, 0x40},
 147         {0x3503, 0x88},
 148         {0x3507, 0x00},
 149         {0x3508, 0x00},
 150         {0x3509, 0x80},
 151         {0x350c, 0x00},
 152         {0x350d, 0x80},
 153         {0x3510, 0x00},
 154         {0x3511, 0x00},
 155         {0x3512, 0x20},
 156         {0x3632, 0x00},
 157         {0x3633, 0x10},
 158         {0x3634, 0x10},
 159         {0x3635, 0x10},
 160         {0x3645, 0x13},
 161         {0x3646, 0x81},
 162         {0x3636, 0x10},
 163         {0x3651, 0x0a},
 164         {0x3656, 0x02},
 165         {0x3659, 0x04},
 166         {0x365a, 0xda},
 167         {0x365b, 0xa2},
 168         {0x365c, 0x04},
 169         {0x365d, 0x1d},
 170         {0x365e, 0x1a},
 171         {0x3662, 0xd7},
 172         {0x3667, 0x78},
 173         {0x3669, 0x0a},
 174         {0x366a, 0x92},
 175         {0x3700, 0x54},
 176         {0x3702, 0x10},
 177         {0x3706, 0x42},
 178         {0x3709, 0x30},
 179         {0x370b, 0xc2},
 180         {0x3714, 0x63},
 181         {0x3715, 0x01},
 182         {0x3716, 0x00},
 183         {0x371a, 0x3e},
 184         {0x3732, 0x0e},
 185         {0x3733, 0x10},
 186         {0x375f, 0x0e},
 187         {0x3768, 0x30},
 188         {0x3769, 0x44},
 189         {0x376a, 0x22},
 190         {0x377b, 0x20},
 191         {0x377c, 0x00},
 192         {0x377d, 0x0c},
 193         {0x3798, 0x00},
 194         {0x37a1, 0x55},
 195         {0x37a8, 0x6d},
 196         {0x37c2, 0x04},
 197         {0x37c5, 0x00},
 198         {0x37c8, 0x00},
 199         {0x3800, 0x00},
 200         {0x3801, 0x00},
 201         {0x3802, 0x00},
 202         {0x3803, 0x00},
 203         {0x3804, 0x07},
 204         {0x3805, 0x8f},
 205         {0x3806, 0x04},
 206         {0x3807, 0x47},
 207         {0x3808, 0x07},
 208         {0x3809, 0x88},
 209         {0x380a, 0x04},
 210         {0x380b, 0x40},
 211         {0x380c, 0x04},
 212         {0x380d, 0x38},
 213         {0x380e, 0x04},
 214         {0x380f, 0x60},
 215         {0x3810, 0x00},
 216         {0x3811, 0x04},
 217         {0x3812, 0x00},
 218         {0x3813, 0x04},
 219         {0x3814, 0x01},
 220         {0x3815, 0x01},
 221         {0x3820, 0x80},
 222         {0x3821, 0x46},
 223         {0x3822, 0x84},
 224         {0x3829, 0x00},
 225         {0x382a, 0x01},
 226         {0x382b, 0x01},
 227         {0x3830, 0x04},
 228         {0x3836, 0x01},
 229         {0x3837, 0x08},
 230         {0x3839, 0x01},
 231         {0x383a, 0x00},
 232         {0x383b, 0x08},
 233         {0x383c, 0x00},
 234         {0x3f0b, 0x00},
 235         {0x4001, 0x20},
 236         {0x4009, 0x07},
 237         {0x4003, 0x10},
 238         {0x4010, 0xe0},
 239         {0x4016, 0x00},
 240         {0x4017, 0x10},
 241         {0x4044, 0x02},
 242         {0x4304, 0x08},
 243         {0x4307, 0x30},
 244         {0x4320, 0x80},
 245         {0x4322, 0x00},
 246         {0x4323, 0x00},
 247         {0x4324, 0x00},
 248         {0x4325, 0x00},
 249         {0x4326, 0x00},
 250         {0x4327, 0x00},
 251         {0x4328, 0x00},
 252         {0x4329, 0x00},
 253         {0x432c, 0x03},
 254         {0x432d, 0x81},
 255         {0x4501, 0x84},
 256         {0x4502, 0x40},
 257         {0x4503, 0x18},
 258         {0x4504, 0x04},
 259         {0x4508, 0x02},
 260         {0x4601, 0x10},
 261         {0x4800, 0x00},
 262         {0x4816, 0x52},
 263         {0x4837, 0x16},
 264         {0x5000, 0x7f},
 265         {0x5001, 0x00},
 266         {0x5005, 0x38},
 267         {0x501e, 0x0d},
 268         {0x5040, 0x00},
 269         {0x5901, 0x00},
 270         {0x3800, 0x00},
 271         {0x3801, 0x00},
 272         {0x3802, 0x00},
 273         {0x3803, 0x00},
 274         {0x3804, 0x07},
 275         {0x3805, 0x8f},
 276         {0x3806, 0x04},
 277         {0x3807, 0x47},
 278         {0x3808, 0x07},
 279         {0x3809, 0x8c},
 280         {0x380a, 0x04},
 281         {0x380b, 0x44},
 282         {0x3810, 0x00},
 283         {0x3811, 0x00},
 284         {0x3812, 0x00},
 285         {0x3813, 0x01},
 286 };
 287
 288 static const char * const ov2740_test_pattern_menu[] = {
 289         "Disabled",
 290         "Color Bar",
 291         "Top-Bottom Darker Color Bar",
 292         "Right-Left Darker Color Bar",
 293         "Bottom-Top Darker Color Bar",
 294 };
 295
 296 static const s64 link_freq_menu_items[] = {
 297         OV2740_LINK_FREQ_360MHZ,
 298 };
 299
 300 static const struct ov2740_link_freq_config link_freq_configs[] = {
 301         [OV2740_LINK_FREQ_360MHZ_INDEX] = {
 302                 .reg_list = {
 303                         .num_of_regs = ARRAY_SIZE(mipi_data_rate_720mbps),
 304                         .regs = mipi_data_rate_720mbps,
 305                 }
 306         },
 307 };
 308
 309 static const struct ov2740_mode supported_modes[] = {
 310         {
 311                 .width = 1932,
 312                 .height = 1092,
 313                 .hts = 1080,
 314                 .vts_def = OV2740_VTS_DEF,
 315                 .vts_min = OV2740_VTS_MIN,
 316                 .reg_list = {
 317                         .num_of_regs = ARRAY_SIZE(mode_1932x1092_regs),
 318                         .regs = mode_1932x1092_regs,
 319                 },
 320                 .link_freq_index = OV2740_LINK_FREQ_360MHZ_INDEX,
 321         },
 322 };
 323
 324 struct ov2740 {
 325         struct v4l2_subdev sd;
 326         struct media_pad pad;
 327         struct v4l2_ctrl_handler ctrl_handler;
 328
 329         /* V4L2 Controls */
 330         struct v4l2_ctrl *link_freq;
 331         struct v4l2_ctrl *pixel_rate;
 332         struct v4l2_ctrl *vblank;
 333         struct v4l2_ctrl *hblank;
 334         struct v4l2_ctrl *exposure;
 335
 336         /* Current mode */
 337         const struct ov2740_mode *cur_mode;
 338
 339         /* To serialize asynchronus callbacks */
 340         struct mutex mutex;
 341
 342         /* Streaming on/off */
 343         bool streaming;
 344
 345         /* NVM data inforamtion */
 346         struct nvm_data *nvm;
 347
 348         /* True if the device has been identified */
 349         bool identified;
 350 };
 351
 352 static inline struct ov2740 *to_ov2740(struct v4l2_subdev *subdev)
 353 {
 354         return container_of(subdev, struct ov2740, sd);
 355 }
 356
 357 static u64 to_pixel_rate(u32 f_index)
 358 {
 359         u64 pixel_rate = link_freq_menu_items[f_index] * 2 * OV2740_DATA_LANES;
 360
 361         do_div(pixel_rate, OV2740_RGB_DEPTH);
 362
 363         return pixel_rate;
 364 }
 365
 366 static u64 to_pixels_per_line(u32 hts, u32 f_index)
 367 {
 368         u64 ppl = hts * to_pixel_rate(f_index);
 369
 370         do_div(ppl, OV2740_SCLK);
 371
 372         return ppl;
 373 }
 374
 375 static int ov2740_read_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 *val)
 376 {
 377         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 378         struct i2c_msg msgs[2];
 379         u8 addr_buf[2];
 380         u8 data_buf[4] = {0};
 381         int ret;
 382
 383         if (len > sizeof(data_buf))
 384                 return -EINVAL;
 385
 386         put_unaligned_be16(reg, addr_buf);
 387         msgs[0].addr = client->addr;
 388         msgs[0].flags = 0;
 389         msgs[0].len = sizeof(addr_buf);
 390         msgs[0].buf = addr_buf;
 391         msgs[1].addr = client->addr;
 392         msgs[1].flags = I2C_M_RD;
 393         msgs[1].len = len;
 394         msgs[1].buf = &data_buf[sizeof(data_buf) - len];
 395
 396         ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
 397         if (ret != ARRAY_SIZE(msgs))
 398                 return ret < 0 ? ret : -EIO;
 399
 400         *val = get_unaligned_be32(data_buf);
 401
 402         return 0;
 403 }
 404
 405 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)
 406 {
 407         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 408         u8 buf[6];
 409         int ret;
 410
 411         if (len > 4)
 412                 return -EINVAL;
 413
 414         put_unaligned_be16(reg, buf);
 415         put_unaligned_be32(val << 8 * (4 - len), buf + 2);
 416
 417         ret = i2c_master_send(client, buf, len + 2);
 418         if (ret != len + 2)
 419                 return ret < 0 ? ret : -EIO;
 420
 421         return 0;
 422 }
 423
 424 static int ov2740_write_reg_list(struct ov2740 *ov2740,
 425                                  const struct ov2740_reg_list *r_list)
 426 {
 427         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 428         unsigned int i;
 429         int ret;
 430
 431         for (i = 0; i < r_list->num_of_regs; i++) {
 432                 ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,
 433                                        r_list->regs[i].val);
 434                 if (ret) {
 435                         dev_err_ratelimited(&client->dev,
 436                                             "write reg 0x%4.4x return err = %d\n",
 437                                             r_list->regs[i].address, ret);
 438                         return ret;
 439                 }
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int ov2740_identify_module(struct ov2740 *ov2740)
 446 {
 447         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 448         int ret;
 449         u32 val;
 450
 451         if (ov2740->identified)
 452                 return 0;
 453
 454         ret = ov2740_read_reg(ov2740, OV2740_REG_CHIP_ID, 3, &val);
 455         if (ret)
 456                 return ret;
 457
 458         if (val != OV2740_CHIP_ID) {
 459                 dev_err(&client->dev, "chip id mismatch: %x != %x\n",
 460                         OV2740_CHIP_ID, val);
 461                 return -ENXIO;
 462         }
 463
 464         ov2740->identified = true;
 465
 466         return 0;
 467 }
 468
 469 static int ov2740_update_digital_gain(struct ov2740 *ov2740, u32 d_gain)
 470 {
 471         int ret;
 472
 473         ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
 474                                OV2740_GROUP_HOLD_START);
 475         if (ret)
 476                 return ret;
 477
 478         ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);
 479         if (ret)
 480                 return ret;
 481
 482         ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);
 483         if (ret)
 484                 return ret;
 485
 486         ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);
 487         if (ret)
 488                 return ret;
 489
 490         ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
 491                                OV2740_GROUP_HOLD_END);
 492         if (ret)
 493                 return ret;
 494
 495         ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,
 496                                OV2740_GROUP_HOLD_LAUNCH);
 497         return ret;
 498 }
 499
 500 static int ov2740_test_pattern(struct ov2740 *ov2740, u32 pattern)
 501 {
 502         if (pattern)
 503                 pattern = (pattern - 1) << OV2740_TEST_PATTERN_BAR_SHIFT |
 504                           OV2740_TEST_PATTERN_ENABLE;
 505
 506         return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);
 507 }
 508
 509 static int ov2740_set_ctrl(struct v4l2_ctrl *ctrl)
 510 {
 511         struct ov2740 *ov2740 = container_of(ctrl->handler,
 512                                              struct ov2740, ctrl_handler);
 513         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 514         s64 exposure_max;
 515         int ret;
 516
 517         /* Propagate change of current control to all related controls */
 518         if (ctrl->id == V4L2_CID_VBLANK) {
 519                 /* Update max exposure while meeting expected vblanking */
 520                 exposure_max = ov2740->cur_mode->height + ctrl->val -
 521                                OV2740_EXPOSURE_MAX_MARGIN;
 522                 __v4l2_ctrl_modify_range(ov2740->exposure,
 523                                          ov2740->exposure->minimum,
 524                                          exposure_max, ov2740->exposure->step,
 525                                          exposure_max);
 526         }
 527
 528         /* V4L2 controls values will be applied only when power is already up */
 529         if (!pm_runtime_get_if_in_use(&client->dev))
 530                 return 0;
 531
 532         switch (ctrl->id) {
 533         case V4L2_CID_ANALOGUE_GAIN:
 534                 ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,
 535                                        ctrl->val);
 536                 break;
 537
 538         case V4L2_CID_DIGITAL_GAIN:
 539                 ret = ov2740_update_digital_gain(ov2740, ctrl->val);
 540                 break;
 541
 542         case V4L2_CID_EXPOSURE:
 543                 /* 4 least significant bits of expsoure are fractional part */
 544                 ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,
 545                                        ctrl->val << 4);
 546                 break;
 547
 548         case V4L2_CID_VBLANK:
 549                 ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,
 550                                        ov2740->cur_mode->height + ctrl->val);
 551                 break;
 552
 553         case V4L2_CID_TEST_PATTERN:
 554                 ret = ov2740_test_pattern(ov2740, ctrl->val);
 555                 break;
 556
 557         default:
 558                 ret = -EINVAL;
 559                 break;
 560         }
 561
 562         pm_runtime_put(&client->dev);
 563
 564         return ret;
 565 }
 566
 567 static const struct v4l2_ctrl_ops ov2740_ctrl_ops = {
 568         .s_ctrl = ov2740_set_ctrl,
 569 };
 570
 571 static int ov2740_init_controls(struct ov2740 *ov2740)
 572 {
 573         struct v4l2_ctrl_handler *ctrl_hdlr;
 574         const struct ov2740_mode *cur_mode;
 575         s64 exposure_max, h_blank, pixel_rate;
 576         u32 vblank_min, vblank_max, vblank_default;
 577         int size;
 578         int ret;
 579
 580         ctrl_hdlr = &ov2740->ctrl_handler;
 581         ret = v4l2_ctrl_handler_init(ctrl_hdlr, 8);
 582         if (ret)
 583                 return ret;
 584
 585         ctrl_hdlr->lock = &ov2740->mutex;
 586         cur_mode = ov2740->cur_mode;
 587         size = ARRAY_SIZE(link_freq_menu_items);
 588
 589         ov2740->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, &ov2740_ctrl_ops,
 590                                                    V4L2_CID_LINK_FREQ,
 591                                                    size - 1, 0,
 592                                                    link_freq_menu_items);
 593         if (ov2740->link_freq)
 594                 ov2740->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 595
 596         pixel_rate = to_pixel_rate(OV2740_LINK_FREQ_360MHZ_INDEX);
 597         ov2740->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 598                                                V4L2_CID_PIXEL_RATE, 0,
 599                                                pixel_rate, 1, pixel_rate);
 600
 601         vblank_min = cur_mode->vts_min - cur_mode->height;
 602         vblank_max = OV2740_VTS_MAX - cur_mode->height;
 603         vblank_default = cur_mode->vts_def - cur_mode->height;
 604         ov2740->vblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 605                                            V4L2_CID_VBLANK, vblank_min,
 606                                            vblank_max, 1, vblank_default);
 607
 608         h_blank = to_pixels_per_line(cur_mode->hts, cur_mode->link_freq_index);
 609         h_blank -= cur_mode->width;
 610         ov2740->hblank = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 611                                            V4L2_CID_HBLANK, h_blank, h_blank, 1,
 612                                            h_blank);
 613         if (ov2740->hblank)
 614                 ov2740->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
 615
 616         v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_ANALOGUE_GAIN,
 617                           OV2740_ANAL_GAIN_MIN, OV2740_ANAL_GAIN_MAX,
 618                           OV2740_ANAL_GAIN_STEP, OV2740_ANAL_GAIN_MIN);
 619         v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops, V4L2_CID_DIGITAL_GAIN,
 620                           OV2740_DGTL_GAIN_MIN, OV2740_DGTL_GAIN_MAX,
 621                           OV2740_DGTL_GAIN_STEP, OV2740_DGTL_GAIN_DEFAULT);
 622         exposure_max = cur_mode->vts_def - OV2740_EXPOSURE_MAX_MARGIN;
 623         ov2740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov2740_ctrl_ops,
 624                                              V4L2_CID_EXPOSURE,
 625                                              OV2740_EXPOSURE_MIN, exposure_max,
 626                                              OV2740_EXPOSURE_STEP,
 627                                              exposure_max);
 628         v4l2_ctrl_new_std_menu_items(ctrl_hdlr, &ov2740_ctrl_ops,
 629                                      V4L2_CID_TEST_PATTERN,
 630                                      ARRAY_SIZE(ov2740_test_pattern_menu) - 1,
 631                                      0, 0, ov2740_test_pattern_menu);
 632         if (ctrl_hdlr->error) {
 633                 v4l2_ctrl_handler_free(ctrl_hdlr);
 634                 return ctrl_hdlr->error;
 635         }
 636
 637         ov2740->sd.ctrl_handler = ctrl_hdlr;
 638
 639         return 0;
 640 }
 641
 642 static void ov2740_update_pad_format(const struct ov2740_mode *mode,
 643                                      struct v4l2_mbus_framefmt *fmt)
 644 {
 645         fmt->width = mode->width;
 646         fmt->height = mode->height;
 647         fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 648         fmt->field = V4L2_FIELD_NONE;
 649 }
 650
 651 static int ov2740_load_otp_data(struct nvm_data *nvm)
 652 {
 653         struct device *dev = regmap_get_device(nvm->regmap);
 654         struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
 655         u32 isp_ctrl00 = 0;
 656         u32 isp_ctrl01 = 0;
 657         int ret;
 658
 659         if (nvm->nvm_buffer)
 660                 return 0;
 661
 662         nvm->nvm_buffer = kzalloc(CUSTOMER_USE_OTP_SIZE, GFP_KERNEL);
 663         if (!nvm->nvm_buffer)
 664                 return -ENOMEM;
 665
 666         ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, &isp_ctrl00);
 667         if (ret) {
 668                 dev_err(dev, "failed to read ISP CTRL00\n");
 669                 goto err;
 670         }
 671
 672         ret = ov2740_read_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, &isp_ctrl01);
 673         if (ret) {
 674                 dev_err(dev, "failed to read ISP CTRL01\n");
 675                 goto err;
 676         }
 677
 678         /* Clear bit 5 of ISP CTRL00 */
 679         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,
 680                                isp_ctrl00 & ~BIT(5));
 681         if (ret) {
 682                 dev_err(dev, "failed to set ISP CTRL00\n");
 683                 goto err;
 684         }
 685
 686         /* Clear bit 7 of ISP CTRL01 */
 687         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,
 688                                isp_ctrl01 & ~BIT(7));
 689         if (ret) {
 690                 dev_err(dev, "failed to set ISP CTRL01\n");
 691                 goto err;
 692         }
 693
 694         ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 695                                OV2740_MODE_STREAMING);
 696         if (ret) {
 697                 dev_err(dev, "failed to set streaming mode\n");
 698                 goto err;
 699         }
 700
 701         /*
 702          * Users are not allowed to access OTP-related registers and memory
 703          * during the 20 ms period after streaming starts (0x100 = 0x01).
 704          */
 705         msleep(20);
 706
 707         ret = regmap_bulk_read(nvm->regmap, OV2740_REG_OTP_CUSTOMER,
 708                                nvm->nvm_buffer, CUSTOMER_USE_OTP_SIZE);
 709         if (ret) {
 710                 dev_err(dev, "failed to read OTP data, ret %d\n", ret);
 711                 goto err;
 712         }
 713
 714         ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 715                                OV2740_MODE_STANDBY);
 716         if (ret) {
 717                 dev_err(dev, "failed to set streaming mode\n");
 718                 goto err;
 719         }
 720
 721         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);
 722         if (ret) {
 723                 dev_err(dev, "failed to set ISP CTRL01\n");
 724                 goto err;
 725         }
 726
 727         ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);
 728         if (ret) {
 729                 dev_err(dev, "failed to set ISP CTRL00\n");
 730                 goto err;
 731         }
 732
 733         return 0;
 734 err:
 735         kfree(nvm->nvm_buffer);
 736         nvm->nvm_buffer = NULL;
 737
 738         return ret;
 739 }
 740
 741 static int ov2740_start_streaming(struct ov2740 *ov2740)
 742 {
 743         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 744         const struct ov2740_reg_list *reg_list;
 745         int link_freq_index;
 746         int ret;
 747
 748         ret = ov2740_identify_module(ov2740);
 749         if (ret)
 750                 return ret;
 751
 752         if (ov2740->nvm)
 753                 ov2740_load_otp_data(ov2740->nvm);
 754
 755         link_freq_index = ov2740->cur_mode->link_freq_index;
 756         reg_list = &link_freq_configs[link_freq_index].reg_list;
 757         ret = ov2740_write_reg_list(ov2740, reg_list);
 758         if (ret) {
 759                 dev_err(&client->dev, "failed to set plls\n");
 760                 return ret;
 761         }
 762
 763         reg_list = &ov2740->cur_mode->reg_list;
 764         ret = ov2740_write_reg_list(ov2740, reg_list);
 765         if (ret) {
 766                 dev_err(&client->dev, "failed to set mode\n");
 767                 return ret;
 768         }
 769
 770         ret = __v4l2_ctrl_handler_setup(ov2740->sd.ctrl_handler);
 771         if (ret)
 772                 return ret;
 773
 774         ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 775                                OV2740_MODE_STREAMING);
 776         if (ret)
 777                 dev_err(&client->dev, "failed to start streaming\n");
 778
 779         return ret;
 780 }
 781
 782 static void ov2740_stop_streaming(struct ov2740 *ov2740)
 783 {
 784         struct i2c_client *client = v4l2_get_subdevdata(&ov2740->sd);
 785
 786         if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,
 787                              OV2740_MODE_STANDBY))
 788                 dev_err(&client->dev, "failed to stop streaming\n");
 789 }
 790
 791 static int ov2740_set_stream(struct v4l2_subdev *sd, int enable)
 792 {
 793         struct ov2740 *ov2740 = to_ov2740(sd);
 794         struct i2c_client *client = v4l2_get_subdevdata(sd);
 795         int ret = 0;
 796
 797         if (ov2740->streaming == enable)
 798                 return 0;
 799
 800         mutex_lock(&ov2740->mutex);
 801         if (enable) {
 802                 ret = pm_runtime_resume_and_get(&client->dev);
 803                 if (ret < 0) {
 804                         mutex_unlock(&ov2740->mutex);
 805                         return ret;
 806                 }
 807
 808                 ret = ov2740_start_streaming(ov2740);
 809                 if (ret) {
 810                         enable = 0;
 811                         ov2740_stop_streaming(ov2740);
 812                         pm_runtime_put(&client->dev);
 813                 }
 814         } else {
 815                 ov2740_stop_streaming(ov2740);
 816                 pm_runtime_put(&client->dev);
 817         }
 818
 819         ov2740->streaming = enable;
 820         mutex_unlock(&ov2740->mutex);
 821
 822         return ret;
 823 }
 824
 825 static int ov2740_suspend(struct device *dev)
 826 {
 827         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 828         struct ov2740 *ov2740 = to_ov2740(sd);
 829
 830         mutex_lock(&ov2740->mutex);
 831         if (ov2740->streaming)
 832                 ov2740_stop_streaming(ov2740);
 833
 834         mutex_unlock(&ov2740->mutex);
 835
 836         return 0;
 837 }
 838
 839 static int ov2740_resume(struct device *dev)
 840 {
 841         struct v4l2_subdev *sd = dev_get_drvdata(dev);
 842         struct ov2740 *ov2740 = to_ov2740(sd);
 843         int ret = 0;
 844
 845         mutex_lock(&ov2740->mutex);
 846         if (!ov2740->streaming)
 847                 goto exit;
 848
 849         ret = ov2740_start_streaming(ov2740);
 850         if (ret) {
 851                 ov2740->streaming = false;
 852                 ov2740_stop_streaming(ov2740);
 853         }
 854
 855 exit:
 856         mutex_unlock(&ov2740->mutex);
 857         return ret;
 858 }
 859
 860 static int ov2740_set_format(struct v4l2_subdev *sd,
 861                              struct v4l2_subdev_state *sd_state,
 862                              struct v4l2_subdev_format *fmt)
 863 {
 864         struct ov2740 *ov2740 = to_ov2740(sd);
 865         const struct ov2740_mode *mode;
 866         s32 vblank_def, h_blank;
 867
 868         mode = v4l2_find_nearest_size(supported_modes,
 869                                       ARRAY_SIZE(supported_modes), width,
 870                                       height, fmt->format.width,
 871                                       fmt->format.height);
 872
 873         mutex_lock(&ov2740->mutex);
 874         ov2740_update_pad_format(mode, &fmt->format);
 875         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
 876                 *v4l2_subdev_get_try_format(sd, sd_state, fmt->pad) = fmt->format;
 877         } else {
 878                 ov2740->cur_mode = mode;
 879                 __v4l2_ctrl_s_ctrl(ov2740->link_freq, mode->link_freq_index);
 880                 __v4l2_ctrl_s_ctrl_int64(ov2740->pixel_rate,
 881                                          to_pixel_rate(mode->link_freq_index));
 882
 883                 /* Update limits and set FPS to default */
 884                 vblank_def = mode->vts_def - mode->height;
 885                 __v4l2_ctrl_modify_range(ov2740->vblank,
 886                                          mode->vts_min - mode->height,
 887                                          OV2740_VTS_MAX - mode->height, 1,
 888                                          vblank_def);
 889                 __v4l2_ctrl_s_ctrl(ov2740->vblank, vblank_def);
 890                 h_blank = to_pixels_per_line(mode->hts, mode->link_freq_index) -
 891                           mode->width;
 892                 __v4l2_ctrl_modify_range(ov2740->hblank, h_blank, h_blank, 1,
 893                                          h_blank);
 894         }
 895         mutex_unlock(&ov2740->mutex);
 896
 897         return 0;
 898 }
 899
 900 static int ov2740_get_format(struct v4l2_subdev *sd,
 901                              struct v4l2_subdev_state *sd_state,
 902                              struct v4l2_subdev_format *fmt)
 903 {
 904         struct ov2740 *ov2740 = to_ov2740(sd);
 905
 906         mutex_lock(&ov2740->mutex);
 907         if (fmt->which == V4L2_SUBDEV_FORMAT_TRY)
 908                 fmt->format = *v4l2_subdev_get_try_format(&ov2740->sd,
 909                                                           sd_state,
 910                                                           fmt->pad);
 911         else
 912                 ov2740_update_pad_format(ov2740->cur_mode, &fmt->format);
 913
 914         mutex_unlock(&ov2740->mutex);
 915
 916         return 0;
 917 }
 918
 919 static int ov2740_enum_mbus_code(struct v4l2_subdev *sd,
 920                                  struct v4l2_subdev_state *sd_state,
 921                                  struct v4l2_subdev_mbus_code_enum *code)
 922 {
 923         if (code->index > 0)
 924                 return -EINVAL;
 925
 926         code->code = MEDIA_BUS_FMT_SGRBG10_1X10;
 927
 928         return 0;
 929 }
 930
 931 static int ov2740_enum_frame_size(struct v4l2_subdev *sd,
 932                                   struct v4l2_subdev_state *sd_state,
 933                                   struct v4l2_subdev_frame_size_enum *fse)
 934 {
 935         if (fse->index >= ARRAY_SIZE(supported_modes))
 936                 return -EINVAL;
 937
 938         if (fse->code != MEDIA_BUS_FMT_SGRBG10_1X10)
 939                 return -EINVAL;
 940
 941         fse->min_width = supported_modes[fse->index].width;
 942         fse->max_width = fse->min_width;
 943         fse->min_height = supported_modes[fse->index].height;
 944         fse->max_height = fse->min_height;
 945
 946         return 0;
 947 }
 948
 949 static int ov2740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
 950 {
 951         struct ov2740 *ov2740 = to_ov2740(sd);
 952
 953         mutex_lock(&ov2740->mutex);
 954         ov2740_update_pad_format(&supported_modes[0],
 955                                  v4l2_subdev_get_try_format(sd, fh->state, 0));
 956         mutex_unlock(&ov2740->mutex);
 957
 958         return 0;
 959 }
 960
 961 static const struct v4l2_subdev_video_ops ov2740_video_ops = {
 962         .s_stream = ov2740_set_stream,
 963 };
 964
 965 static const struct v4l2_subdev_pad_ops ov2740_pad_ops = {
 966         .set_fmt = ov2740_set_format,
 967         .get_fmt = ov2740_get_format,
 968         .enum_mbus_code = ov2740_enum_mbus_code,
 969         .enum_frame_size = ov2740_enum_frame_size,
 970 };
 971
 972 static const struct v4l2_subdev_ops ov2740_subdev_ops = {
 973         .video = &ov2740_video_ops,
 974         .pad = &ov2740_pad_ops,
 975 };
 976
 977 static const struct media_entity_operations ov2740_subdev_entity_ops = {
 978         .link_validate = v4l2_subdev_link_validate,
 979 };
 980
 981 static const struct v4l2_subdev_internal_ops ov2740_internal_ops = {
 982         .open = ov2740_open,
 983 };
 984
 985 static int ov2740_check_hwcfg(struct device *dev)
 986 {
 987         struct fwnode_handle *ep;
 988         struct fwnode_handle *fwnode = dev_fwnode(dev);
 989         struct v4l2_fwnode_endpoint bus_cfg = {
 990                 .bus_type = V4L2_MBUS_CSI2_DPHY
 991         };
 992         u32 mclk;
 993         int ret;
 994         unsigned int i, j;
 995
 996         ret = fwnode_property_read_u32(fwnode, "clock-frequency", &mclk);
 997         if (ret)
 998                 return ret;
 999
1000         if (mclk != OV2740_MCLK)
1001                 return dev_err_probe(dev, -EINVAL,
1002                                      "external clock %d is not supported\n",
1003                                      mclk);
1004
1005         ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
1006         if (!ep)
1007                 return -ENXIO;
1008
1009         ret = v4l2_fwnode_endpoint_alloc_parse(ep, &bus_cfg);
1010         fwnode_handle_put(ep);
1011         if (ret)
1012                 return ret;
1013
1014         if (bus_cfg.bus.mipi_csi2.num_data_lanes != OV2740_DATA_LANES) {
1015                 ret = dev_err_probe(dev, -EINVAL,
1016                                     "number of CSI2 data lanes %d is not supported\n",
1017                                     bus_cfg.bus.mipi_csi2.num_data_lanes);
1018                 goto check_hwcfg_error;
1019         }
1020
1021         if (!bus_cfg.nr_of_link_frequencies) {
1022                 ret = dev_err_probe(dev, -EINVAL, "no link frequencies defined\n");
1023                 goto check_hwcfg_error;
1024         }
1025
1026         for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); i++) {
1027                 for (j = 0; j < bus_cfg.nr_of_link_frequencies; j++) {
1028                         if (link_freq_menu_items[i] ==
1029                                 bus_cfg.link_frequencies[j])
1030                                 break;
1031                 }
1032
1033                 if (j == bus_cfg.nr_of_link_frequencies) {
1034                         ret = dev_err_probe(dev, -EINVAL,
1035                                             "no link frequency %lld supported\n",
1036                                             link_freq_menu_items[i]);
1037                         goto check_hwcfg_error;
1038                 }
1039         }
1040
1041 check_hwcfg_error:
1042         v4l2_fwnode_endpoint_free(&bus_cfg);
1043
1044         return ret;
1045 }
1046
1047 static void ov2740_remove(struct i2c_client *client)
1048 {
1049         struct v4l2_subdev *sd = i2c_get_clientdata(client);
1050         struct ov2740 *ov2740 = to_ov2740(sd);
1051
1052         v4l2_async_unregister_subdev(sd);
1053         media_entity_cleanup(&sd->entity);
1054         v4l2_ctrl_handler_free(sd->ctrl_handler);
1055         pm_runtime_disable(&client->dev);
1056         mutex_destroy(&ov2740->mutex);
1057 }
1058
1059 static int ov2740_nvmem_read(void *priv, unsigned int off, void *val,
1060                              size_t count)
1061 {
1062         struct nvm_data *nvm = priv;
1063         struct device *dev = regmap_get_device(nvm->regmap);
1064         struct ov2740 *ov2740 = to_ov2740(dev_get_drvdata(dev));
1065         int ret = 0;
1066
1067         mutex_lock(&ov2740->mutex);
1068
1069         if (nvm->nvm_buffer) {
1070                 memcpy(val, nvm->nvm_buffer + off, count);
1071                 goto exit;
1072         }
1073
1074         ret = pm_runtime_resume_and_get(dev);
1075         if (ret < 0) {
1076                 goto exit;
1077         }
1078
1079         ret = ov2740_load_otp_data(nvm);
1080         if (!ret)
1081                 memcpy(val, nvm->nvm_buffer + off, count);
1082
1083         pm_runtime_put(dev);
1084 exit:
1085         mutex_unlock(&ov2740->mutex);
1086         return ret;
1087 }
1088
1089 static int ov2740_register_nvmem(struct i2c_client *client,
1090                                  struct ov2740 *ov2740)
1091 {
1092         struct nvm_data *nvm;
1093         struct regmap_config regmap_config = { };
1094         struct nvmem_config nvmem_config = { };
1095         struct regmap *regmap;
1096         struct device *dev = &client->dev;
1097
1098         nvm = devm_kzalloc(dev, sizeof(*nvm), GFP_KERNEL);
1099         if (!nvm)
1100                 return -ENOMEM;
1101
1102         regmap_config.val_bits = 8;
1103         regmap_config.reg_bits = 16;
1104         regmap_config.disable_locking = true;
1105         regmap = devm_regmap_init_i2c(client, &regmap_config);
1106         if (IS_ERR(regmap))
1107                 return PTR_ERR(regmap);
1108
1109         nvm->regmap = regmap;
1110
1111         nvmem_config.name = dev_name(dev);
1112         nvmem_config.dev = dev;
1113         nvmem_config.read_only = true;
1114         nvmem_config.root_only = true;
1115         nvmem_config.owner = THIS_MODULE;
1116         nvmem_config.compat = true;
1117         nvmem_config.base_dev = dev;
1118         nvmem_config.reg_read = ov2740_nvmem_read;
1119         nvmem_config.reg_write = NULL;
1120         nvmem_config.priv = nvm;
1121         nvmem_config.stride = 1;
1122         nvmem_config.word_size = 1;
1123         nvmem_config.size = CUSTOMER_USE_OTP_SIZE;
1124
1125         nvm->nvmem = devm_nvmem_register(dev, &nvmem_config);
1126         if (IS_ERR(nvm->nvmem))
1127                 return PTR_ERR(nvm->nvmem);
1128
1129         ov2740->nvm = nvm;
1130         return 0;
1131 }
1132
1133 static int ov2740_probe(struct i2c_client *client)
1134 {
1135         struct device *dev = &client->dev;
1136         struct ov2740 *ov2740;
1137         bool full_power;
1138         int ret;
1139
1140         ret = ov2740_check_hwcfg(&client->dev);
1141         if (ret)
1142                 return dev_err_probe(dev, ret, "failed to check HW configuration\n");
1143
1144         ov2740 = devm_kzalloc(&client->dev, sizeof(*ov2740), GFP_KERNEL);
1145         if (!ov2740)
1146                 return -ENOMEM;
1147
1148         v4l2_i2c_subdev_init(&ov2740->sd, client, &ov2740_subdev_ops);
1149         full_power = acpi_dev_state_d0(&client->dev);
1150         if (full_power) {
1151                 ret = ov2740_identify_module(ov2740);
1152                 if (ret)
1153                         return dev_err_probe(dev, ret, "failed to find sensor\n");
1154         }
1155
1156         mutex_init(&ov2740->mutex);
1157         ov2740->cur_mode = &supported_modes[0];
1158         ret = ov2740_init_controls(ov2740);
1159         if (ret) {
1160                 dev_err_probe(dev, ret, "failed to init controls\n");
1161                 goto probe_error_v4l2_ctrl_handler_free;
1162         }
1163
1164         ov2740->sd.internal_ops = &ov2740_internal_ops;
1165         ov2740->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1166         ov2740->sd.entity.ops = &ov2740_subdev_entity_ops;
1167         ov2740->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
1168         ov2740->pad.flags = MEDIA_PAD_FL_SOURCE;
1169         ret = media_entity_pads_init(&ov2740->sd.entity, 1, &ov2740->pad);
1170         if (ret) {
1171                 dev_err_probe(dev, ret, "failed to init entity pads\n");
1172                 goto probe_error_v4l2_ctrl_handler_free;
1173         }
1174
1175         ret = v4l2_async_register_subdev_sensor(&ov2740->sd);
1176         if (ret < 0) {
1177                 dev_err_probe(dev, ret, "failed to register V4L2 subdev\n");
1178                 goto probe_error_media_entity_cleanup;
1179         }
1180
1181         ret = ov2740_register_nvmem(client, ov2740);
1182         if (ret)
1183                 dev_warn(&client->dev, "register nvmem failed, ret %d\n", ret);
1184
1185         /* Set the device's state to active if it's in D0 state. */
1186         if (full_power)
1187                 pm_runtime_set_active(&client->dev);
1188         pm_runtime_enable(&client->dev);
1189         pm_runtime_idle(&client->dev);
1190
1191         return 0;
1192
1193 probe_error_media_entity_cleanup:
1194         media_entity_cleanup(&ov2740->sd.entity);
1195
1196 probe_error_v4l2_ctrl_handler_free:
1197         v4l2_ctrl_handler_free(ov2740->sd.ctrl_handler);
1198         mutex_destroy(&ov2740->mutex);
1199
1200         return ret;
1201 }
1202
1203 static DEFINE_SIMPLE_DEV_PM_OPS(ov2740_pm_ops, ov2740_suspend, ov2740_resume);
1204
1205 static const struct acpi_device_id ov2740_acpi_ids[] = {
1206         {"INT3474"},
1207         {}
1208 };
1209
1210 MODULE_DEVICE_TABLE(acpi, ov2740_acpi_ids);
1211
1212 static struct i2c_driver ov2740_i2c_driver = {
1213         .driver = {
1214                 .name = "ov2740",
1215                 .pm = pm_sleep_ptr(&ov2740_pm_ops),
1216                 .acpi_match_table = ov2740_acpi_ids,
1217         },
1218         .probe = ov2740_probe,
1219         .remove = ov2740_remove,
1220         .flags = I2C_DRV_ACPI_WAIVE_D0_PROBE,
1221 };
1222
1223 module_i2c_driver(ov2740_i2c_driver);
1224
1225 MODULE_AUTHOR("Qiu, Tianshu <tian.shu.qiu@intel.com>");
1226 MODULE_AUTHOR("Shawn Tu <shawnx.tu@intel.com>");
1227 MODULE_AUTHOR("Bingbu Cao <bingbu.cao@intel.com>");
1228 MODULE_DESCRIPTION("OmniVision OV2740 sensor driver");
1229 MODULE_LICENSE("GPL v2");