2 * Driver for Zarlink DVB-T MT352 demodulator
4 * Written by Holger Waechtler <holger@qanu.de>
5 * and Daniel Mack <daniel@qanu.de>
7 * AVerMedia AVerTV DVB-T 771 support by
8 * Wolfram Joost <dbox2@frokaschwei.de>
10 * Support for Samsung TDTC9251DH01C(M) tuner
11 * Copyright (C) 2004 Antonio Mancuso <antonio.mancuso@digitaltelevision.it>
12 * Amauri Celani <acelani@essegi.net>
14 * DVICO FusionHDTV DVB-T1 and DVICO FusionHDTV DVB-T Lite support by
15 * Christopher Pascoe <c.pascoe@itee.uq.edu.au>
17 * This program is free software; you can redistribute it and/or modify
18 * it under the terms of the GNU General Public License as published by
19 * the Free Software Foundation; either version 2 of the License, or
20 * (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/init.h>
37 #include <linux/delay.h>
38 #include <linux/string.h>
39 #include <linux/slab.h>
41 #include "dvb_frontend.h"
42 #include "mt352_priv.h"
46 struct i2c_adapter* i2c;
47 struct dvb_frontend frontend;
49 /* configuration settings */
50 struct mt352_config config;
54 #define dprintk(args...) \
56 if (debug) printk(KERN_DEBUG "mt352: " args); \
59 static int mt352_single_write(struct dvb_frontend *fe, u8 reg, u8 val)
61 struct mt352_state* state = fe->demodulator_priv;
62 u8 buf[2] = { reg, val };
63 struct i2c_msg msg = { .addr = state->config.demod_address, .flags = 0,
64 .buf = buf, .len = 2 };
65 int err = i2c_transfer(state->i2c, &msg, 1);
67 printk("mt352_write() to reg %x failed (err = %d)!\n", reg, err);
73 static int _mt352_write(struct dvb_frontend* fe, u8* ibuf, int ilen)
76 for (i=0; i < ilen-1; i++)
77 if ((err = mt352_single_write(fe,ibuf[0]+i,ibuf[i+1])))
83 static int mt352_read_register(struct mt352_state* state, u8 reg)
88 struct i2c_msg msg [] = { { .addr = state->config.demod_address,
90 .buf = b0, .len = 1 },
91 { .addr = state->config.demod_address,
93 .buf = b1, .len = 1 } };
95 ret = i2c_transfer(state->i2c, msg, 2);
98 printk("%s: readreg error (reg=%d, ret==%i)\n",
99 __FUNCTION__, reg, ret);
106 static int mt352_sleep(struct dvb_frontend* fe)
108 static u8 mt352_softdown[] = { CLOCK_CTL, 0x20, 0x08 };
110 _mt352_write(fe, mt352_softdown, sizeof(mt352_softdown));
114 static void mt352_calc_nominal_rate(struct mt352_state* state,
115 enum fe_bandwidth bandwidth,
118 u32 adc_clock = 20480; /* 20.340 MHz */
122 case BANDWIDTH_6_MHZ:
125 case BANDWIDTH_7_MHZ:
128 case BANDWIDTH_8_MHZ:
133 if (state->config.adc_clock)
134 adc_clock = state->config.adc_clock;
136 value = 64 * bw * (1<<16) / (7 * 8);
137 value = value * 1000 / adc_clock;
138 dprintk("%s: bw %d, adc_clock %d => 0x%x\n",
139 __FUNCTION__, bw, adc_clock, value);
144 static void mt352_calc_input_freq(struct mt352_state* state,
147 int adc_clock = 20480; /* 20.480000 MHz */
148 int if2 = 36167; /* 36.166667 MHz */
151 if (state->config.adc_clock)
152 adc_clock = state->config.adc_clock;
153 if (state->config.if2)
154 if2 = state->config.if2;
156 ife = (2*adc_clock - if2);
157 value = -16374 * ife / adc_clock;
158 dprintk("%s: if2 %d, ife %d, adc_clock %d => %d / 0x%x\n",
159 __FUNCTION__, if2, ife, adc_clock, value, value & 0x3fff);
164 static int mt352_set_parameters(struct dvb_frontend* fe,
165 struct dvb_frontend_parameters *param)
167 struct mt352_state* state = fe->demodulator_priv;
168 unsigned char buf[13];
169 static unsigned char tuner_go[] = { 0x5d, 0x01 };
170 static unsigned char fsm_go[] = { 0x5e, 0x01 };
171 unsigned int tps = 0;
172 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
174 switch (op->code_rate_HP) {
194 switch (op->code_rate_LP) {
211 if (op->hierarchy_information == HIERARCHY_AUTO ||
212 op->hierarchy_information == HIERARCHY_NONE)
218 switch (op->constellation) {
232 switch (op->transmission_mode) {
233 case TRANSMISSION_MODE_2K:
234 case TRANSMISSION_MODE_AUTO:
236 case TRANSMISSION_MODE_8K:
243 switch (op->guard_interval) {
244 case GUARD_INTERVAL_1_32:
245 case GUARD_INTERVAL_AUTO:
247 case GUARD_INTERVAL_1_16:
250 case GUARD_INTERVAL_1_8:
253 case GUARD_INTERVAL_1_4:
260 switch (op->hierarchy_information) {
278 buf[0] = TPS_GIVEN_1; /* TPS_GIVEN_1 and following registers */
280 buf[1] = msb(tps); /* TPS_GIVEN_(1|0) */
283 buf[3] = 0x50; // old
284 // buf[3] = 0xf4; // pinnacle
286 mt352_calc_nominal_rate(state, op->bandwidth, buf+4);
287 mt352_calc_input_freq(state, buf+6);
289 if (state->config.no_tuner) {
290 if (fe->ops.tuner_ops.set_params) {
291 fe->ops.tuner_ops.set_params(fe, param);
292 if (fe->ops.i2c_gate_ctrl)
293 fe->ops.i2c_gate_ctrl(fe, 0);
296 _mt352_write(fe, buf, 8);
297 _mt352_write(fe, fsm_go, 2);
299 if (fe->ops.tuner_ops.calc_regs) {
300 fe->ops.tuner_ops.calc_regs(fe, param, buf+8, 5);
302 _mt352_write(fe, buf, sizeof(buf));
303 _mt352_write(fe, tuner_go, 2);
310 static int mt352_get_parameters(struct dvb_frontend* fe,
311 struct dvb_frontend_parameters *param)
313 struct mt352_state* state = fe->demodulator_priv;
317 struct dvb_ofdm_parameters *op = ¶m->u.ofdm;
318 static const u8 tps_fec_to_api[8] =
330 if ( (mt352_read_register(state,0x00) & 0xC0) != 0xC0 )
333 /* Use TPS_RECEIVED-registers, not the TPS_CURRENT-registers because
334 * the mt352 sometimes works with the wrong parameters
336 tps = (mt352_read_register(state, TPS_RECEIVED_1) << 8) | mt352_read_register(state, TPS_RECEIVED_0);
337 div = (mt352_read_register(state, CHAN_START_1) << 8) | mt352_read_register(state, CHAN_START_0);
338 trl = mt352_read_register(state, TRL_NOMINAL_RATE_1);
340 op->code_rate_HP = tps_fec_to_api[(tps >> 7) & 7];
341 op->code_rate_LP = tps_fec_to_api[(tps >> 4) & 7];
343 switch ( (tps >> 13) & 3)
346 op->constellation = QPSK;
349 op->constellation = QAM_16;
352 op->constellation = QAM_64;
355 op->constellation = QAM_AUTO;
359 op->transmission_mode = (tps & 0x01) ? TRANSMISSION_MODE_8K : TRANSMISSION_MODE_2K;
361 switch ( (tps >> 2) & 3)
364 op->guard_interval = GUARD_INTERVAL_1_32;
367 op->guard_interval = GUARD_INTERVAL_1_16;
370 op->guard_interval = GUARD_INTERVAL_1_8;
373 op->guard_interval = GUARD_INTERVAL_1_4;
376 op->guard_interval = GUARD_INTERVAL_AUTO;
380 switch ( (tps >> 10) & 7)
383 op->hierarchy_information = HIERARCHY_NONE;
386 op->hierarchy_information = HIERARCHY_1;
389 op->hierarchy_information = HIERARCHY_2;
392 op->hierarchy_information = HIERARCHY_4;
395 op->hierarchy_information = HIERARCHY_AUTO;
399 param->frequency = ( 500 * (div - IF_FREQUENCYx6) ) / 3 * 1000;
402 op->bandwidth = BANDWIDTH_8_MHZ;
403 else if (trl == 0x64)
404 op->bandwidth = BANDWIDTH_7_MHZ;
406 op->bandwidth = BANDWIDTH_6_MHZ;
409 if (mt352_read_register(state, STATUS_2) & 0x02)
410 param->inversion = INVERSION_OFF;
412 param->inversion = INVERSION_ON;
417 static int mt352_read_status(struct dvb_frontend* fe, fe_status_t* status)
419 struct mt352_state* state = fe->demodulator_priv;
424 * The MT352 design manual from Zarlink states (page 46-47):
426 * Notes about the TUNER_GO register:
428 * If the Read_Tuner_Byte (bit-1) is activated, then the tuner status
429 * byte is copied from the tuner to the STATUS_3 register and
430 * completion of the read operation is indicated by bit-5 of the
431 * INTERRUPT_3 register.
434 if ((s0 = mt352_read_register(state, STATUS_0)) < 0)
436 if ((s1 = mt352_read_register(state, STATUS_1)) < 0)
438 if ((s3 = mt352_read_register(state, STATUS_3)) < 0)
443 *status |= FE_HAS_CARRIER;
445 *status |= FE_HAS_VITERBI;
447 *status |= FE_HAS_LOCK;
449 *status |= FE_HAS_SYNC;
451 *status |= FE_HAS_SIGNAL;
453 if ((*status & (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC)) !=
454 (FE_HAS_CARRIER | FE_HAS_VITERBI | FE_HAS_SYNC))
455 *status &= ~FE_HAS_LOCK;
460 static int mt352_read_ber(struct dvb_frontend* fe, u32* ber)
462 struct mt352_state* state = fe->demodulator_priv;
464 *ber = (mt352_read_register (state, RS_ERR_CNT_2) << 16) |
465 (mt352_read_register (state, RS_ERR_CNT_1) << 8) |
466 (mt352_read_register (state, RS_ERR_CNT_0));
471 static int mt352_read_signal_strength(struct dvb_frontend* fe, u16* strength)
473 struct mt352_state* state = fe->demodulator_priv;
475 /* align the 12 bit AGC gain with the most significant bits */
476 u16 signal = ((mt352_read_register(state, AGC_GAIN_1) & 0x0f) << 12) |
477 (mt352_read_register(state, AGC_GAIN_0) << 4);
479 /* inverse of gain is signal strength */
484 static int mt352_read_snr(struct dvb_frontend* fe, u16* snr)
486 struct mt352_state* state = fe->demodulator_priv;
488 u8 _snr = mt352_read_register (state, SNR);
489 *snr = (_snr << 8) | _snr;
494 static int mt352_read_ucblocks(struct dvb_frontend* fe, u32* ucblocks)
496 struct mt352_state* state = fe->demodulator_priv;
498 *ucblocks = (mt352_read_register (state, RS_UBC_1) << 8) |
499 (mt352_read_register (state, RS_UBC_0));
504 static int mt352_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fe_tune_settings)
506 fe_tune_settings->min_delay_ms = 800;
507 fe_tune_settings->step_size = 0;
508 fe_tune_settings->max_drift = 0;
513 static int mt352_init(struct dvb_frontend* fe)
515 struct mt352_state* state = fe->demodulator_priv;
517 static u8 mt352_reset_attach [] = { RESET, 0xC0 };
519 dprintk("%s: hello\n",__FUNCTION__);
521 if ((mt352_read_register(state, CLOCK_CTL) & 0x10) == 0 ||
522 (mt352_read_register(state, CONFIG) & 0x20) == 0) {
524 /* Do a "hard" reset */
525 _mt352_write(fe, mt352_reset_attach, sizeof(mt352_reset_attach));
526 return state->config.demod_init(fe);
532 static void mt352_release(struct dvb_frontend* fe)
534 struct mt352_state* state = fe->demodulator_priv;
538 static struct dvb_frontend_ops mt352_ops;
540 struct dvb_frontend* mt352_attach(const struct mt352_config* config,
541 struct i2c_adapter* i2c)
543 struct mt352_state* state = NULL;
545 /* allocate memory for the internal state */
546 state = kzalloc(sizeof(struct mt352_state), GFP_KERNEL);
547 if (state == NULL) goto error;
549 /* setup the state */
551 memcpy(&state->config,config,sizeof(struct mt352_config));
553 /* check if the demod is there */
554 if (mt352_read_register(state, CHIP_ID) != ID_MT352) goto error;
556 /* create dvb_frontend */
557 memcpy(&state->frontend.ops, &mt352_ops, sizeof(struct dvb_frontend_ops));
558 state->frontend.demodulator_priv = state;
559 return &state->frontend;
566 static struct dvb_frontend_ops mt352_ops = {
569 .name = "Zarlink MT352 DVB-T",
571 .frequency_min = 174000000,
572 .frequency_max = 862000000,
573 .frequency_stepsize = 166667,
574 .frequency_tolerance = 0,
575 .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
576 FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
578 FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
579 FE_CAN_TRANSMISSION_MODE_AUTO | FE_CAN_GUARD_INTERVAL_AUTO |
580 FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER |
584 .release = mt352_release,
587 .sleep = mt352_sleep,
588 .write = _mt352_write,
590 .set_frontend = mt352_set_parameters,
591 .get_frontend = mt352_get_parameters,
592 .get_tune_settings = mt352_get_tune_settings,
594 .read_status = mt352_read_status,
595 .read_ber = mt352_read_ber,
596 .read_signal_strength = mt352_read_signal_strength,
597 .read_snr = mt352_read_snr,
598 .read_ucblocks = mt352_read_ucblocks,
601 module_param(debug, int, 0644);
602 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
604 MODULE_DESCRIPTION("Zarlink MT352 DVB-T Demodulator driver");
605 MODULE_AUTHOR("Holger Waechtler, Daniel Mack, Antonio Mancuso");
606 MODULE_LICENSE("GPL");
608 EXPORT_SYMBOL(mt352_attach);