drivers/media/dvb/frontends/drxd_hard.c

   1 /*
   2  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
   3  *
   4  * Copyright (C) 2003-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <asm/div64.h>
  32
  33 #include "dvb_frontend.h"
  34 #include "drxd.h"
  35 #include "drxd_firm.h"
  36
  37 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
  38 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
  39
  40 #define CHUNK_SIZE 48
  41
  42 #define DRX_I2C_RMW           0x10
  43 #define DRX_I2C_BROADCAST     0x20
  44 #define DRX_I2C_CLEARCRC      0x80
  45 #define DRX_I2C_SINGLE_MASTER 0xC0
  46 #define DRX_I2C_MODEFLAGS     0xC0
  47 #define DRX_I2C_FLAGS         0xF0
  48
  49 #ifndef SIZEOF_ARRAY
  50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
  51 #endif
  52
  53 #define DEFAULT_LOCK_TIMEOUT    1100
  54
  55 #define DRX_CHANNEL_AUTO 0
  56 #define DRX_CHANNEL_HIGH 1
  57 #define DRX_CHANNEL_LOW  2
  58
  59 #define DRX_LOCK_MPEG  1
  60 #define DRX_LOCK_FEC   2
  61 #define DRX_LOCK_DEMOD 4
  62
  63 /****************************************************************************/
  64
  65 enum CSCDState {
  66         CSCD_INIT = 0,
  67         CSCD_SET,
  68         CSCD_SAVED
  69 };
  70
  71 enum CDrxdState {
  72         DRXD_UNINITIALIZED = 0,
  73         DRXD_STOPPED,
  74         DRXD_STARTED
  75 };
  76
  77 enum AGC_CTRL_MODE {
  78         AGC_CTRL_AUTO = 0,
  79         AGC_CTRL_USER,
  80         AGC_CTRL_OFF
  81 };
  82
  83 enum OperationMode {
  84         OM_Default,
  85         OM_DVBT_Diversity_Front,
  86         OM_DVBT_Diversity_End
  87 };
  88
  89 struct SCfgAgc {
  90         enum AGC_CTRL_MODE ctrlMode;
  91         u16 outputLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  92         u16 settleLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  93         u16 minOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  94         u16 maxOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  95         u16 speed;              /* range [0, ... , 1023], 1/n of fullscale range */
  96
  97         u16 R1;
  98         u16 R2;
  99         u16 R3;
 100 };
 101
 102 struct SNoiseCal {
 103         int cpOpt;
 104         u16 cpNexpOfs;
 105         u16 tdCal2k;
 106         u16 tdCal8k;
 107 };
 108
 109 enum app_env {
 110         APPENV_STATIC = 0,
 111         APPENV_PORTABLE = 1,
 112         APPENV_MOBILE = 2
 113 };
 114
 115 enum EIFFilter {
 116         IFFILTER_SAW = 0,
 117         IFFILTER_DISCRETE = 1
 118 };
 119
 120 struct drxd_state {
 121         struct dvb_frontend frontend;
 122         struct dvb_frontend_ops ops;
 123         struct dvb_frontend_parameters param;
 124
 125         const struct firmware *fw;
 126         struct device *dev;
 127
 128         struct i2c_adapter *i2c;
 129         void *priv;
 130         struct drxd_config config;
 131
 132         int i2c_access;
 133         int init_done;
 134         struct mutex mutex;
 135
 136         u8 chip_adr;
 137         u16 hi_cfg_timing_div;
 138         u16 hi_cfg_bridge_delay;
 139         u16 hi_cfg_wakeup_key;
 140         u16 hi_cfg_ctrl;
 141
 142         u16 intermediate_freq;
 143         u16 osc_clock_freq;
 144
 145         enum CSCDState cscd_state;
 146         enum CDrxdState drxd_state;
 147
 148         u16 sys_clock_freq;
 149         s16 osc_clock_deviation;
 150         u16 expected_sys_clock_freq;
 151
 152         u16 insert_rs_byte;
 153         u16 enable_parallel;
 154
 155         int operation_mode;
 156
 157         struct SCfgAgc if_agc_cfg;
 158         struct SCfgAgc rf_agc_cfg;
 159
 160         struct SNoiseCal noise_cal;
 161
 162         u32 fe_fs_add_incr;
 163         u32 org_fe_fs_add_incr;
 164         u16 current_fe_if_incr;
 165
 166         u16 m_FeAgRegAgPwd;
 167         u16 m_FeAgRegAgAgcSio;
 168
 169         u16 m_EcOcRegOcModeLop;
 170         u16 m_EcOcRegSncSncLvl;
 171         u8 *m_InitAtomicRead;
 172         u8 *m_HiI2cPatch;
 173
 174         u8 *m_ResetCEFR;
 175         u8 *m_InitFE_1;
 176         u8 *m_InitFE_2;
 177         u8 *m_InitCP;
 178         u8 *m_InitCE;
 179         u8 *m_InitEQ;
 180         u8 *m_InitSC;
 181         u8 *m_InitEC;
 182         u8 *m_ResetECRAM;
 183         u8 *m_InitDiversityFront;
 184         u8 *m_InitDiversityEnd;
 185         u8 *m_DisableDiversity;
 186         u8 *m_StartDiversityFront;
 187         u8 *m_StartDiversityEnd;
 188
 189         u8 *m_DiversityDelay8MHZ;
 190         u8 *m_DiversityDelay6MHZ;
 191
 192         u8 *microcode;
 193         u32 microcode_length;
 194
 195         int type_A;
 196         int PGA;
 197         int diversity;
 198         int tuner_mirrors;
 199
 200         enum app_env app_env_default;
 201         enum app_env app_env_diversity;
 202
 203 };
 204
 205 /****************************************************************************/
 206 /* I2C **********************************************************************/
 207 /****************************************************************************/
 208
 209 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
 210 {
 211         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
 212
 213         if (i2c_transfer(adap, &msg, 1) != 1)
 214                 return -1;
 215         return 0;
 216 }
 217
 218 static int i2c_read(struct i2c_adapter *adap,
 219                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 220 {
 221         struct i2c_msg msgs[2] = {
 222                 {
 223                         .addr = adr, .flags = 0,
 224                         .buf = msg, .len = len
 225                 }, {
 226                         .addr = adr, .flags = I2C_M_RD,
 227                         .buf = answ, .len = alen
 228                 }
 229         };
 230         if (i2c_transfer(adap, msgs, 2) != 2)
 231                 return -1;
 232         return 0;
 233 }
 234
 235 inline u32 MulDiv32(u32 a, u32 b, u32 c)
 236 {
 237         u64 tmp64;
 238
 239         tmp64 = (u64)a * (u64)b;
 240         do_div(tmp64, c);
 241
 242         return (u32) tmp64;
 243 }
 244
 245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
 246 {
 247         u8 adr = state->config.demod_address;
 248         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 249                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 250         };
 251         u8 mm2[2];
 252         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
 253                 return -1;
 254         if (data)
 255                 *data = mm2[0] | (mm2[1] << 8);
 256         return mm2[0] | (mm2[1] << 8);
 257 }
 258
 259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
 260 {
 261         u8 adr = state->config.demod_address;
 262         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 263                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 264         };
 265         u8 mm2[4];
 266
 267         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
 268                 return -1;
 269         if (data)
 270                 *data =
 271                     mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
 272         return 0;
 273 }
 274
 275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
 276 {
 277         u8 adr = state->config.demod_address;
 278         u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
 279                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 280                 data & 0xff, (data >> 8) & 0xff
 281         };
 282
 283         if (i2c_write(state->i2c, adr, mm, 6) < 0)
 284                 return -1;
 285         return 0;
 286 }
 287
 288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
 289 {
 290         u8 adr = state->config.demod_address;
 291         u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
 292                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 293                 data & 0xff, (data >> 8) & 0xff,
 294                 (data >> 16) & 0xff, (data >> 24) & 0xff
 295         };
 296
 297         if (i2c_write(state->i2c, adr, mm, 8) < 0)
 298                 return -1;
 299         return 0;
 300 }
 301
 302 static int write_chunk(struct drxd_state *state,
 303                        u32 reg, u8 *data, u32 len, u8 flags)
 304 {
 305         u8 adr = state->config.demod_address;
 306         u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
 307                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 308         };
 309         int i;
 310
 311         for (i = 0; i < len; i++)
 312                 mm[4 + i] = data[i];
 313         if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
 314                 printk(KERN_ERR "error in write_chunk\n");
 315                 return -1;
 316         }
 317         return 0;
 318 }
 319
 320 static int WriteBlock(struct drxd_state *state,
 321                       u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
 322 {
 323         while (BlockSize > 0) {
 324                 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
 325
 326                 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
 327                         return -1;
 328                 pBlock += Chunk;
 329                 Address += (Chunk >> 1);
 330                 BlockSize -= Chunk;
 331         }
 332         return 0;
 333 }
 334
 335 static int WriteTable(struct drxd_state *state, u8 * pTable)
 336 {
 337         int status = 0;
 338
 339         if (pTable == NULL)
 340                 return 0;
 341
 342         while (!status) {
 343                 u16 Length;
 344                 u32 Address = pTable[0] | (pTable[1] << 8) |
 345                     (pTable[2] << 16) | (pTable[3] << 24);
 346
 347                 if (Address == 0xFFFFFFFF)
 348                         break;
 349                 pTable += sizeof(u32);
 350
 351                 Length = pTable[0] | (pTable[1] << 8);
 352                 pTable += sizeof(u16);
 353                 if (!Length)
 354                         break;
 355                 status = WriteBlock(state, Address, Length * 2, pTable, 0);
 356                 pTable += (Length * 2);
 357         }
 358         return status;
 359 }
 360
 361 /****************************************************************************/
 362 /****************************************************************************/
 363 /****************************************************************************/
 364
 365 static int ResetCEFR(struct drxd_state *state)
 366 {
 367         return WriteTable(state, state->m_ResetCEFR);
 368 }
 369
 370 static int InitCP(struct drxd_state *state)
 371 {
 372         return WriteTable(state, state->m_InitCP);
 373 }
 374
 375 static int InitCE(struct drxd_state *state)
 376 {
 377         int status;
 378         enum app_env AppEnv = state->app_env_default;
 379
 380         do {
 381                 status = WriteTable(state, state->m_InitCE);
 382                 if (status < 0)
 383                         break;
 384
 385                 if (state->operation_mode == OM_DVBT_Diversity_Front ||
 386                     state->operation_mode == OM_DVBT_Diversity_End) {
 387                         AppEnv = state->app_env_diversity;
 388                 }
 389                 if (AppEnv == APPENV_STATIC) {
 390                         status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
 391                         if (status < 0)
 392                                 break;
 393                 } else if (AppEnv == APPENV_PORTABLE) {
 394                         status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
 395                         if (status < 0)
 396                                 break;
 397                 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
 398                         status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
 399                         if (status < 0)
 400                                 break;
 401                 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
 402                         status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
 403                         if (status < 0)
 404                                 break;
 405                 }
 406
 407                 /* start ce */
 408                 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
 409                 if (status < 0)
 410                         break;
 411         } while (0);
 412         return status;
 413 }
 414
 415 static int StopOC(struct drxd_state *state)
 416 {
 417         int status = 0;
 418         u16 ocSyncLvl = 0;
 419         u16 ocModeLop = state->m_EcOcRegOcModeLop;
 420         u16 dtoIncLop = 0;
 421         u16 dtoIncHip = 0;
 422
 423         do {
 424                 /* Store output configuration */
 425                 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
 426                 if (status < 0)
 427                         break;
 428                 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
 429                 state->m_EcOcRegSncSncLvl = ocSyncLvl;
 430                 /* m_EcOcRegOcModeLop = ocModeLop; */
 431
 432                 /* Flush FIFO (byte-boundary) at fixed rate */
 433                 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
 434                 if (status < 0)
 435                         break;
 436                 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
 437                 if (status < 0)
 438                         break;
 439                 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
 440                 if (status < 0)
 441                         break;
 442                 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
 443                 if (status < 0)
 444                         break;
 445                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
 446                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
 447                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 448                 if (status < 0)
 449                         break;
 450                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 451                 if (status < 0)
 452                         break;
 453
 454                 msleep(1);
 455                 /* Output pins to '0' */
 456                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
 457                 if (status < 0)
 458                         break;
 459
 460                 /* Force the OC out of sync */
 461                 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
 462                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
 463                 if (status < 0)
 464                         break;
 465                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
 466                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
 467                 ocModeLop |= 0x2;       /* Magically-out-of-sync */
 468                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 469                 if (status < 0)
 470                         break;
 471                 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
 472                 if (status < 0)
 473                         break;
 474                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 475                 if (status < 0)
 476                         break;
 477         } while (0);
 478
 479         return status;
 480 }
 481
 482 static int StartOC(struct drxd_state *state)
 483 {
 484         int status = 0;
 485
 486         do {
 487                 /* Stop OC */
 488                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 489                 if (status < 0)
 490                         break;
 491
 492                 /* Restore output configuration */
 493                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
 494                 if (status < 0)
 495                         break;
 496                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
 497                 if (status < 0)
 498                         break;
 499
 500                 /* Output pins active again */
 501                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
 502                 if (status < 0)
 503                         break;
 504
 505                 /* Start OC */
 506                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 507                 if (status < 0)
 508                         break;
 509         } while (0);
 510         return status;
 511 }
 512
 513 static int InitEQ(struct drxd_state *state)
 514 {
 515         return WriteTable(state, state->m_InitEQ);
 516 }
 517
 518 static int InitEC(struct drxd_state *state)
 519 {
 520         return WriteTable(state, state->m_InitEC);
 521 }
 522
 523 static int InitSC(struct drxd_state *state)
 524 {
 525         return WriteTable(state, state->m_InitSC);
 526 }
 527
 528 static int InitAtomicRead(struct drxd_state *state)
 529 {
 530         return WriteTable(state, state->m_InitAtomicRead);
 531 }
 532
 533 static int CorrectSysClockDeviation(struct drxd_state *state);
 534
 535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
 536 {
 537         u16 ScRaRamLock = 0;
 538         const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
 539                                     SC_RA_RAM_LOCK_FEC__M |
 540                                     SC_RA_RAM_LOCK_DEMOD__M);
 541         const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
 542                                    SC_RA_RAM_LOCK_DEMOD__M);
 543         const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
 544
 545         int status;
 546
 547         *pLockStatus = 0;
 548
 549         status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
 550         if (status < 0) {
 551                 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
 552                 return status;
 553         }
 554
 555         if (state->drxd_state != DRXD_STARTED)
 556                 return 0;
 557
 558         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
 559                 *pLockStatus |= DRX_LOCK_MPEG;
 560                 CorrectSysClockDeviation(state);
 561         }
 562
 563         if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
 564                 *pLockStatus |= DRX_LOCK_FEC;
 565
 566         if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
 567                 *pLockStatus |= DRX_LOCK_DEMOD;
 568         return 0;
 569 }
 570
 571 /****************************************************************************/
 572
 573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 574 {
 575         int status;
 576
 577         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 578                 return -1;
 579
 580         if (cfg->ctrlMode == AGC_CTRL_USER) {
 581                 do {
 582                         u16 FeAgRegPm1AgcWri;
 583                         u16 FeAgRegAgModeLop;
 584
 585                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 586                         if (status < 0)
 587                                 break;
 588                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 589                         FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
 590                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 591                         if (status < 0)
 592                                 break;
 593
 594                         FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
 595                                                   FE_AG_REG_PM1_AGC_WRI__M);
 596                         status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
 597                         if (status < 0)
 598                                 break;
 599                 } while (0);
 600         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 601                 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
 602                     ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
 603                     ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
 604                     ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
 605                     )
 606                         return -1;
 607                 do {
 608                         u16 FeAgRegAgModeLop;
 609                         u16 FeAgRegEgcSetLvl;
 610                         u16 slope, offset;
 611
 612                         /* == Mode == */
 613
 614                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 615                         if (status < 0)
 616                                 break;
 617                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 618                         FeAgRegAgModeLop |=
 619                             FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
 620                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 621                         if (status < 0)
 622                                 break;
 623
 624                         /* == Settle level == */
 625
 626                         FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
 627                                                   FE_AG_REG_EGC_SET_LVL__M);
 628                         status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
 629                         if (status < 0)
 630                                 break;
 631
 632                         /* == Min/Max == */
 633
 634                         slope = (u16) ((cfg->maxOutputLevel -
 635                                         cfg->minOutputLevel) / 2);
 636                         offset = (u16) ((cfg->maxOutputLevel +
 637                                          cfg->minOutputLevel) / 2 - 511);
 638
 639                         status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
 640                         if (status < 0)
 641                                 break;
 642                         status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
 643                         if (status < 0)
 644                                 break;
 645
 646                         /* == Speed == */
 647                         {
 648                                 const u16 maxRur = 8;
 649                                 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
 650                                 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
 651                                         17, 18, 18, 19,
 652                                         20, 21, 22, 23,
 653                                         24, 26, 27, 28,
 654                                         29, 31
 655                                 };
 656
 657                                 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
 658                                     (maxRur + 1);
 659                                 u16 fineSpeed = (u16) (cfg->speed -
 660                                                        ((cfg->speed /
 661                                                          fineSteps) *
 662                                                         fineSteps));
 663                                 u16 invRurCount = (u16) (cfg->speed /
 664                                                          fineSteps);
 665                                 u16 rurCount;
 666                                 if (invRurCount > maxRur) {
 667                                         rurCount = 0;
 668                                         fineSpeed += fineSteps;
 669                                 } else {
 670                                         rurCount = maxRur - invRurCount;
 671                                 }
 672
 673                                 /*
 674                                    fastInc = default *
 675                                    (2^(fineSpeed/fineSteps))
 676                                    => range[default...2*default>
 677                                    slowInc = default *
 678                                    (2^(fineSpeed/fineSteps))
 679                                  */
 680                                 {
 681                                         u16 fastIncrDec =
 682                                             fastIncrDecLUT[fineSpeed /
 683                                                            ((fineSteps /
 684                                                              (14 + 1)) + 1)];
 685                                         u16 slowIncrDec =
 686                                             slowIncrDecLUT[fineSpeed /
 687                                                            (fineSteps /
 688                                                             (3 + 1))];
 689
 690                                         status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
 691                                         if (status < 0)
 692                                                 break;
 693                                         status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
 694                                         if (status < 0)
 695                                                 break;
 696                                         status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
 697                                         if (status < 0)
 698                                                 break;
 699                                         status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
 700                                         if (status < 0)
 701                                                 break;
 702                                         status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
 703                                         if (status < 0)
 704                                                 break;
 705                                 }
 706                         }
 707                 } while (0);
 708
 709         } else {
 710                 /* No OFF mode for IF control */
 711                 return -1;
 712         }
 713         return status;
 714 }
 715
 716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 717 {
 718         int status = 0;
 719
 720         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 721                 return -1;
 722
 723         if (cfg->ctrlMode == AGC_CTRL_USER) {
 724                 do {
 725                         u16 AgModeLop = 0;
 726                         u16 level = (cfg->outputLevel);
 727
 728                         if (level == DRXD_FE_CTRL_MAX)
 729                                 level++;
 730
 731                         status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
 732                         if (status < 0)
 733                                 break;
 734
 735                         /*==== Mode ====*/
 736
 737                         /* Powerdown PD2, WRI source */
 738                         state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 739                         state->m_FeAgRegAgPwd |=
 740                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 741                         status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
 742                         if (status < 0)
 743                                 break;
 744
 745                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 746                         if (status < 0)
 747                                 break;
 748                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 749                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 750                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 751                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 752                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 753                         if (status < 0)
 754                                 break;
 755
 756                         /* enable AGC2 pin */
 757                         {
 758                                 u16 FeAgRegAgAgcSio = 0;
 759                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 760                                 if (status < 0)
 761                                         break;
 762                                 FeAgRegAgAgcSio &=
 763                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 764                                 FeAgRegAgAgcSio |=
 765                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 766                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 767                                 if (status < 0)
 768                                         break;
 769                         }
 770
 771                 } while (0);
 772         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 773                 u16 AgModeLop = 0;
 774
 775                 do {
 776                         u16 level;
 777                         /* Automatic control */
 778                         /* Powerup PD2, AGC2 as output, TGC source */
 779                         (state->m_FeAgRegAgPwd) &=
 780                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 781                         (state->m_FeAgRegAgPwd) |=
 782                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 783                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 784                         if (status < 0)
 785                                 break;
 786
 787                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 788                         if (status < 0)
 789                                 break;
 790                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 791                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 792                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 793                                       FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
 794                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 795                         if (status < 0)
 796                                 break;
 797                         /* Settle level */
 798                         level = (((cfg->settleLevel) >> 4) &
 799                                  FE_AG_REG_TGC_SET_LVL__M);
 800                         status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
 801                         if (status < 0)
 802                                 break;
 803
 804                         /* Min/max: don't care */
 805
 806                         /* Speed: TODO */
 807
 808                         /* enable AGC2 pin */
 809                         {
 810                                 u16 FeAgRegAgAgcSio = 0;
 811                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 812                                 if (status < 0)
 813                                         break;
 814                                 FeAgRegAgAgcSio &=
 815                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 816                                 FeAgRegAgAgcSio |=
 817                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 818                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 819                                 if (status < 0)
 820                                         break;
 821                         }
 822
 823                 } while (0);
 824         } else {
 825                 u16 AgModeLop = 0;
 826
 827                 do {
 828                         /* No RF AGC control */
 829                         /* Powerdown PD2, AGC2 as output, WRI source */
 830                         (state->m_FeAgRegAgPwd) &=
 831                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 832                         (state->m_FeAgRegAgPwd) |=
 833                             FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
 834                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 835                         if (status < 0)
 836                                 break;
 837
 838                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 839                         if (status < 0)
 840                                 break;
 841                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 842                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 843                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 844                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 845                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 846                         if (status < 0)
 847                                 break;
 848
 849                         /* set FeAgRegAgAgcSio AGC2 (RF) as input */
 850                         {
 851                                 u16 FeAgRegAgAgcSio = 0;
 852                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 853                                 if (status < 0)
 854                                         break;
 855                                 FeAgRegAgAgcSio &=
 856                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 857                                 FeAgRegAgAgcSio |=
 858                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
 859                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 860                                 if (status < 0)
 861                                         break;
 862                         }
 863                 } while (0);
 864         }
 865         return status;
 866 }
 867
 868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
 869 {
 870         int status = 0;
 871
 872         *pValue = 0;
 873         if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
 874                 u16 Value;
 875                 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
 876                 Value &= FE_AG_REG_GC1_AGC_DAT__M;
 877                 if (status >= 0) {
 878                         /*           3.3V
 879                            |
 880                            R1
 881                            |
 882                            Vin - R3 - * -- Vout
 883                            |
 884                            R2
 885                            |
 886                            GND
 887                          */
 888                         u32 R1 = state->if_agc_cfg.R1;
 889                         u32 R2 = state->if_agc_cfg.R2;
 890                         u32 R3 = state->if_agc_cfg.R3;
 891
 892                         u32 Vmax = (3300 * R2) / (R1 + R2);
 893                         u32 Rpar = (R2 * R3) / (R3 + R2);
 894                         u32 Vmin = (3300 * Rpar) / (R1 + Rpar);
 895                         u32 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
 896
 897                         *pValue = Vout;
 898                 }
 899         }
 900         return status;
 901 }
 902
 903 static int load_firmware(struct drxd_state *state, const char *fw_name)
 904 {
 905         const struct firmware *fw;
 906
 907         if (request_firmware(&fw, fw_name, state->dev) < 0) {
 908                 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
 909                 return -EIO;
 910         }
 911
 912         state->microcode = kzalloc(fw->size, GFP_KERNEL);
 913         if (state->microcode == NULL) {
 914                 printk(KERN_ERR "drxd: firmware load failure: nomemory\n");
 915                 return -ENOMEM;
 916         }
 917
 918         memcpy(state->microcode, fw->data, fw->size);
 919         state->microcode_length = fw->size;
 920         return 0;
 921 }
 922
 923 static int DownloadMicrocode(struct drxd_state *state,
 924                              const u8 *pMCImage, u32 Length)
 925 {
 926         u8 *pSrc;
 927         u16 Flags;
 928         u32 Address;
 929         u16 nBlocks;
 930         u16 BlockSize;
 931         u16 BlockCRC;
 932         u32 offset = 0;
 933         int i, status = 0;
 934
 935         pSrc = (u8 *) pMCImage;
 936         Flags = (pSrc[0] << 8) | pSrc[1];
 937         pSrc += sizeof(u16);
 938         offset += sizeof(u16);
 939         nBlocks = (pSrc[0] << 8) | pSrc[1];
 940         pSrc += sizeof(u16);
 941         offset += sizeof(u16);
 942
 943         for (i = 0; i < nBlocks; i++) {
 944                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
 945                     (pSrc[2] << 8) | pSrc[3];
 946                 pSrc += sizeof(u32);
 947                 offset += sizeof(u32);
 948
 949                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
 950                 pSrc += sizeof(u16);
 951                 offset += sizeof(u16);
 952
 953                 Flags = (pSrc[0] << 8) | pSrc[1];
 954                 pSrc += sizeof(u16);
 955                 offset += sizeof(u16);
 956
 957                 BlockCRC = (pSrc[0] << 8) | pSrc[1];
 958                 pSrc += sizeof(u16);
 959                 offset += sizeof(u16);
 960
 961                 status = WriteBlock(state, Address, BlockSize,
 962                                     pSrc, DRX_I2C_CLEARCRC);
 963                 if (status < 0)
 964                         break;
 965                 pSrc += BlockSize;
 966                 offset += BlockSize;
 967         }
 968
 969         return status;
 970 }
 971
 972 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
 973 {
 974         u32 nrRetries = 0;
 975         u16 waitCmd;
 976         int status;
 977
 978         status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
 979         if (status < 0)
 980                 return status;
 981
 982         do {
 983                 nrRetries += 1;
 984                 if (nrRetries > DRXD_MAX_RETRIES) {
 985                         status = -1;
 986                         break;
 987                 };
 988                 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
 989         } while (waitCmd != 0);
 990
 991         if (status >= 0)
 992                 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
 993         return status;
 994 }
 995
 996 static int HI_CfgCommand(struct drxd_state *state)
 997 {
 998         int status = 0;
 999
1000         mutex_lock(&state->mutex);
1001         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1002         Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1003         Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1004         Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1005         Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1006
1007         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1008
1009         if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1010             HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1011                 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1012                                  HI_RA_RAM_SRV_CMD_CONFIG, 0);
1013         else
1014                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1015         mutex_unlock(&state->mutex);
1016         return status;
1017 }
1018
1019 static int InitHI(struct drxd_state *state)
1020 {
1021         state->hi_cfg_wakeup_key = (state->chip_adr);
1022         /* port/bridge/power down ctrl */
1023         state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1024         return HI_CfgCommand(state);
1025 }
1026
1027 static int HI_ResetCommand(struct drxd_state *state)
1028 {
1029         int status;
1030
1031         mutex_lock(&state->mutex);
1032         status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1033                          HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1034         if (status == 0)
1035                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1036         mutex_unlock(&state->mutex);
1037         msleep(1);
1038         return status;
1039 }
1040
1041 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1042 {
1043         state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1044         if (bEnableBridge)
1045                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1046         else
1047                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1048
1049         return HI_CfgCommand(state);
1050 }
1051
1052 #define HI_TR_WRITE      0x9
1053 #define HI_TR_READ       0xA
1054 #define HI_TR_READ_WRITE 0xB
1055 #define HI_TR_BROADCAST  0x4
1056
1057 #if 0
1058 static int AtomicReadBlock(struct drxd_state *state,
1059                            u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1060 {
1061         int status;
1062         int i = 0;
1063
1064         /* Parameter check */
1065         if ((!pData) || ((DataSize & 1) != 0))
1066                 return -1;
1067
1068         mutex_lock(&state->mutex);
1069
1070         do {
1071                 /* Instruct HI to read n bytes */
1072                 /* TODO use proper names forthese egisters */
1073                 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1074                 if (status < 0)
1075                         break;
1076                 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1077                 if (status < 0)
1078                         break;
1079                 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1080                 if (status < 0)
1081                         break;
1082                 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1083                 if (status < 0)
1084                         break;
1085                 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1086                 if (status < 0)
1087                         break;
1088
1089                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1090                 if (status < 0)
1091                         break;
1092
1093         } while (0);
1094
1095         if (status >= 0) {
1096                 for (i = 0; i < (DataSize / 2); i += 1) {
1097                         u16 word;
1098
1099                         status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1100                                         &word, 0);
1101                         if (status < 0)
1102                                 break;
1103                         pData[2 * i] = (u8) (word & 0xFF);
1104                         pData[(2 * i) + 1] = (u8) (word >> 8);
1105                 }
1106         }
1107         mutex_unlock(&state->mutex);
1108         return status;
1109 }
1110
1111 static int AtomicReadReg32(struct drxd_state *state,
1112                            u32 Addr, u32 *pData, u8 Flags)
1113 {
1114         u8 buf[sizeof(u32)];
1115         int status;
1116
1117         if (!pData)
1118                 return -1;
1119         status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1120         *pData = (((u32) buf[0]) << 0) +
1121             (((u32) buf[1]) << 8) +
1122             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1123         return status;
1124 }
1125 #endif
1126
1127 static int StopAllProcessors(struct drxd_state *state)
1128 {
1129         return Write16(state, HI_COMM_EXEC__A,
1130                        SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1131 }
1132
1133 static int EnableAndResetMB(struct drxd_state *state)
1134 {
1135         if (state->type_A) {
1136                 /* disable? monitor bus observe @ EC_OC */
1137                 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1138         }
1139
1140         /* do inverse broadcast, followed by explicit write to HI */
1141         Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1142         Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1143         return 0;
1144 }
1145
1146 static int InitCC(struct drxd_state *state)
1147 {
1148         if (state->osc_clock_freq == 0 ||
1149             state->osc_clock_freq > 20000 ||
1150             (state->osc_clock_freq % 4000) != 0) {
1151                 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1152                 return -1;
1153         }
1154
1155         Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1156         Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1157                 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1158         Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1159         Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1160         Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1161
1162         return 0;
1163 }
1164
1165 static int ResetECOD(struct drxd_state *state)
1166 {
1167         int status = 0;
1168
1169         if (state->type_A)
1170                 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1171         else
1172                 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1173
1174         if (!(status < 0))
1175                 status = WriteTable(state, state->m_ResetECRAM);
1176         if (!(status < 0))
1177                 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1178         return status;
1179 }
1180
1181 /* Configure PGA switch */
1182
1183 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1184 {
1185         int status;
1186         u16 AgModeLop = 0;
1187         u16 AgModeHip = 0;
1188         do {
1189                 if (pgaSwitch) {
1190                         /* PGA on */
1191                         /* fine gain */
1192                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1193                         if (status < 0)
1194                                 break;
1195                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1196                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1197                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1198                         if (status < 0)
1199                                 break;
1200
1201                         /* coarse gain */
1202                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1203                         if (status < 0)
1204                                 break;
1205                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1206                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1207                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1208                         if (status < 0)
1209                                 break;
1210
1211                         /* enable fine and coarse gain, enable AAF,
1212                            no ext resistor */
1213                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1214                         if (status < 0)
1215                                 break;
1216                 } else {
1217                         /* PGA off, bypass */
1218
1219                         /* fine gain */
1220                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1221                         if (status < 0)
1222                                 break;
1223                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1224                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1225                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1226                         if (status < 0)
1227                                 break;
1228
1229                         /* coarse gain */
1230                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1231                         if (status < 0)
1232                                 break;
1233                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1234                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1235                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1236                         if (status < 0)
1237                                 break;
1238
1239                         /* disable fine and coarse gain, enable AAF,
1240                            no ext resistor */
1241                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1242                         if (status < 0)
1243                                 break;
1244                 }
1245         } while (0);
1246         return status;
1247 }
1248
1249 static int InitFE(struct drxd_state *state)
1250 {
1251         int status;
1252
1253         do {
1254                 status = WriteTable(state, state->m_InitFE_1);
1255                 if (status < 0)
1256                         break;
1257
1258                 if (state->type_A) {
1259                         status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1260                                          FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1261                                          0);
1262                 } else {
1263                         if (state->PGA)
1264                                 status = SetCfgPga(state, 0);
1265                         else
1266                                 status =
1267                                     Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1268                                             B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1269                                             0);
1270                 }
1271
1272                 if (status < 0)
1273                         break;
1274                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1275                 if (status < 0)
1276                         break;
1277                 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1278                 if (status < 0)
1279                         break;
1280
1281                 status = WriteTable(state, state->m_InitFE_2);
1282                 if (status < 0)
1283                         break;
1284
1285         } while (0);
1286
1287         return status;
1288 }
1289
1290 static int InitFT(struct drxd_state *state)
1291 {
1292         /*
1293            norm OFFSET,  MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1294            SC stuff
1295          */
1296         return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1297 }
1298
1299 static int SC_WaitForReady(struct drxd_state *state)
1300 {
1301         u16 curCmd;
1302         int i;
1303
1304         for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1305                 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1306                 if (status == 0 || curCmd == 0)
1307                         return status;
1308         }
1309         return -1;
1310 }
1311
1312 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1313 {
1314         int status = 0;
1315         u16 errCode;
1316
1317         Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1318         SC_WaitForReady(state);
1319
1320         Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1321
1322         if (errCode == 0xFFFF) {
1323                 printk(KERN_ERR "Command Error\n");
1324                 status = -1;
1325         }
1326
1327         return status;
1328 }
1329
1330 static int SC_ProcStartCommand(struct drxd_state *state,
1331                                u16 subCmd, u16 param0, u16 param1)
1332 {
1333         int status = 0;
1334         u16 scExec;
1335
1336         mutex_lock(&state->mutex);
1337         do {
1338                 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1339                 if (scExec != 1) {
1340                         status = -1;
1341                         break;
1342                 }
1343                 SC_WaitForReady(state);
1344                 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1345                 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1346                 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1347
1348                 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1349         } while (0);
1350         mutex_unlock(&state->mutex);
1351         return status;
1352 }
1353
1354 static int SC_SetPrefParamCommand(struct drxd_state *state,
1355                                   u16 subCmd, u16 param0, u16 param1)
1356 {
1357         int status;
1358
1359         mutex_lock(&state->mutex);
1360         do {
1361                 status = SC_WaitForReady(state);
1362                 if (status < 0)
1363                         break;
1364                 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1365                 if (status < 0)
1366                         break;
1367                 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1368                 if (status < 0)
1369                         break;
1370                 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1371                 if (status < 0)
1372                         break;
1373
1374                 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1375                 if (status < 0)
1376                         break;
1377         } while (0);
1378         mutex_unlock(&state->mutex);
1379         return status;
1380 }
1381
1382 #if 0
1383 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1384 {
1385         int status = 0;
1386
1387         mutex_lock(&state->mutex);
1388         do {
1389                 status = SC_WaitForReady(state);
1390                 if (status < 0)
1391                         break;
1392                 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1393                 if (status < 0)
1394                         break;
1395                 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1396                 if (status < 0)
1397                         break;
1398         } while (0);
1399         mutex_unlock(&state->mutex);
1400         return status;
1401 }
1402 #endif
1403
1404 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1405 {
1406         int status;
1407
1408         do {
1409                 u16 EcOcRegIprInvMpg = 0;
1410                 u16 EcOcRegOcModeLop = 0;
1411                 u16 EcOcRegOcModeHip = 0;
1412                 u16 EcOcRegOcMpgSio = 0;
1413
1414                 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1415
1416                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1417                         if (bEnableOutput) {
1418                                 EcOcRegOcModeHip |=
1419                                     B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1420                         } else
1421                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1422                         EcOcRegOcModeLop |=
1423                             EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1424                 } else {
1425                         EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1426
1427                         if (bEnableOutput)
1428                                 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1429                         else
1430                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1431
1432                         /* Don't Insert RS Byte */
1433                         if (state->insert_rs_byte) {
1434                                 EcOcRegOcModeLop &=
1435                                     (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1436                                 EcOcRegOcModeHip &=
1437                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1438                                 EcOcRegOcModeHip |=
1439                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1440                         } else {
1441                                 EcOcRegOcModeLop |=
1442                                     EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1443                                 EcOcRegOcModeHip &=
1444                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1445                                 EcOcRegOcModeHip |=
1446                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1447                         }
1448
1449                         /* Mode = Parallel */
1450                         if (state->enable_parallel)
1451                                 EcOcRegOcModeLop &=
1452                                     (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1453                         else
1454                                 EcOcRegOcModeLop |=
1455                                     EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1456                 }
1457                 /* Invert Data */
1458                 /* EcOcRegIprInvMpg |= 0x00FF; */
1459                 EcOcRegIprInvMpg &= (~(0x00FF));
1460
1461                 /* Invert Error ( we don't use the pin ) */
1462                 /*  EcOcRegIprInvMpg |= 0x0100; */
1463                 EcOcRegIprInvMpg &= (~(0x0100));
1464
1465                 /* Invert Start ( we don't use the pin ) */
1466                 /* EcOcRegIprInvMpg |= 0x0200; */
1467                 EcOcRegIprInvMpg &= (~(0x0200));
1468
1469                 /* Invert Valid ( we don't use the pin ) */
1470                 /* EcOcRegIprInvMpg |= 0x0400; */
1471                 EcOcRegIprInvMpg &= (~(0x0400));
1472
1473                 /* Invert Clock */
1474                 /* EcOcRegIprInvMpg |= 0x0800; */
1475                 EcOcRegIprInvMpg &= (~(0x0800));
1476
1477                 /* EcOcRegOcModeLop =0x05; */
1478                 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1479                 if (status < 0)
1480                         break;
1481                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1482                 if (status < 0)
1483                         break;
1484                 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1485                 if (status < 0)
1486                         break;
1487                 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1488                 if (status < 0)
1489                         break;
1490         } while (0);
1491         return status;
1492 }
1493
1494 static int SetDeviceTypeId(struct drxd_state *state)
1495 {
1496         int status = 0;
1497         u16 deviceId = 0;
1498
1499         do {
1500                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1501                 if (status < 0)
1502                         break;
1503                 /* TODO: why twice? */
1504                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1505                 if (status < 0)
1506                         break;
1507                 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1508
1509                 state->type_A = 0;
1510                 state->PGA = 0;
1511                 state->diversity = 0;
1512                 if (deviceId == 0) {    /* on A2 only 3975 available */
1513                         state->type_A = 1;
1514                         printk(KERN_INFO "DRX3975D-A2\n");
1515                 } else {
1516                         deviceId >>= 12;
1517                         printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1518                         switch (deviceId) {
1519                         case 4:
1520                                 state->diversity = 1;
1521                         case 3:
1522                         case 7:
1523                                 state->PGA = 1;
1524                                 break;
1525                         case 6:
1526                                 state->diversity = 1;
1527                         case 5:
1528                         case 8:
1529                                 break;
1530                         default:
1531                                 status = -1;
1532                                 break;
1533                         }
1534                 }
1535         } while (0);
1536
1537         if (status < 0)
1538                 return status;
1539
1540         /* Init Table selection */
1541         state->m_InitAtomicRead = DRXD_InitAtomicRead;
1542         state->m_InitSC = DRXD_InitSC;
1543         state->m_ResetECRAM = DRXD_ResetECRAM;
1544         if (state->type_A) {
1545                 state->m_ResetCEFR = DRXD_ResetCEFR;
1546                 state->m_InitFE_1 = DRXD_InitFEA2_1;
1547                 state->m_InitFE_2 = DRXD_InitFEA2_2;
1548                 state->m_InitCP = DRXD_InitCPA2;
1549                 state->m_InitCE = DRXD_InitCEA2;
1550                 state->m_InitEQ = DRXD_InitEQA2;
1551                 state->m_InitEC = DRXD_InitECA2;
1552                 if (load_firmware(state, DRX_FW_FILENAME_A2))
1553                         return -EIO;
1554         } else {
1555                 state->m_ResetCEFR = NULL;
1556                 state->m_InitFE_1 = DRXD_InitFEB1_1;
1557                 state->m_InitFE_2 = DRXD_InitFEB1_2;
1558                 state->m_InitCP = DRXD_InitCPB1;
1559                 state->m_InitCE = DRXD_InitCEB1;
1560                 state->m_InitEQ = DRXD_InitEQB1;
1561                 state->m_InitEC = DRXD_InitECB1;
1562                 if (load_firmware(state, DRX_FW_FILENAME_B1))
1563                         return -EIO;
1564         }
1565         if (state->diversity) {
1566                 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1567                 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1568                 state->m_DisableDiversity = DRXD_DisableDiversity;
1569                 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1570                 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1571                 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1572                 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1573         } else {
1574                 state->m_InitDiversityFront = NULL;
1575                 state->m_InitDiversityEnd = NULL;
1576                 state->m_DisableDiversity = NULL;
1577                 state->m_StartDiversityFront = NULL;
1578                 state->m_StartDiversityEnd = NULL;
1579                 state->m_DiversityDelay8MHZ = NULL;
1580                 state->m_DiversityDelay6MHZ = NULL;
1581         }
1582
1583         return status;
1584 }
1585
1586 static int CorrectSysClockDeviation(struct drxd_state *state)
1587 {
1588         int status;
1589         s32 incr = 0;
1590         s32 nomincr = 0;
1591         u32 bandwidth = 0;
1592         u32 sysClockInHz = 0;
1593         u32 sysClockFreq = 0;   /* in kHz */
1594         s16 oscClockDeviation;
1595         s16 Diff;
1596
1597         do {
1598                 /* Retrieve bandwidth and incr, sanity check */
1599
1600                 /* These accesses should be AtomicReadReg32, but that
1601                    causes trouble (at least for diversity */
1602                 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1603                 if (status < 0)
1604                         break;
1605                 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1606                 if (status < 0)
1607                         break;
1608
1609                 if (state->type_A) {
1610                         if ((nomincr - incr < -500) || (nomincr - incr > 500))
1611                                 break;
1612                 } else {
1613                         if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1614                                 break;
1615                 }
1616
1617                 switch (state->param.u.ofdm.bandwidth) {
1618                 case BANDWIDTH_8_MHZ:
1619                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1620                         break;
1621                 case BANDWIDTH_7_MHZ:
1622                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1623                         break;
1624                 case BANDWIDTH_6_MHZ:
1625                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1626                         break;
1627                 default:
1628                         return -1;
1629                         break;
1630                 }
1631
1632                 /* Compute new sysclock value
1633                    sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1634                 incr += (1 << 23);
1635                 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1636                 sysClockFreq = (u32) (sysClockInHz / 1000);
1637                 /* rounding */
1638                 if ((sysClockInHz % 1000) > 500)
1639                         sysClockFreq++;
1640
1641                 /* Compute clock deviation in ppm */
1642                 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1643                                              (s32)
1644                                              (state->expected_sys_clock_freq)) *
1645                                             1000000L) /
1646                                            (s32)
1647                                            (state->expected_sys_clock_freq));
1648
1649                 Diff = oscClockDeviation - state->osc_clock_deviation;
1650                 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1651                 if (Diff >= -200 && Diff <= 200) {
1652                         state->sys_clock_freq = (u16) sysClockFreq;
1653                         if (oscClockDeviation != state->osc_clock_deviation) {
1654                                 if (state->config.osc_deviation) {
1655                                         state->config.osc_deviation(state->priv,
1656                                                                     oscClockDeviation,
1657                                                                     1);
1658                                         state->osc_clock_deviation =
1659                                             oscClockDeviation;
1660                                 }
1661                         }
1662                         /* switch OFF SRMM scan in SC */
1663                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1664                         if (status < 0)
1665                                 break;
1666                         /* overrule FE_IF internal value for
1667                            proper re-locking */
1668                         status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1669                         if (status < 0)
1670                                 break;
1671                         state->cscd_state = CSCD_SAVED;
1672                 }
1673         } while (0);
1674
1675         return status;
1676 }
1677
1678 static int DRX_Stop(struct drxd_state *state)
1679 {
1680         int status;
1681
1682         if (state->drxd_state != DRXD_STARTED)
1683                 return 0;
1684
1685         do {
1686                 if (state->cscd_state != CSCD_SAVED) {
1687                         u32 lock;
1688                         status = DRX_GetLockStatus(state, &lock);
1689                         if (status < 0)
1690                                 break;
1691                 }
1692
1693                 status = StopOC(state);
1694                 if (status < 0)
1695                         break;
1696
1697                 state->drxd_state = DRXD_STOPPED;
1698
1699                 status = ConfigureMPEGOutput(state, 0);
1700                 if (status < 0)
1701                         break;
1702
1703                 if (state->type_A) {
1704                         /* Stop relevant processors off the device */
1705                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1706                         if (status < 0)
1707                                 break;
1708
1709                         status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1710                         if (status < 0)
1711                                 break;
1712                         status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1713                         if (status < 0)
1714                                 break;
1715                 } else {
1716                         /* Stop all processors except HI & CC & FE */
1717                         status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1718                         if (status < 0)
1719                                 break;
1720                         status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1721                         if (status < 0)
1722                                 break;
1723                         status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1724                         if (status < 0)
1725                                 break;
1726                         status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1727                         if (status < 0)
1728                                 break;
1729                         status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1730                         if (status < 0)
1731                                 break;
1732                         status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1733                         if (status < 0)
1734                                 break;
1735                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1736                         if (status < 0)
1737                                 break;
1738                 }
1739
1740         } while (0);
1741         return status;
1742 }
1743
1744 int SetOperationMode(struct drxd_state *state, int oMode)
1745 {
1746         int status;
1747
1748         do {
1749                 if (state->drxd_state != DRXD_STOPPED) {
1750                         status = -1;
1751                         break;
1752                 }
1753
1754                 if (oMode == state->operation_mode) {
1755                         status = 0;
1756                         break;
1757                 }
1758
1759                 if (oMode != OM_Default && !state->diversity) {
1760                         status = -1;
1761                         break;
1762                 }
1763
1764                 switch (oMode) {
1765                 case OM_DVBT_Diversity_Front:
1766                         status = WriteTable(state, state->m_InitDiversityFront);
1767                         break;
1768                 case OM_DVBT_Diversity_End:
1769                         status = WriteTable(state, state->m_InitDiversityEnd);
1770                         break;
1771                 case OM_Default:
1772                         /* We need to check how to
1773                            get DRXD out of diversity */
1774                 default:
1775                         status = WriteTable(state, state->m_DisableDiversity);
1776                         break;
1777                 }
1778         } while (0);
1779
1780         if (!status)
1781                 state->operation_mode = oMode;
1782         return status;
1783 }
1784
1785 static int StartDiversity(struct drxd_state *state)
1786 {
1787         int status = 0;
1788         u16 rcControl;
1789
1790         do {
1791                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1792                         status = WriteTable(state, state->m_StartDiversityFront);
1793                         if (status < 0)
1794                                 break;
1795                 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1796                         status = WriteTable(state, state->m_StartDiversityEnd);
1797                         if (status < 0)
1798                                 break;
1799                         if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1800                                 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1801                                 if (status < 0)
1802                                         break;
1803                         } else {
1804                                 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1805                                 if (status < 0)
1806                                         break;
1807                         }
1808
1809                         status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1810                         if (status < 0)
1811                                 break;
1812                         rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1813                         rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1814                             /*  combining enabled */
1815                             B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1816                             B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1817                             B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1818                         status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1819                         if (status < 0)
1820                                 break;
1821                 }
1822         } while (0);
1823         return status;
1824 }
1825
1826 static int SetFrequencyShift(struct drxd_state *state,
1827                              u32 offsetFreq, int channelMirrored)
1828 {
1829         int negativeShift = (state->tuner_mirrors == channelMirrored);
1830
1831         /* Handle all mirroring
1832          *
1833          * Note: ADC mirroring (aliasing) is implictly handled by limiting
1834          * feFsRegAddInc to 28 bits below
1835          * (if the result before masking is more than 28 bits, this means
1836          *  that the ADC is mirroring.
1837          * The masking is in fact the aliasing of the ADC)
1838          *
1839          */
1840
1841         /* Compute register value, unsigned computation */
1842         state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1843                                          offsetFreq,
1844                                          1 << 28, state->sys_clock_freq);
1845         /* Remove integer part */
1846         state->fe_fs_add_incr &= 0x0FFFFFFFL;
1847         if (negativeShift)
1848                 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1849
1850         /* Save the frequency shift without tunerOffset compensation
1851            for CtrlGetChannel. */
1852         state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1853                                              1 << 28, state->sys_clock_freq);
1854         /* Remove integer part */
1855         state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1856         if (negativeShift)
1857                 state->org_fe_fs_add_incr = ((1L << 28) -
1858                                              state->org_fe_fs_add_incr);
1859
1860         return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1861                        state->fe_fs_add_incr, 0);
1862 }
1863
1864 static int SetCfgNoiseCalibration(struct drxd_state *state,
1865                                   struct SNoiseCal *noiseCal)
1866 {
1867         u16 beOptEna;
1868         int status = 0;
1869
1870         do {
1871                 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1872                 if (status < 0)
1873                         break;
1874                 if (noiseCal->cpOpt) {
1875                         beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1876                 } else {
1877                         beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1878                         status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1879                         if (status < 0)
1880                                 break;
1881                 }
1882                 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1883                 if (status < 0)
1884                         break;
1885
1886                 if (!state->type_A) {
1887                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1888                         if (status < 0)
1889                                 break;
1890                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1891                         if (status < 0)
1892                                 break;
1893                 }
1894         } while (0);
1895
1896         return status;
1897 }
1898
1899 static int DRX_Start(struct drxd_state *state, s32 off)
1900 {
1901         struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1902         int status;
1903
1904         u16 transmissionParams = 0;
1905         u16 operationMode = 0;
1906         u16 qpskTdTpsPwr = 0;
1907         u16 qam16TdTpsPwr = 0;
1908         u16 qam64TdTpsPwr = 0;
1909         u32 feIfIncr = 0;
1910         u32 bandwidth = 0;
1911         int mirrorFreqSpect;
1912
1913         u16 qpskSnCeGain = 0;
1914         u16 qam16SnCeGain = 0;
1915         u16 qam64SnCeGain = 0;
1916         u16 qpskIsGainMan = 0;
1917         u16 qam16IsGainMan = 0;
1918         u16 qam64IsGainMan = 0;
1919         u16 qpskIsGainExp = 0;
1920         u16 qam16IsGainExp = 0;
1921         u16 qam64IsGainExp = 0;
1922         u16 bandwidthParam = 0;
1923
1924         if (off < 0)
1925                 off = (off - 500) / 1000;
1926         else
1927                 off = (off + 500) / 1000;
1928
1929         do {
1930                 if (state->drxd_state != DRXD_STOPPED)
1931                         return -1;
1932                 status = ResetECOD(state);
1933                 if (status < 0)
1934                         break;
1935                 if (state->type_A) {
1936                         status = InitSC(state);
1937                         if (status < 0)
1938                                 break;
1939                 } else {
1940                         status = InitFT(state);
1941                         if (status < 0)
1942                                 break;
1943                         status = InitCP(state);
1944                         if (status < 0)
1945                                 break;
1946                         status = InitCE(state);
1947                         if (status < 0)
1948                                 break;
1949                         status = InitEQ(state);
1950                         if (status < 0)
1951                                 break;
1952                         status = InitSC(state);
1953                         if (status < 0)
1954                                 break;
1955                 }
1956
1957                 /* Restore current IF & RF AGC settings */
1958
1959                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1960                 if (status < 0)
1961                         break;
1962                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1963                 if (status < 0)
1964                         break;
1965
1966                 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1967
1968                 switch (p->transmission_mode) {
1969                 default:        /* Not set, detect it automatically */
1970                         operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1971                         /* fall through , try first guess DRX_FFTMODE_8K */
1972                 case TRANSMISSION_MODE_8K:
1973                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1974                         if (state->type_A) {
1975                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1976                                 if (status < 0)
1977                                         break;
1978                                 qpskSnCeGain = 99;
1979                                 qam16SnCeGain = 83;
1980                                 qam64SnCeGain = 67;
1981                         }
1982                         break;
1983                 case TRANSMISSION_MODE_2K:
1984                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1985                         if (state->type_A) {
1986                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1987                                 if (status < 0)
1988                                         break;
1989                                 qpskSnCeGain = 97;
1990                                 qam16SnCeGain = 71;
1991                                 qam64SnCeGain = 65;
1992                         }
1993                         break;
1994                 }
1995
1996                 switch (p->guard_interval) {
1997                 case GUARD_INTERVAL_1_4:
1998                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
1999                         break;
2000                 case GUARD_INTERVAL_1_8:
2001                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2002                         break;
2003                 case GUARD_INTERVAL_1_16:
2004                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2005                         break;
2006                 case GUARD_INTERVAL_1_32:
2007                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2008                         break;
2009                 default:        /* Not set, detect it automatically */
2010                         operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2011                         /* try first guess 1/4 */
2012                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2013                         break;
2014                 }
2015
2016                 switch (p->hierarchy_information) {
2017                 case HIERARCHY_1:
2018                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2019                         if (state->type_A) {
2020                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2021                                 if (status < 0)
2022                                         break;
2023                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2024                                 if (status < 0)
2025                                         break;
2026
2027                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2028                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2029                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2030
2031                                 qpskIsGainMan =
2032                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2033                                 qam16IsGainMan =
2034                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2035                                 qam64IsGainMan =
2036                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2037
2038                                 qpskIsGainExp =
2039                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2040                                 qam16IsGainExp =
2041                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2042                                 qam64IsGainExp =
2043                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2044                         }
2045                         break;
2046
2047                 case HIERARCHY_2:
2048                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2049                         if (state->type_A) {
2050                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2051                                 if (status < 0)
2052                                         break;
2053                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2054                                 if (status < 0)
2055                                         break;
2056
2057                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2058                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2059                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2060
2061                                 qpskIsGainMan =
2062                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2063                                 qam16IsGainMan =
2064                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2065                                 qam64IsGainMan =
2066                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2067
2068                                 qpskIsGainExp =
2069                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2070                                 qam16IsGainExp =
2071                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2072                                 qam64IsGainExp =
2073                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2074                         }
2075                         break;
2076                 case HIERARCHY_4:
2077                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2078                         if (state->type_A) {
2079                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2080                                 if (status < 0)
2081                                         break;
2082                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2083                                 if (status < 0)
2084                                         break;
2085
2086                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2087                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2088                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2089
2090                                 qpskIsGainMan =
2091                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2092                                 qam16IsGainMan =
2093                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2094                                 qam64IsGainMan =
2095                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2096
2097                                 qpskIsGainExp =
2098                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2099                                 qam16IsGainExp =
2100                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2101                                 qam64IsGainExp =
2102                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2103                         }
2104                         break;
2105                 case HIERARCHY_AUTO:
2106                 default:
2107                         /* Not set, detect it automatically, start with none */
2108                         operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2109                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2110                         if (state->type_A) {
2111                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2112                                 if (status < 0)
2113                                         break;
2114                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2115                                 if (status < 0)
2116                                         break;
2117
2118                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2119                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2120                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2121
2122                                 qpskIsGainMan =
2123                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2124                                 qam16IsGainMan =
2125                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2126                                 qam64IsGainMan =
2127                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2128
2129                                 qpskIsGainExp =
2130                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2131                                 qam16IsGainExp =
2132                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2133                                 qam64IsGainExp =
2134                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2135                         }
2136                         break;
2137                 }
2138                 status = status;
2139                 if (status < 0)
2140                         break;
2141
2142                 switch (p->constellation) {
2143                 default:
2144                         operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2145                         /* fall through , try first guess
2146                            DRX_CONSTELLATION_QAM64 */
2147                 case QAM_64:
2148                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2149                         if (state->type_A) {
2150                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2151                                 if (status < 0)
2152                                         break;
2153                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2154                                 if (status < 0)
2155                                         break;
2156                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2157                                 if (status < 0)
2158                                         break;
2159                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2160                                 if (status < 0)
2161                                         break;
2162                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2163                                 if (status < 0)
2164                                         break;
2165
2166                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2167                                 if (status < 0)
2168                                         break;
2169                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2170                                 if (status < 0)
2171                                         break;
2172                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2173                                 if (status < 0)
2174                                         break;
2175                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2176                                 if (status < 0)
2177                                         break;
2178                         }
2179                         break;
2180                 case QPSK:
2181                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2182                         if (state->type_A) {
2183                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2184                                 if (status < 0)
2185                                         break;
2186                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2187                                 if (status < 0)
2188                                         break;
2189                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2190                                 if (status < 0)
2191                                         break;
2192                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2193                                 if (status < 0)
2194                                         break;
2195                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2196                                 if (status < 0)
2197                                         break;
2198
2199                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2200                                 if (status < 0)
2201                                         break;
2202                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2203                                 if (status < 0)
2204                                         break;
2205                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2206                                 if (status < 0)
2207                                         break;
2208                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2209                                 if (status < 0)
2210                                         break;
2211                         }
2212                         break;
2213
2214                 case QAM_16:
2215                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2216                         if (state->type_A) {
2217                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2218                                 if (status < 0)
2219                                         break;
2220                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2221                                 if (status < 0)
2222                                         break;
2223                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2224                                 if (status < 0)
2225                                         break;
2226                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2227                                 if (status < 0)
2228                                         break;
2229                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2230                                 if (status < 0)
2231                                         break;
2232
2233                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2234                                 if (status < 0)
2235                                         break;
2236                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2237                                 if (status < 0)
2238                                         break;
2239                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2240                                 if (status < 0)
2241                                         break;
2242                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2243                                 if (status < 0)
2244                                         break;
2245                         }
2246                         break;
2247
2248                 }
2249                 status = status;
2250                 if (status < 0)
2251                         break;
2252
2253                 switch (DRX_CHANNEL_HIGH) {
2254                 default:
2255                 case DRX_CHANNEL_AUTO:
2256                 case DRX_CHANNEL_LOW:
2257                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2258                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2259                         if (status < 0)
2260                                 break;
2261                         break;
2262                 case DRX_CHANNEL_HIGH:
2263                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2264                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2265                         if (status < 0)
2266                                 break;
2267                         break;
2268
2269                 }
2270
2271                 switch (p->code_rate_HP) {
2272                 case FEC_1_2:
2273                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2274                         if (state->type_A) {
2275                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2276                                 if (status < 0)
2277                                         break;
2278                         }
2279                         break;
2280                 default:
2281                         operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2282                 case FEC_2_3:
2283                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2284                         if (state->type_A) {
2285                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2286                                 if (status < 0)
2287                                         break;
2288                         }
2289                         break;
2290                 case FEC_3_4:
2291                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2292                         if (state->type_A) {
2293                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2294                                 if (status < 0)
2295                                         break;
2296                         }
2297                         break;
2298                 case FEC_5_6:
2299                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2300                         if (state->type_A) {
2301                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2302                                 if (status < 0)
2303                                         break;
2304                         }
2305                         break;
2306                 case FEC_7_8:
2307                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2308                         if (state->type_A) {
2309                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2310                                 if (status < 0)
2311                                         break;
2312                         }
2313                         break;
2314                 }
2315                 status = status;
2316                 if (status < 0)
2317                         break;
2318
2319                 /* First determine real bandwidth (Hz) */
2320                 /* Also set delay for impulse noise cruncher (only A2) */
2321                 /* Also set parameters for EC_OC fix, note
2322                    EC_OC_REG_TMD_HIL_MAR is changed
2323                    by SC for fix for some 8K,1/8 guard but is restored by
2324                    InitEC and ResetEC
2325                    functions */
2326                 switch (p->bandwidth) {
2327                 case BANDWIDTH_AUTO:
2328                 case BANDWIDTH_8_MHZ:
2329                         /* (64/7)*(8/8)*1000000 */
2330                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2331
2332                         bandwidthParam = 0;
2333                         status = Write16(state,
2334                                          FE_AG_REG_IND_DEL__A, 50, 0x0000);
2335                         break;
2336                 case BANDWIDTH_7_MHZ:
2337                         /* (64/7)*(7/8)*1000000 */
2338                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2339                         bandwidthParam = 0x4807;        /*binary:0100 1000 0000 0111 */
2340                         status = Write16(state,
2341                                          FE_AG_REG_IND_DEL__A, 59, 0x0000);
2342                         break;
2343                 case BANDWIDTH_6_MHZ:
2344                         /* (64/7)*(6/8)*1000000 */
2345                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2346                         bandwidthParam = 0x0F07;        /*binary: 0000 1111 0000 0111 */
2347                         status = Write16(state,
2348                                          FE_AG_REG_IND_DEL__A, 71, 0x0000);
2349                         break;
2350                 default:
2351                         status = -EINVAL;
2352                 }
2353                 if (status < 0)
2354                         break;
2355
2356                 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2357                 if (status < 0)
2358                         break;
2359
2360                 {
2361                         u16 sc_config;
2362                         status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2363                         if (status < 0)
2364                                 break;
2365
2366                         /* enable SLAVE mode in 2k 1/32 to
2367                            prevent timing change glitches */
2368                         if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2369                             (p->guard_interval == GUARD_INTERVAL_1_32)) {
2370                                 /* enable slave */
2371                                 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2372                         } else {
2373                                 /* disable slave */
2374                                 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2375                         }
2376                         status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2377                         if (status < 0)
2378                                 break;
2379                 }
2380
2381                 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2382                 if (status < 0)
2383                         break;
2384
2385                 if (state->cscd_state == CSCD_INIT) {
2386                         /* switch on SRMM scan in SC */
2387                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2388                         if (status < 0)
2389                                 break;
2390 /*            CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2391                         state->cscd_state = CSCD_SET;
2392                 }
2393
2394                 /* Now compute FE_IF_REG_INCR */
2395                 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2396                    ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2397                 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2398                                     (1ULL << 21), bandwidth) - (1 << 23);
2399                 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2400                 if (status < 0)
2401                         break;
2402                 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2403                 if (status < 0)
2404                         break;
2405                 /* Bandwidth setting done */
2406
2407                 /* Mirror & frequency offset */
2408                 SetFrequencyShift(state, off, mirrorFreqSpect);
2409
2410                 /* Start SC, write channel settings to SC */
2411
2412                 /* Enable SC after setting all other parameters */
2413                 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2414                 if (status < 0)
2415                         break;
2416                 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2417                 if (status < 0)
2418                         break;
2419
2420                 /* Write SC parameter registers, operation mode */
2421 #if 1
2422                 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2423                                  SC_RA_RAM_OP_AUTO_GUARD__M |
2424                                  SC_RA_RAM_OP_AUTO_CONST__M |
2425                                  SC_RA_RAM_OP_AUTO_HIER__M |
2426                                  SC_RA_RAM_OP_AUTO_RATE__M);
2427 #endif
2428                 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2429                 if (status < 0)
2430                         break;
2431
2432                 /* Start correct processes to get in lock */
2433                 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2434                 if (status < 0)
2435                         break;
2436
2437                 status = StartOC(state);
2438                 if (status < 0)
2439                         break;
2440
2441                 if (state->operation_mode != OM_Default) {
2442                         status = StartDiversity(state);
2443                         if (status < 0)
2444                                 break;
2445                 }
2446
2447                 state->drxd_state = DRXD_STARTED;
2448         } while (0);
2449
2450         return status;
2451 }
2452
2453 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2454 {
2455         u32 ulRfAgcOutputLevel = 0xffffffff;
2456         u32 ulRfAgcSettleLevel = 528;   /* Optimum value for MT2060 */
2457         u32 ulRfAgcMinLevel = 0;        /* Currently unused */
2458         u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2459         u32 ulRfAgcSpeed = 0;   /* Currently unused */
2460         u32 ulRfAgcMode = 0;    /*2;   Off */
2461         u32 ulRfAgcR1 = 820;
2462         u32 ulRfAgcR2 = 2200;
2463         u32 ulRfAgcR3 = 150;
2464         u32 ulIfAgcMode = 0;    /* Auto */
2465         u32 ulIfAgcOutputLevel = 0xffffffff;
2466         u32 ulIfAgcSettleLevel = 0xffffffff;
2467         u32 ulIfAgcMinLevel = 0xffffffff;
2468         u32 ulIfAgcMaxLevel = 0xffffffff;
2469         u32 ulIfAgcSpeed = 0xffffffff;
2470         u32 ulIfAgcR1 = 820;
2471         u32 ulIfAgcR2 = 2200;
2472         u32 ulIfAgcR3 = 150;
2473         u32 ulClock = state->config.clock;
2474         u32 ulSerialMode = 0;
2475         u32 ulEcOcRegOcModeLop = 4;     /* Dynamic DTO source */
2476         u32 ulHiI2cDelay = HI_I2C_DELAY;
2477         u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2478         u32 ulHiI2cPatch = 0;
2479         u32 ulEnvironment = APPENV_PORTABLE;
2480         u32 ulEnvironmentDiversity = APPENV_MOBILE;
2481         u32 ulIFFilter = IFFILTER_SAW;
2482
2483         state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2484         state->if_agc_cfg.outputLevel = 0;
2485         state->if_agc_cfg.settleLevel = 140;
2486         state->if_agc_cfg.minOutputLevel = 0;
2487         state->if_agc_cfg.maxOutputLevel = 1023;
2488         state->if_agc_cfg.speed = 904;
2489
2490         if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2491                 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2492                 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2493         }
2494
2495         if (ulIfAgcMode == 0 &&
2496             ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2497             ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2498             ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2499             ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2500                 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2501                 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2502                 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2503                 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2504                 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2505         }
2506
2507         state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2508         state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2509         state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2510
2511         state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2512         state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2513         state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2514
2515         state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2516         /* rest of the RFAgcCfg structure currently unused */
2517         if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2518                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2519                 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2520         }
2521
2522         if (ulRfAgcMode == 0 &&
2523             ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2524             ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2525             ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2526             ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2527                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2528                 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2529                 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2530                 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2531                 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2532         }
2533
2534         if (ulRfAgcMode == 2)
2535                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2536
2537         if (ulEnvironment <= 2)
2538                 state->app_env_default = (enum app_env)
2539                     (ulEnvironment);
2540         if (ulEnvironmentDiversity <= 2)
2541                 state->app_env_diversity = (enum app_env)
2542                     (ulEnvironmentDiversity);
2543
2544         if (ulIFFilter == IFFILTER_DISCRETE) {
2545                 /* discrete filter */
2546                 state->noise_cal.cpOpt = 0;
2547                 state->noise_cal.cpNexpOfs = 40;
2548                 state->noise_cal.tdCal2k = -40;
2549                 state->noise_cal.tdCal8k = -24;
2550         } else {
2551                 /* SAW filter */
2552                 state->noise_cal.cpOpt = 1;
2553                 state->noise_cal.cpNexpOfs = 0;
2554                 state->noise_cal.tdCal2k = -21;
2555                 state->noise_cal.tdCal8k = -24;
2556         }
2557         state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2558
2559         state->chip_adr = (state->config.demod_address << 1) | 1;
2560         switch (ulHiI2cPatch) {
2561         case 1:
2562                 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2563                 break;
2564         case 3:
2565                 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2566                 break;
2567         default:
2568                 state->m_HiI2cPatch = NULL;
2569         }
2570
2571         /* modify tuner and clock attributes */
2572         state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2573         /* expected system clock frequency in kHz */
2574         state->expected_sys_clock_freq = 48000;
2575         /* real system clock frequency in kHz */
2576         state->sys_clock_freq = 48000;
2577         state->osc_clock_freq = (u16) ulClock;
2578         state->osc_clock_deviation = 0;
2579         state->cscd_state = CSCD_INIT;
2580         state->drxd_state = DRXD_UNINITIALIZED;
2581
2582         state->PGA = 0;
2583         state->type_A = 0;
2584         state->tuner_mirrors = 0;
2585
2586         /* modify MPEG output attributes */
2587         state->insert_rs_byte = state->config.insert_rs_byte;
2588         state->enable_parallel = (ulSerialMode != 1);
2589
2590         /* Timing div, 250ns/Psys */
2591         /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2592
2593         state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2594                                           ulHiI2cDelay) / 1000;
2595         /* Bridge delay, uses oscilator clock */
2596         /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2597         state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2598                                             ulHiI2cBridgeDelay) / 1000;
2599
2600         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2601         /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2602         state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2603         return 0;
2604 }
2605
2606 int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2607 {
2608         int status = 0;
2609         u32 driverVersion;
2610
2611         if (state->init_done)
2612                 return 0;
2613
2614         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2615
2616         do {
2617                 state->operation_mode = OM_Default;
2618
2619                 status = SetDeviceTypeId(state);
2620                 if (status < 0)
2621                         break;
2622
2623                 /* Apply I2c address patch to B1 */
2624                 if (!state->type_A && state->m_HiI2cPatch != NULL)
2625                         status = WriteTable(state, state->m_HiI2cPatch);
2626                         if (status < 0)
2627                                 break;
2628
2629                 if (state->type_A) {
2630                         /* HI firmware patch for UIO readout,
2631                            avoid clearing of result register */
2632                         status = Write16(state, 0x43012D, 0x047f, 0);
2633                         if (status < 0)
2634                                 break;
2635                 }
2636
2637                 status = HI_ResetCommand(state);
2638                 if (status < 0)
2639                         break;
2640
2641                 status = StopAllProcessors(state);
2642                 if (status < 0)
2643                         break;
2644                 status = InitCC(state);
2645                 if (status < 0)
2646                         break;
2647
2648                 state->osc_clock_deviation = 0;
2649
2650                 if (state->config.osc_deviation)
2651                         state->osc_clock_deviation =
2652                             state->config.osc_deviation(state->priv, 0, 0);
2653                 {
2654                         /* Handle clock deviation */
2655                         s32 devB;
2656                         s32 devA = (s32) (state->osc_clock_deviation) *
2657                             (s32) (state->expected_sys_clock_freq);
2658                         /* deviation in kHz */
2659                         s32 deviation = (devA / (1000000L));
2660                         /* rounding, signed */
2661                         if (devA > 0)
2662                                 devB = (2);
2663                         else
2664                                 devB = (-2);
2665                         if ((devB * (devA % 1000000L) > 1000000L)) {
2666                                 /* add +1 or -1 */
2667                                 deviation += (devB / 2);
2668                         }
2669
2670                         state->sys_clock_freq =
2671                             (u16) ((state->expected_sys_clock_freq) +
2672                                    deviation);
2673                 }
2674                 status = InitHI(state);
2675                 if (status < 0)
2676                         break;
2677                 status = InitAtomicRead(state);
2678                 if (status < 0)
2679                         break;
2680
2681                 status = EnableAndResetMB(state);
2682                 if (status < 0)
2683                         break;
2684                 if (state->type_A)
2685                         status = ResetCEFR(state);
2686                         if (status < 0)
2687                                 break;
2688
2689                 if (fw) {
2690                         status = DownloadMicrocode(state, fw, fw_size);
2691                         if (status < 0)
2692                                 break;
2693                 } else {
2694                         status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2695                         if (status < 0)
2696                                 break;
2697                 }
2698
2699                 if (state->PGA) {
2700                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2701                         SetCfgPga(state, 0);    /* PGA = 0 dB */
2702                 } else {
2703                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2704                 }
2705
2706                 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2707
2708                 status = InitFE(state);
2709                 if (status < 0)
2710                         break;
2711                 status = InitFT(state);
2712                 if (status < 0)
2713                         break;
2714                 status = InitCP(state);
2715                 if (status < 0)
2716                         break;
2717                 status = InitCE(state);
2718                 if (status < 0)
2719                         break;
2720                 status = InitEQ(state);
2721                 if (status < 0)
2722                         break;
2723                 status = InitEC(state);
2724                 if (status < 0)
2725                         break;
2726                 status = InitSC(state);
2727                 if (status < 0)
2728                         break;
2729
2730                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2731                 if (status < 0)
2732                         break;
2733                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2734                 if (status < 0)
2735                         break;
2736
2737                 state->cscd_state = CSCD_INIT;
2738                 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2739                 if (status < 0)
2740                         break;
2741                 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2742                 if (status < 0)
2743                         break;
2744
2745                 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2746                                  (VERSION_MAJOR % 10)) << 24;
2747                 driverVersion += (((VERSION_MINOR / 10) << 4) +
2748                                   (VERSION_MINOR % 10)) << 16;
2749                 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2750                     ((VERSION_PATCH / 100) << 8) +
2751                     ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2752
2753                 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2754                 if (status < 0)
2755                         break;
2756
2757                 status = StopOC(state);
2758                 if (status < 0)
2759                         break;
2760
2761                 state->drxd_state = DRXD_STOPPED;
2762                 state->init_done = 1;
2763                 status = 0;
2764         } while (0);
2765         return status;
2766 }
2767
2768 int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2769 {
2770         DRX_GetLockStatus(state, pLockStatus);
2771
2772         /*if (*pLockStatus&DRX_LOCK_MPEG) */
2773         if (*pLockStatus & DRX_LOCK_FEC) {
2774                 ConfigureMPEGOutput(state, 1);
2775                 /* Get status again, in case we have MPEG lock now */
2776                 /*DRX_GetLockStatus(state, pLockStatus); */
2777         }
2778
2779         return 0;
2780 }
2781
2782 /****************************************************************************/
2783 /****************************************************************************/
2784 /****************************************************************************/
2785
2786 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2787 {
2788         struct drxd_state *state = fe->demodulator_priv;
2789         u32 value;
2790         int res;
2791
2792         res = ReadIFAgc(state, &value);
2793         if (res < 0)
2794                 *strength = 0;
2795         else
2796                 *strength = 0xffff - (value << 4);
2797         return 0;
2798 }
2799
2800 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2801 {
2802         struct drxd_state *state = fe->demodulator_priv;
2803         u32 lock;
2804
2805         DRXD_status(state, &lock);
2806         *status = 0;
2807         /* No MPEG lock in V255 firmware, bug ? */
2808 #if 1
2809         if (lock & DRX_LOCK_MPEG)
2810                 *status |= FE_HAS_LOCK;
2811 #else
2812         if (lock & DRX_LOCK_FEC)
2813                 *status |= FE_HAS_LOCK;
2814 #endif
2815         if (lock & DRX_LOCK_FEC)
2816                 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2817         if (lock & DRX_LOCK_DEMOD)
2818                 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2819
2820         return 0;
2821 }
2822
2823 static int drxd_init(struct dvb_frontend *fe)
2824 {
2825         struct drxd_state *state = fe->demodulator_priv;
2826         int err = 0;
2827
2828 /*      if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2829         return DRXD_init(state, 0, 0);
2830
2831         err = DRXD_init(state, state->fw->data, state->fw->size);
2832         release_firmware(state->fw);
2833         return err;
2834 }
2835
2836 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2837 {
2838         struct drxd_state *state = fe->demodulator_priv;
2839
2840         if (state->config.disable_i2c_gate_ctrl == 1)
2841                 return 0;
2842
2843         return DRX_ConfigureI2CBridge(state, onoff);
2844 }
2845 EXPORT_SYMBOL(drxd_config_i2c);
2846
2847 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2848                                   struct dvb_frontend_tune_settings *sets)
2849 {
2850         sets->min_delay_ms = 10000;
2851         sets->max_drift = 0;
2852         sets->step_size = 0;
2853         return 0;
2854 }
2855
2856 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2857 {
2858         *ber = 0;
2859         return 0;
2860 }
2861
2862 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2863 {
2864         *snr = 0;
2865         return 0;
2866 }
2867
2868 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2869 {
2870         *ucblocks = 0;
2871         return 0;
2872 }
2873
2874 static int drxd_sleep(struct dvb_frontend *fe)
2875 {
2876         struct drxd_state *state = fe->demodulator_priv;
2877
2878         ConfigureMPEGOutput(state, 0);
2879         return 0;
2880 }
2881
2882 static int drxd_get_frontend(struct dvb_frontend *fe,
2883                              struct dvb_frontend_parameters *param)
2884 {
2885         return 0;
2886 }
2887
2888 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2889 {
2890         return drxd_config_i2c(fe, enable);
2891 }
2892
2893 static int drxd_set_frontend(struct dvb_frontend *fe,
2894                              struct dvb_frontend_parameters *param)
2895 {
2896         struct drxd_state *state = fe->demodulator_priv;
2897         s32 off = 0;
2898
2899         state->param = *param;
2900         DRX_Stop(state);
2901
2902         if (fe->ops.tuner_ops.set_params) {
2903                 fe->ops.tuner_ops.set_params(fe, param);
2904                 if (fe->ops.i2c_gate_ctrl)
2905                         fe->ops.i2c_gate_ctrl(fe, 0);
2906         }
2907
2908         /* FIXME: move PLL drivers */
2909         if (state->config.pll_set &&
2910             state->config.pll_set(state->priv, param,
2911                                   state->config.pll_address,
2912                                   state->config.demoda_address, &off) < 0) {
2913                 printk(KERN_ERR "Error in pll_set\n");
2914                 return -1;
2915         }
2916
2917         msleep(200);
2918
2919         return DRX_Start(state, off);
2920 }
2921
2922 static void drxd_release(struct dvb_frontend *fe)
2923 {
2924         struct drxd_state *state = fe->demodulator_priv;
2925
2926         kfree(state);
2927 }
2928
2929 static struct dvb_frontend_ops drxd_ops = {
2930
2931         .info = {
2932                  .name = "Micronas DRXD DVB-T",
2933                  .type = FE_OFDM,
2934                  .frequency_min = 47125000,
2935                  .frequency_max = 855250000,
2936                  .frequency_stepsize = 166667,
2937                  .frequency_tolerance = 0,
2938                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2939                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2940                  FE_CAN_FEC_AUTO |
2941                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2942                  FE_CAN_QAM_AUTO |
2943                  FE_CAN_TRANSMISSION_MODE_AUTO |
2944                  FE_CAN_GUARD_INTERVAL_AUTO |
2945                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2946
2947         .release = drxd_release,
2948         .init = drxd_init,
2949         .sleep = drxd_sleep,
2950         .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2951
2952         .set_frontend = drxd_set_frontend,
2953         .get_frontend = drxd_get_frontend,
2954         .get_tune_settings = drxd_get_tune_settings,
2955
2956         .read_status = drxd_read_status,
2957         .read_ber = drxd_read_ber,
2958         .read_signal_strength = drxd_read_signal_strength,
2959         .read_snr = drxd_read_snr,
2960         .read_ucblocks = drxd_read_ucblocks,
2961 };
2962
2963 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2964                                  void *priv, struct i2c_adapter *i2c,
2965                                  struct device *dev)
2966 {
2967         struct drxd_state *state = NULL;
2968
2969         state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2970         if (!state)
2971                 return NULL;
2972         memset(state, 0, sizeof(*state));
2973
2974         memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2975         state->dev = dev;
2976         state->config = *config;
2977         state->i2c = i2c;
2978         state->priv = priv;
2979
2980         mutex_init(&state->mutex);
2981
2982         if (Read16(state, 0, 0, 0) < 0)
2983                 goto error;
2984
2985         memcpy(&state->frontend.ops, &drxd_ops,
2986                sizeof(struct dvb_frontend_ops));
2987         state->frontend.demodulator_priv = state;
2988         ConfigureMPEGOutput(state, 0);
2989         return &state->frontend;
2990
2991 error:
2992         printk(KERN_ERR "drxd: not found\n");
2993         kfree(state);
2994         return NULL;
2995 }
2996 EXPORT_SYMBOL(drxd_attach);
2997
2998 MODULE_DESCRIPTION("DRXD driver");
2999 MODULE_AUTHOR("Micronas");
3000 MODULE_LICENSE("GPL");