drivers/media/dvb/frontends/drxd_hard.c

   1 /*
   2  * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
   3  *
   4  * Copyright (C) 2003-2007 Micronas
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * version 2 only, as published by the Free Software Foundation.
   9  *
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  20  * 02110-1301, USA
  21  * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/delay.h>
  29 #include <linux/firmware.h>
  30 #include <linux/i2c.h>
  31 #include <asm/div64.h>
  32
  33 #include "dvb_frontend.h"
  34 #include "drxd.h"
  35 #include "drxd_firm.h"
  36
  37 #define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
  38 #define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
  39
  40 #define CHUNK_SIZE 48
  41
  42 #define DRX_I2C_RMW           0x10
  43 #define DRX_I2C_BROADCAST     0x20
  44 #define DRX_I2C_CLEARCRC      0x80
  45 #define DRX_I2C_SINGLE_MASTER 0xC0
  46 #define DRX_I2C_MODEFLAGS     0xC0
  47 #define DRX_I2C_FLAGS         0xF0
  48
  49 #ifndef SIZEOF_ARRAY
  50 #define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
  51 #endif
  52
  53 #define DEFAULT_LOCK_TIMEOUT    1100
  54
  55 #define DRX_CHANNEL_AUTO 0
  56 #define DRX_CHANNEL_HIGH 1
  57 #define DRX_CHANNEL_LOW  2
  58
  59 #define DRX_LOCK_MPEG  1
  60 #define DRX_LOCK_FEC   2
  61 #define DRX_LOCK_DEMOD 4
  62
  63 /****************************************************************************/
  64
  65 enum CSCDState {
  66         CSCD_INIT = 0,
  67         CSCD_SET,
  68         CSCD_SAVED
  69 };
  70
  71 enum CDrxdState {
  72         DRXD_UNINITIALIZED = 0,
  73         DRXD_STOPPED,
  74         DRXD_STARTED
  75 };
  76
  77 enum AGC_CTRL_MODE {
  78         AGC_CTRL_AUTO = 0,
  79         AGC_CTRL_USER,
  80         AGC_CTRL_OFF
  81 };
  82
  83 enum OperationMode {
  84         OM_Default,
  85         OM_DVBT_Diversity_Front,
  86         OM_DVBT_Diversity_End
  87 };
  88
  89 struct SCfgAgc {
  90         enum AGC_CTRL_MODE ctrlMode;
  91         u16 outputLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  92         u16 settleLevel;        /* range [0, ... , 1023], 1/n of fullscale range */
  93         u16 minOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  94         u16 maxOutputLevel;     /* range [0, ... , 1023], 1/n of fullscale range */
  95         u16 speed;              /* range [0, ... , 1023], 1/n of fullscale range */
  96
  97         u16 R1;
  98         u16 R2;
  99         u16 R3;
 100 };
 101
 102 struct SNoiseCal {
 103         int cpOpt;
 104         u16 cpNexpOfs;
 105         u16 tdCal2k;
 106         u16 tdCal8k;
 107 };
 108
 109 enum app_env {
 110         APPENV_STATIC = 0,
 111         APPENV_PORTABLE = 1,
 112         APPENV_MOBILE = 2
 113 };
 114
 115 enum EIFFilter {
 116         IFFILTER_SAW = 0,
 117         IFFILTER_DISCRETE = 1
 118 };
 119
 120 struct drxd_state {
 121         struct dvb_frontend frontend;
 122         struct dvb_frontend_ops ops;
 123         struct dvb_frontend_parameters param;
 124
 125         const struct firmware *fw;
 126         struct device *dev;
 127
 128         struct i2c_adapter *i2c;
 129         void *priv;
 130         struct drxd_config config;
 131
 132         int i2c_access;
 133         int init_done;
 134         struct mutex mutex;
 135
 136         u8 chip_adr;
 137         u16 hi_cfg_timing_div;
 138         u16 hi_cfg_bridge_delay;
 139         u16 hi_cfg_wakeup_key;
 140         u16 hi_cfg_ctrl;
 141
 142         u16 intermediate_freq;
 143         u16 osc_clock_freq;
 144
 145         enum CSCDState cscd_state;
 146         enum CDrxdState drxd_state;
 147
 148         u16 sys_clock_freq;
 149         s16 osc_clock_deviation;
 150         u16 expected_sys_clock_freq;
 151
 152         u16 insert_rs_byte;
 153         u16 enable_parallel;
 154
 155         int operation_mode;
 156
 157         struct SCfgAgc if_agc_cfg;
 158         struct SCfgAgc rf_agc_cfg;
 159
 160         struct SNoiseCal noise_cal;
 161
 162         u32 fe_fs_add_incr;
 163         u32 org_fe_fs_add_incr;
 164         u16 current_fe_if_incr;
 165
 166         u16 m_FeAgRegAgPwd;
 167         u16 m_FeAgRegAgAgcSio;
 168
 169         u16 m_EcOcRegOcModeLop;
 170         u16 m_EcOcRegSncSncLvl;
 171         u8 *m_InitAtomicRead;
 172         u8 *m_HiI2cPatch;
 173
 174         u8 *m_ResetCEFR;
 175         u8 *m_InitFE_1;
 176         u8 *m_InitFE_2;
 177         u8 *m_InitCP;
 178         u8 *m_InitCE;
 179         u8 *m_InitEQ;
 180         u8 *m_InitSC;
 181         u8 *m_InitEC;
 182         u8 *m_ResetECRAM;
 183         u8 *m_InitDiversityFront;
 184         u8 *m_InitDiversityEnd;
 185         u8 *m_DisableDiversity;
 186         u8 *m_StartDiversityFront;
 187         u8 *m_StartDiversityEnd;
 188
 189         u8 *m_DiversityDelay8MHZ;
 190         u8 *m_DiversityDelay6MHZ;
 191
 192         u8 *microcode;
 193         u32 microcode_length;
 194
 195         int type_A;
 196         int PGA;
 197         int diversity;
 198         int tuner_mirrors;
 199
 200         enum app_env app_env_default;
 201         enum app_env app_env_diversity;
 202
 203 };
 204
 205 /****************************************************************************/
 206 /* I2C **********************************************************************/
 207 /****************************************************************************/
 208
 209 static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
 210 {
 211         struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
 212
 213         if (i2c_transfer(adap, &msg, 1) != 1)
 214                 return -1;
 215         return 0;
 216 }
 217
 218 static int i2c_read(struct i2c_adapter *adap,
 219                     u8 adr, u8 *msg, int len, u8 *answ, int alen)
 220 {
 221         struct i2c_msg msgs[2] = {
 222                 {
 223                         .addr = adr, .flags = 0,
 224                         .buf = msg, .len = len
 225                 }, {
 226                         .addr = adr, .flags = I2C_M_RD,
 227                         .buf = answ, .len = alen
 228                 }
 229         };
 230         if (i2c_transfer(adap, msgs, 2) != 2)
 231                 return -1;
 232         return 0;
 233 }
 234
 235 static inline u32 MulDiv32(u32 a, u32 b, u32 c)
 236 {
 237         u64 tmp64;
 238
 239         tmp64 = (u64)a * (u64)b;
 240         do_div(tmp64, c);
 241
 242         return (u32) tmp64;
 243 }
 244
 245 static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
 246 {
 247         u8 adr = state->config.demod_address;
 248         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 249                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 250         };
 251         u8 mm2[2];
 252         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
 253                 return -1;
 254         if (data)
 255                 *data = mm2[0] | (mm2[1] << 8);
 256         return mm2[0] | (mm2[1] << 8);
 257 }
 258
 259 static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
 260 {
 261         u8 adr = state->config.demod_address;
 262         u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
 263                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 264         };
 265         u8 mm2[4];
 266
 267         if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
 268                 return -1;
 269         if (data)
 270                 *data =
 271                     mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
 272         return 0;
 273 }
 274
 275 static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
 276 {
 277         u8 adr = state->config.demod_address;
 278         u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
 279                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 280                 data & 0xff, (data >> 8) & 0xff
 281         };
 282
 283         if (i2c_write(state->i2c, adr, mm, 6) < 0)
 284                 return -1;
 285         return 0;
 286 }
 287
 288 static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
 289 {
 290         u8 adr = state->config.demod_address;
 291         u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
 292                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
 293                 data & 0xff, (data >> 8) & 0xff,
 294                 (data >> 16) & 0xff, (data >> 24) & 0xff
 295         };
 296
 297         if (i2c_write(state->i2c, adr, mm, 8) < 0)
 298                 return -1;
 299         return 0;
 300 }
 301
 302 static int write_chunk(struct drxd_state *state,
 303                        u32 reg, u8 *data, u32 len, u8 flags)
 304 {
 305         u8 adr = state->config.demod_address;
 306         u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
 307                 flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
 308         };
 309         int i;
 310
 311         for (i = 0; i < len; i++)
 312                 mm[4 + i] = data[i];
 313         if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
 314                 printk(KERN_ERR "error in write_chunk\n");
 315                 return -1;
 316         }
 317         return 0;
 318 }
 319
 320 static int WriteBlock(struct drxd_state *state,
 321                       u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
 322 {
 323         while (BlockSize > 0) {
 324                 u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
 325
 326                 if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
 327                         return -1;
 328                 pBlock += Chunk;
 329                 Address += (Chunk >> 1);
 330                 BlockSize -= Chunk;
 331         }
 332         return 0;
 333 }
 334
 335 static int WriteTable(struct drxd_state *state, u8 * pTable)
 336 {
 337         int status = 0;
 338
 339         if (pTable == NULL)
 340                 return 0;
 341
 342         while (!status) {
 343                 u16 Length;
 344                 u32 Address = pTable[0] | (pTable[1] << 8) |
 345                     (pTable[2] << 16) | (pTable[3] << 24);
 346
 347                 if (Address == 0xFFFFFFFF)
 348                         break;
 349                 pTable += sizeof(u32);
 350
 351                 Length = pTable[0] | (pTable[1] << 8);
 352                 pTable += sizeof(u16);
 353                 if (!Length)
 354                         break;
 355                 status = WriteBlock(state, Address, Length * 2, pTable, 0);
 356                 pTable += (Length * 2);
 357         }
 358         return status;
 359 }
 360
 361 /****************************************************************************/
 362 /****************************************************************************/
 363 /****************************************************************************/
 364
 365 static int ResetCEFR(struct drxd_state *state)
 366 {
 367         return WriteTable(state, state->m_ResetCEFR);
 368 }
 369
 370 static int InitCP(struct drxd_state *state)
 371 {
 372         return WriteTable(state, state->m_InitCP);
 373 }
 374
 375 static int InitCE(struct drxd_state *state)
 376 {
 377         int status;
 378         enum app_env AppEnv = state->app_env_default;
 379
 380         do {
 381                 status = WriteTable(state, state->m_InitCE);
 382                 if (status < 0)
 383                         break;
 384
 385                 if (state->operation_mode == OM_DVBT_Diversity_Front ||
 386                     state->operation_mode == OM_DVBT_Diversity_End) {
 387                         AppEnv = state->app_env_diversity;
 388                 }
 389                 if (AppEnv == APPENV_STATIC) {
 390                         status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
 391                         if (status < 0)
 392                                 break;
 393                 } else if (AppEnv == APPENV_PORTABLE) {
 394                         status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
 395                         if (status < 0)
 396                                 break;
 397                 } else if (AppEnv == APPENV_MOBILE && state->type_A) {
 398                         status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
 399                         if (status < 0)
 400                                 break;
 401                 } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
 402                         status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
 403                         if (status < 0)
 404                                 break;
 405                 }
 406
 407                 /* start ce */
 408                 status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
 409                 if (status < 0)
 410                         break;
 411         } while (0);
 412         return status;
 413 }
 414
 415 static int StopOC(struct drxd_state *state)
 416 {
 417         int status = 0;
 418         u16 ocSyncLvl = 0;
 419         u16 ocModeLop = state->m_EcOcRegOcModeLop;
 420         u16 dtoIncLop = 0;
 421         u16 dtoIncHip = 0;
 422
 423         do {
 424                 /* Store output configuration */
 425                 status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
 426                 if (status < 0)
 427                         break;
 428                 /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
 429                 state->m_EcOcRegSncSncLvl = ocSyncLvl;
 430                 /* m_EcOcRegOcModeLop = ocModeLop; */
 431
 432                 /* Flush FIFO (byte-boundary) at fixed rate */
 433                 status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
 434                 if (status < 0)
 435                         break;
 436                 status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
 437                 if (status < 0)
 438                         break;
 439                 status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
 440                 if (status < 0)
 441                         break;
 442                 status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
 443                 if (status < 0)
 444                         break;
 445                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
 446                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
 447                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 448                 if (status < 0)
 449                         break;
 450                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 451                 if (status < 0)
 452                         break;
 453
 454                 msleep(1);
 455                 /* Output pins to '0' */
 456                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
 457                 if (status < 0)
 458                         break;
 459
 460                 /* Force the OC out of sync */
 461                 ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
 462                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
 463                 if (status < 0)
 464                         break;
 465                 ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
 466                 ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
 467                 ocModeLop |= 0x2;       /* Magically-out-of-sync */
 468                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
 469                 if (status < 0)
 470                         break;
 471                 status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
 472                 if (status < 0)
 473                         break;
 474                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 475                 if (status < 0)
 476                         break;
 477         } while (0);
 478
 479         return status;
 480 }
 481
 482 static int StartOC(struct drxd_state *state)
 483 {
 484         int status = 0;
 485
 486         do {
 487                 /* Stop OC */
 488                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
 489                 if (status < 0)
 490                         break;
 491
 492                 /* Restore output configuration */
 493                 status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
 494                 if (status < 0)
 495                         break;
 496                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
 497                 if (status < 0)
 498                         break;
 499
 500                 /* Output pins active again */
 501                 status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
 502                 if (status < 0)
 503                         break;
 504
 505                 /* Start OC */
 506                 status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
 507                 if (status < 0)
 508                         break;
 509         } while (0);
 510         return status;
 511 }
 512
 513 static int InitEQ(struct drxd_state *state)
 514 {
 515         return WriteTable(state, state->m_InitEQ);
 516 }
 517
 518 static int InitEC(struct drxd_state *state)
 519 {
 520         return WriteTable(state, state->m_InitEC);
 521 }
 522
 523 static int InitSC(struct drxd_state *state)
 524 {
 525         return WriteTable(state, state->m_InitSC);
 526 }
 527
 528 static int InitAtomicRead(struct drxd_state *state)
 529 {
 530         return WriteTable(state, state->m_InitAtomicRead);
 531 }
 532
 533 static int CorrectSysClockDeviation(struct drxd_state *state);
 534
 535 static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
 536 {
 537         u16 ScRaRamLock = 0;
 538         const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
 539                                     SC_RA_RAM_LOCK_FEC__M |
 540                                     SC_RA_RAM_LOCK_DEMOD__M);
 541         const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
 542                                    SC_RA_RAM_LOCK_DEMOD__M);
 543         const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
 544
 545         int status;
 546
 547         *pLockStatus = 0;
 548
 549         status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
 550         if (status < 0) {
 551                 printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
 552                 return status;
 553         }
 554
 555         if (state->drxd_state != DRXD_STARTED)
 556                 return 0;
 557
 558         if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
 559                 *pLockStatus |= DRX_LOCK_MPEG;
 560                 CorrectSysClockDeviation(state);
 561         }
 562
 563         if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
 564                 *pLockStatus |= DRX_LOCK_FEC;
 565
 566         if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
 567                 *pLockStatus |= DRX_LOCK_DEMOD;
 568         return 0;
 569 }
 570
 571 /****************************************************************************/
 572
 573 static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 574 {
 575         int status;
 576
 577         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 578                 return -1;
 579
 580         if (cfg->ctrlMode == AGC_CTRL_USER) {
 581                 do {
 582                         u16 FeAgRegPm1AgcWri;
 583                         u16 FeAgRegAgModeLop;
 584
 585                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 586                         if (status < 0)
 587                                 break;
 588                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 589                         FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
 590                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 591                         if (status < 0)
 592                                 break;
 593
 594                         FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
 595                                                   FE_AG_REG_PM1_AGC_WRI__M);
 596                         status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
 597                         if (status < 0)
 598                                 break;
 599                 } while (0);
 600         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 601                 if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
 602                     ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
 603                     ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
 604                     ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
 605                     )
 606                         return -1;
 607                 do {
 608                         u16 FeAgRegAgModeLop;
 609                         u16 FeAgRegEgcSetLvl;
 610                         u16 slope, offset;
 611
 612                         /* == Mode == */
 613
 614                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
 615                         if (status < 0)
 616                                 break;
 617                         FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
 618                         FeAgRegAgModeLop |=
 619                             FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
 620                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
 621                         if (status < 0)
 622                                 break;
 623
 624                         /* == Settle level == */
 625
 626                         FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
 627                                                   FE_AG_REG_EGC_SET_LVL__M);
 628                         status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
 629                         if (status < 0)
 630                                 break;
 631
 632                         /* == Min/Max == */
 633
 634                         slope = (u16) ((cfg->maxOutputLevel -
 635                                         cfg->minOutputLevel) / 2);
 636                         offset = (u16) ((cfg->maxOutputLevel +
 637                                          cfg->minOutputLevel) / 2 - 511);
 638
 639                         status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
 640                         if (status < 0)
 641                                 break;
 642                         status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
 643                         if (status < 0)
 644                                 break;
 645
 646                         /* == Speed == */
 647                         {
 648                                 const u16 maxRur = 8;
 649                                 const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
 650                                 const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
 651                                         17, 18, 18, 19,
 652                                         20, 21, 22, 23,
 653                                         24, 26, 27, 28,
 654                                         29, 31
 655                                 };
 656
 657                                 u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
 658                                     (maxRur + 1);
 659                                 u16 fineSpeed = (u16) (cfg->speed -
 660                                                        ((cfg->speed /
 661                                                          fineSteps) *
 662                                                         fineSteps));
 663                                 u16 invRurCount = (u16) (cfg->speed /
 664                                                          fineSteps);
 665                                 u16 rurCount;
 666                                 if (invRurCount > maxRur) {
 667                                         rurCount = 0;
 668                                         fineSpeed += fineSteps;
 669                                 } else {
 670                                         rurCount = maxRur - invRurCount;
 671                                 }
 672
 673                                 /*
 674                                    fastInc = default *
 675                                    (2^(fineSpeed/fineSteps))
 676                                    => range[default...2*default>
 677                                    slowInc = default *
 678                                    (2^(fineSpeed/fineSteps))
 679                                  */
 680                                 {
 681                                         u16 fastIncrDec =
 682                                             fastIncrDecLUT[fineSpeed /
 683                                                            ((fineSteps /
 684                                                              (14 + 1)) + 1)];
 685                                         u16 slowIncrDec =
 686                                             slowIncrDecLUT[fineSpeed /
 687                                                            (fineSteps /
 688                                                             (3 + 1))];
 689
 690                                         status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
 691                                         if (status < 0)
 692                                                 break;
 693                                         status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
 694                                         if (status < 0)
 695                                                 break;
 696                                         status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
 697                                         if (status < 0)
 698                                                 break;
 699                                         status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
 700                                         if (status < 0)
 701                                                 break;
 702                                         status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
 703                                         if (status < 0)
 704                                                 break;
 705                                 }
 706                         }
 707                 } while (0);
 708
 709         } else {
 710                 /* No OFF mode for IF control */
 711                 return -1;
 712         }
 713         return status;
 714 }
 715
 716 static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
 717 {
 718         int status = 0;
 719
 720         if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
 721                 return -1;
 722
 723         if (cfg->ctrlMode == AGC_CTRL_USER) {
 724                 do {
 725                         u16 AgModeLop = 0;
 726                         u16 level = (cfg->outputLevel);
 727
 728                         if (level == DRXD_FE_CTRL_MAX)
 729                                 level++;
 730
 731                         status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
 732                         if (status < 0)
 733                                 break;
 734
 735                         /*==== Mode ====*/
 736
 737                         /* Powerdown PD2, WRI source */
 738                         state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 739                         state->m_FeAgRegAgPwd |=
 740                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 741                         status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
 742                         if (status < 0)
 743                                 break;
 744
 745                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 746                         if (status < 0)
 747                                 break;
 748                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 749                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 750                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 751                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 752                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 753                         if (status < 0)
 754                                 break;
 755
 756                         /* enable AGC2 pin */
 757                         {
 758                                 u16 FeAgRegAgAgcSio = 0;
 759                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 760                                 if (status < 0)
 761                                         break;
 762                                 FeAgRegAgAgcSio &=
 763                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 764                                 FeAgRegAgAgcSio |=
 765                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 766                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 767                                 if (status < 0)
 768                                         break;
 769                         }
 770
 771                 } while (0);
 772         } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
 773                 u16 AgModeLop = 0;
 774
 775                 do {
 776                         u16 level;
 777                         /* Automatic control */
 778                         /* Powerup PD2, AGC2 as output, TGC source */
 779                         (state->m_FeAgRegAgPwd) &=
 780                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 781                         (state->m_FeAgRegAgPwd) |=
 782                             FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
 783                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 784                         if (status < 0)
 785                                 break;
 786
 787                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 788                         if (status < 0)
 789                                 break;
 790                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 791                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 792                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 793                                       FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
 794                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 795                         if (status < 0)
 796                                 break;
 797                         /* Settle level */
 798                         level = (((cfg->settleLevel) >> 4) &
 799                                  FE_AG_REG_TGC_SET_LVL__M);
 800                         status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
 801                         if (status < 0)
 802                                 break;
 803
 804                         /* Min/max: don't care */
 805
 806                         /* Speed: TODO */
 807
 808                         /* enable AGC2 pin */
 809                         {
 810                                 u16 FeAgRegAgAgcSio = 0;
 811                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 812                                 if (status < 0)
 813                                         break;
 814                                 FeAgRegAgAgcSio &=
 815                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 816                                 FeAgRegAgAgcSio |=
 817                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
 818                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 819                                 if (status < 0)
 820                                         break;
 821                         }
 822
 823                 } while (0);
 824         } else {
 825                 u16 AgModeLop = 0;
 826
 827                 do {
 828                         /* No RF AGC control */
 829                         /* Powerdown PD2, AGC2 as output, WRI source */
 830                         (state->m_FeAgRegAgPwd) &=
 831                             ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
 832                         (state->m_FeAgRegAgPwd) |=
 833                             FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
 834                         status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
 835                         if (status < 0)
 836                                 break;
 837
 838                         status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
 839                         if (status < 0)
 840                                 break;
 841                         AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
 842                                         FE_AG_REG_AG_MODE_LOP_MODE_E__M));
 843                         AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
 844                                       FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
 845                         status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
 846                         if (status < 0)
 847                                 break;
 848
 849                         /* set FeAgRegAgAgcSio AGC2 (RF) as input */
 850                         {
 851                                 u16 FeAgRegAgAgcSio = 0;
 852                                 status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
 853                                 if (status < 0)
 854                                         break;
 855                                 FeAgRegAgAgcSio &=
 856                                     ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
 857                                 FeAgRegAgAgcSio |=
 858                                     FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
 859                                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
 860                                 if (status < 0)
 861                                         break;
 862                         }
 863                 } while (0);
 864         }
 865         return status;
 866 }
 867
 868 static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
 869 {
 870         int status = 0;
 871
 872         *pValue = 0;
 873         if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
 874                 u16 Value;
 875                 status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
 876                 Value &= FE_AG_REG_GC1_AGC_DAT__M;
 877                 if (status >= 0) {
 878                         /*           3.3V
 879                            |
 880                            R1
 881                            |
 882                            Vin - R3 - * -- Vout
 883                            |
 884                            R2
 885                            |
 886                            GND
 887                          */
 888                         u32 R1 = state->if_agc_cfg.R1;
 889                         u32 R2 = state->if_agc_cfg.R2;
 890                         u32 R3 = state->if_agc_cfg.R3;
 891
 892                         u32 Vmax, Rpar, Vmin, Vout;
 893
 894                         if (R2 == 0 && (R1 == 0 || R3 == 0))
 895                                 return 0;
 896
 897                         Vmax = (3300 * R2) / (R1 + R2);
 898                         Rpar = (R2 * R3) / (R3 + R2);
 899                         Vmin = (3300 * Rpar) / (R1 + Rpar);
 900                         Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
 901
 902                         *pValue = Vout;
 903                 }
 904         }
 905         return status;
 906 }
 907
 908 static int load_firmware(struct drxd_state *state, const char *fw_name)
 909 {
 910         const struct firmware *fw;
 911
 912         if (request_firmware(&fw, fw_name, state->dev) < 0) {
 913                 printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
 914                 return -EIO;
 915         }
 916
 917         state->microcode = kmalloc(fw->size, GFP_KERNEL);
 918         if (state->microcode == NULL) {
 919                 release_firmware(fw);
 920                 printk(KERN_ERR "drxd: firmware load failure: no memory\n");
 921                 return -ENOMEM;
 922         }
 923
 924         memcpy(state->microcode, fw->data, fw->size);
 925         state->microcode_length = fw->size;
 926         release_firmware(fw);
 927         return 0;
 928 }
 929
 930 static int DownloadMicrocode(struct drxd_state *state,
 931                              const u8 *pMCImage, u32 Length)
 932 {
 933         u8 *pSrc;
 934         u32 Address;
 935         u16 nBlocks;
 936         u16 BlockSize;
 937         u32 offset = 0;
 938         int i, status = 0;
 939
 940         pSrc = (u8 *) pMCImage;
 941         /* We're not using Flags */
 942         /* Flags = (pSrc[0] << 8) | pSrc[1]; */
 943         pSrc += sizeof(u16);
 944         offset += sizeof(u16);
 945         nBlocks = (pSrc[0] << 8) | pSrc[1];
 946         pSrc += sizeof(u16);
 947         offset += sizeof(u16);
 948
 949         for (i = 0; i < nBlocks; i++) {
 950                 Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
 951                     (pSrc[2] << 8) | pSrc[3];
 952                 pSrc += sizeof(u32);
 953                 offset += sizeof(u32);
 954
 955                 BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
 956                 pSrc += sizeof(u16);
 957                 offset += sizeof(u16);
 958
 959                 /* We're not using Flags */
 960                 /* u16 Flags = (pSrc[0] << 8) | pSrc[1]; */
 961                 pSrc += sizeof(u16);
 962                 offset += sizeof(u16);
 963
 964                 /* We're not using BlockCRC */
 965                 /* u16 BlockCRC = (pSrc[0] << 8) | pSrc[1]; */
 966                 pSrc += sizeof(u16);
 967                 offset += sizeof(u16);
 968
 969                 status = WriteBlock(state, Address, BlockSize,
 970                                     pSrc, DRX_I2C_CLEARCRC);
 971                 if (status < 0)
 972                         break;
 973                 pSrc += BlockSize;
 974                 offset += BlockSize;
 975         }
 976
 977         return status;
 978 }
 979
 980 static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
 981 {
 982         u32 nrRetries = 0;
 983         u16 waitCmd;
 984         int status;
 985
 986         status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
 987         if (status < 0)
 988                 return status;
 989
 990         do {
 991                 nrRetries += 1;
 992                 if (nrRetries > DRXD_MAX_RETRIES) {
 993                         status = -1;
 994                         break;
 995                 };
 996                 status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
 997         } while (waitCmd != 0);
 998
 999         if (status >= 0)
1000                 status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
1001         return status;
1002 }
1003
1004 static int HI_CfgCommand(struct drxd_state *state)
1005 {
1006         int status = 0;
1007
1008         mutex_lock(&state->mutex);
1009         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1010         Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
1011         Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
1012         Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
1013         Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
1014
1015         Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1016
1017         if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
1018             HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
1019                 status = Write16(state, HI_RA_RAM_SRV_CMD__A,
1020                                  HI_RA_RAM_SRV_CMD_CONFIG, 0);
1021         else
1022                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
1023         mutex_unlock(&state->mutex);
1024         return status;
1025 }
1026
1027 static int InitHI(struct drxd_state *state)
1028 {
1029         state->hi_cfg_wakeup_key = (state->chip_adr);
1030         /* port/bridge/power down ctrl */
1031         state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
1032         return HI_CfgCommand(state);
1033 }
1034
1035 static int HI_ResetCommand(struct drxd_state *state)
1036 {
1037         int status;
1038
1039         mutex_lock(&state->mutex);
1040         status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
1041                          HI_RA_RAM_SRV_RST_KEY_ACT, 0);
1042         if (status == 0)
1043                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
1044         mutex_unlock(&state->mutex);
1045         msleep(1);
1046         return status;
1047 }
1048
1049 static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
1050 {
1051         state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
1052         if (bEnableBridge)
1053                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
1054         else
1055                 state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
1056
1057         return HI_CfgCommand(state);
1058 }
1059
1060 #define HI_TR_WRITE      0x9
1061 #define HI_TR_READ       0xA
1062 #define HI_TR_READ_WRITE 0xB
1063 #define HI_TR_BROADCAST  0x4
1064
1065 #if 0
1066 static int AtomicReadBlock(struct drxd_state *state,
1067                            u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
1068 {
1069         int status;
1070         int i = 0;
1071
1072         /* Parameter check */
1073         if ((!pData) || ((DataSize & 1) != 0))
1074                 return -1;
1075
1076         mutex_lock(&state->mutex);
1077
1078         do {
1079                 /* Instruct HI to read n bytes */
1080                 /* TODO use proper names forthese egisters */
1081                 status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
1082                 if (status < 0)
1083                         break;
1084                 status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
1085                 if (status < 0)
1086                         break;
1087                 status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
1088                 if (status < 0)
1089                         break;
1090                 status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
1091                 if (status < 0)
1092                         break;
1093                 status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
1094                 if (status < 0)
1095                         break;
1096
1097                 status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
1098                 if (status < 0)
1099                         break;
1100
1101         } while (0);
1102
1103         if (status >= 0) {
1104                 for (i = 0; i < (DataSize / 2); i += 1) {
1105                         u16 word;
1106
1107                         status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
1108                                         &word, 0);
1109                         if (status < 0)
1110                                 break;
1111                         pData[2 * i] = (u8) (word & 0xFF);
1112                         pData[(2 * i) + 1] = (u8) (word >> 8);
1113                 }
1114         }
1115         mutex_unlock(&state->mutex);
1116         return status;
1117 }
1118
1119 static int AtomicReadReg32(struct drxd_state *state,
1120                            u32 Addr, u32 *pData, u8 Flags)
1121 {
1122         u8 buf[sizeof(u32)];
1123         int status;
1124
1125         if (!pData)
1126                 return -1;
1127         status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
1128         *pData = (((u32) buf[0]) << 0) +
1129             (((u32) buf[1]) << 8) +
1130             (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
1131         return status;
1132 }
1133 #endif
1134
1135 static int StopAllProcessors(struct drxd_state *state)
1136 {
1137         return Write16(state, HI_COMM_EXEC__A,
1138                        SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
1139 }
1140
1141 static int EnableAndResetMB(struct drxd_state *state)
1142 {
1143         if (state->type_A) {
1144                 /* disable? monitor bus observe @ EC_OC */
1145                 Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
1146         }
1147
1148         /* do inverse broadcast, followed by explicit write to HI */
1149         Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
1150         Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
1151         return 0;
1152 }
1153
1154 static int InitCC(struct drxd_state *state)
1155 {
1156         if (state->osc_clock_freq == 0 ||
1157             state->osc_clock_freq > 20000 ||
1158             (state->osc_clock_freq % 4000) != 0) {
1159                 printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
1160                 return -1;
1161         }
1162
1163         Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
1164         Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
1165                 CC_REG_PLL_MODE_PUMP_CUR_12, 0);
1166         Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
1167         Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
1168         Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
1169
1170         return 0;
1171 }
1172
1173 static int ResetECOD(struct drxd_state *state)
1174 {
1175         int status = 0;
1176
1177         if (state->type_A)
1178                 status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
1179         else
1180                 status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
1181
1182         if (!(status < 0))
1183                 status = WriteTable(state, state->m_ResetECRAM);
1184         if (!(status < 0))
1185                 status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
1186         return status;
1187 }
1188
1189 /* Configure PGA switch */
1190
1191 static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
1192 {
1193         int status;
1194         u16 AgModeLop = 0;
1195         u16 AgModeHip = 0;
1196         do {
1197                 if (pgaSwitch) {
1198                         /* PGA on */
1199                         /* fine gain */
1200                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1201                         if (status < 0)
1202                                 break;
1203                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1204                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
1205                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1206                         if (status < 0)
1207                                 break;
1208
1209                         /* coarse gain */
1210                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1211                         if (status < 0)
1212                                 break;
1213                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1214                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
1215                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1216                         if (status < 0)
1217                                 break;
1218
1219                         /* enable fine and coarse gain, enable AAF,
1220                            no ext resistor */
1221                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
1222                         if (status < 0)
1223                                 break;
1224                 } else {
1225                         /* PGA off, bypass */
1226
1227                         /* fine gain */
1228                         status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
1229                         if (status < 0)
1230                                 break;
1231                         AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
1232                         AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
1233                         status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
1234                         if (status < 0)
1235                                 break;
1236
1237                         /* coarse gain */
1238                         status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
1239                         if (status < 0)
1240                                 break;
1241                         AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
1242                         AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
1243                         status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
1244                         if (status < 0)
1245                                 break;
1246
1247                         /* disable fine and coarse gain, enable AAF,
1248                            no ext resistor */
1249                         status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
1250                         if (status < 0)
1251                                 break;
1252                 }
1253         } while (0);
1254         return status;
1255 }
1256
1257 static int InitFE(struct drxd_state *state)
1258 {
1259         int status;
1260
1261         do {
1262                 status = WriteTable(state, state->m_InitFE_1);
1263                 if (status < 0)
1264                         break;
1265
1266                 if (state->type_A) {
1267                         status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
1268                                          FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1269                                          0);
1270                 } else {
1271                         if (state->PGA)
1272                                 status = SetCfgPga(state, 0);
1273                         else
1274                                 status =
1275                                     Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
1276                                             B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
1277                                             0);
1278                 }
1279
1280                 if (status < 0)
1281                         break;
1282                 status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
1283                 if (status < 0)
1284                         break;
1285                 status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
1286                 if (status < 0)
1287                         break;
1288
1289                 status = WriteTable(state, state->m_InitFE_2);
1290                 if (status < 0)
1291                         break;
1292
1293         } while (0);
1294
1295         return status;
1296 }
1297
1298 static int InitFT(struct drxd_state *state)
1299 {
1300         /*
1301            norm OFFSET,  MB says =2 voor 8K en =3 voor 2K waarschijnlijk
1302            SC stuff
1303          */
1304         return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
1305 }
1306
1307 static int SC_WaitForReady(struct drxd_state *state)
1308 {
1309         u16 curCmd;
1310         int i;
1311
1312         for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
1313                 int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
1314                 if (status == 0 || curCmd == 0)
1315                         return status;
1316         }
1317         return -1;
1318 }
1319
1320 static int SC_SendCommand(struct drxd_state *state, u16 cmd)
1321 {
1322         int status = 0;
1323         u16 errCode;
1324
1325         Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
1326         SC_WaitForReady(state);
1327
1328         Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
1329
1330         if (errCode == 0xFFFF) {
1331                 printk(KERN_ERR "Command Error\n");
1332                 status = -1;
1333         }
1334
1335         return status;
1336 }
1337
1338 static int SC_ProcStartCommand(struct drxd_state *state,
1339                                u16 subCmd, u16 param0, u16 param1)
1340 {
1341         int status = 0;
1342         u16 scExec;
1343
1344         mutex_lock(&state->mutex);
1345         do {
1346                 Read16(state, SC_COMM_EXEC__A, &scExec, 0);
1347                 if (scExec != 1) {
1348                         status = -1;
1349                         break;
1350                 }
1351                 SC_WaitForReady(state);
1352                 Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1353                 Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1354                 Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1355
1356                 SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
1357         } while (0);
1358         mutex_unlock(&state->mutex);
1359         return status;
1360 }
1361
1362 static int SC_SetPrefParamCommand(struct drxd_state *state,
1363                                   u16 subCmd, u16 param0, u16 param1)
1364 {
1365         int status;
1366
1367         mutex_lock(&state->mutex);
1368         do {
1369                 status = SC_WaitForReady(state);
1370                 if (status < 0)
1371                         break;
1372                 status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
1373                 if (status < 0)
1374                         break;
1375                 status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
1376                 if (status < 0)
1377                         break;
1378                 status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
1379                 if (status < 0)
1380                         break;
1381
1382                 status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
1383                 if (status < 0)
1384                         break;
1385         } while (0);
1386         mutex_unlock(&state->mutex);
1387         return status;
1388 }
1389
1390 #if 0
1391 static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
1392 {
1393         int status = 0;
1394
1395         mutex_lock(&state->mutex);
1396         do {
1397                 status = SC_WaitForReady(state);
1398                 if (status < 0)
1399                         break;
1400                 status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
1401                 if (status < 0)
1402                         break;
1403                 status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
1404                 if (status < 0)
1405                         break;
1406         } while (0);
1407         mutex_unlock(&state->mutex);
1408         return status;
1409 }
1410 #endif
1411
1412 static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
1413 {
1414         int status;
1415
1416         do {
1417                 u16 EcOcRegIprInvMpg = 0;
1418                 u16 EcOcRegOcModeLop = 0;
1419                 u16 EcOcRegOcModeHip = 0;
1420                 u16 EcOcRegOcMpgSio = 0;
1421
1422                 /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
1423
1424                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1425                         if (bEnableOutput) {
1426                                 EcOcRegOcModeHip |=
1427                                     B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
1428                         } else
1429                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1430                         EcOcRegOcModeLop |=
1431                             EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1432                 } else {
1433                         EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
1434
1435                         if (bEnableOutput)
1436                                 EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
1437                         else
1438                                 EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
1439
1440                         /* Don't Insert RS Byte */
1441                         if (state->insert_rs_byte) {
1442                                 EcOcRegOcModeLop &=
1443                                     (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
1444                                 EcOcRegOcModeHip &=
1445                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1446                                 EcOcRegOcModeHip |=
1447                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
1448                         } else {
1449                                 EcOcRegOcModeLop |=
1450                                     EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
1451                                 EcOcRegOcModeHip &=
1452                                     (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
1453                                 EcOcRegOcModeHip |=
1454                                     EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
1455                         }
1456
1457                         /* Mode = Parallel */
1458                         if (state->enable_parallel)
1459                                 EcOcRegOcModeLop &=
1460                                     (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
1461                         else
1462                                 EcOcRegOcModeLop |=
1463                                     EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
1464                 }
1465                 /* Invert Data */
1466                 /* EcOcRegIprInvMpg |= 0x00FF; */
1467                 EcOcRegIprInvMpg &= (~(0x00FF));
1468
1469                 /* Invert Error ( we don't use the pin ) */
1470                 /*  EcOcRegIprInvMpg |= 0x0100; */
1471                 EcOcRegIprInvMpg &= (~(0x0100));
1472
1473                 /* Invert Start ( we don't use the pin ) */
1474                 /* EcOcRegIprInvMpg |= 0x0200; */
1475                 EcOcRegIprInvMpg &= (~(0x0200));
1476
1477                 /* Invert Valid ( we don't use the pin ) */
1478                 /* EcOcRegIprInvMpg |= 0x0400; */
1479                 EcOcRegIprInvMpg &= (~(0x0400));
1480
1481                 /* Invert Clock */
1482                 /* EcOcRegIprInvMpg |= 0x0800; */
1483                 EcOcRegIprInvMpg &= (~(0x0800));
1484
1485                 /* EcOcRegOcModeLop =0x05; */
1486                 status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
1487                 if (status < 0)
1488                         break;
1489                 status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
1490                 if (status < 0)
1491                         break;
1492                 status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
1493                 if (status < 0)
1494                         break;
1495                 status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
1496                 if (status < 0)
1497                         break;
1498         } while (0);
1499         return status;
1500 }
1501
1502 static int SetDeviceTypeId(struct drxd_state *state)
1503 {
1504         int status = 0;
1505         u16 deviceId = 0;
1506
1507         do {
1508                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1509                 if (status < 0)
1510                         break;
1511                 /* TODO: why twice? */
1512                 status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
1513                 if (status < 0)
1514                         break;
1515                 printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
1516
1517                 state->type_A = 0;
1518                 state->PGA = 0;
1519                 state->diversity = 0;
1520                 if (deviceId == 0) {    /* on A2 only 3975 available */
1521                         state->type_A = 1;
1522                         printk(KERN_INFO "DRX3975D-A2\n");
1523                 } else {
1524                         deviceId >>= 12;
1525                         printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
1526                         switch (deviceId) {
1527                         case 4:
1528                                 state->diversity = 1;
1529                         case 3:
1530                         case 7:
1531                                 state->PGA = 1;
1532                                 break;
1533                         case 6:
1534                                 state->diversity = 1;
1535                         case 5:
1536                         case 8:
1537                                 break;
1538                         default:
1539                                 status = -1;
1540                                 break;
1541                         }
1542                 }
1543         } while (0);
1544
1545         if (status < 0)
1546                 return status;
1547
1548         /* Init Table selection */
1549         state->m_InitAtomicRead = DRXD_InitAtomicRead;
1550         state->m_InitSC = DRXD_InitSC;
1551         state->m_ResetECRAM = DRXD_ResetECRAM;
1552         if (state->type_A) {
1553                 state->m_ResetCEFR = DRXD_ResetCEFR;
1554                 state->m_InitFE_1 = DRXD_InitFEA2_1;
1555                 state->m_InitFE_2 = DRXD_InitFEA2_2;
1556                 state->m_InitCP = DRXD_InitCPA2;
1557                 state->m_InitCE = DRXD_InitCEA2;
1558                 state->m_InitEQ = DRXD_InitEQA2;
1559                 state->m_InitEC = DRXD_InitECA2;
1560                 if (load_firmware(state, DRX_FW_FILENAME_A2))
1561                         return -EIO;
1562         } else {
1563                 state->m_ResetCEFR = NULL;
1564                 state->m_InitFE_1 = DRXD_InitFEB1_1;
1565                 state->m_InitFE_2 = DRXD_InitFEB1_2;
1566                 state->m_InitCP = DRXD_InitCPB1;
1567                 state->m_InitCE = DRXD_InitCEB1;
1568                 state->m_InitEQ = DRXD_InitEQB1;
1569                 state->m_InitEC = DRXD_InitECB1;
1570                 if (load_firmware(state, DRX_FW_FILENAME_B1))
1571                         return -EIO;
1572         }
1573         if (state->diversity) {
1574                 state->m_InitDiversityFront = DRXD_InitDiversityFront;
1575                 state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
1576                 state->m_DisableDiversity = DRXD_DisableDiversity;
1577                 state->m_StartDiversityFront = DRXD_StartDiversityFront;
1578                 state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
1579                 state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
1580                 state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
1581         } else {
1582                 state->m_InitDiversityFront = NULL;
1583                 state->m_InitDiversityEnd = NULL;
1584                 state->m_DisableDiversity = NULL;
1585                 state->m_StartDiversityFront = NULL;
1586                 state->m_StartDiversityEnd = NULL;
1587                 state->m_DiversityDelay8MHZ = NULL;
1588                 state->m_DiversityDelay6MHZ = NULL;
1589         }
1590
1591         return status;
1592 }
1593
1594 static int CorrectSysClockDeviation(struct drxd_state *state)
1595 {
1596         int status;
1597         s32 incr = 0;
1598         s32 nomincr = 0;
1599         u32 bandwidth = 0;
1600         u32 sysClockInHz = 0;
1601         u32 sysClockFreq = 0;   /* in kHz */
1602         s16 oscClockDeviation;
1603         s16 Diff;
1604
1605         do {
1606                 /* Retrieve bandwidth and incr, sanity check */
1607
1608                 /* These accesses should be AtomicReadReg32, but that
1609                    causes trouble (at least for diversity */
1610                 status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
1611                 if (status < 0)
1612                         break;
1613                 status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
1614                 if (status < 0)
1615                         break;
1616
1617                 if (state->type_A) {
1618                         if ((nomincr - incr < -500) || (nomincr - incr > 500))
1619                                 break;
1620                 } else {
1621                         if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
1622                                 break;
1623                 }
1624
1625                 switch (state->param.u.ofdm.bandwidth) {
1626                 case BANDWIDTH_8_MHZ:
1627                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
1628                         break;
1629                 case BANDWIDTH_7_MHZ:
1630                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
1631                         break;
1632                 case BANDWIDTH_6_MHZ:
1633                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
1634                         break;
1635                 default:
1636                         return -1;
1637                         break;
1638                 }
1639
1640                 /* Compute new sysclock value
1641                    sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
1642                 incr += (1 << 23);
1643                 sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
1644                 sysClockFreq = (u32) (sysClockInHz / 1000);
1645                 /* rounding */
1646                 if ((sysClockInHz % 1000) > 500)
1647                         sysClockFreq++;
1648
1649                 /* Compute clock deviation in ppm */
1650                 oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
1651                                              (s32)
1652                                              (state->expected_sys_clock_freq)) *
1653                                             1000000L) /
1654                                            (s32)
1655                                            (state->expected_sys_clock_freq));
1656
1657                 Diff = oscClockDeviation - state->osc_clock_deviation;
1658                 /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
1659                 if (Diff >= -200 && Diff <= 200) {
1660                         state->sys_clock_freq = (u16) sysClockFreq;
1661                         if (oscClockDeviation != state->osc_clock_deviation) {
1662                                 if (state->config.osc_deviation) {
1663                                         state->config.osc_deviation(state->priv,
1664                                                                     oscClockDeviation,
1665                                                                     1);
1666                                         state->osc_clock_deviation =
1667                                             oscClockDeviation;
1668                                 }
1669                         }
1670                         /* switch OFF SRMM scan in SC */
1671                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
1672                         if (status < 0)
1673                                 break;
1674                         /* overrule FE_IF internal value for
1675                            proper re-locking */
1676                         status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
1677                         if (status < 0)
1678                                 break;
1679                         state->cscd_state = CSCD_SAVED;
1680                 }
1681         } while (0);
1682
1683         return status;
1684 }
1685
1686 static int DRX_Stop(struct drxd_state *state)
1687 {
1688         int status;
1689
1690         if (state->drxd_state != DRXD_STARTED)
1691                 return 0;
1692
1693         do {
1694                 if (state->cscd_state != CSCD_SAVED) {
1695                         u32 lock;
1696                         status = DRX_GetLockStatus(state, &lock);
1697                         if (status < 0)
1698                                 break;
1699                 }
1700
1701                 status = StopOC(state);
1702                 if (status < 0)
1703                         break;
1704
1705                 state->drxd_state = DRXD_STOPPED;
1706
1707                 status = ConfigureMPEGOutput(state, 0);
1708                 if (status < 0)
1709                         break;
1710
1711                 if (state->type_A) {
1712                         /* Stop relevant processors off the device */
1713                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
1714                         if (status < 0)
1715                                 break;
1716
1717                         status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1718                         if (status < 0)
1719                                 break;
1720                         status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1721                         if (status < 0)
1722                                 break;
1723                 } else {
1724                         /* Stop all processors except HI & CC & FE */
1725                         status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1726                         if (status < 0)
1727                                 break;
1728                         status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1729                         if (status < 0)
1730                                 break;
1731                         status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1732                         if (status < 0)
1733                                 break;
1734                         status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1735                         if (status < 0)
1736                                 break;
1737                         status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1738                         if (status < 0)
1739                                 break;
1740                         status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
1741                         if (status < 0)
1742                                 break;
1743                         status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
1744                         if (status < 0)
1745                                 break;
1746                 }
1747
1748         } while (0);
1749         return status;
1750 }
1751
1752 int SetOperationMode(struct drxd_state *state, int oMode)
1753 {
1754         int status;
1755
1756         do {
1757                 if (state->drxd_state != DRXD_STOPPED) {
1758                         status = -1;
1759                         break;
1760                 }
1761
1762                 if (oMode == state->operation_mode) {
1763                         status = 0;
1764                         break;
1765                 }
1766
1767                 if (oMode != OM_Default && !state->diversity) {
1768                         status = -1;
1769                         break;
1770                 }
1771
1772                 switch (oMode) {
1773                 case OM_DVBT_Diversity_Front:
1774                         status = WriteTable(state, state->m_InitDiversityFront);
1775                         break;
1776                 case OM_DVBT_Diversity_End:
1777                         status = WriteTable(state, state->m_InitDiversityEnd);
1778                         break;
1779                 case OM_Default:
1780                         /* We need to check how to
1781                            get DRXD out of diversity */
1782                 default:
1783                         status = WriteTable(state, state->m_DisableDiversity);
1784                         break;
1785                 }
1786         } while (0);
1787
1788         if (!status)
1789                 state->operation_mode = oMode;
1790         return status;
1791 }
1792
1793 static int StartDiversity(struct drxd_state *state)
1794 {
1795         int status = 0;
1796         u16 rcControl;
1797
1798         do {
1799                 if (state->operation_mode == OM_DVBT_Diversity_Front) {
1800                         status = WriteTable(state, state->m_StartDiversityFront);
1801                         if (status < 0)
1802                                 break;
1803                 } else if (state->operation_mode == OM_DVBT_Diversity_End) {
1804                         status = WriteTable(state, state->m_StartDiversityEnd);
1805                         if (status < 0)
1806                                 break;
1807                         if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
1808                                 status = WriteTable(state, state->m_DiversityDelay8MHZ);
1809                                 if (status < 0)
1810                                         break;
1811                         } else {
1812                                 status = WriteTable(state, state->m_DiversityDelay6MHZ);
1813                                 if (status < 0)
1814                                         break;
1815                         }
1816
1817                         status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
1818                         if (status < 0)
1819                                 break;
1820                         rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
1821                         rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
1822                             /*  combining enabled */
1823                             B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
1824                             B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
1825                             B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
1826                         status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
1827                         if (status < 0)
1828                                 break;
1829                 }
1830         } while (0);
1831         return status;
1832 }
1833
1834 static int SetFrequencyShift(struct drxd_state *state,
1835                              u32 offsetFreq, int channelMirrored)
1836 {
1837         int negativeShift = (state->tuner_mirrors == channelMirrored);
1838
1839         /* Handle all mirroring
1840          *
1841          * Note: ADC mirroring (aliasing) is implictly handled by limiting
1842          * feFsRegAddInc to 28 bits below
1843          * (if the result before masking is more than 28 bits, this means
1844          *  that the ADC is mirroring.
1845          * The masking is in fact the aliasing of the ADC)
1846          *
1847          */
1848
1849         /* Compute register value, unsigned computation */
1850         state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
1851                                          offsetFreq,
1852                                          1 << 28, state->sys_clock_freq);
1853         /* Remove integer part */
1854         state->fe_fs_add_incr &= 0x0FFFFFFFL;
1855         if (negativeShift)
1856                 state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
1857
1858         /* Save the frequency shift without tunerOffset compensation
1859            for CtrlGetChannel. */
1860         state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
1861                                              1 << 28, state->sys_clock_freq);
1862         /* Remove integer part */
1863         state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
1864         if (negativeShift)
1865                 state->org_fe_fs_add_incr = ((1L << 28) -
1866                                              state->org_fe_fs_add_incr);
1867
1868         return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
1869                        state->fe_fs_add_incr, 0);
1870 }
1871
1872 static int SetCfgNoiseCalibration(struct drxd_state *state,
1873                                   struct SNoiseCal *noiseCal)
1874 {
1875         u16 beOptEna;
1876         int status = 0;
1877
1878         do {
1879                 status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
1880                 if (status < 0)
1881                         break;
1882                 if (noiseCal->cpOpt) {
1883                         beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1884                 } else {
1885                         beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
1886                         status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
1887                         if (status < 0)
1888                                 break;
1889                 }
1890                 status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
1891                 if (status < 0)
1892                         break;
1893
1894                 if (!state->type_A) {
1895                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
1896                         if (status < 0)
1897                                 break;
1898                         status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
1899                         if (status < 0)
1900                                 break;
1901                 }
1902         } while (0);
1903
1904         return status;
1905 }
1906
1907 static int DRX_Start(struct drxd_state *state, s32 off)
1908 {
1909         struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
1910         int status;
1911
1912         u16 transmissionParams = 0;
1913         u16 operationMode = 0;
1914         u16 qpskTdTpsPwr = 0;
1915         u16 qam16TdTpsPwr = 0;
1916         u16 qam64TdTpsPwr = 0;
1917         u32 feIfIncr = 0;
1918         u32 bandwidth = 0;
1919         int mirrorFreqSpect;
1920
1921         u16 qpskSnCeGain = 0;
1922         u16 qam16SnCeGain = 0;
1923         u16 qam64SnCeGain = 0;
1924         u16 qpskIsGainMan = 0;
1925         u16 qam16IsGainMan = 0;
1926         u16 qam64IsGainMan = 0;
1927         u16 qpskIsGainExp = 0;
1928         u16 qam16IsGainExp = 0;
1929         u16 qam64IsGainExp = 0;
1930         u16 bandwidthParam = 0;
1931
1932         if (off < 0)
1933                 off = (off - 500) / 1000;
1934         else
1935                 off = (off + 500) / 1000;
1936
1937         do {
1938                 if (state->drxd_state != DRXD_STOPPED)
1939                         return -1;
1940                 status = ResetECOD(state);
1941                 if (status < 0)
1942                         break;
1943                 if (state->type_A) {
1944                         status = InitSC(state);
1945                         if (status < 0)
1946                                 break;
1947                 } else {
1948                         status = InitFT(state);
1949                         if (status < 0)
1950                                 break;
1951                         status = InitCP(state);
1952                         if (status < 0)
1953                                 break;
1954                         status = InitCE(state);
1955                         if (status < 0)
1956                                 break;
1957                         status = InitEQ(state);
1958                         if (status < 0)
1959                                 break;
1960                         status = InitSC(state);
1961                         if (status < 0)
1962                                 break;
1963                 }
1964
1965                 /* Restore current IF & RF AGC settings */
1966
1967                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
1968                 if (status < 0)
1969                         break;
1970                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
1971                 if (status < 0)
1972                         break;
1973
1974                 mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
1975
1976                 switch (p->transmission_mode) {
1977                 default:        /* Not set, detect it automatically */
1978                         operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
1979                         /* fall through , try first guess DRX_FFTMODE_8K */
1980                 case TRANSMISSION_MODE_8K:
1981                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
1982                         if (state->type_A) {
1983                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
1984                                 if (status < 0)
1985                                         break;
1986                                 qpskSnCeGain = 99;
1987                                 qam16SnCeGain = 83;
1988                                 qam64SnCeGain = 67;
1989                         }
1990                         break;
1991                 case TRANSMISSION_MODE_2K:
1992                         transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
1993                         if (state->type_A) {
1994                                 status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
1995                                 if (status < 0)
1996                                         break;
1997                                 qpskSnCeGain = 97;
1998                                 qam16SnCeGain = 71;
1999                                 qam64SnCeGain = 65;
2000                         }
2001                         break;
2002                 }
2003
2004                 switch (p->guard_interval) {
2005                 case GUARD_INTERVAL_1_4:
2006                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2007                         break;
2008                 case GUARD_INTERVAL_1_8:
2009                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
2010                         break;
2011                 case GUARD_INTERVAL_1_16:
2012                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
2013                         break;
2014                 case GUARD_INTERVAL_1_32:
2015                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
2016                         break;
2017                 default:        /* Not set, detect it automatically */
2018                         operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
2019                         /* try first guess 1/4 */
2020                         transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
2021                         break;
2022                 }
2023
2024                 switch (p->hierarchy_information) {
2025                 case HIERARCHY_1:
2026                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
2027                         if (state->type_A) {
2028                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
2029                                 if (status < 0)
2030                                         break;
2031                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
2032                                 if (status < 0)
2033                                         break;
2034
2035                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2036                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
2037                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
2038
2039                                 qpskIsGainMan =
2040                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2041                                 qam16IsGainMan =
2042                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2043                                 qam64IsGainMan =
2044                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2045
2046                                 qpskIsGainExp =
2047                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2048                                 qam16IsGainExp =
2049                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2050                                 qam64IsGainExp =
2051                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2052                         }
2053                         break;
2054
2055                 case HIERARCHY_2:
2056                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
2057                         if (state->type_A) {
2058                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
2059                                 if (status < 0)
2060                                         break;
2061                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
2062                                 if (status < 0)
2063                                         break;
2064
2065                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2066                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
2067                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
2068
2069                                 qpskIsGainMan =
2070                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2071                                 qam16IsGainMan =
2072                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
2073                                 qam64IsGainMan =
2074                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
2075
2076                                 qpskIsGainExp =
2077                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2078                                 qam16IsGainExp =
2079                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
2080                                 qam64IsGainExp =
2081                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
2082                         }
2083                         break;
2084                 case HIERARCHY_4:
2085                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
2086                         if (state->type_A) {
2087                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
2088                                 if (status < 0)
2089                                         break;
2090                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
2091                                 if (status < 0)
2092                                         break;
2093
2094                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
2095                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
2096                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
2097
2098                                 qpskIsGainMan =
2099                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
2100                                 qam16IsGainMan =
2101                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
2102                                 qam64IsGainMan =
2103                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
2104
2105                                 qpskIsGainExp =
2106                                     SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
2107                                 qam16IsGainExp =
2108                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
2109                                 qam64IsGainExp =
2110                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
2111                         }
2112                         break;
2113                 case HIERARCHY_AUTO:
2114                 default:
2115                         /* Not set, detect it automatically, start with none */
2116                         operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
2117                         transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
2118                         if (state->type_A) {
2119                                 status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
2120                                 if (status < 0)
2121                                         break;
2122                                 status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
2123                                 if (status < 0)
2124                                         break;
2125
2126                                 qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
2127                                 qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
2128                                 qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
2129
2130                                 qpskIsGainMan =
2131                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
2132                                 qam16IsGainMan =
2133                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
2134                                 qam64IsGainMan =
2135                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
2136
2137                                 qpskIsGainExp =
2138                                     SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
2139                                 qam16IsGainExp =
2140                                     SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
2141                                 qam64IsGainExp =
2142                                     SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
2143                         }
2144                         break;
2145                 }
2146                 status = status;
2147                 if (status < 0)
2148                         break;
2149
2150                 switch (p->constellation) {
2151                 default:
2152                         operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
2153                         /* fall through , try first guess
2154                            DRX_CONSTELLATION_QAM64 */
2155                 case QAM_64:
2156                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
2157                         if (state->type_A) {
2158                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
2159                                 if (status < 0)
2160                                         break;
2161                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
2162                                 if (status < 0)
2163                                         break;
2164                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
2165                                 if (status < 0)
2166                                         break;
2167                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
2168                                 if (status < 0)
2169                                         break;
2170                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
2171                                 if (status < 0)
2172                                         break;
2173
2174                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
2175                                 if (status < 0)
2176                                         break;
2177                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
2178                                 if (status < 0)
2179                                         break;
2180                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
2181                                 if (status < 0)
2182                                         break;
2183                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
2184                                 if (status < 0)
2185                                         break;
2186                         }
2187                         break;
2188                 case QPSK:
2189                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
2190                         if (state->type_A) {
2191                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
2192                                 if (status < 0)
2193                                         break;
2194                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
2195                                 if (status < 0)
2196                                         break;
2197                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2198                                 if (status < 0)
2199                                         break;
2200                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
2201                                 if (status < 0)
2202                                         break;
2203                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2204                                 if (status < 0)
2205                                         break;
2206
2207                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
2208                                 if (status < 0)
2209                                         break;
2210                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
2211                                 if (status < 0)
2212                                         break;
2213                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
2214                                 if (status < 0)
2215                                         break;
2216                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
2217                                 if (status < 0)
2218                                         break;
2219                         }
2220                         break;
2221
2222                 case QAM_16:
2223                         transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
2224                         if (state->type_A) {
2225                                 status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
2226                                 if (status < 0)
2227                                         break;
2228                                 status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
2229                                 if (status < 0)
2230                                         break;
2231                                 status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
2232                                 if (status < 0)
2233                                         break;
2234                                 status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
2235                                 if (status < 0)
2236                                         break;
2237                                 status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
2238                                 if (status < 0)
2239                                         break;
2240
2241                                 status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
2242                                 if (status < 0)
2243                                         break;
2244                                 status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
2245                                 if (status < 0)
2246                                         break;
2247                                 status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
2248                                 if (status < 0)
2249                                         break;
2250                                 status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
2251                                 if (status < 0)
2252                                         break;
2253                         }
2254                         break;
2255
2256                 }
2257                 status = status;
2258                 if (status < 0)
2259                         break;
2260
2261                 switch (DRX_CHANNEL_HIGH) {
2262                 default:
2263                 case DRX_CHANNEL_AUTO:
2264                 case DRX_CHANNEL_LOW:
2265                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
2266                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
2267                         if (status < 0)
2268                                 break;
2269                         break;
2270                 case DRX_CHANNEL_HIGH:
2271                         transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
2272                         status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
2273                         if (status < 0)
2274                                 break;
2275                         break;
2276
2277                 }
2278
2279                 switch (p->code_rate_HP) {
2280                 case FEC_1_2:
2281                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
2282                         if (state->type_A) {
2283                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
2284                                 if (status < 0)
2285                                         break;
2286                         }
2287                         break;
2288                 default:
2289                         operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
2290                 case FEC_2_3:
2291                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
2292                         if (state->type_A) {
2293                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
2294                                 if (status < 0)
2295                                         break;
2296                         }
2297                         break;
2298                 case FEC_3_4:
2299                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
2300                         if (state->type_A) {
2301                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
2302                                 if (status < 0)
2303                                         break;
2304                         }
2305                         break;
2306                 case FEC_5_6:
2307                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
2308                         if (state->type_A) {
2309                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
2310                                 if (status < 0)
2311                                         break;
2312                         }
2313                         break;
2314                 case FEC_7_8:
2315                         transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
2316                         if (state->type_A) {
2317                                 status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
2318                                 if (status < 0)
2319                                         break;
2320                         }
2321                         break;
2322                 }
2323                 status = status;
2324                 if (status < 0)
2325                         break;
2326
2327                 /* First determine real bandwidth (Hz) */
2328                 /* Also set delay for impulse noise cruncher (only A2) */
2329                 /* Also set parameters for EC_OC fix, note
2330                    EC_OC_REG_TMD_HIL_MAR is changed
2331                    by SC for fix for some 8K,1/8 guard but is restored by
2332                    InitEC and ResetEC
2333                    functions */
2334                 switch (p->bandwidth) {
2335                 case BANDWIDTH_AUTO:
2336                 case BANDWIDTH_8_MHZ:
2337                         /* (64/7)*(8/8)*1000000 */
2338                         bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
2339
2340                         bandwidthParam = 0;
2341                         status = Write16(state,
2342                                          FE_AG_REG_IND_DEL__A, 50, 0x0000);
2343                         break;
2344                 case BANDWIDTH_7_MHZ:
2345                         /* (64/7)*(7/8)*1000000 */
2346                         bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
2347                         bandwidthParam = 0x4807;        /*binary:0100 1000 0000 0111 */
2348                         status = Write16(state,
2349                                          FE_AG_REG_IND_DEL__A, 59, 0x0000);
2350                         break;
2351                 case BANDWIDTH_6_MHZ:
2352                         /* (64/7)*(6/8)*1000000 */
2353                         bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
2354                         bandwidthParam = 0x0F07;        /*binary: 0000 1111 0000 0111 */
2355                         status = Write16(state,
2356                                          FE_AG_REG_IND_DEL__A, 71, 0x0000);
2357                         break;
2358                 default:
2359                         status = -EINVAL;
2360                 }
2361                 if (status < 0)
2362                         break;
2363
2364                 status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
2365                 if (status < 0)
2366                         break;
2367
2368                 {
2369                         u16 sc_config;
2370                         status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
2371                         if (status < 0)
2372                                 break;
2373
2374                         /* enable SLAVE mode in 2k 1/32 to
2375                            prevent timing change glitches */
2376                         if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
2377                             (p->guard_interval == GUARD_INTERVAL_1_32)) {
2378                                 /* enable slave */
2379                                 sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
2380                         } else {
2381                                 /* disable slave */
2382                                 sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
2383                         }
2384                         status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
2385                         if (status < 0)
2386                                 break;
2387                 }
2388
2389                 status = SetCfgNoiseCalibration(state, &state->noise_cal);
2390                 if (status < 0)
2391                         break;
2392
2393                 if (state->cscd_state == CSCD_INIT) {
2394                         /* switch on SRMM scan in SC */
2395                         status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
2396                         if (status < 0)
2397                                 break;
2398 /*            CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
2399                         state->cscd_state = CSCD_SET;
2400                 }
2401
2402                 /* Now compute FE_IF_REG_INCR */
2403                 /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
2404                    ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
2405                 feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
2406                                     (1ULL << 21), bandwidth) - (1 << 23);
2407                 status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
2408                 if (status < 0)
2409                         break;
2410                 status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
2411                 if (status < 0)
2412                         break;
2413                 /* Bandwidth setting done */
2414
2415                 /* Mirror & frequency offset */
2416                 SetFrequencyShift(state, off, mirrorFreqSpect);
2417
2418                 /* Start SC, write channel settings to SC */
2419
2420                 /* Enable SC after setting all other parameters */
2421                 status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
2422                 if (status < 0)
2423                         break;
2424                 status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
2425                 if (status < 0)
2426                         break;
2427
2428                 /* Write SC parameter registers, operation mode */
2429 #if 1
2430                 operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
2431                                  SC_RA_RAM_OP_AUTO_GUARD__M |
2432                                  SC_RA_RAM_OP_AUTO_CONST__M |
2433                                  SC_RA_RAM_OP_AUTO_HIER__M |
2434                                  SC_RA_RAM_OP_AUTO_RATE__M);
2435 #endif
2436                 status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
2437                 if (status < 0)
2438                         break;
2439
2440                 /* Start correct processes to get in lock */
2441                 status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
2442                 if (status < 0)
2443                         break;
2444
2445                 status = StartOC(state);
2446                 if (status < 0)
2447                         break;
2448
2449                 if (state->operation_mode != OM_Default) {
2450                         status = StartDiversity(state);
2451                         if (status < 0)
2452                                 break;
2453                 }
2454
2455                 state->drxd_state = DRXD_STARTED;
2456         } while (0);
2457
2458         return status;
2459 }
2460
2461 static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
2462 {
2463         u32 ulRfAgcOutputLevel = 0xffffffff;
2464         u32 ulRfAgcSettleLevel = 528;   /* Optimum value for MT2060 */
2465         u32 ulRfAgcMinLevel = 0;        /* Currently unused */
2466         u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
2467         u32 ulRfAgcSpeed = 0;   /* Currently unused */
2468         u32 ulRfAgcMode = 0;    /*2;   Off */
2469         u32 ulRfAgcR1 = 820;
2470         u32 ulRfAgcR2 = 2200;
2471         u32 ulRfAgcR3 = 150;
2472         u32 ulIfAgcMode = 0;    /* Auto */
2473         u32 ulIfAgcOutputLevel = 0xffffffff;
2474         u32 ulIfAgcSettleLevel = 0xffffffff;
2475         u32 ulIfAgcMinLevel = 0xffffffff;
2476         u32 ulIfAgcMaxLevel = 0xffffffff;
2477         u32 ulIfAgcSpeed = 0xffffffff;
2478         u32 ulIfAgcR1 = 820;
2479         u32 ulIfAgcR2 = 2200;
2480         u32 ulIfAgcR3 = 150;
2481         u32 ulClock = state->config.clock;
2482         u32 ulSerialMode = 0;
2483         u32 ulEcOcRegOcModeLop = 4;     /* Dynamic DTO source */
2484         u32 ulHiI2cDelay = HI_I2C_DELAY;
2485         u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
2486         u32 ulHiI2cPatch = 0;
2487         u32 ulEnvironment = APPENV_PORTABLE;
2488         u32 ulEnvironmentDiversity = APPENV_MOBILE;
2489         u32 ulIFFilter = IFFILTER_SAW;
2490
2491         state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2492         state->if_agc_cfg.outputLevel = 0;
2493         state->if_agc_cfg.settleLevel = 140;
2494         state->if_agc_cfg.minOutputLevel = 0;
2495         state->if_agc_cfg.maxOutputLevel = 1023;
2496         state->if_agc_cfg.speed = 904;
2497
2498         if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2499                 state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
2500                 state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
2501         }
2502
2503         if (ulIfAgcMode == 0 &&
2504             ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2505             ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2506             ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2507             ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2508                 state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2509                 state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
2510                 state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
2511                 state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
2512                 state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
2513         }
2514
2515         state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
2516         state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
2517         state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
2518
2519         state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
2520         state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
2521         state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
2522
2523         state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2524         /* rest of the RFAgcCfg structure currently unused */
2525         if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
2526                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
2527                 state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
2528         }
2529
2530         if (ulRfAgcMode == 0 &&
2531             ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
2532             ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
2533             ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
2534             ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
2535                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
2536                 state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
2537                 state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
2538                 state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
2539                 state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
2540         }
2541
2542         if (ulRfAgcMode == 2)
2543                 state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
2544
2545         if (ulEnvironment <= 2)
2546                 state->app_env_default = (enum app_env)
2547                     (ulEnvironment);
2548         if (ulEnvironmentDiversity <= 2)
2549                 state->app_env_diversity = (enum app_env)
2550                     (ulEnvironmentDiversity);
2551
2552         if (ulIFFilter == IFFILTER_DISCRETE) {
2553                 /* discrete filter */
2554                 state->noise_cal.cpOpt = 0;
2555                 state->noise_cal.cpNexpOfs = 40;
2556                 state->noise_cal.tdCal2k = -40;
2557                 state->noise_cal.tdCal8k = -24;
2558         } else {
2559                 /* SAW filter */
2560                 state->noise_cal.cpOpt = 1;
2561                 state->noise_cal.cpNexpOfs = 0;
2562                 state->noise_cal.tdCal2k = -21;
2563                 state->noise_cal.tdCal8k = -24;
2564         }
2565         state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
2566
2567         state->chip_adr = (state->config.demod_address << 1) | 1;
2568         switch (ulHiI2cPatch) {
2569         case 1:
2570                 state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
2571                 break;
2572         case 3:
2573                 state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
2574                 break;
2575         default:
2576                 state->m_HiI2cPatch = NULL;
2577         }
2578
2579         /* modify tuner and clock attributes */
2580         state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
2581         /* expected system clock frequency in kHz */
2582         state->expected_sys_clock_freq = 48000;
2583         /* real system clock frequency in kHz */
2584         state->sys_clock_freq = 48000;
2585         state->osc_clock_freq = (u16) ulClock;
2586         state->osc_clock_deviation = 0;
2587         state->cscd_state = CSCD_INIT;
2588         state->drxd_state = DRXD_UNINITIALIZED;
2589
2590         state->PGA = 0;
2591         state->type_A = 0;
2592         state->tuner_mirrors = 0;
2593
2594         /* modify MPEG output attributes */
2595         state->insert_rs_byte = state->config.insert_rs_byte;
2596         state->enable_parallel = (ulSerialMode != 1);
2597
2598         /* Timing div, 250ns/Psys */
2599         /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
2600
2601         state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
2602                                           ulHiI2cDelay) / 1000;
2603         /* Bridge delay, uses oscilator clock */
2604         /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
2605         state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
2606                                             ulHiI2cBridgeDelay) / 1000;
2607
2608         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2609         /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
2610         state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2611         return 0;
2612 }
2613
2614 int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
2615 {
2616         int status = 0;
2617         u32 driverVersion;
2618
2619         if (state->init_done)
2620                 return 0;
2621
2622         CDRXD(state, state->config.IF ? state->config.IF : 36000000);
2623
2624         do {
2625                 state->operation_mode = OM_Default;
2626
2627                 status = SetDeviceTypeId(state);
2628                 if (status < 0)
2629                         break;
2630
2631                 /* Apply I2c address patch to B1 */
2632                 if (!state->type_A && state->m_HiI2cPatch != NULL)
2633                         status = WriteTable(state, state->m_HiI2cPatch);
2634                         if (status < 0)
2635                                 break;
2636
2637                 if (state->type_A) {
2638                         /* HI firmware patch for UIO readout,
2639                            avoid clearing of result register */
2640                         status = Write16(state, 0x43012D, 0x047f, 0);
2641                         if (status < 0)
2642                                 break;
2643                 }
2644
2645                 status = HI_ResetCommand(state);
2646                 if (status < 0)
2647                         break;
2648
2649                 status = StopAllProcessors(state);
2650                 if (status < 0)
2651                         break;
2652                 status = InitCC(state);
2653                 if (status < 0)
2654                         break;
2655
2656                 state->osc_clock_deviation = 0;
2657
2658                 if (state->config.osc_deviation)
2659                         state->osc_clock_deviation =
2660                             state->config.osc_deviation(state->priv, 0, 0);
2661                 {
2662                         /* Handle clock deviation */
2663                         s32 devB;
2664                         s32 devA = (s32) (state->osc_clock_deviation) *
2665                             (s32) (state->expected_sys_clock_freq);
2666                         /* deviation in kHz */
2667                         s32 deviation = (devA / (1000000L));
2668                         /* rounding, signed */
2669                         if (devA > 0)
2670                                 devB = (2);
2671                         else
2672                                 devB = (-2);
2673                         if ((devB * (devA % 1000000L) > 1000000L)) {
2674                                 /* add +1 or -1 */
2675                                 deviation += (devB / 2);
2676                         }
2677
2678                         state->sys_clock_freq =
2679                             (u16) ((state->expected_sys_clock_freq) +
2680                                    deviation);
2681                 }
2682                 status = InitHI(state);
2683                 if (status < 0)
2684                         break;
2685                 status = InitAtomicRead(state);
2686                 if (status < 0)
2687                         break;
2688
2689                 status = EnableAndResetMB(state);
2690                 if (status < 0)
2691                         break;
2692                 if (state->type_A)
2693                         status = ResetCEFR(state);
2694                         if (status < 0)
2695                                 break;
2696
2697                 if (fw) {
2698                         status = DownloadMicrocode(state, fw, fw_size);
2699                         if (status < 0)
2700                                 break;
2701                 } else {
2702                         status = DownloadMicrocode(state, state->microcode, state->microcode_length);
2703                         if (status < 0)
2704                                 break;
2705                 }
2706
2707                 if (state->PGA) {
2708                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
2709                         SetCfgPga(state, 0);    /* PGA = 0 dB */
2710                 } else {
2711                         state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
2712                 }
2713
2714                 state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
2715
2716                 status = InitFE(state);
2717                 if (status < 0)
2718                         break;
2719                 status = InitFT(state);
2720                 if (status < 0)
2721                         break;
2722                 status = InitCP(state);
2723                 if (status < 0)
2724                         break;
2725                 status = InitCE(state);
2726                 if (status < 0)
2727                         break;
2728                 status = InitEQ(state);
2729                 if (status < 0)
2730                         break;
2731                 status = InitEC(state);
2732                 if (status < 0)
2733                         break;
2734                 status = InitSC(state);
2735                 if (status < 0)
2736                         break;
2737
2738                 status = SetCfgIfAgc(state, &state->if_agc_cfg);
2739                 if (status < 0)
2740                         break;
2741                 status = SetCfgRfAgc(state, &state->rf_agc_cfg);
2742                 if (status < 0)
2743                         break;
2744
2745                 state->cscd_state = CSCD_INIT;
2746                 status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2747                 if (status < 0)
2748                         break;
2749                 status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
2750                 if (status < 0)
2751                         break;
2752
2753                 driverVersion = (((VERSION_MAJOR / 10) << 4) +
2754                                  (VERSION_MAJOR % 10)) << 24;
2755                 driverVersion += (((VERSION_MINOR / 10) << 4) +
2756                                   (VERSION_MINOR % 10)) << 16;
2757                 driverVersion += ((VERSION_PATCH / 1000) << 12) +
2758                     ((VERSION_PATCH / 100) << 8) +
2759                     ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
2760
2761                 status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
2762                 if (status < 0)
2763                         break;
2764
2765                 status = StopOC(state);
2766                 if (status < 0)
2767                         break;
2768
2769                 state->drxd_state = DRXD_STOPPED;
2770                 state->init_done = 1;
2771                 status = 0;
2772         } while (0);
2773         return status;
2774 }
2775
2776 int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
2777 {
2778         DRX_GetLockStatus(state, pLockStatus);
2779
2780         /*if (*pLockStatus&DRX_LOCK_MPEG) */
2781         if (*pLockStatus & DRX_LOCK_FEC) {
2782                 ConfigureMPEGOutput(state, 1);
2783                 /* Get status again, in case we have MPEG lock now */
2784                 /*DRX_GetLockStatus(state, pLockStatus); */
2785         }
2786
2787         return 0;
2788 }
2789
2790 /****************************************************************************/
2791 /****************************************************************************/
2792 /****************************************************************************/
2793
2794 static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
2795 {
2796         struct drxd_state *state = fe->demodulator_priv;
2797         u32 value;
2798         int res;
2799
2800         res = ReadIFAgc(state, &value);
2801         if (res < 0)
2802                 *strength = 0;
2803         else
2804                 *strength = 0xffff - (value << 4);
2805         return 0;
2806 }
2807
2808 static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
2809 {
2810         struct drxd_state *state = fe->demodulator_priv;
2811         u32 lock;
2812
2813         DRXD_status(state, &lock);
2814         *status = 0;
2815         /* No MPEG lock in V255 firmware, bug ? */
2816 #if 1
2817         if (lock & DRX_LOCK_MPEG)
2818                 *status |= FE_HAS_LOCK;
2819 #else
2820         if (lock & DRX_LOCK_FEC)
2821                 *status |= FE_HAS_LOCK;
2822 #endif
2823         if (lock & DRX_LOCK_FEC)
2824                 *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
2825         if (lock & DRX_LOCK_DEMOD)
2826                 *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
2827
2828         return 0;
2829 }
2830
2831 static int drxd_init(struct dvb_frontend *fe)
2832 {
2833         struct drxd_state *state = fe->demodulator_priv;
2834         int err = 0;
2835
2836 /*      if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
2837         return DRXD_init(state, 0, 0);
2838
2839         err = DRXD_init(state, state->fw->data, state->fw->size);
2840         release_firmware(state->fw);
2841         return err;
2842 }
2843
2844 int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
2845 {
2846         struct drxd_state *state = fe->demodulator_priv;
2847
2848         if (state->config.disable_i2c_gate_ctrl == 1)
2849                 return 0;
2850
2851         return DRX_ConfigureI2CBridge(state, onoff);
2852 }
2853 EXPORT_SYMBOL(drxd_config_i2c);
2854
2855 static int drxd_get_tune_settings(struct dvb_frontend *fe,
2856                                   struct dvb_frontend_tune_settings *sets)
2857 {
2858         sets->min_delay_ms = 10000;
2859         sets->max_drift = 0;
2860         sets->step_size = 0;
2861         return 0;
2862 }
2863
2864 static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
2865 {
2866         *ber = 0;
2867         return 0;
2868 }
2869
2870 static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
2871 {
2872         *snr = 0;
2873         return 0;
2874 }
2875
2876 static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
2877 {
2878         *ucblocks = 0;
2879         return 0;
2880 }
2881
2882 static int drxd_sleep(struct dvb_frontend *fe)
2883 {
2884         struct drxd_state *state = fe->demodulator_priv;
2885
2886         ConfigureMPEGOutput(state, 0);
2887         return 0;
2888 }
2889
2890 static int drxd_get_frontend(struct dvb_frontend *fe,
2891                              struct dvb_frontend_parameters *param)
2892 {
2893         return 0;
2894 }
2895
2896 static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
2897 {
2898         return drxd_config_i2c(fe, enable);
2899 }
2900
2901 static int drxd_set_frontend(struct dvb_frontend *fe,
2902                              struct dvb_frontend_parameters *param)
2903 {
2904         struct drxd_state *state = fe->demodulator_priv;
2905         s32 off = 0;
2906
2907         state->param = *param;
2908         DRX_Stop(state);
2909
2910         if (fe->ops.tuner_ops.set_params) {
2911                 fe->ops.tuner_ops.set_params(fe, param);
2912                 if (fe->ops.i2c_gate_ctrl)
2913                         fe->ops.i2c_gate_ctrl(fe, 0);
2914         }
2915
2916         /* FIXME: move PLL drivers */
2917         if (state->config.pll_set &&
2918             state->config.pll_set(state->priv, param,
2919                                   state->config.pll_address,
2920                                   state->config.demoda_address, &off) < 0) {
2921                 printk(KERN_ERR "Error in pll_set\n");
2922                 return -1;
2923         }
2924
2925         msleep(200);
2926
2927         return DRX_Start(state, off);
2928 }
2929
2930 static void drxd_release(struct dvb_frontend *fe)
2931 {
2932         struct drxd_state *state = fe->demodulator_priv;
2933
2934         kfree(state);
2935 }
2936
2937 static struct dvb_frontend_ops drxd_ops = {
2938
2939         .info = {
2940                  .name = "Micronas DRXD DVB-T",
2941                  .type = FE_OFDM,
2942                  .frequency_min = 47125000,
2943                  .frequency_max = 855250000,
2944                  .frequency_stepsize = 166667,
2945                  .frequency_tolerance = 0,
2946                  .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
2947                  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
2948                  FE_CAN_FEC_AUTO |
2949                  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
2950                  FE_CAN_QAM_AUTO |
2951                  FE_CAN_TRANSMISSION_MODE_AUTO |
2952                  FE_CAN_GUARD_INTERVAL_AUTO |
2953                  FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
2954
2955         .release = drxd_release,
2956         .init = drxd_init,
2957         .sleep = drxd_sleep,
2958         .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
2959
2960         .set_frontend = drxd_set_frontend,
2961         .get_frontend = drxd_get_frontend,
2962         .get_tune_settings = drxd_get_tune_settings,
2963
2964         .read_status = drxd_read_status,
2965         .read_ber = drxd_read_ber,
2966         .read_signal_strength = drxd_read_signal_strength,
2967         .read_snr = drxd_read_snr,
2968         .read_ucblocks = drxd_read_ucblocks,
2969 };
2970
2971 struct dvb_frontend *drxd_attach(const struct drxd_config *config,
2972                                  void *priv, struct i2c_adapter *i2c,
2973                                  struct device *dev)
2974 {
2975         struct drxd_state *state = NULL;
2976
2977         state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
2978         if (!state)
2979                 return NULL;
2980         memset(state, 0, sizeof(*state));
2981
2982         memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
2983         state->dev = dev;
2984         state->config = *config;
2985         state->i2c = i2c;
2986         state->priv = priv;
2987
2988         mutex_init(&state->mutex);
2989
2990         if (Read16(state, 0, 0, 0) < 0)
2991                 goto error;
2992
2993         memcpy(&state->frontend.ops, &drxd_ops,
2994                sizeof(struct dvb_frontend_ops));
2995         state->frontend.demodulator_priv = state;
2996         ConfigureMPEGOutput(state, 0);
2997         return &state->frontend;
2998
2999 error:
3000         printk(KERN_ERR "drxd: not found\n");
3001         kfree(state);
3002         return NULL;
3003 }
3004 EXPORT_SYMBOL(drxd_attach);
3005
3006 MODULE_DESCRIPTION("DRXD driver");
3007 MODULE_AUTHOR("Micronas");
3008 MODULE_LICENSE("GPL");