drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/mm_types.h>
  28 #include <asm/page.h>
  29
  30 #include "intel-pasid.h"
  31
  32 static irqreturn_t prq_event_thread(int irq, void *d);
  33
  34 int intel_svm_init(struct intel_iommu *iommu)
  35 {
  36         if (cpu_feature_enabled(X86_FEATURE_GBPAGES) &&
  37                         !cap_fl1gp_support(iommu->cap))
  38                 return -EINVAL;
  39
  40         if (cpu_feature_enabled(X86_FEATURE_LA57) &&
  41                         !cap_5lp_support(iommu->cap))
  42                 return -EINVAL;
  43
  44         return 0;
  45 }
  46
  47 #define PRQ_ORDER 0
  48
  49 int intel_svm_enable_prq(struct intel_iommu *iommu)
  50 {
  51         struct page *pages;
  52         int irq, ret;
  53
  54         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
  55         if (!pages) {
  56                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
  57                         iommu->name);
  58                 return -ENOMEM;
  59         }
  60         iommu->prq = page_address(pages);
  61
  62         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
  63         if (irq <= 0) {
  64                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
  65                        iommu->name);
  66                 ret = -EINVAL;
  67         err:
  68                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
  69                 iommu->prq = NULL;
  70                 return ret;
  71         }
  72         iommu->pr_irq = irq;
  73
  74         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
  75
  76         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
  77                                    iommu->prq_name, iommu);
  78         if (ret) {
  79                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
  80                        iommu->name);
  81                 dmar_free_hwirq(irq);
  82                 iommu->pr_irq = 0;
  83                 goto err;
  84         }
  85         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  86         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  87         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
  88
  89         return 0;
  90 }
  91
  92 int intel_svm_finish_prq(struct intel_iommu *iommu)
  93 {
  94         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
  95         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
  96         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
  97
  98         if (iommu->pr_irq) {
  99                 free_irq(iommu->pr_irq, iommu);
 100                 dmar_free_hwirq(iommu->pr_irq);
 101                 iommu->pr_irq = 0;
 102         }
 103
 104         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 105         iommu->prq = NULL;
 106
 107         return 0;
 108 }
 109
 110 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 111                                        unsigned long address, unsigned long pages, int ih, int gl)
 112 {
 113         struct qi_desc desc;
 114
 115         if (pages == -1) {
 116                 /* For global kernel pages we have to flush them in *all* PASIDs
 117                  * because that's the only option the hardware gives us. Despite
 118                  * the fact that they are actually only accessible through one. */
 119                 if (gl)
 120                         desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 121                                         QI_EIOTLB_DID(sdev->did) |
 122                                         QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) |
 123                                         QI_EIOTLB_TYPE;
 124                 else
 125                         desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 126                                         QI_EIOTLB_DID(sdev->did) |
 127                                         QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) |
 128                                         QI_EIOTLB_TYPE;
 129                 desc.qw1 = 0;
 130         } else {
 131                 int mask = ilog2(__roundup_pow_of_two(pages));
 132
 133                 desc.qw0 = QI_EIOTLB_PASID(svm->pasid) |
 134                                 QI_EIOTLB_DID(sdev->did) |
 135                                 QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) |
 136                                 QI_EIOTLB_TYPE;
 137                 desc.qw1 = QI_EIOTLB_ADDR(address) |
 138                                 QI_EIOTLB_GL(gl) |
 139                                 QI_EIOTLB_IH(ih) |
 140                                 QI_EIOTLB_AM(mask);
 141         }
 142         desc.qw2 = 0;
 143         desc.qw3 = 0;
 144         qi_submit_sync(&desc, svm->iommu);
 145
 146         if (sdev->dev_iotlb) {
 147                 desc.qw0 = QI_DEV_EIOTLB_PASID(svm->pasid) |
 148                                 QI_DEV_EIOTLB_SID(sdev->sid) |
 149                                 QI_DEV_EIOTLB_QDEP(sdev->qdep) |
 150                                 QI_DEIOTLB_TYPE;
 151                 if (pages == -1) {
 152                         desc.qw1 = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) |
 153                                         QI_DEV_EIOTLB_SIZE;
 154                 } else if (pages > 1) {
 155                         /* The least significant zero bit indicates the size. So,
 156                          * for example, an "address" value of 0x12345f000 will
 157                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 158                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 159                         unsigned long mask = __rounddown_pow_of_two(address ^ last);
 160
 161                         desc.qw1 = QI_DEV_EIOTLB_ADDR((address & ~mask) |
 162                                         (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 163                 } else {
 164                         desc.qw1 = QI_DEV_EIOTLB_ADDR(address);
 165                 }
 166                 desc.qw2 = 0;
 167                 desc.qw3 = 0;
 168                 qi_submit_sync(&desc, svm->iommu);
 169         }
 170 }
 171
 172 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 173                                   unsigned long pages, int ih, int gl)
 174 {
 175         struct intel_svm_dev *sdev;
 176
 177         rcu_read_lock();
 178         list_for_each_entry_rcu(sdev, &svm->devs, list)
 179                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 180         rcu_read_unlock();
 181 }
 182
 183 /* Pages have been freed at this point */
 184 static void intel_invalidate_range(struct mmu_notifier *mn,
 185                                    struct mm_struct *mm,
 186                                    unsigned long start, unsigned long end)
 187 {
 188         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 189
 190         intel_flush_svm_range(svm, start,
 191                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 192 }
 193
 194 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 195 {
 196         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 197         struct intel_svm_dev *sdev;
 198
 199         /* This might end up being called from exit_mmap(), *before* the page
 200          * tables are cleared. And __mmu_notifier_release() will delete us from
 201          * the list of notifiers so that our invalidate_range() callback doesn't
 202          * get called when the page tables are cleared. So we need to protect
 203          * against hardware accessing those page tables.
 204          *
 205          * We do it by clearing the entry in the PASID table and then flushing
 206          * the IOTLB and the PASID table caches. This might upset hardware;
 207          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 208          * page) so that we end up taking a fault that the hardware really
 209          * *has* to handle gracefully without affecting other processes.
 210          */
 211         rcu_read_lock();
 212         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 213                 intel_pasid_tear_down_entry(svm->iommu, sdev->dev, svm->pasid);
 214                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 215         }
 216         rcu_read_unlock();
 217
 218 }
 219
 220 static const struct mmu_notifier_ops intel_mmuops = {
 221         .release = intel_mm_release,
 222         .invalidate_range = intel_invalidate_range,
 223 };
 224
 225 static DEFINE_MUTEX(pasid_mutex);
 226 static LIST_HEAD(global_svm_list);
 227
 228 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 229 {
 230         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 231         struct device_domain_info *info;
 232         struct intel_svm_dev *sdev;
 233         struct intel_svm *svm = NULL;
 234         struct mm_struct *mm = NULL;
 235         int pasid_max;
 236         int ret;
 237
 238         if (!iommu || dmar_disabled)
 239                 return -EINVAL;
 240
 241         if (dev_is_pci(dev)) {
 242                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 243                 if (pasid_max < 0)
 244                         return -EINVAL;
 245         } else
 246                 pasid_max = 1 << 20;
 247
 248         if (flags & SVM_FLAG_SUPERVISOR_MODE) {
 249                 if (!ecap_srs(iommu->ecap))
 250                         return -EINVAL;
 251         } else if (pasid) {
 252                 mm = get_task_mm(current);
 253                 BUG_ON(!mm);
 254         }
 255
 256         mutex_lock(&pasid_mutex);
 257         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 258                 struct intel_svm *t;
 259
 260                 list_for_each_entry(t, &global_svm_list, list) {
 261                         if (t->mm != mm || (t->flags & SVM_FLAG_PRIVATE_PASID))
 262                                 continue;
 263
 264                         svm = t;
 265                         if (svm->pasid >= pasid_max) {
 266                                 dev_warn(dev,
 267                                          "Limited PASID width. Cannot use existing PASID %d\n",
 268                                          svm->pasid);
 269                                 ret = -ENOSPC;
 270                                 goto out;
 271                         }
 272
 273                         list_for_each_entry(sdev, &svm->devs, list) {
 274                                 if (dev == sdev->dev) {
 275                                         if (sdev->ops != ops) {
 276                                                 ret = -EBUSY;
 277                                                 goto out;
 278                                         }
 279                                         sdev->users++;
 280                                         goto success;
 281                                 }
 282                         }
 283
 284                         break;
 285                 }
 286         }
 287
 288         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 289         if (!sdev) {
 290                 ret = -ENOMEM;
 291                 goto out;
 292         }
 293         sdev->dev = dev;
 294
 295         ret = intel_iommu_enable_pasid(iommu, dev);
 296         if (ret || !pasid) {
 297                 /* If they don't actually want to assign a PASID, this is
 298                  * just an enabling check/preparation. */
 299                 kfree(sdev);
 300                 goto out;
 301         }
 302
 303         info = dev->archdata.iommu;
 304         if (!info || !info->pasid_supported) {
 305                 kfree(sdev);
 306                 goto out;
 307         }
 308
 309         sdev->did = FLPT_DEFAULT_DID;
 310         sdev->sid = PCI_DEVID(info->bus, info->devfn);
 311         if (info->ats_enabled) {
 312                 sdev->dev_iotlb = 1;
 313                 sdev->qdep = info->ats_qdep;
 314                 if (sdev->qdep >= QI_DEV_EIOTLB_MAX_INVS)
 315                         sdev->qdep = 0;
 316         }
 317
 318         /* Finish the setup now we know we're keeping it */
 319         sdev->users = 1;
 320         sdev->ops = ops;
 321         init_rcu_head(&sdev->rcu);
 322
 323         if (!svm) {
 324                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 325                 if (!svm) {
 326                         ret = -ENOMEM;
 327                         kfree(sdev);
 328                         goto out;
 329                 }
 330                 svm->iommu = iommu;
 331
 332                 if (pasid_max > intel_pasid_max_id)
 333                         pasid_max = intel_pasid_max_id;
 334
 335                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 336                 ret = intel_pasid_alloc_id(svm,
 337                                            !!cap_caching_mode(iommu->cap),
 338                                            pasid_max - 1, GFP_KERNEL);
 339                 if (ret < 0) {
 340                         kfree(svm);
 341                         kfree(sdev);
 342                         goto out;
 343                 }
 344                 svm->pasid = ret;
 345                 svm->notifier.ops = &intel_mmuops;
 346                 svm->mm = mm;
 347                 svm->flags = flags;
 348                 INIT_LIST_HEAD_RCU(&svm->devs);
 349                 INIT_LIST_HEAD(&svm->list);
 350                 ret = -ENOMEM;
 351                 if (mm) {
 352                         ret = mmu_notifier_register(&svm->notifier, mm);
 353                         if (ret) {
 354                                 intel_pasid_free_id(svm->pasid);
 355                                 kfree(svm);
 356                                 kfree(sdev);
 357                                 goto out;
 358                         }
 359                 }
 360
 361                 spin_lock(&iommu->lock);
 362                 ret = intel_pasid_setup_first_level(iommu, dev,
 363                                 mm ? mm->pgd : init_mm.pgd,
 364                                 svm->pasid, FLPT_DEFAULT_DID,
 365                                 mm ? 0 : PASID_FLAG_SUPERVISOR_MODE);
 366                 spin_unlock(&iommu->lock);
 367                 if (ret) {
 368                         if (mm)
 369                                 mmu_notifier_unregister(&svm->notifier, mm);
 370                         intel_pasid_free_id(svm->pasid);
 371                         kfree(svm);
 372                         kfree(sdev);
 373                         goto out;
 374                 }
 375
 376                 list_add_tail(&svm->list, &global_svm_list);
 377         }
 378         list_add_rcu(&sdev->list, &svm->devs);
 379
 380  success:
 381         *pasid = svm->pasid;
 382         ret = 0;
 383  out:
 384         mutex_unlock(&pasid_mutex);
 385         if (mm)
 386                 mmput(mm);
 387         return ret;
 388 }
 389 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 390
 391 int intel_svm_unbind_mm(struct device *dev, int pasid)
 392 {
 393         struct intel_svm_dev *sdev;
 394         struct intel_iommu *iommu;
 395         struct intel_svm *svm;
 396         int ret = -EINVAL;
 397
 398         mutex_lock(&pasid_mutex);
 399         iommu = intel_svm_device_to_iommu(dev);
 400         if (!iommu)
 401                 goto out;
 402
 403         svm = intel_pasid_lookup_id(pasid);
 404         if (!svm)
 405                 goto out;
 406
 407         list_for_each_entry(sdev, &svm->devs, list) {
 408                 if (dev == sdev->dev) {
 409                         ret = 0;
 410                         sdev->users--;
 411                         if (!sdev->users) {
 412                                 list_del_rcu(&sdev->list);
 413                                 /* Flush the PASID cache and IOTLB for this device.
 414                                  * Note that we do depend on the hardware *not* using
 415                                  * the PASID any more. Just as we depend on other
 416                                  * devices never using PASIDs that they have no right
 417                                  * to use. We have a *shared* PASID table, because it's
 418                                  * large and has to be physically contiguous. So it's
 419                                  * hard to be as defensive as we might like. */
 420                                 intel_pasid_tear_down_entry(iommu, dev, svm->pasid);
 421                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 422                                 kfree_rcu(sdev, rcu);
 423
 424                                 if (list_empty(&svm->devs)) {
 425                                         intel_pasid_free_id(svm->pasid);
 426                                         if (svm->mm)
 427                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 428
 429                                         list_del(&svm->list);
 430
 431                                         /* We mandate that no page faults may be outstanding
 432                                          * for the PASID when intel_svm_unbind_mm() is called.
 433                                          * If that is not obeyed, subtle errors will happen.
 434                                          * Let's make them less subtle... */
 435                                         memset(svm, 0x6b, sizeof(*svm));
 436                                         kfree(svm);
 437                                 }
 438                         }
 439                         break;
 440                 }
 441         }
 442  out:
 443         mutex_unlock(&pasid_mutex);
 444
 445         return ret;
 446 }
 447 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 448
 449 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 450 {
 451         struct intel_iommu *iommu;
 452         struct intel_svm *svm;
 453         int ret = -EINVAL;
 454
 455         mutex_lock(&pasid_mutex);
 456         iommu = intel_svm_device_to_iommu(dev);
 457         if (!iommu)
 458                 goto out;
 459
 460         svm = intel_pasid_lookup_id(pasid);
 461         if (!svm)
 462                 goto out;
 463
 464         /* init_mm is used in this case */
 465         if (!svm->mm)
 466                 ret = 1;
 467         else if (atomic_read(&svm->mm->mm_users) > 0)
 468                 ret = 1;
 469         else
 470                 ret = 0;
 471
 472  out:
 473         mutex_unlock(&pasid_mutex);
 474
 475         return ret;
 476 }
 477 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 478
 479 /* Page request queue descriptor */
 480 struct page_req_dsc {
 481         union {
 482                 struct {
 483                         u64 type:8;
 484                         u64 pasid_present:1;
 485                         u64 priv_data_present:1;
 486                         u64 rsvd:6;
 487                         u64 rid:16;
 488                         u64 pasid:20;
 489                         u64 exe_req:1;
 490                         u64 pm_req:1;
 491                         u64 rsvd2:10;
 492                 };
 493                 u64 qw_0;
 494         };
 495         union {
 496                 struct {
 497                         u64 rd_req:1;
 498                         u64 wr_req:1;
 499                         u64 lpig:1;
 500                         u64 prg_index:9;
 501                         u64 addr:52;
 502                 };
 503                 u64 qw_1;
 504         };
 505         u64 priv_data[2];
 506 };
 507
 508 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 509
 510 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 511 {
 512         unsigned long requested = 0;
 513
 514         if (req->exe_req)
 515                 requested |= VM_EXEC;
 516
 517         if (req->rd_req)
 518                 requested |= VM_READ;
 519
 520         if (req->wr_req)
 521                 requested |= VM_WRITE;
 522
 523         return (requested & ~vma->vm_flags) != 0;
 524 }
 525
 526 static bool is_canonical_address(u64 addr)
 527 {
 528         int shift = 64 - (__VIRTUAL_MASK_SHIFT + 1);
 529         long saddr = (long) addr;
 530
 531         return (((saddr << shift) >> shift) == saddr);
 532 }
 533
 534 static irqreturn_t prq_event_thread(int irq, void *d)
 535 {
 536         struct intel_iommu *iommu = d;
 537         struct intel_svm *svm = NULL;
 538         int head, tail, handled = 0;
 539
 540         /* Clear PPR bit before reading head/tail registers, to
 541          * ensure that we get a new interrupt if needed. */
 542         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 543
 544         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 545         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 546         while (head != tail) {
 547                 struct intel_svm_dev *sdev;
 548                 struct vm_area_struct *vma;
 549                 struct page_req_dsc *req;
 550                 struct qi_desc resp;
 551                 int result;
 552                 vm_fault_t ret;
 553                 u64 address;
 554
 555                 handled = 1;
 556
 557                 req = &iommu->prq[head / sizeof(*req)];
 558
 559                 result = QI_RESP_FAILURE;
 560                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 561                 if (!req->pasid_present) {
 562                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 563                                iommu->name, ((unsigned long long *)req)[0],
 564                                ((unsigned long long *)req)[1]);
 565                         goto no_pasid;
 566                 }
 567
 568                 if (!svm || svm->pasid != req->pasid) {
 569                         rcu_read_lock();
 570                         svm = intel_pasid_lookup_id(req->pasid);
 571                         /* It *can't* go away, because the driver is not permitted
 572                          * to unbind the mm while any page faults are outstanding.
 573                          * So we only need RCU to protect the internal idr code. */
 574                         rcu_read_unlock();
 575
 576                         if (!svm) {
 577                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 578                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 579                                        ((unsigned long long *)req)[1]);
 580                                 goto no_pasid;
 581                         }
 582                 }
 583
 584                 result = QI_RESP_INVALID;
 585                 /* Since we're using init_mm.pgd directly, we should never take
 586                  * any faults on kernel addresses. */
 587                 if (!svm->mm)
 588                         goto bad_req;
 589                 /* If the mm is already defunct, don't handle faults. */
 590                 if (!mmget_not_zero(svm->mm))
 591                         goto bad_req;
 592
 593                 /* If address is not canonical, return invalid response */
 594                 if (!is_canonical_address(address))
 595                         goto bad_req;
 596
 597                 down_read(&svm->mm->mmap_sem);
 598                 vma = find_extend_vma(svm->mm, address);
 599                 if (!vma || address < vma->vm_start)
 600                         goto invalid;
 601
 602                 if (access_error(vma, req))
 603                         goto invalid;
 604
 605                 ret = handle_mm_fault(vma, address,
 606                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 607                 if (ret & VM_FAULT_ERROR)
 608                         goto invalid;
 609
 610                 result = QI_RESP_SUCCESS;
 611         invalid:
 612                 up_read(&svm->mm->mmap_sem);
 613                 mmput(svm->mm);
 614         bad_req:
 615                 /* Accounting for major/minor faults? */
 616                 rcu_read_lock();
 617                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 618                         if (sdev->sid == req->rid)
 619                                 break;
 620                 }
 621                 /* Other devices can go away, but the drivers are not permitted
 622                  * to unbind while any page faults might be in flight. So it's
 623                  * OK to drop the 'lock' here now we have it. */
 624                 rcu_read_unlock();
 625
 626                 if (WARN_ON(&sdev->list == &svm->devs))
 627                         sdev = NULL;
 628
 629                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 630                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 631                                 (req->exe_req << 1) | (req->pm_req);
 632                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr,
 633                                             req->priv_data, rwxp, result);
 634                 }
 635                 /* We get here in the error case where the PASID lookup failed,
 636                    and these can be NULL. Do not use them below this point! */
 637                 sdev = NULL;
 638                 svm = NULL;
 639         no_pasid:
 640                 if (req->lpig || req->priv_data_present) {
 641                         /*
 642                          * Per VT-d spec. v3.0 ch7.7, system software must
 643                          * respond with page group response if private data
 644                          * is present (PDP) or last page in group (LPIG) bit
 645                          * is set. This is an additional VT-d feature beyond
 646                          * PCI ATS spec.
 647                          */
 648                         resp.qw0 = QI_PGRP_PASID(req->pasid) |
 649                                 QI_PGRP_DID(req->rid) |
 650                                 QI_PGRP_PASID_P(req->pasid_present) |
 651                                 QI_PGRP_PDP(req->pasid_present) |
 652                                 QI_PGRP_RESP_CODE(result) |
 653                                 QI_PGRP_RESP_TYPE;
 654                         resp.qw1 = QI_PGRP_IDX(req->prg_index) |
 655                                 QI_PGRP_LPIG(req->lpig);
 656
 657                         if (req->priv_data_present)
 658                                 memcpy(&resp.qw2, req->priv_data,
 659                                        sizeof(req->priv_data));
 660                 }
 661                 resp.qw2 = 0;
 662                 resp.qw3 = 0;
 663                 qi_submit_sync(&resp, iommu);
 664
 665                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 666         }
 667
 668         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 669
 670         return IRQ_RETVAL(handled);
 671 }