1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "DMAR-IR: " fmt
5 #include <linux/interrupt.h>
6 #include <linux/dmar.h>
7 #include <linux/spinlock.h>
8 #include <linux/slab.h>
9 #include <linux/jiffies.h>
10 #include <linux/hpet.h>
11 #include <linux/pci.h>
12 #include <linux/irq.h>
13 #include <linux/acpi.h>
14 #include <linux/irqdomain.h>
15 #include <linux/crash_dump.h>
16 #include <asm/io_apic.h>
20 #include <asm/irq_remapping.h>
21 #include <asm/pci-direct.h>
22 #include <asm/posted_intr.h>
25 #include "../irq_remapping.h"
26 #include "../iommu-pages.h"
27 #include "cap_audit.h"
35 struct intel_iommu *iommu;
37 unsigned int bus; /* PCI bus number */
38 unsigned int devfn; /* PCI devfn number */
42 struct intel_iommu *iommu;
49 struct intel_iommu *iommu;
57 struct intel_ir_data {
58 struct irq_2_iommu irq_2_iommu;
59 struct irte irte_entry;
61 struct msi_msg msi_entry;
65 #define IR_X2APIC_MODE(mode) (mode ? (1 << 11) : 0)
66 #define IRTE_DEST(dest) ((eim_mode) ? dest : dest << 8)
68 static int __read_mostly eim_mode;
69 static struct ioapic_scope ir_ioapic[MAX_IO_APICS];
70 static struct hpet_scope ir_hpet[MAX_HPET_TBS];
77 * ->iommu->register_lock
79 * intel_irq_remap_ops.{supported,prepare,enable,disable,reenable} are called
80 * in single-threaded environment with interrupt disabled, so no need to tabke
81 * the dmar_global_lock.
83 DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
84 static const struct irq_domain_ops intel_ir_domain_ops;
86 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
87 static int __init parse_ioapics_under_ir(void);
88 static const struct msi_parent_ops dmar_msi_parent_ops, virt_dmar_msi_parent_ops;
90 static bool ir_pre_enabled(struct intel_iommu *iommu)
92 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED);
95 static void clear_ir_pre_enabled(struct intel_iommu *iommu)
97 iommu->flags &= ~VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
100 static void init_ir_status(struct intel_iommu *iommu)
104 gsts = readl(iommu->reg + DMAR_GSTS_REG);
105 if (gsts & DMA_GSTS_IRES)
106 iommu->flags |= VTD_FLAG_IRQ_REMAP_PRE_ENABLED;
109 static int alloc_irte(struct intel_iommu *iommu,
110 struct irq_2_iommu *irq_iommu, u16 count)
112 struct ir_table *table = iommu->ir_table;
113 unsigned int mask = 0;
117 if (!count || !irq_iommu)
121 count = __roundup_pow_of_two(count);
125 if (mask > ecap_max_handle_mask(iommu->ecap)) {
126 pr_err("Requested mask %x exceeds the max invalidation handle"
127 " mask value %Lx\n", mask,
128 ecap_max_handle_mask(iommu->ecap));
132 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
133 index = bitmap_find_free_region(table->bitmap,
134 INTR_REMAP_TABLE_ENTRIES, mask);
136 pr_warn("IR%d: can't allocate an IRTE\n", iommu->seq_id);
138 irq_iommu->iommu = iommu;
139 irq_iommu->irte_index = index;
140 irq_iommu->sub_handle = 0;
141 irq_iommu->irte_mask = mask;
142 irq_iommu->mode = IRQ_REMAPPING;
144 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
149 static int qi_flush_iec(struct intel_iommu *iommu, int index, int mask)
153 desc.qw0 = QI_IEC_IIDEX(index) | QI_IEC_TYPE | QI_IEC_IM(mask)
159 return qi_submit_sync(iommu, &desc, 1, 0);
162 static int modify_irte(struct irq_2_iommu *irq_iommu,
163 struct irte *irte_modified)
165 struct intel_iommu *iommu;
173 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
175 iommu = irq_iommu->iommu;
177 index = irq_iommu->irte_index + irq_iommu->sub_handle;
178 irte = &iommu->ir_table->base[index];
180 if ((irte->pst == 1) || (irte_modified->pst == 1)) {
182 * We use cmpxchg16 to atomically update the 128-bit IRTE,
183 * and it cannot be updated by the hardware or other processors
184 * behind us, so the return value of cmpxchg16 should be the
185 * same as the old value.
187 u128 old = irte->irte;
188 WARN_ON(!try_cmpxchg128(&irte->irte, &old, irte_modified->irte));
190 WRITE_ONCE(irte->low, irte_modified->low);
191 WRITE_ONCE(irte->high, irte_modified->high);
193 __iommu_flush_cache(iommu, irte, sizeof(*irte));
195 rc = qi_flush_iec(iommu, index, 0);
197 /* Update iommu mode according to the IRTE mode */
198 irq_iommu->mode = irte->pst ? IRQ_POSTING : IRQ_REMAPPING;
199 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
204 static struct intel_iommu *map_hpet_to_iommu(u8 hpet_id)
208 for (i = 0; i < MAX_HPET_TBS; i++) {
209 if (ir_hpet[i].id == hpet_id && ir_hpet[i].iommu)
210 return ir_hpet[i].iommu;
215 static struct intel_iommu *map_ioapic_to_iommu(int apic)
219 for (i = 0; i < MAX_IO_APICS; i++) {
220 if (ir_ioapic[i].id == apic && ir_ioapic[i].iommu)
221 return ir_ioapic[i].iommu;
226 static struct irq_domain *map_dev_to_ir(struct pci_dev *dev)
228 struct dmar_drhd_unit *drhd = dmar_find_matched_drhd_unit(dev);
230 return drhd ? drhd->iommu->ir_domain : NULL;
233 static int clear_entries(struct irq_2_iommu *irq_iommu)
235 struct irte *start, *entry, *end;
236 struct intel_iommu *iommu;
239 if (irq_iommu->sub_handle)
242 iommu = irq_iommu->iommu;
243 index = irq_iommu->irte_index;
245 start = iommu->ir_table->base + index;
246 end = start + (1 << irq_iommu->irte_mask);
248 for (entry = start; entry < end; entry++) {
249 WRITE_ONCE(entry->low, 0);
250 WRITE_ONCE(entry->high, 0);
252 bitmap_release_region(iommu->ir_table->bitmap, index,
253 irq_iommu->irte_mask);
255 return qi_flush_iec(iommu, index, irq_iommu->irte_mask);
259 * source validation type
261 #define SVT_NO_VERIFY 0x0 /* no verification is required */
262 #define SVT_VERIFY_SID_SQ 0x1 /* verify using SID and SQ fields */
263 #define SVT_VERIFY_BUS 0x2 /* verify bus of request-id */
266 * source-id qualifier
268 #define SQ_ALL_16 0x0 /* verify all 16 bits of request-id */
269 #define SQ_13_IGNORE_1 0x1 /* verify most significant 13 bits, ignore
270 * the third least significant bit
272 #define SQ_13_IGNORE_2 0x2 /* verify most significant 13 bits, ignore
273 * the second and third least significant bits
275 #define SQ_13_IGNORE_3 0x3 /* verify most significant 13 bits, ignore
276 * the least three significant bits
280 * set SVT, SQ and SID fields of irte to verify
281 * source ids of interrupt requests
283 static void set_irte_sid(struct irte *irte, unsigned int svt,
284 unsigned int sq, unsigned int sid)
286 if (disable_sourceid_checking)
294 * Set an IRTE to match only the bus number. Interrupt requests that reference
295 * this IRTE must have a requester-id whose bus number is between or equal
296 * to the start_bus and end_bus arguments.
298 static void set_irte_verify_bus(struct irte *irte, unsigned int start_bus,
299 unsigned int end_bus)
301 set_irte_sid(irte, SVT_VERIFY_BUS, SQ_ALL_16,
302 (start_bus << 8) | end_bus);
305 static int set_ioapic_sid(struct irte *irte, int apic)
313 for (i = 0; i < MAX_IO_APICS; i++) {
314 if (ir_ioapic[i].iommu && ir_ioapic[i].id == apic) {
315 sid = (ir_ioapic[i].bus << 8) | ir_ioapic[i].devfn;
321 pr_warn("Failed to set source-id of IOAPIC (%d)\n", apic);
325 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, sid);
330 static int set_hpet_sid(struct irte *irte, u8 id)
338 for (i = 0; i < MAX_HPET_TBS; i++) {
339 if (ir_hpet[i].iommu && ir_hpet[i].id == id) {
340 sid = (ir_hpet[i].bus << 8) | ir_hpet[i].devfn;
346 pr_warn("Failed to set source-id of HPET block (%d)\n", id);
351 * Should really use SQ_ALL_16. Some platforms are broken.
352 * While we figure out the right quirks for these broken platforms, use
353 * SQ_13_IGNORE_3 for now.
355 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_13_IGNORE_3, sid);
360 struct set_msi_sid_data {
361 struct pci_dev *pdev;
367 static int set_msi_sid_cb(struct pci_dev *pdev, u16 alias, void *opaque)
369 struct set_msi_sid_data *data = opaque;
371 if (data->count == 0 || PCI_BUS_NUM(alias) == PCI_BUS_NUM(data->alias))
372 data->busmatch_count++;
381 static int set_msi_sid(struct irte *irte, struct pci_dev *dev)
383 struct set_msi_sid_data data;
389 data.busmatch_count = 0;
390 pci_for_each_dma_alias(dev, set_msi_sid_cb, &data);
393 * DMA alias provides us with a PCI device and alias. The only case
394 * where the it will return an alias on a different bus than the
395 * device is the case of a PCIe-to-PCI bridge, where the alias is for
396 * the subordinate bus. In this case we can only verify the bus.
398 * If there are multiple aliases, all with the same bus number,
399 * then all we can do is verify the bus. This is typical in NTB
400 * hardware which use proxy IDs where the device will generate traffic
401 * from multiple devfn numbers on the same bus.
403 * If the alias device is on a different bus than our source device
404 * then we have a topology based alias, use it.
406 * Otherwise, the alias is for a device DMA quirk and we cannot
407 * assume that MSI uses the same requester ID. Therefore use the
410 if (PCI_BUS_NUM(data.alias) != data.pdev->bus->number)
411 set_irte_verify_bus(irte, PCI_BUS_NUM(data.alias),
413 else if (data.count >= 2 && data.busmatch_count == data.count)
414 set_irte_verify_bus(irte, dev->bus->number, dev->bus->number);
415 else if (data.pdev->bus->number != dev->bus->number)
416 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16, data.alias);
418 set_irte_sid(irte, SVT_VERIFY_SID_SQ, SQ_ALL_16,
424 static int iommu_load_old_irte(struct intel_iommu *iommu)
426 struct irte *old_ir_table;
427 phys_addr_t irt_phys;
432 /* Check whether the old ir-table has the same size as ours */
433 irta = dmar_readq(iommu->reg + DMAR_IRTA_REG);
434 if ((irta & INTR_REMAP_TABLE_REG_SIZE_MASK)
435 != INTR_REMAP_TABLE_REG_SIZE)
438 irt_phys = irta & VTD_PAGE_MASK;
439 size = INTR_REMAP_TABLE_ENTRIES*sizeof(struct irte);
441 /* Map the old IR table */
442 old_ir_table = memremap(irt_phys, size, MEMREMAP_WB);
447 memcpy(iommu->ir_table->base, old_ir_table, size);
449 __iommu_flush_cache(iommu, iommu->ir_table->base, size);
452 * Now check the table for used entries and mark those as
453 * allocated in the bitmap
455 for (i = 0; i < INTR_REMAP_TABLE_ENTRIES; i++) {
456 if (iommu->ir_table->base[i].present)
457 bitmap_set(iommu->ir_table->bitmap, i, 1);
460 memunmap(old_ir_table);
466 static void iommu_set_irq_remapping(struct intel_iommu *iommu, int mode)
472 addr = virt_to_phys((void *)iommu->ir_table->base);
474 raw_spin_lock_irqsave(&iommu->register_lock, flags);
476 dmar_writeq(iommu->reg + DMAR_IRTA_REG,
477 (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
479 /* Set interrupt-remapping table pointer */
480 writel(iommu->gcmd | DMA_GCMD_SIRTP, iommu->reg + DMAR_GCMD_REG);
482 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
483 readl, (sts & DMA_GSTS_IRTPS), sts);
484 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
487 * Global invalidation of interrupt entry cache to make sure the
488 * hardware uses the new irq remapping table.
490 if (!cap_esirtps(iommu->cap))
491 qi_global_iec(iommu);
494 static void iommu_enable_irq_remapping(struct intel_iommu *iommu)
499 raw_spin_lock_irqsave(&iommu->register_lock, flags);
501 /* Enable interrupt-remapping */
502 iommu->gcmd |= DMA_GCMD_IRE;
503 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
504 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
505 readl, (sts & DMA_GSTS_IRES), sts);
507 /* Block compatibility-format MSIs */
508 if (sts & DMA_GSTS_CFIS) {
509 iommu->gcmd &= ~DMA_GCMD_CFI;
510 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
511 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
512 readl, !(sts & DMA_GSTS_CFIS), sts);
516 * With CFI clear in the Global Command register, we should be
517 * protected from dangerous (i.e. compatibility) interrupts
518 * regardless of x2apic status. Check just to be sure.
520 if (sts & DMA_GSTS_CFIS)
522 "Compatibility-format IRQs enabled despite intr remapping;\n"
523 "you are vulnerable to IRQ injection.\n");
525 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
528 static int intel_setup_irq_remapping(struct intel_iommu *iommu)
530 struct ir_table *ir_table;
531 struct fwnode_handle *fn;
532 unsigned long *bitmap;
538 ir_table = kzalloc(sizeof(struct ir_table), GFP_KERNEL);
542 ir_table_base = iommu_alloc_pages_node(iommu->node, GFP_KERNEL,
543 INTR_REMAP_PAGE_ORDER);
544 if (!ir_table_base) {
545 pr_err("IR%d: failed to allocate pages of order %d\n",
546 iommu->seq_id, INTR_REMAP_PAGE_ORDER);
550 bitmap = bitmap_zalloc(INTR_REMAP_TABLE_ENTRIES, GFP_KERNEL);
551 if (bitmap == NULL) {
552 pr_err("IR%d: failed to allocate bitmap\n", iommu->seq_id);
556 fn = irq_domain_alloc_named_id_fwnode("INTEL-IR", iommu->seq_id);
558 goto out_free_bitmap;
561 irq_domain_create_hierarchy(arch_get_ir_parent_domain(),
562 0, INTR_REMAP_TABLE_ENTRIES,
563 fn, &intel_ir_domain_ops,
565 if (!iommu->ir_domain) {
566 pr_err("IR%d: failed to allocate irqdomain\n", iommu->seq_id);
567 goto out_free_fwnode;
570 irq_domain_update_bus_token(iommu->ir_domain, DOMAIN_BUS_DMAR);
571 iommu->ir_domain->flags |= IRQ_DOMAIN_FLAG_MSI_PARENT |
572 IRQ_DOMAIN_FLAG_ISOLATED_MSI;
574 if (cap_caching_mode(iommu->cap))
575 iommu->ir_domain->msi_parent_ops = &virt_dmar_msi_parent_ops;
577 iommu->ir_domain->msi_parent_ops = &dmar_msi_parent_ops;
579 ir_table->base = ir_table_base;
580 ir_table->bitmap = bitmap;
581 iommu->ir_table = ir_table;
584 * If the queued invalidation is already initialized,
585 * shouldn't disable it.
589 * Clear previous faults.
591 dmar_fault(-1, iommu);
592 dmar_disable_qi(iommu);
594 if (dmar_enable_qi(iommu)) {
595 pr_err("Failed to enable queued invalidation\n");
596 goto out_free_ir_domain;
600 init_ir_status(iommu);
602 if (ir_pre_enabled(iommu)) {
603 if (!is_kdump_kernel()) {
604 pr_warn("IRQ remapping was enabled on %s but we are not in kdump mode\n",
606 clear_ir_pre_enabled(iommu);
607 iommu_disable_irq_remapping(iommu);
608 } else if (iommu_load_old_irte(iommu))
609 pr_err("Failed to copy IR table for %s from previous kernel\n",
612 pr_info("Copied IR table for %s from previous kernel\n",
616 iommu_set_irq_remapping(iommu, eim_mode);
621 irq_domain_remove(iommu->ir_domain);
622 iommu->ir_domain = NULL;
624 irq_domain_free_fwnode(fn);
628 iommu_free_pages(ir_table_base, INTR_REMAP_PAGE_ORDER);
632 iommu->ir_table = NULL;
637 static void intel_teardown_irq_remapping(struct intel_iommu *iommu)
639 struct fwnode_handle *fn;
641 if (iommu && iommu->ir_table) {
642 if (iommu->ir_domain) {
643 fn = iommu->ir_domain->fwnode;
645 irq_domain_remove(iommu->ir_domain);
646 irq_domain_free_fwnode(fn);
647 iommu->ir_domain = NULL;
649 iommu_free_pages(iommu->ir_table->base, INTR_REMAP_PAGE_ORDER);
650 bitmap_free(iommu->ir_table->bitmap);
651 kfree(iommu->ir_table);
652 iommu->ir_table = NULL;
657 * Disable Interrupt Remapping.
659 static void iommu_disable_irq_remapping(struct intel_iommu *iommu)
664 if (!ecap_ir_support(iommu->ecap))
668 * global invalidation of interrupt entry cache before disabling
669 * interrupt-remapping.
671 if (!cap_esirtps(iommu->cap))
672 qi_global_iec(iommu);
674 raw_spin_lock_irqsave(&iommu->register_lock, flags);
676 sts = readl(iommu->reg + DMAR_GSTS_REG);
677 if (!(sts & DMA_GSTS_IRES))
680 iommu->gcmd &= ~DMA_GCMD_IRE;
681 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
683 IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
684 readl, !(sts & DMA_GSTS_IRES), sts);
687 raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
690 static int __init dmar_x2apic_optout(void)
692 struct acpi_table_dmar *dmar;
693 dmar = (struct acpi_table_dmar *)dmar_tbl;
694 if (!dmar || no_x2apic_optout)
696 return dmar->flags & DMAR_X2APIC_OPT_OUT;
699 static void __init intel_cleanup_irq_remapping(void)
701 struct dmar_drhd_unit *drhd;
702 struct intel_iommu *iommu;
704 for_each_iommu(iommu, drhd) {
705 if (ecap_ir_support(iommu->ecap)) {
706 iommu_disable_irq_remapping(iommu);
707 intel_teardown_irq_remapping(iommu);
711 if (x2apic_supported())
712 pr_warn("Failed to enable irq remapping. You are vulnerable to irq-injection attacks.\n");
715 static int __init intel_prepare_irq_remapping(void)
717 struct dmar_drhd_unit *drhd;
718 struct intel_iommu *iommu;
721 if (irq_remap_broken) {
722 pr_warn("This system BIOS has enabled interrupt remapping\n"
723 "on a chipset that contains an erratum making that\n"
724 "feature unstable. To maintain system stability\n"
725 "interrupt remapping is being disabled. Please\n"
726 "contact your BIOS vendor for an update\n");
727 add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
731 if (dmar_table_init() < 0)
734 if (intel_cap_audit(CAP_AUDIT_STATIC_IRQR, NULL))
737 if (!dmar_ir_support())
740 if (parse_ioapics_under_ir()) {
741 pr_info("Not enabling interrupt remapping\n");
745 /* First make sure all IOMMUs support IRQ remapping */
746 for_each_iommu(iommu, drhd)
747 if (!ecap_ir_support(iommu->ecap))
750 /* Detect remapping mode: lapic or x2apic */
751 if (x2apic_supported()) {
752 eim = !dmar_x2apic_optout();
754 pr_info("x2apic is disabled because BIOS sets x2apic opt out bit.");
755 pr_info("Use 'intremap=no_x2apic_optout' to override the BIOS setting.\n");
759 for_each_iommu(iommu, drhd) {
760 if (eim && !ecap_eim_support(iommu->ecap)) {
761 pr_info("%s does not support EIM\n", iommu->name);
768 pr_info("Queued invalidation will be enabled to support x2apic and Intr-remapping.\n");
770 /* Do the initializations early */
771 for_each_iommu(iommu, drhd) {
772 if (intel_setup_irq_remapping(iommu)) {
773 pr_err("Failed to setup irq remapping for %s\n",
782 intel_cleanup_irq_remapping();
787 * Set Posted-Interrupts capability.
789 static inline void set_irq_posting_cap(void)
791 struct dmar_drhd_unit *drhd;
792 struct intel_iommu *iommu;
794 if (!disable_irq_post) {
796 * If IRTE is in posted format, the 'pda' field goes across the
797 * 64-bit boundary, we need use cmpxchg16b to atomically update
798 * it. We only expose posted-interrupt when X86_FEATURE_CX16
799 * is supported. Actually, hardware platforms supporting PI
800 * should have X86_FEATURE_CX16 support, this has been confirmed
801 * with Intel hardware guys.
803 if (boot_cpu_has(X86_FEATURE_CX16))
804 intel_irq_remap_ops.capability |= 1 << IRQ_POSTING_CAP;
806 for_each_iommu(iommu, drhd)
807 if (!cap_pi_support(iommu->cap)) {
808 intel_irq_remap_ops.capability &=
809 ~(1 << IRQ_POSTING_CAP);
815 static int __init intel_enable_irq_remapping(void)
817 struct dmar_drhd_unit *drhd;
818 struct intel_iommu *iommu;
822 * Setup Interrupt-remapping for all the DRHD's now.
824 for_each_iommu(iommu, drhd) {
825 if (!ir_pre_enabled(iommu))
826 iommu_enable_irq_remapping(iommu);
833 irq_remapping_enabled = 1;
835 set_irq_posting_cap();
837 pr_info("Enabled IRQ remapping in %s mode\n", eim_mode ? "x2apic" : "xapic");
839 return eim_mode ? IRQ_REMAP_X2APIC_MODE : IRQ_REMAP_XAPIC_MODE;
842 intel_cleanup_irq_remapping();
846 static int ir_parse_one_hpet_scope(struct acpi_dmar_device_scope *scope,
847 struct intel_iommu *iommu,
848 struct acpi_dmar_hardware_unit *drhd)
850 struct acpi_dmar_pci_path *path;
852 int count, free = -1;
855 path = (struct acpi_dmar_pci_path *)(scope + 1);
856 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
857 / sizeof(struct acpi_dmar_pci_path);
859 while (--count > 0) {
861 * Access PCI directly due to the PCI
862 * subsystem isn't initialized yet.
864 bus = read_pci_config_byte(bus, path->device, path->function,
869 for (count = 0; count < MAX_HPET_TBS; count++) {
870 if (ir_hpet[count].iommu == iommu &&
871 ir_hpet[count].id == scope->enumeration_id)
873 else if (ir_hpet[count].iommu == NULL && free == -1)
877 pr_warn("Exceeded Max HPET blocks\n");
881 ir_hpet[free].iommu = iommu;
882 ir_hpet[free].id = scope->enumeration_id;
883 ir_hpet[free].bus = bus;
884 ir_hpet[free].devfn = PCI_DEVFN(path->device, path->function);
885 pr_info("HPET id %d under DRHD base 0x%Lx\n",
886 scope->enumeration_id, drhd->address);
891 static int ir_parse_one_ioapic_scope(struct acpi_dmar_device_scope *scope,
892 struct intel_iommu *iommu,
893 struct acpi_dmar_hardware_unit *drhd)
895 struct acpi_dmar_pci_path *path;
897 int count, free = -1;
900 path = (struct acpi_dmar_pci_path *)(scope + 1);
901 count = (scope->length - sizeof(struct acpi_dmar_device_scope))
902 / sizeof(struct acpi_dmar_pci_path);
904 while (--count > 0) {
906 * Access PCI directly due to the PCI
907 * subsystem isn't initialized yet.
909 bus = read_pci_config_byte(bus, path->device, path->function,
914 for (count = 0; count < MAX_IO_APICS; count++) {
915 if (ir_ioapic[count].iommu == iommu &&
916 ir_ioapic[count].id == scope->enumeration_id)
918 else if (ir_ioapic[count].iommu == NULL && free == -1)
922 pr_warn("Exceeded Max IO APICS\n");
926 ir_ioapic[free].bus = bus;
927 ir_ioapic[free].devfn = PCI_DEVFN(path->device, path->function);
928 ir_ioapic[free].iommu = iommu;
929 ir_ioapic[free].id = scope->enumeration_id;
930 pr_info("IOAPIC id %d under DRHD base 0x%Lx IOMMU %d\n",
931 scope->enumeration_id, drhd->address, iommu->seq_id);
936 static int ir_parse_ioapic_hpet_scope(struct acpi_dmar_header *header,
937 struct intel_iommu *iommu)
940 struct acpi_dmar_hardware_unit *drhd;
941 struct acpi_dmar_device_scope *scope;
944 drhd = (struct acpi_dmar_hardware_unit *)header;
945 start = (void *)(drhd + 1);
946 end = ((void *)drhd) + header->length;
948 while (start < end && ret == 0) {
950 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_IOAPIC)
951 ret = ir_parse_one_ioapic_scope(scope, iommu, drhd);
952 else if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_HPET)
953 ret = ir_parse_one_hpet_scope(scope, iommu, drhd);
954 start += scope->length;
960 static void ir_remove_ioapic_hpet_scope(struct intel_iommu *iommu)
964 for (i = 0; i < MAX_HPET_TBS; i++)
965 if (ir_hpet[i].iommu == iommu)
966 ir_hpet[i].iommu = NULL;
968 for (i = 0; i < MAX_IO_APICS; i++)
969 if (ir_ioapic[i].iommu == iommu)
970 ir_ioapic[i].iommu = NULL;
974 * Finds the assocaition between IOAPIC's and its Interrupt-remapping
977 static int __init parse_ioapics_under_ir(void)
979 struct dmar_drhd_unit *drhd;
980 struct intel_iommu *iommu;
981 bool ir_supported = false;
984 for_each_iommu(iommu, drhd) {
987 if (!ecap_ir_support(iommu->ecap))
990 ret = ir_parse_ioapic_hpet_scope(drhd->hdr, iommu);
1000 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
1001 int ioapic_id = mpc_ioapic_id(ioapic_idx);
1002 if (!map_ioapic_to_iommu(ioapic_id)) {
1003 pr_err(FW_BUG "ioapic %d has no mapping iommu, "
1004 "interrupt remapping will be disabled\n",
1013 static int __init ir_dev_scope_init(void)
1017 if (!irq_remapping_enabled)
1020 down_write(&dmar_global_lock);
1021 ret = dmar_dev_scope_init();
1022 up_write(&dmar_global_lock);
1026 rootfs_initcall(ir_dev_scope_init);
1028 static void disable_irq_remapping(void)
1030 struct dmar_drhd_unit *drhd;
1031 struct intel_iommu *iommu = NULL;
1034 * Disable Interrupt-remapping for all the DRHD's now.
1036 for_each_iommu(iommu, drhd) {
1037 if (!ecap_ir_support(iommu->ecap))
1040 iommu_disable_irq_remapping(iommu);
1044 * Clear Posted-Interrupts capability.
1046 if (!disable_irq_post)
1047 intel_irq_remap_ops.capability &= ~(1 << IRQ_POSTING_CAP);
1050 static int reenable_irq_remapping(int eim)
1052 struct dmar_drhd_unit *drhd;
1054 struct intel_iommu *iommu = NULL;
1056 for_each_iommu(iommu, drhd)
1058 dmar_reenable_qi(iommu);
1061 * Setup Interrupt-remapping for all the DRHD's now.
1063 for_each_iommu(iommu, drhd) {
1064 if (!ecap_ir_support(iommu->ecap))
1067 /* Set up interrupt remapping for iommu.*/
1068 iommu_set_irq_remapping(iommu, eim);
1069 iommu_enable_irq_remapping(iommu);
1076 set_irq_posting_cap();
1082 * handle error condition gracefully here!
1088 * Store the MSI remapping domain pointer in the device if enabled.
1090 * This is called from dmar_pci_bus_add_dev() so it works even when DMA
1091 * remapping is disabled. Only update the pointer if the device is not
1092 * already handled by a non default PCI/MSI interrupt domain. This protects
1095 void intel_irq_remap_add_device(struct dmar_pci_notify_info *info)
1097 if (!irq_remapping_enabled || !pci_dev_has_default_msi_parent_domain(info->dev))
1100 dev_set_msi_domain(&info->dev->dev, map_dev_to_ir(info->dev));
1103 static void prepare_irte(struct irte *irte, int vector, unsigned int dest)
1105 memset(irte, 0, sizeof(*irte));
1108 irte->dst_mode = apic->dest_mode_logical;
1110 * Trigger mode in the IRTE will always be edge, and for IO-APIC, the
1111 * actual level or edge trigger will be setup in the IO-APIC
1112 * RTE. This will help simplify level triggered irq migration.
1113 * For more details, see the comments (in io_apic.c) explainig IO-APIC
1114 * irq migration in the presence of interrupt-remapping.
1116 irte->trigger_mode = 0;
1117 irte->dlvry_mode = APIC_DELIVERY_MODE_FIXED;
1118 irte->vector = vector;
1119 irte->dest_id = IRTE_DEST(dest);
1120 irte->redir_hint = 1;
1123 static void prepare_irte_posted(struct irte *irte)
1125 memset(irte, 0, sizeof(*irte));
1131 struct irq_remap_ops intel_irq_remap_ops = {
1132 .prepare = intel_prepare_irq_remapping,
1133 .enable = intel_enable_irq_remapping,
1134 .disable = disable_irq_remapping,
1135 .reenable = reenable_irq_remapping,
1136 .enable_faulting = enable_drhd_fault_handling,
1139 #ifdef CONFIG_X86_POSTED_MSI
1141 static phys_addr_t get_pi_desc_addr(struct irq_data *irqd)
1143 int cpu = cpumask_first(irq_data_get_effective_affinity_mask(irqd));
1145 if (WARN_ON(cpu >= nr_cpu_ids))
1148 return __pa(per_cpu_ptr(&posted_msi_pi_desc, cpu));
1151 static void intel_ir_reconfigure_irte_posted(struct irq_data *irqd)
1153 struct intel_ir_data *ir_data = irqd->chip_data;
1154 struct irte *irte = &ir_data->irte_entry;
1155 struct irte irte_pi;
1158 pid_addr = get_pi_desc_addr(irqd);
1161 pr_warn("Failed to setup IRQ %d for posted mode", irqd->irq);
1165 memset(&irte_pi, 0, sizeof(irte_pi));
1167 /* The shared IRTE already be set up as posted during alloc_irte */
1168 dmar_copy_shared_irte(&irte_pi, irte);
1170 irte_pi.pda_l = (pid_addr >> (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1171 irte_pi.pda_h = (pid_addr >> 32) & ~(-1UL << PDA_HIGH_BIT);
1173 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1177 static inline void intel_ir_reconfigure_irte_posted(struct irq_data *irqd) {}
1180 static void intel_ir_reconfigure_irte(struct irq_data *irqd, bool force)
1182 struct intel_ir_data *ir_data = irqd->chip_data;
1183 struct irte *irte = &ir_data->irte_entry;
1184 struct irq_cfg *cfg = irqd_cfg(irqd);
1187 * Atomically updates the IRTE with the new destination, vector
1188 * and flushes the interrupt entry cache.
1190 irte->vector = cfg->vector;
1191 irte->dest_id = IRTE_DEST(cfg->dest_apicid);
1193 if (ir_data->irq_2_iommu.posted_msi)
1194 intel_ir_reconfigure_irte_posted(irqd);
1195 else if (force || ir_data->irq_2_iommu.mode == IRQ_REMAPPING)
1196 modify_irte(&ir_data->irq_2_iommu, irte);
1200 * Migrate the IO-APIC irq in the presence of intr-remapping.
1202 * For both level and edge triggered, irq migration is a simple atomic
1203 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
1205 * For level triggered, we eliminate the io-apic RTE modification (with the
1206 * updated vector information), by using a virtual vector (io-apic pin number).
1207 * Real vector that is used for interrupting cpu will be coming from
1208 * the interrupt-remapping table entry.
1210 * As the migration is a simple atomic update of IRTE, the same mechanism
1211 * is used to migrate MSI irq's in the presence of interrupt-remapping.
1214 intel_ir_set_affinity(struct irq_data *data, const struct cpumask *mask,
1217 struct irq_data *parent = data->parent_data;
1218 struct irq_cfg *cfg = irqd_cfg(data);
1221 ret = parent->chip->irq_set_affinity(parent, mask, force);
1222 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
1225 intel_ir_reconfigure_irte(data, false);
1227 * After this point, all the interrupts will start arriving
1228 * at the new destination. So, time to cleanup the previous
1229 * vector allocation.
1231 vector_schedule_cleanup(cfg);
1233 return IRQ_SET_MASK_OK_DONE;
1236 static void intel_ir_compose_msi_msg(struct irq_data *irq_data,
1237 struct msi_msg *msg)
1239 struct intel_ir_data *ir_data = irq_data->chip_data;
1241 *msg = ir_data->msi_entry;
1244 static int intel_ir_set_vcpu_affinity(struct irq_data *data, void *info)
1246 struct intel_ir_data *ir_data = data->chip_data;
1247 struct vcpu_data *vcpu_pi_info = info;
1249 /* stop posting interrupts, back to the default mode */
1250 if (!vcpu_pi_info) {
1251 modify_irte(&ir_data->irq_2_iommu, &ir_data->irte_entry);
1253 struct irte irte_pi;
1256 * We are not caching the posted interrupt entry. We
1257 * copy the data from the remapped entry and modify
1258 * the fields which are relevant for posted mode. The
1259 * cached remapped entry is used for switching back to
1262 memset(&irte_pi, 0, sizeof(irte_pi));
1263 dmar_copy_shared_irte(&irte_pi, &ir_data->irte_entry);
1265 /* Update the posted mode fields */
1267 irte_pi.p_urgent = 0;
1268 irte_pi.p_vector = vcpu_pi_info->vector;
1269 irte_pi.pda_l = (vcpu_pi_info->pi_desc_addr >>
1270 (32 - PDA_LOW_BIT)) & ~(-1UL << PDA_LOW_BIT);
1271 irte_pi.pda_h = (vcpu_pi_info->pi_desc_addr >> 32) &
1272 ~(-1UL << PDA_HIGH_BIT);
1274 modify_irte(&ir_data->irq_2_iommu, &irte_pi);
1280 static struct irq_chip intel_ir_chip = {
1282 .irq_ack = apic_ack_irq,
1283 .irq_set_affinity = intel_ir_set_affinity,
1284 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1285 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1289 * With posted MSIs, all vectors are multiplexed into a single notification
1290 * vector. Devices MSIs are then dispatched in a demux loop where
1291 * EOIs can be coalesced as well.
1293 * "INTEL-IR-POST" IRQ chip does not do EOI on ACK, thus the dummy irq_ack()
1294 * function. Instead EOI is performed by the posted interrupt notification
1297 * For the example below, 3 MSIs are coalesced into one CPU notification. Only
1298 * one apic_eoi() is needed.
1300 * __sysvec_posted_msi_notification()
1303 * irq_chip_ack_parent()
1304 * dummy(); // No EOI
1305 * handle_irq_event()
1308 * irq_chip_ack_parent()
1309 * dummy(); // No EOI
1310 * handle_irq_event()
1313 * irq_chip_ack_parent()
1314 * dummy(); // No EOI
1315 * handle_irq_event()
1321 static void dummy_ack(struct irq_data *d) { }
1323 static struct irq_chip intel_ir_chip_post_msi = {
1324 .name = "INTEL-IR-POST",
1325 .irq_ack = dummy_ack,
1326 .irq_set_affinity = intel_ir_set_affinity,
1327 .irq_compose_msi_msg = intel_ir_compose_msi_msg,
1328 .irq_set_vcpu_affinity = intel_ir_set_vcpu_affinity,
1331 static void fill_msi_msg(struct msi_msg *msg, u32 index, u32 subhandle)
1333 memset(msg, 0, sizeof(*msg));
1335 msg->arch_addr_lo.dmar_base_address = X86_MSI_BASE_ADDRESS_LOW;
1336 msg->arch_addr_lo.dmar_subhandle_valid = true;
1337 msg->arch_addr_lo.dmar_format = true;
1338 msg->arch_addr_lo.dmar_index_0_14 = index & 0x7FFF;
1339 msg->arch_addr_lo.dmar_index_15 = !!(index & 0x8000);
1341 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
1343 msg->arch_data.dmar_subhandle = subhandle;
1346 static void intel_irq_remapping_prepare_irte(struct intel_ir_data *data,
1347 struct irq_cfg *irq_cfg,
1348 struct irq_alloc_info *info,
1349 int index, int sub_handle)
1351 struct irte *irte = &data->irte_entry;
1353 prepare_irte(irte, irq_cfg->vector, irq_cfg->dest_apicid);
1355 switch (info->type) {
1356 case X86_IRQ_ALLOC_TYPE_IOAPIC:
1357 /* Set source-id of interrupt request */
1358 set_ioapic_sid(irte, info->devid);
1359 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: Set IRTE entry (P:%d FPD:%d Dst_Mode:%d Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X Avail:%X Vector:%02X Dest:%08X SID:%04X SQ:%X SVT:%X)\n",
1360 info->devid, irte->present, irte->fpd,
1361 irte->dst_mode, irte->redir_hint,
1362 irte->trigger_mode, irte->dlvry_mode,
1363 irte->avail, irte->vector, irte->dest_id,
1364 irte->sid, irte->sq, irte->svt);
1365 sub_handle = info->ioapic.pin;
1367 case X86_IRQ_ALLOC_TYPE_HPET:
1368 set_hpet_sid(irte, info->devid);
1370 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
1371 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
1372 if (posted_msi_supported()) {
1373 prepare_irte_posted(irte);
1374 data->irq_2_iommu.posted_msi = 1;
1378 pci_real_dma_dev(msi_desc_to_pci_dev(info->desc)));
1384 fill_msi_msg(&data->msi_entry, index, sub_handle);
1387 static void intel_free_irq_resources(struct irq_domain *domain,
1388 unsigned int virq, unsigned int nr_irqs)
1390 struct irq_data *irq_data;
1391 struct intel_ir_data *data;
1392 struct irq_2_iommu *irq_iommu;
1393 unsigned long flags;
1395 for (i = 0; i < nr_irqs; i++) {
1396 irq_data = irq_domain_get_irq_data(domain, virq + i);
1397 if (irq_data && irq_data->chip_data) {
1398 data = irq_data->chip_data;
1399 irq_iommu = &data->irq_2_iommu;
1400 raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
1401 clear_entries(irq_iommu);
1402 raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
1403 irq_domain_reset_irq_data(irq_data);
1409 static int intel_irq_remapping_alloc(struct irq_domain *domain,
1410 unsigned int virq, unsigned int nr_irqs,
1413 struct intel_iommu *iommu = domain->host_data;
1414 struct irq_alloc_info *info = arg;
1415 struct intel_ir_data *data, *ird;
1416 struct irq_data *irq_data;
1417 struct irq_cfg *irq_cfg;
1420 if (!info || !iommu)
1422 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI)
1425 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
1430 data = kzalloc(sizeof(*data), GFP_KERNEL);
1432 goto out_free_parent;
1434 index = alloc_irte(iommu, &data->irq_2_iommu, nr_irqs);
1436 pr_warn("Failed to allocate IRTE\n");
1438 goto out_free_parent;
1441 for (i = 0; i < nr_irqs; i++) {
1442 irq_data = irq_domain_get_irq_data(domain, virq + i);
1443 irq_cfg = irqd_cfg(irq_data);
1444 if (!irq_data || !irq_cfg) {
1452 ird = kzalloc(sizeof(*ird), GFP_KERNEL);
1455 /* Initialize the common data */
1456 ird->irq_2_iommu = data->irq_2_iommu;
1457 ird->irq_2_iommu.sub_handle = i;
1462 irq_data->hwirq = (index << 16) + i;
1463 irq_data->chip_data = ird;
1464 if (posted_msi_supported() &&
1465 ((info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI) ||
1466 (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX)))
1467 irq_data->chip = &intel_ir_chip_post_msi;
1469 irq_data->chip = &intel_ir_chip;
1470 intel_irq_remapping_prepare_irte(ird, irq_cfg, info, index, i);
1471 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
1476 intel_free_irq_resources(domain, virq, i);
1478 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1482 static void intel_irq_remapping_free(struct irq_domain *domain,
1483 unsigned int virq, unsigned int nr_irqs)
1485 intel_free_irq_resources(domain, virq, nr_irqs);
1486 irq_domain_free_irqs_common(domain, virq, nr_irqs);
1489 static int intel_irq_remapping_activate(struct irq_domain *domain,
1490 struct irq_data *irq_data, bool reserve)
1492 intel_ir_reconfigure_irte(irq_data, true);
1496 static void intel_irq_remapping_deactivate(struct irq_domain *domain,
1497 struct irq_data *irq_data)
1499 struct intel_ir_data *data = irq_data->chip_data;
1502 memset(&entry, 0, sizeof(entry));
1503 modify_irte(&data->irq_2_iommu, &entry);
1506 static int intel_irq_remapping_select(struct irq_domain *d,
1507 struct irq_fwspec *fwspec,
1508 enum irq_domain_bus_token bus_token)
1510 struct intel_iommu *iommu = NULL;
1512 if (x86_fwspec_is_ioapic(fwspec))
1513 iommu = map_ioapic_to_iommu(fwspec->param[0]);
1514 else if (x86_fwspec_is_hpet(fwspec))
1515 iommu = map_hpet_to_iommu(fwspec->param[0]);
1517 return iommu && d == iommu->ir_domain;
1520 static const struct irq_domain_ops intel_ir_domain_ops = {
1521 .select = intel_irq_remapping_select,
1522 .alloc = intel_irq_remapping_alloc,
1523 .free = intel_irq_remapping_free,
1524 .activate = intel_irq_remapping_activate,
1525 .deactivate = intel_irq_remapping_deactivate,
1528 static const struct msi_parent_ops dmar_msi_parent_ops = {
1529 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED |
1530 MSI_FLAG_MULTI_PCI_MSI |
1533 .init_dev_msi_info = msi_parent_init_dev_msi_info,
1536 static const struct msi_parent_ops virt_dmar_msi_parent_ops = {
1537 .supported_flags = X86_VECTOR_MSI_FLAGS_SUPPORTED |
1538 MSI_FLAG_MULTI_PCI_MSI,
1540 .init_dev_msi_info = msi_parent_init_dev_msi_info,
1544 * Support of Interrupt Remapping Unit Hotplug
1546 static int dmar_ir_add(struct dmar_drhd_unit *dmaru, struct intel_iommu *iommu)
1549 int eim = x2apic_enabled();
1551 ret = intel_cap_audit(CAP_AUDIT_HOTPLUG_IRQR, iommu);
1555 if (eim && !ecap_eim_support(iommu->ecap)) {
1556 pr_info("DRHD %Lx: EIM not supported by DRHD, ecap %Lx\n",
1557 iommu->reg_phys, iommu->ecap);
1561 if (ir_parse_ioapic_hpet_scope(dmaru->hdr, iommu)) {
1562 pr_warn("DRHD %Lx: failed to parse managed IOAPIC/HPET\n",
1567 /* TODO: check all IOAPICs are covered by IOMMU */
1569 /* Setup Interrupt-remapping now. */
1570 ret = intel_setup_irq_remapping(iommu);
1572 pr_err("Failed to setup irq remapping for %s\n",
1574 intel_teardown_irq_remapping(iommu);
1575 ir_remove_ioapic_hpet_scope(iommu);
1577 iommu_enable_irq_remapping(iommu);
1583 int dmar_ir_hotplug(struct dmar_drhd_unit *dmaru, bool insert)
1586 struct intel_iommu *iommu = dmaru->iommu;
1588 if (!irq_remapping_enabled)
1592 if (!ecap_ir_support(iommu->ecap))
1594 if (irq_remapping_cap(IRQ_POSTING_CAP) &&
1595 !cap_pi_support(iommu->cap))
1599 if (!iommu->ir_table)
1600 ret = dmar_ir_add(dmaru, iommu);
1602 if (iommu->ir_table) {
1603 if (!bitmap_empty(iommu->ir_table->bitmap,
1604 INTR_REMAP_TABLE_ENTRIES)) {
1607 iommu_disable_irq_remapping(iommu);
1608 intel_teardown_irq_remapping(iommu);
1609 ir_remove_ioapic_hpet_scope(iommu);