1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-map-ops.h>
22 #include <linux/dma-direct.h>
23 #include <linux/dma-iommu.h>
24 #include <linux/iommu-helper.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/irqdomain.h>
32 #include <linux/percpu.h>
33 #include <linux/iova.h>
34 #include <linux/io-pgtable.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/proto.h>
40 #include <asm/iommu.h>
44 #include "amd_iommu.h"
45 #include "../irq_remapping.h"
47 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
49 #define LOOP_TIMEOUT 100000
51 /* IO virtual address start page frame number */
52 #define IOVA_START_PFN (1)
53 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
55 /* Reserved IOVA ranges */
56 #define MSI_RANGE_START (0xfee00000)
57 #define MSI_RANGE_END (0xfeefffff)
58 #define HT_RANGE_START (0xfd00000000ULL)
59 #define HT_RANGE_END (0xffffffffffULL)
61 #define DEFAULT_PGTABLE_LEVEL PAGE_MODE_3_LEVEL
63 static DEFINE_SPINLOCK(pd_bitmap_lock);
65 /* List of all available dev_data structures */
66 static LLIST_HEAD(dev_data_list);
68 LIST_HEAD(ioapic_map);
70 LIST_HEAD(acpihid_map);
73 * Domain for untranslated devices - only allocated
74 * if iommu=pt passed on kernel cmd line.
76 const struct iommu_ops amd_iommu_ops;
78 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
79 int amd_iommu_max_glx_val = -1;
82 * general struct to manage commands send to an IOMMU
88 struct kmem_cache *amd_iommu_irq_cache;
90 static void detach_device(struct device *dev);
92 /****************************************************************************
96 ****************************************************************************/
98 static inline u16 get_pci_device_id(struct device *dev)
100 struct pci_dev *pdev = to_pci_dev(dev);
102 return pci_dev_id(pdev);
105 static inline int get_acpihid_device_id(struct device *dev,
106 struct acpihid_map_entry **entry)
108 struct acpi_device *adev = ACPI_COMPANION(dev);
109 struct acpihid_map_entry *p;
114 list_for_each_entry(p, &acpihid_map, list) {
115 if (acpi_dev_hid_uid_match(adev, p->hid,
116 p->uid[0] ? p->uid : NULL)) {
125 static inline int get_device_id(struct device *dev)
130 devid = get_pci_device_id(dev);
132 devid = get_acpihid_device_id(dev, NULL);
137 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
139 return container_of(dom, struct protection_domain, domain);
142 static struct iommu_dev_data *alloc_dev_data(u16 devid)
144 struct iommu_dev_data *dev_data;
146 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
150 spin_lock_init(&dev_data->lock);
151 dev_data->devid = devid;
152 ratelimit_default_init(&dev_data->rs);
154 llist_add(&dev_data->dev_data_list, &dev_data_list);
158 static struct iommu_dev_data *search_dev_data(u16 devid)
160 struct iommu_dev_data *dev_data;
161 struct llist_node *node;
163 if (llist_empty(&dev_data_list))
166 node = dev_data_list.first;
167 llist_for_each_entry(dev_data, node, dev_data_list) {
168 if (dev_data->devid == devid)
175 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
177 u16 devid = pci_dev_id(pdev);
182 amd_iommu_rlookup_table[alias] =
183 amd_iommu_rlookup_table[devid];
184 memcpy(amd_iommu_dev_table[alias].data,
185 amd_iommu_dev_table[devid].data,
186 sizeof(amd_iommu_dev_table[alias].data));
191 static void clone_aliases(struct pci_dev *pdev)
197 * The IVRS alias stored in the alias table may not be
198 * part of the PCI DMA aliases if it's bus differs
199 * from the original device.
201 clone_alias(pdev, amd_iommu_alias_table[pci_dev_id(pdev)], NULL);
203 pci_for_each_dma_alias(pdev, clone_alias, NULL);
206 static struct pci_dev *setup_aliases(struct device *dev)
208 struct pci_dev *pdev = to_pci_dev(dev);
211 /* For ACPI HID devices, there are no aliases */
212 if (!dev_is_pci(dev))
216 * Add the IVRS alias to the pci aliases if it is on the same
217 * bus. The IVRS table may know about a quirk that we don't.
219 ivrs_alias = amd_iommu_alias_table[pci_dev_id(pdev)];
220 if (ivrs_alias != pci_dev_id(pdev) &&
221 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
222 pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
229 static struct iommu_dev_data *find_dev_data(u16 devid)
231 struct iommu_dev_data *dev_data;
232 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
234 dev_data = search_dev_data(devid);
236 if (dev_data == NULL) {
237 dev_data = alloc_dev_data(devid);
241 if (translation_pre_enabled(iommu))
242 dev_data->defer_attach = true;
249 * Find or create an IOMMU group for a acpihid device.
251 static struct iommu_group *acpihid_device_group(struct device *dev)
253 struct acpihid_map_entry *p, *entry = NULL;
256 devid = get_acpihid_device_id(dev, &entry);
258 return ERR_PTR(devid);
260 list_for_each_entry(p, &acpihid_map, list) {
261 if ((devid == p->devid) && p->group)
262 entry->group = p->group;
266 entry->group = generic_device_group(dev);
268 iommu_group_ref_get(entry->group);
273 static bool pci_iommuv2_capable(struct pci_dev *pdev)
275 static const int caps[] = {
277 PCI_EXT_CAP_ID_PASID,
281 if (!pci_ats_supported(pdev))
284 for (i = 0; i < 2; ++i) {
285 pos = pci_find_ext_capability(pdev, caps[i]);
294 * This function checks if the driver got a valid device from the caller to
295 * avoid dereferencing invalid pointers.
297 static bool check_device(struct device *dev)
304 devid = get_device_id(dev);
308 /* Out of our scope? */
309 if (devid > amd_iommu_last_bdf)
312 if (amd_iommu_rlookup_table[devid] == NULL)
318 static int iommu_init_device(struct device *dev)
320 struct iommu_dev_data *dev_data;
323 if (dev_iommu_priv_get(dev))
326 devid = get_device_id(dev);
330 dev_data = find_dev_data(devid);
334 dev_data->pdev = setup_aliases(dev);
337 * By default we use passthrough mode for IOMMUv2 capable device.
338 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
339 * invalid address), we ignore the capability for the device so
340 * it'll be forced to go into translation mode.
342 if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
343 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
344 struct amd_iommu *iommu;
346 iommu = amd_iommu_rlookup_table[dev_data->devid];
347 dev_data->iommu_v2 = iommu->is_iommu_v2;
350 dev_iommu_priv_set(dev, dev_data);
355 static void iommu_ignore_device(struct device *dev)
359 devid = get_device_id(dev);
363 amd_iommu_rlookup_table[devid] = NULL;
364 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
369 static void amd_iommu_uninit_device(struct device *dev)
371 struct iommu_dev_data *dev_data;
373 dev_data = dev_iommu_priv_get(dev);
377 if (dev_data->domain)
380 dev_iommu_priv_set(dev, NULL);
383 * We keep dev_data around for unplugged devices and reuse it when the
384 * device is re-plugged - not doing so would introduce a ton of races.
388 /****************************************************************************
390 * Interrupt handling functions
392 ****************************************************************************/
394 static void dump_dte_entry(u16 devid)
398 for (i = 0; i < 4; ++i)
399 pr_err("DTE[%d]: %016llx\n", i,
400 amd_iommu_dev_table[devid].data[i]);
403 static void dump_command(unsigned long phys_addr)
405 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
408 for (i = 0; i < 4; ++i)
409 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
412 static void amd_iommu_report_rmp_hw_error(volatile u32 *event)
414 struct iommu_dev_data *dev_data = NULL;
415 int devid, vmg_tag, flags;
416 struct pci_dev *pdev;
419 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
420 vmg_tag = (event[1]) & 0xFFFF;
421 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
422 spa = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
424 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
427 dev_data = dev_iommu_priv_get(&pdev->dev);
429 if (dev_data && __ratelimit(&dev_data->rs)) {
430 pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
431 vmg_tag, spa, flags);
433 pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
434 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
435 vmg_tag, spa, flags);
442 static void amd_iommu_report_rmp_fault(volatile u32 *event)
444 struct iommu_dev_data *dev_data = NULL;
445 int devid, flags_rmp, vmg_tag, flags;
446 struct pci_dev *pdev;
449 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
450 flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
451 vmg_tag = (event[1]) & 0xFFFF;
452 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
453 gpa = ((u64)event[3] << 32) | event[2];
455 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
458 dev_data = dev_iommu_priv_get(&pdev->dev);
460 if (dev_data && __ratelimit(&dev_data->rs)) {
461 pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
462 vmg_tag, gpa, flags_rmp, flags);
464 pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
465 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
466 vmg_tag, gpa, flags_rmp, flags);
473 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
474 u64 address, int flags)
476 struct iommu_dev_data *dev_data = NULL;
477 struct pci_dev *pdev;
479 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
482 dev_data = dev_iommu_priv_get(&pdev->dev);
484 if (dev_data && __ratelimit(&dev_data->rs)) {
485 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
486 domain_id, address, flags);
487 } else if (printk_ratelimit()) {
488 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
489 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
490 domain_id, address, flags);
497 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
499 struct device *dev = iommu->iommu.dev;
500 int type, devid, flags, tag;
501 volatile u32 *event = __evt;
507 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
508 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
509 pasid = (event[0] & EVENT_DOMID_MASK_HI) |
510 (event[1] & EVENT_DOMID_MASK_LO);
511 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
512 address = (u64)(((u64)event[3]) << 32) | event[2];
515 /* Did we hit the erratum? */
516 if (++count == LOOP_TIMEOUT) {
517 pr_err("No event written to event log\n");
524 if (type == EVENT_TYPE_IO_FAULT) {
525 amd_iommu_report_page_fault(devid, pasid, address, flags);
530 case EVENT_TYPE_ILL_DEV:
531 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
532 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
533 pasid, address, flags);
534 dump_dte_entry(devid);
536 case EVENT_TYPE_DEV_TAB_ERR:
537 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
538 "address=0x%llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
542 case EVENT_TYPE_PAGE_TAB_ERR:
543 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 pasid, address, flags);
547 case EVENT_TYPE_ILL_CMD:
548 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
549 dump_command(address);
551 case EVENT_TYPE_CMD_HARD_ERR:
552 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
555 case EVENT_TYPE_IOTLB_INV_TO:
556 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
557 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
560 case EVENT_TYPE_INV_DEV_REQ:
561 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
562 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
563 pasid, address, flags);
565 case EVENT_TYPE_RMP_FAULT:
566 amd_iommu_report_rmp_fault(event);
568 case EVENT_TYPE_RMP_HW_ERR:
569 amd_iommu_report_rmp_hw_error(event);
571 case EVENT_TYPE_INV_PPR_REQ:
572 pasid = PPR_PASID(*((u64 *)__evt));
573 tag = event[1] & 0x03FF;
574 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
575 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
576 pasid, address, flags, tag);
579 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
580 event[0], event[1], event[2], event[3]);
583 memset(__evt, 0, 4 * sizeof(u32));
586 static void iommu_poll_events(struct amd_iommu *iommu)
590 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
591 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
593 while (head != tail) {
594 iommu_print_event(iommu, iommu->evt_buf + head);
595 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
598 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
601 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
603 struct amd_iommu_fault fault;
605 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
606 pr_err_ratelimited("Unknown PPR request received\n");
610 fault.address = raw[1];
611 fault.pasid = PPR_PASID(raw[0]);
612 fault.device_id = PPR_DEVID(raw[0]);
613 fault.tag = PPR_TAG(raw[0]);
614 fault.flags = PPR_FLAGS(raw[0]);
616 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
619 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
623 if (iommu->ppr_log == NULL)
626 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
627 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
629 while (head != tail) {
634 raw = (u64 *)(iommu->ppr_log + head);
637 * Hardware bug: Interrupt may arrive before the entry is
638 * written to memory. If this happens we need to wait for the
641 for (i = 0; i < LOOP_TIMEOUT; ++i) {
642 if (PPR_REQ_TYPE(raw[0]) != 0)
647 /* Avoid memcpy function-call overhead */
652 * To detect the hardware bug we need to clear the entry
655 raw[0] = raw[1] = 0UL;
657 /* Update head pointer of hardware ring-buffer */
658 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
659 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
661 /* Handle PPR entry */
662 iommu_handle_ppr_entry(iommu, entry);
664 /* Refresh ring-buffer information */
665 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
666 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
670 #ifdef CONFIG_IRQ_REMAP
671 static int (*iommu_ga_log_notifier)(u32);
673 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
675 iommu_ga_log_notifier = notifier;
679 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
681 static void iommu_poll_ga_log(struct amd_iommu *iommu)
683 u32 head, tail, cnt = 0;
685 if (iommu->ga_log == NULL)
688 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
689 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
691 while (head != tail) {
695 raw = (u64 *)(iommu->ga_log + head);
698 /* Avoid memcpy function-call overhead */
701 /* Update head pointer of hardware ring-buffer */
702 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
703 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
705 /* Handle GA entry */
706 switch (GA_REQ_TYPE(log_entry)) {
708 if (!iommu_ga_log_notifier)
711 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
712 __func__, GA_DEVID(log_entry),
715 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
716 pr_err("GA log notifier failed.\n");
725 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
727 if (!irq_remapping_enabled || !dev_is_pci(dev) ||
728 pci_dev_has_special_msi_domain(to_pci_dev(dev)))
731 dev_set_msi_domain(dev, iommu->msi_domain);
734 #else /* CONFIG_IRQ_REMAP */
736 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
737 #endif /* !CONFIG_IRQ_REMAP */
739 #define AMD_IOMMU_INT_MASK \
740 (MMIO_STATUS_EVT_INT_MASK | \
741 MMIO_STATUS_PPR_INT_MASK | \
742 MMIO_STATUS_GALOG_INT_MASK)
744 irqreturn_t amd_iommu_int_thread(int irq, void *data)
746 struct amd_iommu *iommu = (struct amd_iommu *) data;
747 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
749 while (status & AMD_IOMMU_INT_MASK) {
750 /* Enable EVT and PPR and GA interrupts again */
751 writel(AMD_IOMMU_INT_MASK,
752 iommu->mmio_base + MMIO_STATUS_OFFSET);
754 if (status & MMIO_STATUS_EVT_INT_MASK) {
755 pr_devel("Processing IOMMU Event Log\n");
756 iommu_poll_events(iommu);
759 if (status & MMIO_STATUS_PPR_INT_MASK) {
760 pr_devel("Processing IOMMU PPR Log\n");
761 iommu_poll_ppr_log(iommu);
764 #ifdef CONFIG_IRQ_REMAP
765 if (status & MMIO_STATUS_GALOG_INT_MASK) {
766 pr_devel("Processing IOMMU GA Log\n");
767 iommu_poll_ga_log(iommu);
772 * Hardware bug: ERBT1312
773 * When re-enabling interrupt (by writing 1
774 * to clear the bit), the hardware might also try to set
775 * the interrupt bit in the event status register.
776 * In this scenario, the bit will be set, and disable
777 * subsequent interrupts.
779 * Workaround: The IOMMU driver should read back the
780 * status register and check if the interrupt bits are cleared.
781 * If not, driver will need to go through the interrupt handler
782 * again and re-clear the bits
784 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
789 irqreturn_t amd_iommu_int_handler(int irq, void *data)
791 return IRQ_WAKE_THREAD;
794 /****************************************************************************
796 * IOMMU command queuing functions
798 ****************************************************************************/
800 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
804 while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
809 if (i == LOOP_TIMEOUT) {
810 pr_alert("Completion-Wait loop timed out\n");
817 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
818 struct iommu_cmd *cmd)
823 /* Copy command to buffer */
824 tail = iommu->cmd_buf_tail;
825 target = iommu->cmd_buf + tail;
826 memcpy(target, cmd, sizeof(*cmd));
828 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
829 iommu->cmd_buf_tail = tail;
831 /* Tell the IOMMU about it */
832 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
835 static void build_completion_wait(struct iommu_cmd *cmd,
836 struct amd_iommu *iommu,
839 u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
841 memset(cmd, 0, sizeof(*cmd));
842 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
843 cmd->data[1] = upper_32_bits(paddr);
845 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
848 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
850 memset(cmd, 0, sizeof(*cmd));
851 cmd->data[0] = devid;
852 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
856 * Builds an invalidation address which is suitable for one page or multiple
857 * pages. Sets the size bit (S) as needed is more than one page is flushed.
859 static inline u64 build_inv_address(u64 address, size_t size)
861 u64 pages, end, msb_diff;
863 pages = iommu_num_pages(address, size, PAGE_SIZE);
866 return address & PAGE_MASK;
868 end = address + size - 1;
871 * msb_diff would hold the index of the most significant bit that
872 * flipped between the start and end.
874 msb_diff = fls64(end ^ address) - 1;
877 * Bits 63:52 are sign extended. If for some reason bit 51 is different
878 * between the start and the end, invalidate everything.
880 if (unlikely(msb_diff > 51)) {
881 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
884 * The msb-bit must be clear on the address. Just set all the
887 address |= (1ull << msb_diff) - 1;
890 /* Clear bits 11:0 */
891 address &= PAGE_MASK;
893 /* Set the size bit - we flush more than one 4kb page */
894 return address | CMD_INV_IOMMU_PAGES_SIZE_MASK;
897 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
898 size_t size, u16 domid, int pde)
900 u64 inv_address = build_inv_address(address, size);
902 memset(cmd, 0, sizeof(*cmd));
903 cmd->data[1] |= domid;
904 cmd->data[2] = lower_32_bits(inv_address);
905 cmd->data[3] = upper_32_bits(inv_address);
906 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
907 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
911 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
912 u64 address, size_t size)
914 u64 inv_address = build_inv_address(address, size);
916 memset(cmd, 0, sizeof(*cmd));
917 cmd->data[0] = devid;
918 cmd->data[0] |= (qdep & 0xff) << 24;
919 cmd->data[1] = devid;
920 cmd->data[2] = lower_32_bits(inv_address);
921 cmd->data[3] = upper_32_bits(inv_address);
922 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
925 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
926 u64 address, bool size)
928 memset(cmd, 0, sizeof(*cmd));
930 address &= ~(0xfffULL);
932 cmd->data[0] = pasid;
933 cmd->data[1] = domid;
934 cmd->data[2] = lower_32_bits(address);
935 cmd->data[3] = upper_32_bits(address);
936 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
940 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
943 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
944 int qdep, u64 address, bool size)
946 memset(cmd, 0, sizeof(*cmd));
948 address &= ~(0xfffULL);
950 cmd->data[0] = devid;
951 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
952 cmd->data[0] |= (qdep & 0xff) << 24;
953 cmd->data[1] = devid;
954 cmd->data[1] |= (pasid & 0xff) << 16;
955 cmd->data[2] = lower_32_bits(address);
956 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
957 cmd->data[3] = upper_32_bits(address);
959 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
960 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
963 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
964 int status, int tag, bool gn)
966 memset(cmd, 0, sizeof(*cmd));
968 cmd->data[0] = devid;
970 cmd->data[1] = pasid;
971 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
973 cmd->data[3] = tag & 0x1ff;
974 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
976 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
979 static void build_inv_all(struct iommu_cmd *cmd)
981 memset(cmd, 0, sizeof(*cmd));
982 CMD_SET_TYPE(cmd, CMD_INV_ALL);
985 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
987 memset(cmd, 0, sizeof(*cmd));
988 cmd->data[0] = devid;
989 CMD_SET_TYPE(cmd, CMD_INV_IRT);
993 * Writes the command to the IOMMUs command buffer and informs the
994 * hardware about the new command.
996 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
997 struct iommu_cmd *cmd,
1000 unsigned int count = 0;
1001 u32 left, next_tail;
1003 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1005 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1008 /* Skip udelay() the first time around */
1010 if (count == LOOP_TIMEOUT) {
1011 pr_err("Command buffer timeout\n");
1018 /* Update head and recheck remaining space */
1019 iommu->cmd_buf_head = readl(iommu->mmio_base +
1020 MMIO_CMD_HEAD_OFFSET);
1025 copy_cmd_to_buffer(iommu, cmd);
1027 /* Do we need to make sure all commands are processed? */
1028 iommu->need_sync = sync;
1033 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1034 struct iommu_cmd *cmd,
1037 unsigned long flags;
1040 raw_spin_lock_irqsave(&iommu->lock, flags);
1041 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1042 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1047 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1049 return iommu_queue_command_sync(iommu, cmd, true);
1053 * This function queues a completion wait command into the command
1054 * buffer of an IOMMU
1056 static int iommu_completion_wait(struct amd_iommu *iommu)
1058 struct iommu_cmd cmd;
1059 unsigned long flags;
1063 if (!iommu->need_sync)
1066 raw_spin_lock_irqsave(&iommu->lock, flags);
1068 data = ++iommu->cmd_sem_val;
1069 build_completion_wait(&cmd, iommu, data);
1071 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1075 ret = wait_on_sem(iommu, data);
1078 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1083 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1085 struct iommu_cmd cmd;
1087 build_inv_dte(&cmd, devid);
1089 return iommu_queue_command(iommu, &cmd);
1092 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1096 for (devid = 0; devid <= 0xffff; ++devid)
1097 iommu_flush_dte(iommu, devid);
1099 iommu_completion_wait(iommu);
1103 * This function uses heavy locking and may disable irqs for some time. But
1104 * this is no issue because it is only called during resume.
1106 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1110 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1111 struct iommu_cmd cmd;
1112 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1114 iommu_queue_command(iommu, &cmd);
1117 iommu_completion_wait(iommu);
1120 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1122 struct iommu_cmd cmd;
1124 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1126 iommu_queue_command(iommu, &cmd);
1128 iommu_completion_wait(iommu);
1131 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1133 struct iommu_cmd cmd;
1135 build_inv_all(&cmd);
1137 iommu_queue_command(iommu, &cmd);
1138 iommu_completion_wait(iommu);
1141 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1143 struct iommu_cmd cmd;
1145 build_inv_irt(&cmd, devid);
1147 iommu_queue_command(iommu, &cmd);
1150 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1154 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1155 iommu_flush_irt(iommu, devid);
1157 iommu_completion_wait(iommu);
1160 void iommu_flush_all_caches(struct amd_iommu *iommu)
1162 if (iommu_feature(iommu, FEATURE_IA)) {
1163 amd_iommu_flush_all(iommu);
1165 amd_iommu_flush_dte_all(iommu);
1166 amd_iommu_flush_irt_all(iommu);
1167 amd_iommu_flush_tlb_all(iommu);
1172 * Command send function for flushing on-device TLB
1174 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1175 u64 address, size_t size)
1177 struct amd_iommu *iommu;
1178 struct iommu_cmd cmd;
1181 qdep = dev_data->ats.qdep;
1182 iommu = amd_iommu_rlookup_table[dev_data->devid];
1184 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1186 return iommu_queue_command(iommu, &cmd);
1189 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1191 struct amd_iommu *iommu = data;
1193 return iommu_flush_dte(iommu, alias);
1197 * Command send function for invalidating a device table entry
1199 static int device_flush_dte(struct iommu_dev_data *dev_data)
1201 struct amd_iommu *iommu;
1205 iommu = amd_iommu_rlookup_table[dev_data->devid];
1208 ret = pci_for_each_dma_alias(dev_data->pdev,
1209 device_flush_dte_alias, iommu);
1211 ret = iommu_flush_dte(iommu, dev_data->devid);
1215 alias = amd_iommu_alias_table[dev_data->devid];
1216 if (alias != dev_data->devid) {
1217 ret = iommu_flush_dte(iommu, alias);
1222 if (dev_data->ats.enabled)
1223 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1229 * TLB invalidation function which is called from the mapping functions.
1230 * It invalidates a single PTE if the range to flush is within a single
1231 * page. Otherwise it flushes the whole TLB of the IOMMU.
1233 static void __domain_flush_pages(struct protection_domain *domain,
1234 u64 address, size_t size, int pde)
1236 struct iommu_dev_data *dev_data;
1237 struct iommu_cmd cmd;
1240 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1242 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1243 if (!domain->dev_iommu[i])
1247 * Devices of this domain are behind this IOMMU
1248 * We need a TLB flush
1250 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1253 list_for_each_entry(dev_data, &domain->dev_list, list) {
1255 if (!dev_data->ats.enabled)
1258 ret |= device_flush_iotlb(dev_data, address, size);
1264 static void domain_flush_pages(struct protection_domain *domain,
1265 u64 address, size_t size)
1267 __domain_flush_pages(domain, address, size, 0);
1270 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1271 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)
1273 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1276 void amd_iommu_domain_flush_complete(struct protection_domain *domain)
1280 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1281 if (domain && !domain->dev_iommu[i])
1285 * Devices of this domain are behind this IOMMU
1286 * We need to wait for completion of all commands.
1288 iommu_completion_wait(amd_iommus[i]);
1292 /* Flush the not present cache if it exists */
1293 static void domain_flush_np_cache(struct protection_domain *domain,
1294 dma_addr_t iova, size_t size)
1296 if (unlikely(amd_iommu_np_cache)) {
1297 unsigned long flags;
1299 spin_lock_irqsave(&domain->lock, flags);
1300 domain_flush_pages(domain, iova, size);
1301 amd_iommu_domain_flush_complete(domain);
1302 spin_unlock_irqrestore(&domain->lock, flags);
1308 * This function flushes the DTEs for all devices in domain
1310 static void domain_flush_devices(struct protection_domain *domain)
1312 struct iommu_dev_data *dev_data;
1314 list_for_each_entry(dev_data, &domain->dev_list, list)
1315 device_flush_dte(dev_data);
1318 /****************************************************************************
1320 * The next functions belong to the domain allocation. A domain is
1321 * allocated for every IOMMU as the default domain. If device isolation
1322 * is enabled, every device get its own domain. The most important thing
1323 * about domains is the page table mapping the DMA address space they
1326 ****************************************************************************/
1328 static u16 domain_id_alloc(void)
1332 spin_lock(&pd_bitmap_lock);
1333 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1335 if (id > 0 && id < MAX_DOMAIN_ID)
1336 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1339 spin_unlock(&pd_bitmap_lock);
1344 static void domain_id_free(int id)
1346 spin_lock(&pd_bitmap_lock);
1347 if (id > 0 && id < MAX_DOMAIN_ID)
1348 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1349 spin_unlock(&pd_bitmap_lock);
1352 static void free_gcr3_tbl_level1(u64 *tbl)
1357 for (i = 0; i < 512; ++i) {
1358 if (!(tbl[i] & GCR3_VALID))
1361 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1363 free_page((unsigned long)ptr);
1367 static void free_gcr3_tbl_level2(u64 *tbl)
1372 for (i = 0; i < 512; ++i) {
1373 if (!(tbl[i] & GCR3_VALID))
1376 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1378 free_gcr3_tbl_level1(ptr);
1382 static void free_gcr3_table(struct protection_domain *domain)
1384 if (domain->glx == 2)
1385 free_gcr3_tbl_level2(domain->gcr3_tbl);
1386 else if (domain->glx == 1)
1387 free_gcr3_tbl_level1(domain->gcr3_tbl);
1389 BUG_ON(domain->glx != 0);
1391 free_page((unsigned long)domain->gcr3_tbl);
1394 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1401 if (domain->iop.mode != PAGE_MODE_NONE)
1402 pte_root = iommu_virt_to_phys(domain->iop.root);
1404 pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
1405 << DEV_ENTRY_MODE_SHIFT;
1406 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1408 flags = amd_iommu_dev_table[devid].data[1];
1411 flags |= DTE_FLAG_IOTLB;
1414 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1416 if (iommu_feature(iommu, FEATURE_EPHSUP))
1417 pte_root |= 1ULL << DEV_ENTRY_PPR;
1420 if (domain->flags & PD_IOMMUV2_MASK) {
1421 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1422 u64 glx = domain->glx;
1425 pte_root |= DTE_FLAG_GV;
1426 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1428 /* First mask out possible old values for GCR3 table */
1429 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1432 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1435 /* Encode GCR3 table into DTE */
1436 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1439 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1442 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1446 flags &= ~DEV_DOMID_MASK;
1447 flags |= domain->id;
1449 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1450 amd_iommu_dev_table[devid].data[1] = flags;
1451 amd_iommu_dev_table[devid].data[0] = pte_root;
1454 * A kdump kernel might be replacing a domain ID that was copied from
1455 * the previous kernel--if so, it needs to flush the translation cache
1456 * entries for the old domain ID that is being overwritten
1459 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1461 amd_iommu_flush_tlb_domid(iommu, old_domid);
1465 static void clear_dte_entry(u16 devid)
1467 /* remove entry from the device table seen by the hardware */
1468 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1469 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1471 amd_iommu_apply_erratum_63(devid);
1474 static void do_attach(struct iommu_dev_data *dev_data,
1475 struct protection_domain *domain)
1477 struct amd_iommu *iommu;
1480 iommu = amd_iommu_rlookup_table[dev_data->devid];
1481 ats = dev_data->ats.enabled;
1483 /* Update data structures */
1484 dev_data->domain = domain;
1485 list_add(&dev_data->list, &domain->dev_list);
1487 /* Do reference counting */
1488 domain->dev_iommu[iommu->index] += 1;
1489 domain->dev_cnt += 1;
1491 /* Update device table */
1492 set_dte_entry(dev_data->devid, domain,
1493 ats, dev_data->iommu_v2);
1494 clone_aliases(dev_data->pdev);
1496 device_flush_dte(dev_data);
1499 static void do_detach(struct iommu_dev_data *dev_data)
1501 struct protection_domain *domain = dev_data->domain;
1502 struct amd_iommu *iommu;
1504 iommu = amd_iommu_rlookup_table[dev_data->devid];
1506 /* Update data structures */
1507 dev_data->domain = NULL;
1508 list_del(&dev_data->list);
1509 clear_dte_entry(dev_data->devid);
1510 clone_aliases(dev_data->pdev);
1512 /* Flush the DTE entry */
1513 device_flush_dte(dev_data);
1516 amd_iommu_domain_flush_tlb_pde(domain);
1518 /* Wait for the flushes to finish */
1519 amd_iommu_domain_flush_complete(domain);
1521 /* decrease reference counters - needs to happen after the flushes */
1522 domain->dev_iommu[iommu->index] -= 1;
1523 domain->dev_cnt -= 1;
1526 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1528 pci_disable_ats(pdev);
1529 pci_disable_pri(pdev);
1530 pci_disable_pasid(pdev);
1533 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1537 /* Only allow access to user-accessible pages */
1538 ret = pci_enable_pasid(pdev, 0);
1542 /* First reset the PRI state of the device */
1543 ret = pci_reset_pri(pdev);
1548 /* FIXME: Hardcode number of outstanding requests for now */
1549 ret = pci_enable_pri(pdev, 32);
1553 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1560 pci_disable_pri(pdev);
1561 pci_disable_pasid(pdev);
1567 * If a device is not yet associated with a domain, this function makes the
1568 * device visible in the domain
1570 static int attach_device(struct device *dev,
1571 struct protection_domain *domain)
1573 struct iommu_dev_data *dev_data;
1574 struct pci_dev *pdev;
1575 unsigned long flags;
1578 spin_lock_irqsave(&domain->lock, flags);
1580 dev_data = dev_iommu_priv_get(dev);
1582 spin_lock(&dev_data->lock);
1585 if (dev_data->domain != NULL)
1588 if (!dev_is_pci(dev))
1589 goto skip_ats_check;
1591 pdev = to_pci_dev(dev);
1592 if (domain->flags & PD_IOMMUV2_MASK) {
1593 struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
1596 if (def_domain->type != IOMMU_DOMAIN_IDENTITY)
1599 if (dev_data->iommu_v2) {
1600 if (pdev_iommuv2_enable(pdev) != 0)
1603 dev_data->ats.enabled = true;
1604 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1605 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
1607 } else if (amd_iommu_iotlb_sup &&
1608 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1609 dev_data->ats.enabled = true;
1610 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
1616 do_attach(dev_data, domain);
1619 * We might boot into a crash-kernel here. The crashed kernel
1620 * left the caches in the IOMMU dirty. So we have to flush
1621 * here to evict all dirty stuff.
1623 amd_iommu_domain_flush_tlb_pde(domain);
1625 amd_iommu_domain_flush_complete(domain);
1628 spin_unlock(&dev_data->lock);
1630 spin_unlock_irqrestore(&domain->lock, flags);
1636 * Removes a device from a protection domain (with devtable_lock held)
1638 static void detach_device(struct device *dev)
1640 struct protection_domain *domain;
1641 struct iommu_dev_data *dev_data;
1642 unsigned long flags;
1644 dev_data = dev_iommu_priv_get(dev);
1645 domain = dev_data->domain;
1647 spin_lock_irqsave(&domain->lock, flags);
1649 spin_lock(&dev_data->lock);
1652 * First check if the device is still attached. It might already
1653 * be detached from its domain because the generic
1654 * iommu_detach_group code detached it and we try again here in
1655 * our alias handling.
1657 if (WARN_ON(!dev_data->domain))
1660 do_detach(dev_data);
1662 if (!dev_is_pci(dev))
1665 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
1666 pdev_iommuv2_disable(to_pci_dev(dev));
1667 else if (dev_data->ats.enabled)
1668 pci_disable_ats(to_pci_dev(dev));
1670 dev_data->ats.enabled = false;
1673 spin_unlock(&dev_data->lock);
1675 spin_unlock_irqrestore(&domain->lock, flags);
1678 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
1680 struct iommu_device *iommu_dev;
1681 struct amd_iommu *iommu;
1684 if (!check_device(dev))
1685 return ERR_PTR(-ENODEV);
1687 devid = get_device_id(dev);
1688 iommu = amd_iommu_rlookup_table[devid];
1690 if (dev_iommu_priv_get(dev))
1691 return &iommu->iommu;
1693 ret = iommu_init_device(dev);
1695 if (ret != -ENOTSUPP)
1696 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
1697 iommu_dev = ERR_PTR(ret);
1698 iommu_ignore_device(dev);
1700 amd_iommu_set_pci_msi_domain(dev, iommu);
1701 iommu_dev = &iommu->iommu;
1704 iommu_completion_wait(iommu);
1709 static void amd_iommu_probe_finalize(struct device *dev)
1711 struct iommu_domain *domain;
1713 /* Domains are initialized for this device - have a look what we ended up with */
1714 domain = iommu_get_domain_for_dev(dev);
1715 if (domain->type == IOMMU_DOMAIN_DMA)
1716 iommu_setup_dma_ops(dev, IOVA_START_PFN << PAGE_SHIFT, 0);
1718 set_dma_ops(dev, NULL);
1721 static void amd_iommu_release_device(struct device *dev)
1723 int devid = get_device_id(dev);
1724 struct amd_iommu *iommu;
1726 if (!check_device(dev))
1729 iommu = amd_iommu_rlookup_table[devid];
1731 amd_iommu_uninit_device(dev);
1732 iommu_completion_wait(iommu);
1735 static struct iommu_group *amd_iommu_device_group(struct device *dev)
1737 if (dev_is_pci(dev))
1738 return pci_device_group(dev);
1740 return acpihid_device_group(dev);
1743 /*****************************************************************************
1745 * The next functions belong to the dma_ops mapping/unmapping code.
1747 *****************************************************************************/
1749 static void update_device_table(struct protection_domain *domain)
1751 struct iommu_dev_data *dev_data;
1753 list_for_each_entry(dev_data, &domain->dev_list, list) {
1754 set_dte_entry(dev_data->devid, domain,
1755 dev_data->ats.enabled, dev_data->iommu_v2);
1756 clone_aliases(dev_data->pdev);
1760 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1762 update_device_table(domain);
1763 domain_flush_devices(domain);
1766 void amd_iommu_domain_update(struct protection_domain *domain)
1768 /* Update device table */
1769 amd_iommu_update_and_flush_device_table(domain);
1771 /* Flush domain TLB(s) and wait for completion */
1772 amd_iommu_domain_flush_tlb_pde(domain);
1773 amd_iommu_domain_flush_complete(domain);
1776 int __init amd_iommu_init_api(void)
1780 ret = iova_cache_get();
1784 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
1787 #ifdef CONFIG_ARM_AMBA
1788 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
1792 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
1799 int __init amd_iommu_init_dma_ops(void)
1801 swiotlb = (iommu_default_passthrough() || sme_me_mask) ? 1 : 0;
1803 if (amd_iommu_unmap_flush)
1804 pr_info("IO/TLB flush on unmap enabled\n");
1806 pr_info("Lazy IO/TLB flushing enabled\n");
1807 iommu_set_dma_strict(amd_iommu_unmap_flush);
1812 /*****************************************************************************
1814 * The following functions belong to the exported interface of AMD IOMMU
1816 * This interface allows access to lower level functions of the IOMMU
1817 * like protection domain handling and assignement of devices to domains
1818 * which is not possible with the dma_ops interface.
1820 *****************************************************************************/
1822 static void cleanup_domain(struct protection_domain *domain)
1824 struct iommu_dev_data *entry;
1825 unsigned long flags;
1827 spin_lock_irqsave(&domain->lock, flags);
1829 while (!list_empty(&domain->dev_list)) {
1830 entry = list_first_entry(&domain->dev_list,
1831 struct iommu_dev_data, list);
1832 BUG_ON(!entry->domain);
1836 spin_unlock_irqrestore(&domain->lock, flags);
1839 static void protection_domain_free(struct protection_domain *domain)
1845 domain_id_free(domain->id);
1847 if (domain->iop.pgtbl_cfg.tlb)
1848 free_io_pgtable_ops(&domain->iop.iop.ops);
1853 static int protection_domain_init_v1(struct protection_domain *domain, int mode)
1855 u64 *pt_root = NULL;
1857 BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
1859 spin_lock_init(&domain->lock);
1860 domain->id = domain_id_alloc();
1863 INIT_LIST_HEAD(&domain->dev_list);
1865 if (mode != PAGE_MODE_NONE) {
1866 pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1871 amd_iommu_domain_set_pgtable(domain, pt_root, mode);
1876 static struct protection_domain *protection_domain_alloc(unsigned int type)
1878 struct io_pgtable_ops *pgtbl_ops;
1879 struct protection_domain *domain;
1880 int pgtable = amd_iommu_pgtable;
1881 int mode = DEFAULT_PGTABLE_LEVEL;
1884 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
1889 * Force IOMMU v1 page table when iommu=pt and
1890 * when allocating domain for pass-through devices.
1892 if (type == IOMMU_DOMAIN_IDENTITY) {
1893 pgtable = AMD_IOMMU_V1;
1894 mode = PAGE_MODE_NONE;
1895 } else if (type == IOMMU_DOMAIN_UNMANAGED) {
1896 pgtable = AMD_IOMMU_V1;
1901 ret = protection_domain_init_v1(domain, mode);
1910 pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
1920 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
1922 struct protection_domain *domain;
1924 domain = protection_domain_alloc(type);
1928 domain->domain.geometry.aperture_start = 0;
1929 domain->domain.geometry.aperture_end = ~0ULL;
1930 domain->domain.geometry.force_aperture = true;
1932 if (type == IOMMU_DOMAIN_DMA &&
1933 iommu_get_dma_cookie(&domain->domain) == -ENOMEM)
1936 return &domain->domain;
1939 protection_domain_free(domain);
1944 static void amd_iommu_domain_free(struct iommu_domain *dom)
1946 struct protection_domain *domain;
1948 domain = to_pdomain(dom);
1950 if (domain->dev_cnt > 0)
1951 cleanup_domain(domain);
1953 BUG_ON(domain->dev_cnt != 0);
1958 if (dom->type == IOMMU_DOMAIN_DMA)
1959 iommu_put_dma_cookie(&domain->domain);
1961 if (domain->flags & PD_IOMMUV2_MASK)
1962 free_gcr3_table(domain);
1964 protection_domain_free(domain);
1967 static void amd_iommu_detach_device(struct iommu_domain *dom,
1970 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
1971 int devid = get_device_id(dev);
1972 struct amd_iommu *iommu;
1974 if (!check_device(dev))
1977 if (dev_data->domain != NULL)
1980 iommu = amd_iommu_rlookup_table[devid];
1984 #ifdef CONFIG_IRQ_REMAP
1985 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
1986 (dom->type == IOMMU_DOMAIN_UNMANAGED))
1987 dev_data->use_vapic = 0;
1990 iommu_completion_wait(iommu);
1993 static int amd_iommu_attach_device(struct iommu_domain *dom,
1996 struct protection_domain *domain = to_pdomain(dom);
1997 struct iommu_dev_data *dev_data;
1998 struct amd_iommu *iommu;
2001 if (!check_device(dev))
2004 dev_data = dev_iommu_priv_get(dev);
2005 dev_data->defer_attach = false;
2007 iommu = amd_iommu_rlookup_table[dev_data->devid];
2011 if (dev_data->domain)
2014 ret = attach_device(dev, domain);
2016 #ifdef CONFIG_IRQ_REMAP
2017 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2018 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2019 dev_data->use_vapic = 1;
2021 dev_data->use_vapic = 0;
2025 iommu_completion_wait(iommu);
2030 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
2031 phys_addr_t paddr, size_t page_size, int iommu_prot,
2034 struct protection_domain *domain = to_pdomain(dom);
2035 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2039 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2040 (domain->iop.mode == PAGE_MODE_NONE))
2043 if (iommu_prot & IOMMU_READ)
2044 prot |= IOMMU_PROT_IR;
2045 if (iommu_prot & IOMMU_WRITE)
2046 prot |= IOMMU_PROT_IW;
2049 ret = ops->map(ops, iova, paddr, page_size, prot, gfp);
2050 domain_flush_np_cache(domain, iova, page_size);
2056 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
2058 struct iommu_iotlb_gather *gather)
2060 struct protection_domain *domain = to_pdomain(dom);
2061 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2063 if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2064 (domain->iop.mode == PAGE_MODE_NONE))
2067 return (ops->unmap) ? ops->unmap(ops, iova, page_size, gather) : 0;
2070 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2073 struct protection_domain *domain = to_pdomain(dom);
2074 struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2076 return ops->iova_to_phys(ops, iova);
2079 static bool amd_iommu_capable(enum iommu_cap cap)
2082 case IOMMU_CAP_CACHE_COHERENCY:
2084 case IOMMU_CAP_INTR_REMAP:
2085 return (irq_remapping_enabled == 1);
2086 case IOMMU_CAP_NOEXEC:
2095 static void amd_iommu_get_resv_regions(struct device *dev,
2096 struct list_head *head)
2098 struct iommu_resv_region *region;
2099 struct unity_map_entry *entry;
2102 devid = get_device_id(dev);
2106 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
2110 if (devid < entry->devid_start || devid > entry->devid_end)
2113 type = IOMMU_RESV_DIRECT;
2114 length = entry->address_end - entry->address_start;
2115 if (entry->prot & IOMMU_PROT_IR)
2117 if (entry->prot & IOMMU_PROT_IW)
2118 prot |= IOMMU_WRITE;
2119 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2120 /* Exclusion range */
2121 type = IOMMU_RESV_RESERVED;
2123 region = iommu_alloc_resv_region(entry->address_start,
2124 length, prot, type);
2126 dev_err(dev, "Out of memory allocating dm-regions\n");
2129 list_add_tail(®ion->list, head);
2132 region = iommu_alloc_resv_region(MSI_RANGE_START,
2133 MSI_RANGE_END - MSI_RANGE_START + 1,
2137 list_add_tail(®ion->list, head);
2139 region = iommu_alloc_resv_region(HT_RANGE_START,
2140 HT_RANGE_END - HT_RANGE_START + 1,
2141 0, IOMMU_RESV_RESERVED);
2144 list_add_tail(®ion->list, head);
2147 bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
2150 struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2152 return dev_data->defer_attach;
2154 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2156 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2158 struct protection_domain *dom = to_pdomain(domain);
2159 unsigned long flags;
2161 spin_lock_irqsave(&dom->lock, flags);
2162 amd_iommu_domain_flush_tlb_pde(dom);
2163 amd_iommu_domain_flush_complete(dom);
2164 spin_unlock_irqrestore(&dom->lock, flags);
2167 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2168 struct iommu_iotlb_gather *gather)
2170 amd_iommu_flush_iotlb_all(domain);
2173 static int amd_iommu_def_domain_type(struct device *dev)
2175 struct iommu_dev_data *dev_data;
2177 dev_data = dev_iommu_priv_get(dev);
2182 * Do not identity map IOMMUv2 capable devices when memory encryption is
2183 * active, because some of those devices (AMD GPUs) don't have the
2184 * encryption bit in their DMA-mask and require remapping.
2186 if (!mem_encrypt_active() && dev_data->iommu_v2)
2187 return IOMMU_DOMAIN_IDENTITY;
2192 const struct iommu_ops amd_iommu_ops = {
2193 .capable = amd_iommu_capable,
2194 .domain_alloc = amd_iommu_domain_alloc,
2195 .domain_free = amd_iommu_domain_free,
2196 .attach_dev = amd_iommu_attach_device,
2197 .detach_dev = amd_iommu_detach_device,
2198 .map = amd_iommu_map,
2199 .unmap = amd_iommu_unmap,
2200 .iova_to_phys = amd_iommu_iova_to_phys,
2201 .probe_device = amd_iommu_probe_device,
2202 .release_device = amd_iommu_release_device,
2203 .probe_finalize = amd_iommu_probe_finalize,
2204 .device_group = amd_iommu_device_group,
2205 .get_resv_regions = amd_iommu_get_resv_regions,
2206 .put_resv_regions = generic_iommu_put_resv_regions,
2207 .is_attach_deferred = amd_iommu_is_attach_deferred,
2208 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
2209 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
2210 .iotlb_sync = amd_iommu_iotlb_sync,
2211 .def_domain_type = amd_iommu_def_domain_type,
2214 /*****************************************************************************
2216 * The next functions do a basic initialization of IOMMU for pass through
2219 * In passthrough mode the IOMMU is initialized and enabled but not used for
2220 * DMA-API translation.
2222 *****************************************************************************/
2224 /* IOMMUv2 specific functions */
2225 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2227 return atomic_notifier_chain_register(&ppr_notifier, nb);
2229 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2231 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2233 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2235 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2237 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2239 struct protection_domain *domain = to_pdomain(dom);
2240 unsigned long flags;
2242 spin_lock_irqsave(&domain->lock, flags);
2244 if (domain->iop.pgtbl_cfg.tlb)
2245 free_io_pgtable_ops(&domain->iop.iop.ops);
2247 spin_unlock_irqrestore(&domain->lock, flags);
2249 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2251 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2253 struct protection_domain *domain = to_pdomain(dom);
2254 unsigned long flags;
2257 /* Number of GCR3 table levels required */
2258 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2261 if (levels > amd_iommu_max_glx_val)
2264 spin_lock_irqsave(&domain->lock, flags);
2267 * Save us all sanity checks whether devices already in the
2268 * domain support IOMMUv2. Just force that the domain has no
2269 * devices attached when it is switched into IOMMUv2 mode.
2272 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
2276 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2277 if (domain->gcr3_tbl == NULL)
2280 domain->glx = levels;
2281 domain->flags |= PD_IOMMUV2_MASK;
2283 amd_iommu_domain_update(domain);
2288 spin_unlock_irqrestore(&domain->lock, flags);
2292 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2294 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2295 u64 address, bool size)
2297 struct iommu_dev_data *dev_data;
2298 struct iommu_cmd cmd;
2301 if (!(domain->flags & PD_IOMMUV2_MASK))
2304 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2307 * IOMMU TLB needs to be flushed before Device TLB to
2308 * prevent device TLB refill from IOMMU TLB
2310 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2311 if (domain->dev_iommu[i] == 0)
2314 ret = iommu_queue_command(amd_iommus[i], &cmd);
2319 /* Wait until IOMMU TLB flushes are complete */
2320 amd_iommu_domain_flush_complete(domain);
2322 /* Now flush device TLBs */
2323 list_for_each_entry(dev_data, &domain->dev_list, list) {
2324 struct amd_iommu *iommu;
2328 There might be non-IOMMUv2 capable devices in an IOMMUv2
2331 if (!dev_data->ats.enabled)
2334 qdep = dev_data->ats.qdep;
2335 iommu = amd_iommu_rlookup_table[dev_data->devid];
2337 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2338 qdep, address, size);
2340 ret = iommu_queue_command(iommu, &cmd);
2345 /* Wait until all device TLBs are flushed */
2346 amd_iommu_domain_flush_complete(domain);
2355 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2358 return __flush_pasid(domain, pasid, address, false);
2361 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2364 struct protection_domain *domain = to_pdomain(dom);
2365 unsigned long flags;
2368 spin_lock_irqsave(&domain->lock, flags);
2369 ret = __amd_iommu_flush_page(domain, pasid, address);
2370 spin_unlock_irqrestore(&domain->lock, flags);
2374 EXPORT_SYMBOL(amd_iommu_flush_page);
2376 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2378 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2382 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2384 struct protection_domain *domain = to_pdomain(dom);
2385 unsigned long flags;
2388 spin_lock_irqsave(&domain->lock, flags);
2389 ret = __amd_iommu_flush_tlb(domain, pasid);
2390 spin_unlock_irqrestore(&domain->lock, flags);
2394 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2396 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2403 index = (pasid >> (9 * level)) & 0x1ff;
2409 if (!(*pte & GCR3_VALID)) {
2413 root = (void *)get_zeroed_page(GFP_ATOMIC);
2417 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
2420 root = iommu_phys_to_virt(*pte & PAGE_MASK);
2428 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2433 if (domain->iop.mode != PAGE_MODE_NONE)
2436 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2440 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2442 return __amd_iommu_flush_tlb(domain, pasid);
2445 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2449 if (domain->iop.mode != PAGE_MODE_NONE)
2452 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2458 return __amd_iommu_flush_tlb(domain, pasid);
2461 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2464 struct protection_domain *domain = to_pdomain(dom);
2465 unsigned long flags;
2468 spin_lock_irqsave(&domain->lock, flags);
2469 ret = __set_gcr3(domain, pasid, cr3);
2470 spin_unlock_irqrestore(&domain->lock, flags);
2474 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2476 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2478 struct protection_domain *domain = to_pdomain(dom);
2479 unsigned long flags;
2482 spin_lock_irqsave(&domain->lock, flags);
2483 ret = __clear_gcr3(domain, pasid);
2484 spin_unlock_irqrestore(&domain->lock, flags);
2488 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2490 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2491 int status, int tag)
2493 struct iommu_dev_data *dev_data;
2494 struct amd_iommu *iommu;
2495 struct iommu_cmd cmd;
2497 dev_data = dev_iommu_priv_get(&pdev->dev);
2498 iommu = amd_iommu_rlookup_table[dev_data->devid];
2500 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2501 tag, dev_data->pri_tlp);
2503 return iommu_queue_command(iommu, &cmd);
2505 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2507 int amd_iommu_device_info(struct pci_dev *pdev,
2508 struct amd_iommu_device_info *info)
2513 if (pdev == NULL || info == NULL)
2516 if (!amd_iommu_v2_supported())
2519 memset(info, 0, sizeof(*info));
2521 if (pci_ats_supported(pdev))
2522 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
2524 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2526 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
2528 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
2532 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
2533 max_pasids = min(max_pasids, (1 << 20));
2535 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
2536 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
2538 features = pci_pasid_features(pdev);
2539 if (features & PCI_PASID_CAP_EXEC)
2540 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
2541 if (features & PCI_PASID_CAP_PRIV)
2542 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
2547 EXPORT_SYMBOL(amd_iommu_device_info);
2549 #ifdef CONFIG_IRQ_REMAP
2551 /*****************************************************************************
2553 * Interrupt Remapping Implementation
2555 *****************************************************************************/
2557 static struct irq_chip amd_ir_chip;
2558 static DEFINE_SPINLOCK(iommu_table_lock);
2560 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
2564 dte = amd_iommu_dev_table[devid].data[2];
2565 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
2566 dte |= iommu_virt_to_phys(table->table);
2567 dte |= DTE_IRQ_REMAP_INTCTL;
2568 dte |= DTE_INTTABLEN;
2569 dte |= DTE_IRQ_REMAP_ENABLE;
2571 amd_iommu_dev_table[devid].data[2] = dte;
2574 static struct irq_remap_table *get_irq_table(u16 devid)
2576 struct irq_remap_table *table;
2578 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
2579 "%s: no iommu for devid %x\n", __func__, devid))
2582 table = irq_lookup_table[devid];
2583 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
2589 static struct irq_remap_table *__alloc_irq_table(void)
2591 struct irq_remap_table *table;
2593 table = kzalloc(sizeof(*table), GFP_KERNEL);
2597 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
2598 if (!table->table) {
2602 raw_spin_lock_init(&table->lock);
2604 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2605 memset(table->table, 0,
2606 MAX_IRQS_PER_TABLE * sizeof(u32));
2608 memset(table->table, 0,
2609 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
2613 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
2614 struct irq_remap_table *table)
2616 irq_lookup_table[devid] = table;
2617 set_dte_irq_entry(devid, table);
2618 iommu_flush_dte(iommu, devid);
2621 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
2624 struct irq_remap_table *table = data;
2626 irq_lookup_table[alias] = table;
2627 set_dte_irq_entry(alias, table);
2629 iommu_flush_dte(amd_iommu_rlookup_table[alias], alias);
2634 static struct irq_remap_table *alloc_irq_table(u16 devid, struct pci_dev *pdev)
2636 struct irq_remap_table *table = NULL;
2637 struct irq_remap_table *new_table = NULL;
2638 struct amd_iommu *iommu;
2639 unsigned long flags;
2642 spin_lock_irqsave(&iommu_table_lock, flags);
2644 iommu = amd_iommu_rlookup_table[devid];
2648 table = irq_lookup_table[devid];
2652 alias = amd_iommu_alias_table[devid];
2653 table = irq_lookup_table[alias];
2655 set_remap_table_entry(iommu, devid, table);
2658 spin_unlock_irqrestore(&iommu_table_lock, flags);
2660 /* Nothing there yet, allocate new irq remapping table */
2661 new_table = __alloc_irq_table();
2665 spin_lock_irqsave(&iommu_table_lock, flags);
2667 table = irq_lookup_table[devid];
2671 table = irq_lookup_table[alias];
2673 set_remap_table_entry(iommu, devid, table);
2681 pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
2684 set_remap_table_entry(iommu, devid, table);
2687 set_remap_table_entry(iommu, alias, table);
2690 iommu_completion_wait(iommu);
2693 spin_unlock_irqrestore(&iommu_table_lock, flags);
2696 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
2702 static int alloc_irq_index(u16 devid, int count, bool align,
2703 struct pci_dev *pdev)
2705 struct irq_remap_table *table;
2706 int index, c, alignment = 1;
2707 unsigned long flags;
2708 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2713 table = alloc_irq_table(devid, pdev);
2718 alignment = roundup_pow_of_two(count);
2720 raw_spin_lock_irqsave(&table->lock, flags);
2722 /* Scan table for free entries */
2723 for (index = ALIGN(table->min_index, alignment), c = 0;
2724 index < MAX_IRQS_PER_TABLE;) {
2725 if (!iommu->irte_ops->is_allocated(table, index)) {
2729 index = ALIGN(index + 1, alignment);
2735 iommu->irte_ops->set_allocated(table, index - c + 1);
2747 raw_spin_unlock_irqrestore(&table->lock, flags);
2752 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
2753 struct amd_ir_data *data)
2756 struct irq_remap_table *table;
2757 struct amd_iommu *iommu;
2758 unsigned long flags;
2759 struct irte_ga *entry;
2761 iommu = amd_iommu_rlookup_table[devid];
2765 table = get_irq_table(devid);
2769 raw_spin_lock_irqsave(&table->lock, flags);
2771 entry = (struct irte_ga *)table->table;
2772 entry = &entry[index];
2774 ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
2775 entry->lo.val, entry->hi.val,
2776 irte->lo.val, irte->hi.val);
2778 * We use cmpxchg16 to atomically update the 128-bit IRTE,
2779 * and it cannot be updated by the hardware or other processors
2780 * behind us, so the return value of cmpxchg16 should be the
2781 * same as the old value.
2788 raw_spin_unlock_irqrestore(&table->lock, flags);
2790 iommu_flush_irt(iommu, devid);
2791 iommu_completion_wait(iommu);
2796 static int modify_irte(u16 devid, int index, union irte *irte)
2798 struct irq_remap_table *table;
2799 struct amd_iommu *iommu;
2800 unsigned long flags;
2802 iommu = amd_iommu_rlookup_table[devid];
2806 table = get_irq_table(devid);
2810 raw_spin_lock_irqsave(&table->lock, flags);
2811 table->table[index] = irte->val;
2812 raw_spin_unlock_irqrestore(&table->lock, flags);
2814 iommu_flush_irt(iommu, devid);
2815 iommu_completion_wait(iommu);
2820 static void free_irte(u16 devid, int index)
2822 struct irq_remap_table *table;
2823 struct amd_iommu *iommu;
2824 unsigned long flags;
2826 iommu = amd_iommu_rlookup_table[devid];
2830 table = get_irq_table(devid);
2834 raw_spin_lock_irqsave(&table->lock, flags);
2835 iommu->irte_ops->clear_allocated(table, index);
2836 raw_spin_unlock_irqrestore(&table->lock, flags);
2838 iommu_flush_irt(iommu, devid);
2839 iommu_completion_wait(iommu);
2842 static void irte_prepare(void *entry,
2843 u32 delivery_mode, bool dest_mode,
2844 u8 vector, u32 dest_apicid, int devid)
2846 union irte *irte = (union irte *) entry;
2849 irte->fields.vector = vector;
2850 irte->fields.int_type = delivery_mode;
2851 irte->fields.destination = dest_apicid;
2852 irte->fields.dm = dest_mode;
2853 irte->fields.valid = 1;
2856 static void irte_ga_prepare(void *entry,
2857 u32 delivery_mode, bool dest_mode,
2858 u8 vector, u32 dest_apicid, int devid)
2860 struct irte_ga *irte = (struct irte_ga *) entry;
2864 irte->lo.fields_remap.int_type = delivery_mode;
2865 irte->lo.fields_remap.dm = dest_mode;
2866 irte->hi.fields.vector = vector;
2867 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
2868 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
2869 irte->lo.fields_remap.valid = 1;
2872 static void irte_activate(void *entry, u16 devid, u16 index)
2874 union irte *irte = (union irte *) entry;
2876 irte->fields.valid = 1;
2877 modify_irte(devid, index, irte);
2880 static void irte_ga_activate(void *entry, u16 devid, u16 index)
2882 struct irte_ga *irte = (struct irte_ga *) entry;
2884 irte->lo.fields_remap.valid = 1;
2885 modify_irte_ga(devid, index, irte, NULL);
2888 static void irte_deactivate(void *entry, u16 devid, u16 index)
2890 union irte *irte = (union irte *) entry;
2892 irte->fields.valid = 0;
2893 modify_irte(devid, index, irte);
2896 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
2898 struct irte_ga *irte = (struct irte_ga *) entry;
2900 irte->lo.fields_remap.valid = 0;
2901 modify_irte_ga(devid, index, irte, NULL);
2904 static void irte_set_affinity(void *entry, u16 devid, u16 index,
2905 u8 vector, u32 dest_apicid)
2907 union irte *irte = (union irte *) entry;
2909 irte->fields.vector = vector;
2910 irte->fields.destination = dest_apicid;
2911 modify_irte(devid, index, irte);
2914 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
2915 u8 vector, u32 dest_apicid)
2917 struct irte_ga *irte = (struct irte_ga *) entry;
2919 if (!irte->lo.fields_remap.guest_mode) {
2920 irte->hi.fields.vector = vector;
2921 irte->lo.fields_remap.destination =
2922 APICID_TO_IRTE_DEST_LO(dest_apicid);
2923 irte->hi.fields.destination =
2924 APICID_TO_IRTE_DEST_HI(dest_apicid);
2925 modify_irte_ga(devid, index, irte, NULL);
2929 #define IRTE_ALLOCATED (~1U)
2930 static void irte_set_allocated(struct irq_remap_table *table, int index)
2932 table->table[index] = IRTE_ALLOCATED;
2935 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
2937 struct irte_ga *ptr = (struct irte_ga *)table->table;
2938 struct irte_ga *irte = &ptr[index];
2940 memset(&irte->lo.val, 0, sizeof(u64));
2941 memset(&irte->hi.val, 0, sizeof(u64));
2942 irte->hi.fields.vector = 0xff;
2945 static bool irte_is_allocated(struct irq_remap_table *table, int index)
2947 union irte *ptr = (union irte *)table->table;
2948 union irte *irte = &ptr[index];
2950 return irte->val != 0;
2953 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
2955 struct irte_ga *ptr = (struct irte_ga *)table->table;
2956 struct irte_ga *irte = &ptr[index];
2958 return irte->hi.fields.vector != 0;
2961 static void irte_clear_allocated(struct irq_remap_table *table, int index)
2963 table->table[index] = 0;
2966 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
2968 struct irte_ga *ptr = (struct irte_ga *)table->table;
2969 struct irte_ga *irte = &ptr[index];
2971 memset(&irte->lo.val, 0, sizeof(u64));
2972 memset(&irte->hi.val, 0, sizeof(u64));
2975 static int get_devid(struct irq_alloc_info *info)
2977 switch (info->type) {
2978 case X86_IRQ_ALLOC_TYPE_IOAPIC:
2979 return get_ioapic_devid(info->devid);
2980 case X86_IRQ_ALLOC_TYPE_HPET:
2981 return get_hpet_devid(info->devid);
2982 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
2983 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
2984 return get_device_id(msi_desc_to_dev(info->desc));
2991 struct irq_remap_ops amd_iommu_irq_ops = {
2992 .prepare = amd_iommu_prepare,
2993 .enable = amd_iommu_enable,
2994 .disable = amd_iommu_disable,
2995 .reenable = amd_iommu_reenable,
2996 .enable_faulting = amd_iommu_enable_faulting,
2999 static void fill_msi_msg(struct msi_msg *msg, u32 index)
3002 msg->address_lo = 0;
3003 msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
3004 msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
3007 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3008 struct irq_cfg *irq_cfg,
3009 struct irq_alloc_info *info,
3010 int devid, int index, int sub_handle)
3012 struct irq_2_irte *irte_info = &data->irq_2_irte;
3013 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3018 data->irq_2_irte.devid = devid;
3019 data->irq_2_irte.index = index + sub_handle;
3020 iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
3021 apic->dest_mode_logical, irq_cfg->vector,
3022 irq_cfg->dest_apicid, devid);
3024 switch (info->type) {
3025 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3026 case X86_IRQ_ALLOC_TYPE_HPET:
3027 case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3028 case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3029 fill_msi_msg(&data->msi_entry, irte_info->index);
3038 struct amd_irte_ops irte_32_ops = {
3039 .prepare = irte_prepare,
3040 .activate = irte_activate,
3041 .deactivate = irte_deactivate,
3042 .set_affinity = irte_set_affinity,
3043 .set_allocated = irte_set_allocated,
3044 .is_allocated = irte_is_allocated,
3045 .clear_allocated = irte_clear_allocated,
3048 struct amd_irte_ops irte_128_ops = {
3049 .prepare = irte_ga_prepare,
3050 .activate = irte_ga_activate,
3051 .deactivate = irte_ga_deactivate,
3052 .set_affinity = irte_ga_set_affinity,
3053 .set_allocated = irte_ga_set_allocated,
3054 .is_allocated = irte_ga_is_allocated,
3055 .clear_allocated = irte_ga_clear_allocated,
3058 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3059 unsigned int nr_irqs, void *arg)
3061 struct irq_alloc_info *info = arg;
3062 struct irq_data *irq_data;
3063 struct amd_ir_data *data = NULL;
3064 struct irq_cfg *cfg;
3070 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3071 info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3075 * With IRQ remapping enabled, don't need contiguous CPU vectors
3076 * to support multiple MSI interrupts.
3078 if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3079 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3081 devid = get_devid(info);
3085 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3089 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3090 struct irq_remap_table *table;
3091 struct amd_iommu *iommu;
3093 table = alloc_irq_table(devid, NULL);
3095 if (!table->min_index) {
3097 * Keep the first 32 indexes free for IOAPIC
3100 table->min_index = 32;
3101 iommu = amd_iommu_rlookup_table[devid];
3102 for (i = 0; i < 32; ++i)
3103 iommu->irte_ops->set_allocated(table, i);
3105 WARN_ON(table->min_index != 32);
3106 index = info->ioapic.pin;
3110 } else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3111 info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3112 bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3114 index = alloc_irq_index(devid, nr_irqs, align,
3115 msi_desc_to_pci_dev(info->desc));
3117 index = alloc_irq_index(devid, nr_irqs, false, NULL);
3121 pr_warn("Failed to allocate IRTE\n");
3123 goto out_free_parent;
3126 for (i = 0; i < nr_irqs; i++) {
3127 irq_data = irq_domain_get_irq_data(domain, virq + i);
3128 cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3135 data = kzalloc(sizeof(*data), GFP_KERNEL);
3139 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3140 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3142 data->entry = kzalloc(sizeof(struct irte_ga),
3149 irq_data->hwirq = (devid << 16) + i;
3150 irq_data->chip_data = data;
3151 irq_data->chip = &amd_ir_chip;
3152 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3153 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3159 for (i--; i >= 0; i--) {
3160 irq_data = irq_domain_get_irq_data(domain, virq + i);
3162 kfree(irq_data->chip_data);
3164 for (i = 0; i < nr_irqs; i++)
3165 free_irte(devid, index + i);
3167 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3171 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3172 unsigned int nr_irqs)
3174 struct irq_2_irte *irte_info;
3175 struct irq_data *irq_data;
3176 struct amd_ir_data *data;
3179 for (i = 0; i < nr_irqs; i++) {
3180 irq_data = irq_domain_get_irq_data(domain, virq + i);
3181 if (irq_data && irq_data->chip_data) {
3182 data = irq_data->chip_data;
3183 irte_info = &data->irq_2_irte;
3184 free_irte(irte_info->devid, irte_info->index);
3189 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3192 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3193 struct amd_ir_data *ir_data,
3194 struct irq_2_irte *irte_info,
3195 struct irq_cfg *cfg);
3197 static int irq_remapping_activate(struct irq_domain *domain,
3198 struct irq_data *irq_data, bool reserve)
3200 struct amd_ir_data *data = irq_data->chip_data;
3201 struct irq_2_irte *irte_info = &data->irq_2_irte;
3202 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3203 struct irq_cfg *cfg = irqd_cfg(irq_data);
3208 iommu->irte_ops->activate(data->entry, irte_info->devid,
3210 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3214 static void irq_remapping_deactivate(struct irq_domain *domain,
3215 struct irq_data *irq_data)
3217 struct amd_ir_data *data = irq_data->chip_data;
3218 struct irq_2_irte *irte_info = &data->irq_2_irte;
3219 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3222 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
3226 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
3227 enum irq_domain_bus_token bus_token)
3229 struct amd_iommu *iommu;
3232 if (!amd_iommu_irq_remap)
3235 if (x86_fwspec_is_ioapic(fwspec))
3236 devid = get_ioapic_devid(fwspec->param[0]);
3237 else if (x86_fwspec_is_hpet(fwspec))
3238 devid = get_hpet_devid(fwspec->param[0]);
3243 iommu = amd_iommu_rlookup_table[devid];
3244 return iommu && iommu->ir_domain == d;
3247 static const struct irq_domain_ops amd_ir_domain_ops = {
3248 .select = irq_remapping_select,
3249 .alloc = irq_remapping_alloc,
3250 .free = irq_remapping_free,
3251 .activate = irq_remapping_activate,
3252 .deactivate = irq_remapping_deactivate,
3255 int amd_iommu_activate_guest_mode(void *data)
3257 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3258 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3261 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3262 !entry || entry->lo.fields_vapic.guest_mode)
3265 valid = entry->lo.fields_vapic.valid;
3270 entry->lo.fields_vapic.valid = valid;
3271 entry->lo.fields_vapic.guest_mode = 1;
3272 entry->lo.fields_vapic.ga_log_intr = 1;
3273 entry->hi.fields.ga_root_ptr = ir_data->ga_root_ptr;
3274 entry->hi.fields.vector = ir_data->ga_vector;
3275 entry->lo.fields_vapic.ga_tag = ir_data->ga_tag;
3277 return modify_irte_ga(ir_data->irq_2_irte.devid,
3278 ir_data->irq_2_irte.index, entry, ir_data);
3280 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3282 int amd_iommu_deactivate_guest_mode(void *data)
3284 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3285 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3286 struct irq_cfg *cfg = ir_data->cfg;
3289 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3290 !entry || !entry->lo.fields_vapic.guest_mode)
3293 valid = entry->lo.fields_remap.valid;
3298 entry->lo.fields_remap.valid = valid;
3299 entry->lo.fields_remap.dm = apic->dest_mode_logical;
3300 entry->lo.fields_remap.int_type = apic->delivery_mode;
3301 entry->hi.fields.vector = cfg->vector;
3302 entry->lo.fields_remap.destination =
3303 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3304 entry->hi.fields.destination =
3305 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3307 return modify_irte_ga(ir_data->irq_2_irte.devid,
3308 ir_data->irq_2_irte.index, entry, ir_data);
3310 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3312 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3315 struct amd_iommu *iommu;
3316 struct amd_iommu_pi_data *pi_data = vcpu_info;
3317 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3318 struct amd_ir_data *ir_data = data->chip_data;
3319 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3320 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
3323 * This device has never been set up for guest mode.
3324 * we should not modify the IRTE
3326 if (!dev_data || !dev_data->use_vapic)
3329 ir_data->cfg = irqd_cfg(data);
3330 pi_data->ir_data = ir_data;
3333 * SVM tries to set up for VAPIC mode, but we are in
3334 * legacy mode. So, we force legacy mode instead.
3336 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3337 pr_debug("%s: Fall back to using intr legacy remap\n",
3339 pi_data->is_guest_mode = false;
3342 iommu = amd_iommu_rlookup_table[irte_info->devid];
3346 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3347 if (pi_data->is_guest_mode) {
3348 ir_data->ga_root_ptr = (pi_data->base >> 12);
3349 ir_data->ga_vector = vcpu_pi_info->vector;
3350 ir_data->ga_tag = pi_data->ga_tag;
3351 ret = amd_iommu_activate_guest_mode(ir_data);
3353 ir_data->cached_ga_tag = pi_data->ga_tag;
3355 ret = amd_iommu_deactivate_guest_mode(ir_data);
3358 * This communicates the ga_tag back to the caller
3359 * so that it can do all the necessary clean up.
3362 ir_data->cached_ga_tag = 0;
3369 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3370 struct amd_ir_data *ir_data,
3371 struct irq_2_irte *irte_info,
3372 struct irq_cfg *cfg)
3376 * Atomically updates the IRTE with the new destination, vector
3377 * and flushes the interrupt entry cache.
3379 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
3380 irte_info->index, cfg->vector,
3384 static int amd_ir_set_affinity(struct irq_data *data,
3385 const struct cpumask *mask, bool force)
3387 struct amd_ir_data *ir_data = data->chip_data;
3388 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3389 struct irq_cfg *cfg = irqd_cfg(data);
3390 struct irq_data *parent = data->parent_data;
3391 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
3397 ret = parent->chip->irq_set_affinity(parent, mask, force);
3398 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3401 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3403 * After this point, all the interrupts will start arriving
3404 * at the new destination. So, time to cleanup the previous
3405 * vector allocation.
3407 send_cleanup_vector(cfg);
3409 return IRQ_SET_MASK_OK_DONE;
3412 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3414 struct amd_ir_data *ir_data = irq_data->chip_data;
3416 *msg = ir_data->msi_entry;
3419 static struct irq_chip amd_ir_chip = {
3421 .irq_ack = apic_ack_irq,
3422 .irq_set_affinity = amd_ir_set_affinity,
3423 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
3424 .irq_compose_msi_msg = ir_compose_msi_msg,
3427 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3429 struct fwnode_handle *fn;
3431 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3434 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3435 if (!iommu->ir_domain) {
3436 irq_domain_free_fwnode(fn);
3440 iommu->ir_domain->parent = arch_get_ir_parent_domain();
3441 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3447 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3449 unsigned long flags;
3450 struct amd_iommu *iommu;
3451 struct irq_remap_table *table;
3452 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3453 int devid = ir_data->irq_2_irte.devid;
3454 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3455 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
3457 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3458 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
3461 iommu = amd_iommu_rlookup_table[devid];
3465 table = get_irq_table(devid);
3469 raw_spin_lock_irqsave(&table->lock, flags);
3471 if (ref->lo.fields_vapic.guest_mode) {
3473 ref->lo.fields_vapic.destination =
3474 APICID_TO_IRTE_DEST_LO(cpu);
3475 ref->hi.fields.destination =
3476 APICID_TO_IRTE_DEST_HI(cpu);
3478 ref->lo.fields_vapic.is_run = is_run;
3482 raw_spin_unlock_irqrestore(&table->lock, flags);
3484 iommu_flush_irt(iommu, devid);
3485 iommu_completion_wait(iommu);
3488 EXPORT_SYMBOL(amd_iommu_update_ga);