1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
11 #include <linux/pci.h>
12 #include <linux/acpi.h>
13 #include <linux/list.h>
14 #include <linux/bitmap.h>
15 #include <linux/slab.h>
16 #include <linux/syscore_ops.h>
17 #include <linux/interrupt.h>
18 #include <linux/msi.h>
19 #include <linux/amd-iommu.h>
20 #include <linux/export.h>
21 #include <linux/kmemleak.h>
22 #include <linux/mem_encrypt.h>
23 #include <asm/pci-direct.h>
24 #include <asm/iommu.h>
26 #include <asm/msidef.h>
28 #include <asm/x86_init.h>
29 #include <asm/iommu_table.h>
30 #include <asm/io_apic.h>
31 #include <asm/irq_remapping.h>
32 #include <asm/set_memory.h>
34 #include <linux/crash_dump.h>
36 #include "amd_iommu.h"
37 #include "../irq_remapping.h"
40 * definitions for the ACPI scanning code
42 #define IVRS_HEADER_LENGTH 48
44 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
45 #define ACPI_IVMD_TYPE_ALL 0x20
46 #define ACPI_IVMD_TYPE 0x21
47 #define ACPI_IVMD_TYPE_RANGE 0x22
49 #define IVHD_DEV_ALL 0x01
50 #define IVHD_DEV_SELECT 0x02
51 #define IVHD_DEV_SELECT_RANGE_START 0x03
52 #define IVHD_DEV_RANGE_END 0x04
53 #define IVHD_DEV_ALIAS 0x42
54 #define IVHD_DEV_ALIAS_RANGE 0x43
55 #define IVHD_DEV_EXT_SELECT 0x46
56 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
57 #define IVHD_DEV_SPECIAL 0x48
58 #define IVHD_DEV_ACPI_HID 0xf0
60 #define UID_NOT_PRESENT 0
61 #define UID_IS_INTEGER 1
62 #define UID_IS_CHARACTER 2
64 #define IVHD_SPECIAL_IOAPIC 1
65 #define IVHD_SPECIAL_HPET 2
67 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
68 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
69 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
70 #define IVHD_FLAG_ISOC_EN_MASK 0x08
72 #define IVMD_FLAG_EXCL_RANGE 0x08
73 #define IVMD_FLAG_IW 0x04
74 #define IVMD_FLAG_IR 0x02
75 #define IVMD_FLAG_UNITY_MAP 0x01
77 #define ACPI_DEVFLAG_INITPASS 0x01
78 #define ACPI_DEVFLAG_EXTINT 0x02
79 #define ACPI_DEVFLAG_NMI 0x04
80 #define ACPI_DEVFLAG_SYSMGT1 0x10
81 #define ACPI_DEVFLAG_SYSMGT2 0x20
82 #define ACPI_DEVFLAG_LINT0 0x40
83 #define ACPI_DEVFLAG_LINT1 0x80
84 #define ACPI_DEVFLAG_ATSDIS 0x10000000
86 #define LOOP_TIMEOUT 100000
88 * ACPI table definitions
90 * These data structures are laid over the table to parse the important values
94 extern const struct iommu_ops amd_iommu_ops;
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
98 * or more ivhd_entrys.
111 /* Following only valid on IVHD type 11h and 40h */
112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
114 } __attribute__((packed));
117 * A device entry describing which devices a specific IOMMU translates and
118 * which requestor ids they use.
130 } __attribute__((packed));
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
134 * ranges for devices and regions that should be unity mapped.
145 } __attribute__((packed));
148 bool amd_iommu_irq_remap __read_mostly;
150 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
151 static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
153 static bool amd_iommu_detected;
154 static bool __initdata amd_iommu_disabled;
155 static int amd_iommu_target_ivhd_type;
157 u16 amd_iommu_last_bdf; /* largest PCI device id we have
159 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
161 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
163 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
166 /* Array to assign indices to IOMMUs*/
167 struct amd_iommu *amd_iommus[MAX_IOMMUS];
169 /* Number of IOMMUs present in the system */
170 static int amd_iommus_present;
172 /* IOMMUs have a non-present cache? */
173 bool amd_iommu_np_cache __read_mostly;
174 bool amd_iommu_iotlb_sup __read_mostly = true;
176 u32 amd_iommu_max_pasid __read_mostly = ~0;
178 bool amd_iommu_v2_present __read_mostly;
179 static bool amd_iommu_pc_present __read_mostly;
181 bool amd_iommu_force_isolation __read_mostly;
184 * Pointer to the device table which is shared by all AMD IOMMUs
185 * it is indexed by the PCI device id or the HT unit id and contains
186 * information about the domain the device belongs to as well as the
187 * page table root pointer.
189 struct dev_table_entry *amd_iommu_dev_table;
191 * Pointer to a device table which the content of old device table
192 * will be copied to. It's only be used in kdump kernel.
194 static struct dev_table_entry *old_dev_tbl_cpy;
197 * The alias table is a driver specific data structure which contains the
198 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
199 * More than one device can share the same requestor id.
201 u16 *amd_iommu_alias_table;
204 * The rlookup table is used to find the IOMMU which is responsible
205 * for a specific device. It is also indexed by the PCI device id.
207 struct amd_iommu **amd_iommu_rlookup_table;
208 EXPORT_SYMBOL(amd_iommu_rlookup_table);
211 * This table is used to find the irq remapping table for a given device id
214 struct irq_remap_table **irq_lookup_table;
217 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
218 * to know which ones are already in use.
220 unsigned long *amd_iommu_pd_alloc_bitmap;
222 static u32 dev_table_size; /* size of the device table */
223 static u32 alias_table_size; /* size of the alias table */
224 static u32 rlookup_table_size; /* size if the rlookup table */
226 enum iommu_init_state {
237 IOMMU_CMDLINE_DISABLED,
240 /* Early ioapic and hpet maps from kernel command line */
241 #define EARLY_MAP_SIZE 4
242 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
243 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
244 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
246 static int __initdata early_ioapic_map_size;
247 static int __initdata early_hpet_map_size;
248 static int __initdata early_acpihid_map_size;
250 static bool __initdata cmdline_maps;
252 static enum iommu_init_state init_state = IOMMU_START_STATE;
254 static int amd_iommu_enable_interrupts(void);
255 static int __init iommu_go_to_state(enum iommu_init_state state);
256 static void init_device_table_dma(void);
258 static bool amd_iommu_pre_enabled = true;
260 bool translation_pre_enabled(struct amd_iommu *iommu)
262 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED);
264 EXPORT_SYMBOL(translation_pre_enabled);
266 static void clear_translation_pre_enabled(struct amd_iommu *iommu)
268 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
271 static void init_translation_status(struct amd_iommu *iommu)
275 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
276 if (ctrl & (1<<CONTROL_IOMMU_EN))
277 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED;
280 static inline void update_last_devid(u16 devid)
282 if (devid > amd_iommu_last_bdf)
283 amd_iommu_last_bdf = devid;
286 static inline unsigned long tbl_size(int entry_size)
288 unsigned shift = PAGE_SHIFT +
289 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
294 int amd_iommu_get_num_iommus(void)
296 return amd_iommus_present;
299 /* Access to l1 and l2 indexed register spaces */
301 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
305 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
306 pci_read_config_dword(iommu->dev, 0xfc, &val);
310 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
312 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
313 pci_write_config_dword(iommu->dev, 0xfc, val);
314 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
317 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
321 pci_write_config_dword(iommu->dev, 0xf0, address);
322 pci_read_config_dword(iommu->dev, 0xf4, &val);
326 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
328 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
329 pci_write_config_dword(iommu->dev, 0xf4, val);
332 /****************************************************************************
334 * AMD IOMMU MMIO register space handling functions
336 * These functions are used to program the IOMMU device registers in
337 * MMIO space required for that driver.
339 ****************************************************************************/
342 * This function set the exclusion range in the IOMMU. DMA accesses to the
343 * exclusion range are passed through untranslated
345 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
347 u64 start = iommu->exclusion_start & PAGE_MASK;
348 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
351 if (!iommu->exclusion_start)
354 entry = start | MMIO_EXCL_ENABLE_MASK;
355 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
356 &entry, sizeof(entry));
359 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
360 &entry, sizeof(entry));
363 static void iommu_set_cwwb_range(struct amd_iommu *iommu)
365 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem);
366 u64 entry = start & PM_ADDR_MASK;
368 if (!iommu_feature(iommu, FEATURE_SNP))
372 * Re-purpose Exclusion base/limit registers for Completion wait
373 * write-back base/limit.
375 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
376 &entry, sizeof(entry));
379 * Default to 4 Kbytes, which can be specified by setting base
380 * address equal to the limit address.
382 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
383 &entry, sizeof(entry));
386 /* Programs the physical address of the device table into the IOMMU hardware */
387 static void iommu_set_device_table(struct amd_iommu *iommu)
391 BUG_ON(iommu->mmio_base == NULL);
393 entry = iommu_virt_to_phys(amd_iommu_dev_table);
394 entry |= (dev_table_size >> 12) - 1;
395 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
396 &entry, sizeof(entry));
399 /* Generic functions to enable/disable certain features of the IOMMU. */
400 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
404 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
405 ctrl |= (1ULL << bit);
406 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
409 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
413 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
414 ctrl &= ~(1ULL << bit);
415 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
418 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
422 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET);
423 ctrl &= ~CTRL_INV_TO_MASK;
424 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
425 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
428 /* Function to enable the hardware */
429 static void iommu_enable(struct amd_iommu *iommu)
431 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
434 static void iommu_disable(struct amd_iommu *iommu)
436 if (!iommu->mmio_base)
439 /* Disable command buffer */
440 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
442 /* Disable event logging and event interrupts */
443 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
444 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
446 /* Disable IOMMU GA_LOG */
447 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
448 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
450 /* Disable IOMMU hardware itself */
451 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
455 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
456 * the system has one.
458 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
460 if (!request_mem_region(address, end, "amd_iommu")) {
461 pr_err("Can not reserve memory region %llx-%llx for mmio\n",
463 pr_err("This is a BIOS bug. Please contact your hardware vendor\n");
467 return (u8 __iomem *)ioremap(address, end);
470 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
472 if (iommu->mmio_base)
473 iounmap(iommu->mmio_base);
474 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
477 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
493 /****************************************************************************
495 * The functions below belong to the first pass of AMD IOMMU ACPI table
496 * parsing. In this pass we try to find out the highest device id this
497 * code has to handle. Upon this information the size of the shared data
498 * structures is determined later.
500 ****************************************************************************/
503 * This function calculates the length of a given IVHD entry
505 static inline int ivhd_entry_length(u8 *ivhd)
507 u32 type = ((struct ivhd_entry *)ivhd)->type;
510 return 0x04 << (*ivhd >> 6);
511 } else if (type == IVHD_DEV_ACPI_HID) {
512 /* For ACPI_HID, offset 21 is uid len */
513 return *((u8 *)ivhd + 21) + 22;
519 * After reading the highest device id from the IOMMU PCI capability header
520 * this function looks if there is a higher device id defined in the ACPI table
522 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
524 u8 *p = (void *)h, *end = (void *)h;
525 struct ivhd_entry *dev;
527 u32 ivhd_size = get_ivhd_header_size(h);
530 pr_err("Unsupported IVHD type %#x\n", h->type);
538 dev = (struct ivhd_entry *)p;
541 /* Use maximum BDF value for DEV_ALL */
542 update_last_devid(0xffff);
544 case IVHD_DEV_SELECT:
545 case IVHD_DEV_RANGE_END:
547 case IVHD_DEV_EXT_SELECT:
548 /* all the above subfield types refer to device ids */
549 update_last_devid(dev->devid);
554 p += ivhd_entry_length(p);
562 static int __init check_ivrs_checksum(struct acpi_table_header *table)
565 u8 checksum = 0, *p = (u8 *)table;
567 for (i = 0; i < table->length; ++i)
570 /* ACPI table corrupt */
571 pr_err(FW_BUG "IVRS invalid checksum\n");
579 * Iterate over all IVHD entries in the ACPI table and find the highest device
580 * id which we need to handle. This is the first of three functions which parse
581 * the ACPI table. So we check the checksum here.
583 static int __init find_last_devid_acpi(struct acpi_table_header *table)
585 u8 *p = (u8 *)table, *end = (u8 *)table;
586 struct ivhd_header *h;
588 p += IVRS_HEADER_LENGTH;
590 end += table->length;
592 h = (struct ivhd_header *)p;
593 if (h->type == amd_iommu_target_ivhd_type) {
594 int ret = find_last_devid_from_ivhd(h);
606 /****************************************************************************
608 * The following functions belong to the code path which parses the ACPI table
609 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
610 * data structures, initialize the device/alias/rlookup table and also
611 * basically initialize the hardware.
613 ****************************************************************************/
616 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
617 * write commands to that buffer later and the IOMMU will execute them
620 static int __init alloc_command_buffer(struct amd_iommu *iommu)
622 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
623 get_order(CMD_BUFFER_SIZE));
625 return iommu->cmd_buf ? 0 : -ENOMEM;
629 * This function resets the command buffer if the IOMMU stopped fetching
632 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
634 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
636 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
637 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
638 iommu->cmd_buf_head = 0;
639 iommu->cmd_buf_tail = 0;
641 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
645 * This function writes the command buffer address to the hardware and
648 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
652 BUG_ON(iommu->cmd_buf == NULL);
654 entry = iommu_virt_to_phys(iommu->cmd_buf);
655 entry |= MMIO_CMD_SIZE_512;
657 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
658 &entry, sizeof(entry));
660 amd_iommu_reset_cmd_buffer(iommu);
664 * This function disables the command buffer
666 static void iommu_disable_command_buffer(struct amd_iommu *iommu)
668 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
671 static void __init free_command_buffer(struct amd_iommu *iommu)
673 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
676 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
677 gfp_t gfp, size_t size)
679 int order = get_order(size);
680 void *buf = (void *)__get_free_pages(gfp, order);
683 iommu_feature(iommu, FEATURE_SNP) &&
684 set_memory_4k((unsigned long)buf, (1 << order))) {
685 free_pages((unsigned long)buf, order);
692 /* allocates the memory where the IOMMU will log its events to */
693 static int __init alloc_event_buffer(struct amd_iommu *iommu)
695 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO,
698 return iommu->evt_buf ? 0 : -ENOMEM;
701 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
705 BUG_ON(iommu->evt_buf == NULL);
707 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
709 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
710 &entry, sizeof(entry));
712 /* set head and tail to zero manually */
713 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
714 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
716 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
720 * This function disables the event log buffer
722 static void iommu_disable_event_buffer(struct amd_iommu *iommu)
724 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
727 static void __init free_event_buffer(struct amd_iommu *iommu)
729 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
732 /* allocates the memory where the IOMMU will log its events to */
733 static int __init alloc_ppr_log(struct amd_iommu *iommu)
735 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO,
738 return iommu->ppr_log ? 0 : -ENOMEM;
741 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
745 if (iommu->ppr_log == NULL)
748 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
750 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
751 &entry, sizeof(entry));
753 /* set head and tail to zero manually */
754 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
755 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
757 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN);
758 iommu_feature_enable(iommu, CONTROL_PPR_EN);
761 static void __init free_ppr_log(struct amd_iommu *iommu)
763 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
766 static void free_ga_log(struct amd_iommu *iommu)
768 #ifdef CONFIG_IRQ_REMAP
769 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE));
770 free_pages((unsigned long)iommu->ga_log_tail, get_order(8));
774 static int iommu_ga_log_enable(struct amd_iommu *iommu)
776 #ifdef CONFIG_IRQ_REMAP
782 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
784 /* Check if already running */
785 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
788 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
789 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
791 for (i = 0; i < LOOP_TIMEOUT; ++i) {
792 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
793 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
797 if (i >= LOOP_TIMEOUT)
799 #endif /* CONFIG_IRQ_REMAP */
803 #ifdef CONFIG_IRQ_REMAP
804 static int iommu_init_ga_log(struct amd_iommu *iommu)
808 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
811 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
812 get_order(GA_LOG_SIZE));
816 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
818 if (!iommu->ga_log_tail)
821 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
822 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
823 &entry, sizeof(entry));
824 entry = (iommu_virt_to_phys(iommu->ga_log_tail) &
825 (BIT_ULL(52)-1)) & ~7ULL;
826 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
827 &entry, sizeof(entry));
828 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
829 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
836 #endif /* CONFIG_IRQ_REMAP */
838 static int iommu_init_ga(struct amd_iommu *iommu)
842 #ifdef CONFIG_IRQ_REMAP
843 /* Note: We have already checked GASup from IVRS table.
844 * Now, we need to make sure that GAMSup is set.
846 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
847 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
848 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
850 ret = iommu_init_ga_log(iommu);
851 #endif /* CONFIG_IRQ_REMAP */
856 static int __init alloc_cwwb_sem(struct amd_iommu *iommu)
858 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1);
860 return iommu->cmd_sem ? 0 : -ENOMEM;
863 static void __init free_cwwb_sem(struct amd_iommu *iommu)
866 free_page((unsigned long)iommu->cmd_sem);
869 static void iommu_enable_xt(struct amd_iommu *iommu)
871 #ifdef CONFIG_IRQ_REMAP
873 * XT mode (32-bit APIC destination ID) requires
874 * GA mode (128-bit IRTE support) as a prerequisite.
876 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir) &&
877 amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
878 iommu_feature_enable(iommu, CONTROL_XT_EN);
879 #endif /* CONFIG_IRQ_REMAP */
882 static void iommu_enable_gt(struct amd_iommu *iommu)
884 if (!iommu_feature(iommu, FEATURE_GT))
887 iommu_feature_enable(iommu, CONTROL_GT_EN);
890 /* sets a specific bit in the device table entry. */
891 static void set_dev_entry_bit(u16 devid, u8 bit)
893 int i = (bit >> 6) & 0x03;
894 int _bit = bit & 0x3f;
896 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
899 static int get_dev_entry_bit(u16 devid, u8 bit)
901 int i = (bit >> 6) & 0x03;
902 int _bit = bit & 0x3f;
904 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
908 static bool copy_device_table(void)
910 u64 int_ctl, int_tab_len, entry = 0, last_entry = 0;
911 struct dev_table_entry *old_devtb = NULL;
912 u32 lo, hi, devid, old_devtb_size;
913 phys_addr_t old_devtb_phys;
914 struct amd_iommu *iommu;
915 u16 dom_id, dte_v, irq_v;
919 if (!amd_iommu_pre_enabled)
922 pr_warn("Translation is already enabled - trying to copy translation structures\n");
923 for_each_iommu(iommu) {
924 /* All IOMMUs should use the same device table with the same size */
925 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET);
926 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4);
927 entry = (((u64) hi) << 32) + lo;
928 if (last_entry && last_entry != entry) {
929 pr_err("IOMMU:%d should use the same dev table as others!\n",
935 old_devtb_size = ((entry & ~PAGE_MASK) + 1) << 12;
936 if (old_devtb_size != dev_table_size) {
937 pr_err("The device table size of IOMMU:%d is not expected!\n",
944 * When SME is enabled in the first kernel, the entry includes the
945 * memory encryption mask(sme_me_mask), we must remove the memory
946 * encryption mask to obtain the true physical address in kdump kernel.
948 old_devtb_phys = __sme_clr(entry) & PAGE_MASK;
950 if (old_devtb_phys >= 0x100000000ULL) {
951 pr_err("The address of old device table is above 4G, not trustworthy!\n");
954 old_devtb = (sme_active() && is_kdump_kernel())
955 ? (__force void *)ioremap_encrypted(old_devtb_phys,
957 : memremap(old_devtb_phys, dev_table_size, MEMREMAP_WB);
962 gfp_flag = GFP_KERNEL | __GFP_ZERO | GFP_DMA32;
963 old_dev_tbl_cpy = (void *)__get_free_pages(gfp_flag,
964 get_order(dev_table_size));
965 if (old_dev_tbl_cpy == NULL) {
966 pr_err("Failed to allocate memory for copying old device table!\n");
970 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
971 old_dev_tbl_cpy[devid] = old_devtb[devid];
972 dom_id = old_devtb[devid].data[1] & DEV_DOMID_MASK;
973 dte_v = old_devtb[devid].data[0] & DTE_FLAG_V;
975 if (dte_v && dom_id) {
976 old_dev_tbl_cpy[devid].data[0] = old_devtb[devid].data[0];
977 old_dev_tbl_cpy[devid].data[1] = old_devtb[devid].data[1];
978 __set_bit(dom_id, amd_iommu_pd_alloc_bitmap);
979 /* If gcr3 table existed, mask it out */
980 if (old_devtb[devid].data[0] & DTE_FLAG_GV) {
981 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
982 tmp |= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
983 old_dev_tbl_cpy[devid].data[1] &= ~tmp;
984 tmp = DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A;
986 old_dev_tbl_cpy[devid].data[0] &= ~tmp;
990 irq_v = old_devtb[devid].data[2] & DTE_IRQ_REMAP_ENABLE;
991 int_ctl = old_devtb[devid].data[2] & DTE_IRQ_REMAP_INTCTL_MASK;
992 int_tab_len = old_devtb[devid].data[2] & DTE_IRQ_TABLE_LEN_MASK;
993 if (irq_v && (int_ctl || int_tab_len)) {
994 if ((int_ctl != DTE_IRQ_REMAP_INTCTL) ||
995 (int_tab_len != DTE_IRQ_TABLE_LEN)) {
996 pr_err("Wrong old irq remapping flag: %#x\n", devid);
1000 old_dev_tbl_cpy[devid].data[2] = old_devtb[devid].data[2];
1003 memunmap(old_devtb);
1008 void amd_iommu_apply_erratum_63(u16 devid)
1012 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
1013 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
1016 set_dev_entry_bit(devid, DEV_ENTRY_IW);
1019 /* Writes the specific IOMMU for a device into the rlookup table */
1020 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
1022 amd_iommu_rlookup_table[devid] = iommu;
1026 * This function takes the device specific flags read from the ACPI
1027 * table and sets up the device table entry with that information
1029 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
1030 u16 devid, u32 flags, u32 ext_flags)
1032 if (flags & ACPI_DEVFLAG_INITPASS)
1033 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
1034 if (flags & ACPI_DEVFLAG_EXTINT)
1035 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
1036 if (flags & ACPI_DEVFLAG_NMI)
1037 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
1038 if (flags & ACPI_DEVFLAG_SYSMGT1)
1039 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
1040 if (flags & ACPI_DEVFLAG_SYSMGT2)
1041 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
1042 if (flags & ACPI_DEVFLAG_LINT0)
1043 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
1044 if (flags & ACPI_DEVFLAG_LINT1)
1045 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
1047 amd_iommu_apply_erratum_63(devid);
1049 set_iommu_for_device(iommu, devid);
1052 int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
1054 struct devid_map *entry;
1055 struct list_head *list;
1057 if (type == IVHD_SPECIAL_IOAPIC)
1059 else if (type == IVHD_SPECIAL_HPET)
1064 list_for_each_entry(entry, list, list) {
1065 if (!(entry->id == id && entry->cmd_line))
1068 pr_info("Command-line override present for %s id %d - ignoring\n",
1069 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
1071 *devid = entry->devid;
1076 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1081 entry->devid = *devid;
1082 entry->cmd_line = cmd_line;
1084 list_add_tail(&entry->list, list);
1089 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
1092 struct acpihid_map_entry *entry;
1093 struct list_head *list = &acpihid_map;
1095 list_for_each_entry(entry, list, list) {
1096 if (strcmp(entry->hid, hid) ||
1097 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
1101 pr_info("Command-line override for hid:%s uid:%s\n",
1103 *devid = entry->devid;
1107 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
1111 memcpy(entry->uid, uid, strlen(uid));
1112 memcpy(entry->hid, hid, strlen(hid));
1113 entry->devid = *devid;
1114 entry->cmd_line = cmd_line;
1115 entry->root_devid = (entry->devid & (~0x7));
1117 pr_info("%s, add hid:%s, uid:%s, rdevid:%d\n",
1118 entry->cmd_line ? "cmd" : "ivrs",
1119 entry->hid, entry->uid, entry->root_devid);
1121 list_add_tail(&entry->list, list);
1125 static int __init add_early_maps(void)
1129 for (i = 0; i < early_ioapic_map_size; ++i) {
1130 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
1131 early_ioapic_map[i].id,
1132 &early_ioapic_map[i].devid,
1133 early_ioapic_map[i].cmd_line);
1138 for (i = 0; i < early_hpet_map_size; ++i) {
1139 ret = add_special_device(IVHD_SPECIAL_HPET,
1140 early_hpet_map[i].id,
1141 &early_hpet_map[i].devid,
1142 early_hpet_map[i].cmd_line);
1147 for (i = 0; i < early_acpihid_map_size; ++i) {
1148 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
1149 early_acpihid_map[i].uid,
1150 &early_acpihid_map[i].devid,
1151 early_acpihid_map[i].cmd_line);
1160 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1161 * initializes the hardware and our data structures with it.
1163 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
1164 struct ivhd_header *h)
1167 u8 *end = p, flags = 0;
1168 u16 devid = 0, devid_start = 0, devid_to = 0;
1169 u32 dev_i, ext_flags = 0;
1171 struct ivhd_entry *e;
1176 ret = add_early_maps();
1180 amd_iommu_apply_ivrs_quirks();
1183 * First save the recommended feature enable bits from ACPI
1185 iommu->acpi_flags = h->flags;
1188 * Done. Now parse the device entries
1190 ivhd_size = get_ivhd_header_size(h);
1192 pr_err("Unsupported IVHD type %#x\n", h->type);
1202 e = (struct ivhd_entry *)p;
1206 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1208 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1209 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1211 case IVHD_DEV_SELECT:
1213 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1215 PCI_BUS_NUM(e->devid),
1221 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1223 case IVHD_DEV_SELECT_RANGE_START:
1225 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1226 "devid: %02x:%02x.%x flags: %02x\n",
1227 PCI_BUS_NUM(e->devid),
1232 devid_start = e->devid;
1237 case IVHD_DEV_ALIAS:
1239 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1240 "flags: %02x devid_to: %02x:%02x.%x\n",
1241 PCI_BUS_NUM(e->devid),
1245 PCI_BUS_NUM(e->ext >> 8),
1246 PCI_SLOT(e->ext >> 8),
1247 PCI_FUNC(e->ext >> 8));
1250 devid_to = e->ext >> 8;
1251 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1252 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1253 amd_iommu_alias_table[devid] = devid_to;
1255 case IVHD_DEV_ALIAS_RANGE:
1257 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1258 "devid: %02x:%02x.%x flags: %02x "
1259 "devid_to: %02x:%02x.%x\n",
1260 PCI_BUS_NUM(e->devid),
1264 PCI_BUS_NUM(e->ext >> 8),
1265 PCI_SLOT(e->ext >> 8),
1266 PCI_FUNC(e->ext >> 8));
1268 devid_start = e->devid;
1270 devid_to = e->ext >> 8;
1274 case IVHD_DEV_EXT_SELECT:
1276 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1277 "flags: %02x ext: %08x\n",
1278 PCI_BUS_NUM(e->devid),
1284 set_dev_entry_from_acpi(iommu, devid, e->flags,
1287 case IVHD_DEV_EXT_SELECT_RANGE:
1289 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1290 "%02x:%02x.%x flags: %02x ext: %08x\n",
1291 PCI_BUS_NUM(e->devid),
1296 devid_start = e->devid;
1301 case IVHD_DEV_RANGE_END:
1303 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1304 PCI_BUS_NUM(e->devid),
1306 PCI_FUNC(e->devid));
1309 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1311 amd_iommu_alias_table[dev_i] = devid_to;
1312 set_dev_entry_from_acpi(iommu,
1313 devid_to, flags, ext_flags);
1315 set_dev_entry_from_acpi(iommu, dev_i,
1319 case IVHD_DEV_SPECIAL: {
1325 handle = e->ext & 0xff;
1326 devid = (e->ext >> 8) & 0xffff;
1327 type = (e->ext >> 24) & 0xff;
1329 if (type == IVHD_SPECIAL_IOAPIC)
1331 else if (type == IVHD_SPECIAL_HPET)
1336 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1342 ret = add_special_device(type, handle, &devid, false);
1347 * add_special_device might update the devid in case a
1348 * command-line override is present. So call
1349 * set_dev_entry_from_acpi after add_special_device.
1351 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1355 case IVHD_DEV_ACPI_HID: {
1357 u8 hid[ACPIHID_HID_LEN];
1358 u8 uid[ACPIHID_UID_LEN];
1361 if (h->type != 0x40) {
1362 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1367 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1368 hid[ACPIHID_HID_LEN - 1] = '\0';
1371 pr_err(FW_BUG "Invalid HID.\n");
1377 case UID_NOT_PRESENT:
1380 pr_warn(FW_BUG "Invalid UID length.\n");
1383 case UID_IS_INTEGER:
1385 sprintf(uid, "%d", e->uid);
1388 case UID_IS_CHARACTER:
1390 memcpy(uid, &e->uid, e->uidl);
1391 uid[e->uidl] = '\0';
1399 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1407 ret = add_acpi_hid_device(hid, uid, &devid, false);
1412 * add_special_device might update the devid in case a
1413 * command-line override is present. So call
1414 * set_dev_entry_from_acpi after add_special_device.
1416 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1424 p += ivhd_entry_length(p);
1430 static void __init free_iommu_one(struct amd_iommu *iommu)
1432 free_cwwb_sem(iommu);
1433 free_command_buffer(iommu);
1434 free_event_buffer(iommu);
1435 free_ppr_log(iommu);
1437 iommu_unmap_mmio_space(iommu);
1440 static void __init free_iommu_all(void)
1442 struct amd_iommu *iommu, *next;
1444 for_each_iommu_safe(iommu, next) {
1445 list_del(&iommu->list);
1446 free_iommu_one(iommu);
1452 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1454 * BIOS should disable L2B micellaneous clock gating by setting
1455 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1457 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1461 if ((boot_cpu_data.x86 != 0x15) ||
1462 (boot_cpu_data.x86_model < 0x10) ||
1463 (boot_cpu_data.x86_model > 0x1f))
1466 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1467 pci_read_config_dword(iommu->dev, 0xf4, &value);
1472 /* Select NB indirect register 0x90 and enable writing */
1473 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1475 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1476 pci_info(iommu->dev, "Applying erratum 746 workaround\n");
1478 /* Clear the enable writing bit */
1479 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1483 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1485 * BIOS should enable ATS write permission check by setting
1486 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1488 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1492 if ((boot_cpu_data.x86 != 0x15) ||
1493 (boot_cpu_data.x86_model < 0x30) ||
1494 (boot_cpu_data.x86_model > 0x3f))
1497 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1498 value = iommu_read_l2(iommu, 0x47);
1503 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1504 iommu_write_l2(iommu, 0x47, value | BIT(0));
1506 pci_info(iommu->dev, "Applying ATS write check workaround\n");
1510 * This function clues the initialization function for one IOMMU
1511 * together and also allocates the command buffer and programs the
1512 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1514 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1518 raw_spin_lock_init(&iommu->lock);
1519 iommu->cmd_sem_val = 0;
1521 /* Add IOMMU to internal data structures */
1522 list_add_tail(&iommu->list, &amd_iommu_list);
1523 iommu->index = amd_iommus_present++;
1525 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1526 WARN(1, "System has more IOMMUs than supported by this driver\n");
1530 /* Index is fine - add IOMMU to the array */
1531 amd_iommus[iommu->index] = iommu;
1534 * Copy data from ACPI table entry to the iommu struct
1536 iommu->devid = h->devid;
1537 iommu->cap_ptr = h->cap_ptr;
1538 iommu->pci_seg = h->pci_seg;
1539 iommu->mmio_phys = h->mmio_phys;
1543 /* Check if IVHD EFR contains proper max banks/counters */
1544 if ((h->efr_attr != 0) &&
1545 ((h->efr_attr & (0xF << 13)) != 0) &&
1546 ((h->efr_attr & (0x3F << 17)) != 0))
1547 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1549 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1552 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
1553 * GAM also requires GA mode. Therefore, we need to
1554 * check cmpxchg16b support before enabling it.
1556 if (!boot_cpu_has(X86_FEATURE_CX16) ||
1557 ((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1558 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1562 if (h->efr_reg & (1 << 9))
1563 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1565 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1568 * Note: GA (128-bit IRTE) mode requires cmpxchg16b supports.
1569 * XT, GAM also requires GA mode. Therefore, we need to
1570 * check cmpxchg16b support before enabling them.
1572 if (!boot_cpu_has(X86_FEATURE_CX16) ||
1573 ((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0)) {
1574 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1579 * Note: Since iommu_update_intcapxt() leverages
1580 * the IOMMU MMIO access to MSI capability block registers
1581 * for MSI address lo/hi/data, we need to check both
1582 * EFR[XtSup] and EFR[MsiCapMmioSup] for x2APIC support.
1584 if ((h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) &&
1585 (h->efr_reg & BIT(IOMMU_EFR_MSICAPMMIOSUP_SHIFT)))
1586 amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
1592 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1593 iommu->mmio_phys_end);
1594 if (!iommu->mmio_base)
1597 if (alloc_cwwb_sem(iommu))
1600 if (alloc_command_buffer(iommu))
1603 if (alloc_event_buffer(iommu))
1606 iommu->int_enabled = false;
1608 init_translation_status(iommu);
1609 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) {
1610 iommu_disable(iommu);
1611 clear_translation_pre_enabled(iommu);
1612 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1615 if (amd_iommu_pre_enabled)
1616 amd_iommu_pre_enabled = translation_pre_enabled(iommu);
1618 ret = init_iommu_from_acpi(iommu, h);
1622 ret = amd_iommu_create_irq_domain(iommu);
1627 * Make sure IOMMU is not considered to translate itself. The IVRS
1628 * table tells us so, but this is a lie!
1630 amd_iommu_rlookup_table[iommu->devid] = NULL;
1636 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1637 * @ivrs: Pointer to the IVRS header
1639 * This function search through all IVDB of the maximum supported IVHD
1641 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1643 u8 *base = (u8 *)ivrs;
1644 struct ivhd_header *ivhd = (struct ivhd_header *)
1645 (base + IVRS_HEADER_LENGTH);
1646 u8 last_type = ivhd->type;
1647 u16 devid = ivhd->devid;
1649 while (((u8 *)ivhd - base < ivrs->length) &&
1650 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1651 u8 *p = (u8 *) ivhd;
1653 if (ivhd->devid == devid)
1654 last_type = ivhd->type;
1655 ivhd = (struct ivhd_header *)(p + ivhd->length);
1662 * Iterates over all IOMMU entries in the ACPI table, allocates the
1663 * IOMMU structure and initializes it with init_iommu_one()
1665 static int __init init_iommu_all(struct acpi_table_header *table)
1667 u8 *p = (u8 *)table, *end = (u8 *)table;
1668 struct ivhd_header *h;
1669 struct amd_iommu *iommu;
1672 end += table->length;
1673 p += IVRS_HEADER_LENGTH;
1676 h = (struct ivhd_header *)p;
1677 if (*p == amd_iommu_target_ivhd_type) {
1679 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1680 "seg: %d flags: %01x info %04x\n",
1681 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1682 PCI_FUNC(h->devid), h->cap_ptr,
1683 h->pci_seg, h->flags, h->info);
1684 DUMP_printk(" mmio-addr: %016llx\n",
1687 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1691 ret = init_iommu_one(iommu, h);
1703 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1704 u8 fxn, u64 *value, bool is_write);
1706 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1708 struct pci_dev *pdev = iommu->dev;
1709 u64 val = 0xabcd, val2 = 0, save_reg = 0;
1711 if (!iommu_feature(iommu, FEATURE_PC))
1714 amd_iommu_pc_present = true;
1716 /* save the value to restore, if writable */
1717 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, false))
1720 /* Check if the performance counters can be written to */
1721 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1722 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1727 if (iommu_pc_get_set_reg(iommu, 0, 0, 0, &save_reg, true))
1730 pci_info(pdev, "IOMMU performance counters supported\n");
1732 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1733 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1734 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1739 pci_err(pdev, "Unable to read/write to IOMMU perf counter.\n");
1740 amd_iommu_pc_present = false;
1744 static ssize_t amd_iommu_show_cap(struct device *dev,
1745 struct device_attribute *attr,
1748 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1749 return sprintf(buf, "%x\n", iommu->cap);
1751 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1753 static ssize_t amd_iommu_show_features(struct device *dev,
1754 struct device_attribute *attr,
1757 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1758 return sprintf(buf, "%llx\n", iommu->features);
1760 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1762 static struct attribute *amd_iommu_attrs[] = {
1764 &dev_attr_features.attr,
1768 static struct attribute_group amd_iommu_group = {
1769 .name = "amd-iommu",
1770 .attrs = amd_iommu_attrs,
1773 static const struct attribute_group *amd_iommu_groups[] = {
1778 static int __init iommu_init_pci(struct amd_iommu *iommu)
1780 int cap_ptr = iommu->cap_ptr;
1783 iommu->dev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(iommu->devid),
1784 iommu->devid & 0xff);
1788 /* Prevent binding other PCI device drivers to IOMMU devices */
1789 iommu->dev->match_driver = false;
1791 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1794 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1795 amd_iommu_iotlb_sup = false;
1797 /* read extended feature bits */
1798 iommu->features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);
1800 if (iommu_feature(iommu, FEATURE_GT)) {
1805 pasmax = iommu->features & FEATURE_PASID_MASK;
1806 pasmax >>= FEATURE_PASID_SHIFT;
1807 max_pasid = (1 << (pasmax + 1)) - 1;
1809 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1811 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1813 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1814 glxval >>= FEATURE_GLXVAL_SHIFT;
1816 if (amd_iommu_max_glx_val == -1)
1817 amd_iommu_max_glx_val = glxval;
1819 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1822 if (iommu_feature(iommu, FEATURE_GT) &&
1823 iommu_feature(iommu, FEATURE_PPR)) {
1824 iommu->is_iommu_v2 = true;
1825 amd_iommu_v2_present = true;
1828 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1831 ret = iommu_init_ga(iommu);
1835 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1836 amd_iommu_np_cache = true;
1838 init_iommu_perf_ctr(iommu);
1840 if (is_rd890_iommu(iommu->dev)) {
1844 pci_get_domain_bus_and_slot(0, iommu->dev->bus->number,
1848 * Some rd890 systems may not be fully reconfigured by the
1849 * BIOS, so it's necessary for us to store this information so
1850 * it can be reprogrammed on resume
1852 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1853 &iommu->stored_addr_lo);
1854 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1855 &iommu->stored_addr_hi);
1857 /* Low bit locks writes to configuration space */
1858 iommu->stored_addr_lo &= ~1;
1860 for (i = 0; i < 6; i++)
1861 for (j = 0; j < 0x12; j++)
1862 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1864 for (i = 0; i < 0x83; i++)
1865 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1868 amd_iommu_erratum_746_workaround(iommu);
1869 amd_iommu_ats_write_check_workaround(iommu);
1871 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1872 amd_iommu_groups, "ivhd%d", iommu->index);
1873 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1874 iommu_device_register(&iommu->iommu);
1876 return pci_enable_device(iommu->dev);
1879 static void print_iommu_info(void)
1881 static const char * const feat_str[] = {
1882 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1883 "IA", "GA", "HE", "PC"
1885 struct amd_iommu *iommu;
1887 for_each_iommu(iommu) {
1888 struct pci_dev *pdev = iommu->dev;
1891 pci_info(pdev, "Found IOMMU cap 0x%hx\n", iommu->cap_ptr);
1893 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1894 pci_info(pdev, "Extended features (%#llx):",
1896 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1897 if (iommu_feature(iommu, (1ULL << i)))
1898 pr_cont(" %s", feat_str[i]);
1901 if (iommu->features & FEATURE_GAM_VAPIC)
1902 pr_cont(" GA_vAPIC");
1907 if (irq_remapping_enabled) {
1908 pr_info("Interrupt remapping enabled\n");
1909 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1910 pr_info("Virtual APIC enabled\n");
1911 if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
1912 pr_info("X2APIC enabled\n");
1916 static int __init amd_iommu_init_pci(void)
1918 struct amd_iommu *iommu;
1921 for_each_iommu(iommu) {
1922 ret = iommu_init_pci(iommu);
1926 /* Need to setup range after PCI init */
1927 iommu_set_cwwb_range(iommu);
1931 * Order is important here to make sure any unity map requirements are
1932 * fulfilled. The unity mappings are created and written to the device
1933 * table during the amd_iommu_init_api() call.
1935 * After that we call init_device_table_dma() to make sure any
1936 * uninitialized DTE will block DMA, and in the end we flush the caches
1937 * of all IOMMUs to make sure the changes to the device table are
1940 ret = amd_iommu_init_api();
1942 init_device_table_dma();
1944 for_each_iommu(iommu)
1945 iommu_flush_all_caches(iommu);
1953 /****************************************************************************
1955 * The following functions initialize the MSI interrupts for all IOMMUs
1956 * in the system. It's a bit challenging because there could be multiple
1957 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1960 ****************************************************************************/
1962 static int iommu_setup_msi(struct amd_iommu *iommu)
1966 r = pci_enable_msi(iommu->dev);
1970 r = request_threaded_irq(iommu->dev->irq,
1971 amd_iommu_int_handler,
1972 amd_iommu_int_thread,
1977 pci_disable_msi(iommu->dev);
1981 iommu->int_enabled = true;
1986 #define XT_INT_DEST_MODE(x) (((x) & 0x1ULL) << 2)
1987 #define XT_INT_DEST_LO(x) (((x) & 0xFFFFFFULL) << 8)
1988 #define XT_INT_VEC(x) (((x) & 0xFFULL) << 32)
1989 #define XT_INT_DEST_HI(x) ((((x) >> 24) & 0xFFULL) << 56)
1992 * Setup the IntCapXT registers with interrupt routing information
1993 * based on the PCI MSI capability block registers, accessed via
1994 * MMIO MSI address low/hi and MSI data registers.
1996 static void iommu_update_intcapxt(struct amd_iommu *iommu)
1999 u32 addr_lo = readl(iommu->mmio_base + MMIO_MSI_ADDR_LO_OFFSET);
2000 u32 addr_hi = readl(iommu->mmio_base + MMIO_MSI_ADDR_HI_OFFSET);
2001 u32 data = readl(iommu->mmio_base + MMIO_MSI_DATA_OFFSET);
2002 bool dm = (addr_lo >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
2003 u32 dest = ((addr_lo >> MSI_ADDR_DEST_ID_SHIFT) & 0xFF);
2005 if (x2apic_enabled())
2006 dest |= MSI_ADDR_EXT_DEST_ID(addr_hi);
2008 val = XT_INT_VEC(data & 0xFF) |
2009 XT_INT_DEST_MODE(dm) |
2010 XT_INT_DEST_LO(dest) |
2011 XT_INT_DEST_HI(dest);
2014 * Current IOMMU implemtation uses the same IRQ for all
2015 * 3 IOMMU interrupts.
2017 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_EVT_OFFSET);
2018 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_PPR_OFFSET);
2019 writeq(val, iommu->mmio_base + MMIO_INTCAPXT_GALOG_OFFSET);
2022 static void _irq_notifier_notify(struct irq_affinity_notify *notify,
2023 const cpumask_t *mask)
2025 struct amd_iommu *iommu;
2027 for_each_iommu(iommu) {
2028 if (iommu->dev->irq == notify->irq) {
2029 iommu_update_intcapxt(iommu);
2035 static void _irq_notifier_release(struct kref *ref)
2039 static int iommu_init_intcapxt(struct amd_iommu *iommu)
2042 struct irq_affinity_notify *notify = &iommu->intcapxt_notify;
2045 * IntCapXT requires XTSup=1 and MsiCapMmioSup=1,
2046 * which can be inferred from amd_iommu_xt_mode.
2048 if (amd_iommu_xt_mode != IRQ_REMAP_X2APIC_MODE)
2052 * Also, we need to setup notifier to update the IntCapXT registers
2053 * whenever the irq affinity is changed from user-space.
2055 notify->irq = iommu->dev->irq;
2056 notify->notify = _irq_notifier_notify,
2057 notify->release = _irq_notifier_release,
2058 ret = irq_set_affinity_notifier(iommu->dev->irq, notify);
2060 pr_err("Failed to register irq affinity notifier (devid=%#x, irq %d)\n",
2061 iommu->devid, iommu->dev->irq);
2065 iommu_update_intcapxt(iommu);
2066 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN);
2070 static int iommu_init_msi(struct amd_iommu *iommu)
2074 if (iommu->int_enabled)
2077 if (iommu->dev->msi_cap)
2078 ret = iommu_setup_msi(iommu);
2086 ret = iommu_init_intcapxt(iommu);
2090 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
2092 if (iommu->ppr_log != NULL)
2093 iommu_feature_enable(iommu, CONTROL_PPRINT_EN);
2095 iommu_ga_log_enable(iommu);
2100 /****************************************************************************
2102 * The next functions belong to the third pass of parsing the ACPI
2103 * table. In this last pass the memory mapping requirements are
2104 * gathered (like exclusion and unity mapping ranges).
2106 ****************************************************************************/
2108 static void __init free_unity_maps(void)
2110 struct unity_map_entry *entry, *next;
2112 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
2113 list_del(&entry->list);
2118 /* called for unity map ACPI definition */
2119 static int __init init_unity_map_range(struct ivmd_header *m)
2121 struct unity_map_entry *e = NULL;
2124 e = kzalloc(sizeof(*e), GFP_KERNEL);
2132 case ACPI_IVMD_TYPE:
2133 s = "IVMD_TYPEi\t\t\t";
2134 e->devid_start = e->devid_end = m->devid;
2136 case ACPI_IVMD_TYPE_ALL:
2137 s = "IVMD_TYPE_ALL\t\t";
2139 e->devid_end = amd_iommu_last_bdf;
2141 case ACPI_IVMD_TYPE_RANGE:
2142 s = "IVMD_TYPE_RANGE\t\t";
2143 e->devid_start = m->devid;
2144 e->devid_end = m->aux;
2147 e->address_start = PAGE_ALIGN(m->range_start);
2148 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
2149 e->prot = m->flags >> 1;
2152 * Treat per-device exclusion ranges as r/w unity-mapped regions
2153 * since some buggy BIOSes might lead to the overwritten exclusion
2154 * range (exclusion_start and exclusion_length members). This
2155 * happens when there are multiple exclusion ranges (IVMD entries)
2156 * defined in ACPI table.
2158 if (m->flags & IVMD_FLAG_EXCL_RANGE)
2159 e->prot = (IVMD_FLAG_IW | IVMD_FLAG_IR) >> 1;
2161 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2162 " range_start: %016llx range_end: %016llx flags: %x\n", s,
2163 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
2164 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
2165 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
2166 e->address_start, e->address_end, m->flags);
2168 list_add_tail(&e->list, &amd_iommu_unity_map);
2173 /* iterates over all memory definitions we find in the ACPI table */
2174 static int __init init_memory_definitions(struct acpi_table_header *table)
2176 u8 *p = (u8 *)table, *end = (u8 *)table;
2177 struct ivmd_header *m;
2179 end += table->length;
2180 p += IVRS_HEADER_LENGTH;
2183 m = (struct ivmd_header *)p;
2184 if (m->flags & (IVMD_FLAG_UNITY_MAP | IVMD_FLAG_EXCL_RANGE))
2185 init_unity_map_range(m);
2194 * Init the device table to not allow DMA access for devices
2196 static void init_device_table_dma(void)
2200 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2201 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
2202 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
2206 static void __init uninit_device_table_dma(void)
2210 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
2211 amd_iommu_dev_table[devid].data[0] = 0ULL;
2212 amd_iommu_dev_table[devid].data[1] = 0ULL;
2216 static void init_device_table(void)
2220 if (!amd_iommu_irq_remap)
2223 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
2224 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
2227 static void iommu_init_flags(struct amd_iommu *iommu)
2229 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
2230 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
2231 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
2233 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
2234 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
2235 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
2237 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
2238 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
2239 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
2241 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
2242 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
2243 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
2246 * make IOMMU memory accesses cache coherent
2248 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
2250 /* Set IOTLB invalidation timeout to 1s */
2251 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
2254 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
2257 u32 ioc_feature_control;
2258 struct pci_dev *pdev = iommu->root_pdev;
2260 /* RD890 BIOSes may not have completely reconfigured the iommu */
2261 if (!is_rd890_iommu(iommu->dev) || !pdev)
2265 * First, we need to ensure that the iommu is enabled. This is
2266 * controlled by a register in the northbridge
2269 /* Select Northbridge indirect register 0x75 and enable writing */
2270 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
2271 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
2273 /* Enable the iommu */
2274 if (!(ioc_feature_control & 0x1))
2275 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
2277 /* Restore the iommu BAR */
2278 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2279 iommu->stored_addr_lo);
2280 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
2281 iommu->stored_addr_hi);
2283 /* Restore the l1 indirect regs for each of the 6 l1s */
2284 for (i = 0; i < 6; i++)
2285 for (j = 0; j < 0x12; j++)
2286 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
2288 /* Restore the l2 indirect regs */
2289 for (i = 0; i < 0x83; i++)
2290 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2292 /* Lock PCI setup registers */
2293 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2294 iommu->stored_addr_lo | 1);
2297 static void iommu_enable_ga(struct amd_iommu *iommu)
2299 #ifdef CONFIG_IRQ_REMAP
2300 switch (amd_iommu_guest_ir) {
2301 case AMD_IOMMU_GUEST_IR_VAPIC:
2302 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2304 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2305 iommu_feature_enable(iommu, CONTROL_GA_EN);
2306 iommu->irte_ops = &irte_128_ops;
2309 iommu->irte_ops = &irte_32_ops;
2315 static void early_enable_iommu(struct amd_iommu *iommu)
2317 iommu_disable(iommu);
2318 iommu_init_flags(iommu);
2319 iommu_set_device_table(iommu);
2320 iommu_enable_command_buffer(iommu);
2321 iommu_enable_event_buffer(iommu);
2322 iommu_set_exclusion_range(iommu);
2323 iommu_enable_ga(iommu);
2324 iommu_enable_xt(iommu);
2325 iommu_enable(iommu);
2326 iommu_flush_all_caches(iommu);
2330 * This function finally enables all IOMMUs found in the system after
2331 * they have been initialized.
2333 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2334 * the old content of device table entries. Not this case or copy failed,
2335 * just continue as normal kernel does.
2337 static void early_enable_iommus(void)
2339 struct amd_iommu *iommu;
2342 if (!copy_device_table()) {
2344 * If come here because of failure in copying device table from old
2345 * kernel with all IOMMUs enabled, print error message and try to
2346 * free allocated old_dev_tbl_cpy.
2348 if (amd_iommu_pre_enabled)
2349 pr_err("Failed to copy DEV table from previous kernel.\n");
2350 if (old_dev_tbl_cpy != NULL)
2351 free_pages((unsigned long)old_dev_tbl_cpy,
2352 get_order(dev_table_size));
2354 for_each_iommu(iommu) {
2355 clear_translation_pre_enabled(iommu);
2356 early_enable_iommu(iommu);
2359 pr_info("Copied DEV table from previous kernel.\n");
2360 free_pages((unsigned long)amd_iommu_dev_table,
2361 get_order(dev_table_size));
2362 amd_iommu_dev_table = old_dev_tbl_cpy;
2363 for_each_iommu(iommu) {
2364 iommu_disable_command_buffer(iommu);
2365 iommu_disable_event_buffer(iommu);
2366 iommu_enable_command_buffer(iommu);
2367 iommu_enable_event_buffer(iommu);
2368 iommu_enable_ga(iommu);
2369 iommu_enable_xt(iommu);
2370 iommu_set_device_table(iommu);
2371 iommu_flush_all_caches(iommu);
2375 #ifdef CONFIG_IRQ_REMAP
2376 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2377 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2381 static void enable_iommus_v2(void)
2383 struct amd_iommu *iommu;
2385 for_each_iommu(iommu) {
2386 iommu_enable_ppr_log(iommu);
2387 iommu_enable_gt(iommu);
2391 static void enable_iommus(void)
2393 early_enable_iommus();
2398 static void disable_iommus(void)
2400 struct amd_iommu *iommu;
2402 for_each_iommu(iommu)
2403 iommu_disable(iommu);
2405 #ifdef CONFIG_IRQ_REMAP
2406 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2407 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2412 * Suspend/Resume support
2413 * disable suspend until real resume implemented
2416 static void amd_iommu_resume(void)
2418 struct amd_iommu *iommu;
2420 for_each_iommu(iommu)
2421 iommu_apply_resume_quirks(iommu);
2423 /* re-load the hardware */
2426 amd_iommu_enable_interrupts();
2429 static int amd_iommu_suspend(void)
2431 /* disable IOMMUs to go out of the way for BIOS */
2437 static struct syscore_ops amd_iommu_syscore_ops = {
2438 .suspend = amd_iommu_suspend,
2439 .resume = amd_iommu_resume,
2442 static void __init free_iommu_resources(void)
2444 kmemleak_free(irq_lookup_table);
2445 free_pages((unsigned long)irq_lookup_table,
2446 get_order(rlookup_table_size));
2447 irq_lookup_table = NULL;
2449 kmem_cache_destroy(amd_iommu_irq_cache);
2450 amd_iommu_irq_cache = NULL;
2452 free_pages((unsigned long)amd_iommu_rlookup_table,
2453 get_order(rlookup_table_size));
2454 amd_iommu_rlookup_table = NULL;
2456 free_pages((unsigned long)amd_iommu_alias_table,
2457 get_order(alias_table_size));
2458 amd_iommu_alias_table = NULL;
2460 free_pages((unsigned long)amd_iommu_dev_table,
2461 get_order(dev_table_size));
2462 amd_iommu_dev_table = NULL;
2467 /* SB IOAPIC is always on this device in AMD systems */
2468 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2470 static bool __init check_ioapic_information(void)
2472 const char *fw_bug = FW_BUG;
2473 bool ret, has_sb_ioapic;
2476 has_sb_ioapic = false;
2480 * If we have map overrides on the kernel command line the
2481 * messages in this function might not describe firmware bugs
2482 * anymore - so be careful
2487 for (idx = 0; idx < nr_ioapics; idx++) {
2488 int devid, id = mpc_ioapic_id(idx);
2490 devid = get_ioapic_devid(id);
2492 pr_err("%s: IOAPIC[%d] not in IVRS table\n",
2495 } else if (devid == IOAPIC_SB_DEVID) {
2496 has_sb_ioapic = true;
2501 if (!has_sb_ioapic) {
2503 * We expect the SB IOAPIC to be listed in the IVRS
2504 * table. The system timer is connected to the SB IOAPIC
2505 * and if we don't have it in the list the system will
2506 * panic at boot time. This situation usually happens
2507 * when the BIOS is buggy and provides us the wrong
2508 * device id for the IOAPIC in the system.
2510 pr_err("%s: No southbridge IOAPIC found\n", fw_bug);
2514 pr_err("Disabling interrupt remapping\n");
2519 static void __init free_dma_resources(void)
2521 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2522 get_order(MAX_DOMAIN_ID/8));
2523 amd_iommu_pd_alloc_bitmap = NULL;
2529 * This is the hardware init function for AMD IOMMU in the system.
2530 * This function is called either from amd_iommu_init or from the interrupt
2531 * remapping setup code.
2533 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2536 * 1 pass) Discover the most comprehensive IVHD type to use.
2538 * 2 pass) Find the highest PCI device id the driver has to handle.
2539 * Upon this information the size of the data structures is
2540 * determined that needs to be allocated.
2542 * 3 pass) Initialize the data structures just allocated with the
2543 * information in the ACPI table about available AMD IOMMUs
2544 * in the system. It also maps the PCI devices in the
2545 * system to specific IOMMUs
2547 * 4 pass) After the basic data structures are allocated and
2548 * initialized we update them with information about memory
2549 * remapping requirements parsed out of the ACPI table in
2552 * After everything is set up the IOMMUs are enabled and the necessary
2553 * hotplug and suspend notifiers are registered.
2555 static int __init early_amd_iommu_init(void)
2557 struct acpi_table_header *ivrs_base;
2559 int i, remap_cache_sz, ret = 0;
2562 if (!amd_iommu_detected)
2565 status = acpi_get_table("IVRS", 0, &ivrs_base);
2566 if (status == AE_NOT_FOUND)
2568 else if (ACPI_FAILURE(status)) {
2569 const char *err = acpi_format_exception(status);
2570 pr_err("IVRS table error: %s\n", err);
2575 * Validate checksum here so we don't need to do it when
2576 * we actually parse the table
2578 ret = check_ivrs_checksum(ivrs_base);
2582 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2583 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2586 * First parse ACPI tables to find the largest Bus/Dev/Func
2587 * we need to handle. Upon this information the shared data
2588 * structures for the IOMMUs in the system will be allocated
2590 ret = find_last_devid_acpi(ivrs_base);
2594 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2595 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2596 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2598 /* Device table - directly used by all IOMMUs */
2600 amd_iommu_dev_table = (void *)__get_free_pages(
2601 GFP_KERNEL | __GFP_ZERO | GFP_DMA32,
2602 get_order(dev_table_size));
2603 if (amd_iommu_dev_table == NULL)
2607 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2608 * IOMMU see for that device
2610 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2611 get_order(alias_table_size));
2612 if (amd_iommu_alias_table == NULL)
2615 /* IOMMU rlookup table - find the IOMMU for a specific device */
2616 amd_iommu_rlookup_table = (void *)__get_free_pages(
2617 GFP_KERNEL | __GFP_ZERO,
2618 get_order(rlookup_table_size));
2619 if (amd_iommu_rlookup_table == NULL)
2622 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2623 GFP_KERNEL | __GFP_ZERO,
2624 get_order(MAX_DOMAIN_ID/8));
2625 if (amd_iommu_pd_alloc_bitmap == NULL)
2629 * let all alias entries point to itself
2631 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2632 amd_iommu_alias_table[i] = i;
2635 * never allocate domain 0 because its used as the non-allocated and
2636 * error value placeholder
2638 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2641 * now the data structures are allocated and basically initialized
2642 * start the real acpi table scan
2644 ret = init_iommu_all(ivrs_base);
2648 /* Disable IOMMU if there's Stoney Ridge graphics */
2649 for (i = 0; i < 32; i++) {
2650 pci_id = read_pci_config(0, i, 0, 0);
2651 if ((pci_id & 0xffff) == 0x1002 && (pci_id >> 16) == 0x98e4) {
2652 pr_info("Disable IOMMU on Stoney Ridge\n");
2653 amd_iommu_disabled = true;
2658 /* Disable any previously enabled IOMMUs */
2659 if (!is_kdump_kernel() || amd_iommu_disabled)
2662 if (amd_iommu_irq_remap)
2663 amd_iommu_irq_remap = check_ioapic_information();
2665 if (amd_iommu_irq_remap) {
2667 * Interrupt remapping enabled, create kmem_cache for the
2671 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2672 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2674 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2675 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2677 IRQ_TABLE_ALIGNMENT,
2679 if (!amd_iommu_irq_cache)
2682 irq_lookup_table = (void *)__get_free_pages(
2683 GFP_KERNEL | __GFP_ZERO,
2684 get_order(rlookup_table_size));
2685 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2687 if (!irq_lookup_table)
2691 ret = init_memory_definitions(ivrs_base);
2695 /* init the device table */
2696 init_device_table();
2699 /* Don't leak any ACPI memory */
2700 acpi_put_table(ivrs_base);
2706 static int amd_iommu_enable_interrupts(void)
2708 struct amd_iommu *iommu;
2711 for_each_iommu(iommu) {
2712 ret = iommu_init_msi(iommu);
2721 static bool detect_ivrs(void)
2723 struct acpi_table_header *ivrs_base;
2726 status = acpi_get_table("IVRS", 0, &ivrs_base);
2727 if (status == AE_NOT_FOUND)
2729 else if (ACPI_FAILURE(status)) {
2730 const char *err = acpi_format_exception(status);
2731 pr_err("IVRS table error: %s\n", err);
2735 acpi_put_table(ivrs_base);
2737 /* Make sure ACS will be enabled during PCI probe */
2743 /****************************************************************************
2745 * AMD IOMMU Initialization State Machine
2747 ****************************************************************************/
2749 static int __init state_next(void)
2753 switch (init_state) {
2754 case IOMMU_START_STATE:
2755 if (!detect_ivrs()) {
2756 init_state = IOMMU_NOT_FOUND;
2759 init_state = IOMMU_IVRS_DETECTED;
2762 case IOMMU_IVRS_DETECTED:
2763 ret = early_amd_iommu_init();
2764 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2765 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2766 pr_info("AMD IOMMU disabled\n");
2767 init_state = IOMMU_CMDLINE_DISABLED;
2771 case IOMMU_ACPI_FINISHED:
2772 early_enable_iommus();
2773 x86_platform.iommu_shutdown = disable_iommus;
2774 init_state = IOMMU_ENABLED;
2777 register_syscore_ops(&amd_iommu_syscore_ops);
2778 ret = amd_iommu_init_pci();
2779 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2782 case IOMMU_PCI_INIT:
2783 ret = amd_iommu_enable_interrupts();
2784 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2786 case IOMMU_INTERRUPTS_EN:
2787 ret = amd_iommu_init_dma_ops();
2788 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2791 init_state = IOMMU_INITIALIZED;
2793 case IOMMU_INITIALIZED:
2796 case IOMMU_NOT_FOUND:
2797 case IOMMU_INIT_ERROR:
2798 case IOMMU_CMDLINE_DISABLED:
2799 /* Error states => do nothing */
2808 free_dma_resources();
2809 if (!irq_remapping_enabled) {
2811 free_iommu_resources();
2813 struct amd_iommu *iommu;
2815 uninit_device_table_dma();
2816 for_each_iommu(iommu)
2817 iommu_flush_all_caches(iommu);
2823 static int __init iommu_go_to_state(enum iommu_init_state state)
2827 while (init_state != state) {
2828 if (init_state == IOMMU_NOT_FOUND ||
2829 init_state == IOMMU_INIT_ERROR ||
2830 init_state == IOMMU_CMDLINE_DISABLED)
2838 #ifdef CONFIG_IRQ_REMAP
2839 int __init amd_iommu_prepare(void)
2843 amd_iommu_irq_remap = true;
2845 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2848 return amd_iommu_irq_remap ? 0 : -ENODEV;
2851 int __init amd_iommu_enable(void)
2855 ret = iommu_go_to_state(IOMMU_ENABLED);
2859 irq_remapping_enabled = 1;
2860 return amd_iommu_xt_mode;
2863 void amd_iommu_disable(void)
2865 amd_iommu_suspend();
2868 int amd_iommu_reenable(int mode)
2875 int __init amd_iommu_enable_faulting(void)
2877 /* We enable MSI later when PCI is initialized */
2883 * This is the core init function for AMD IOMMU hardware in the system.
2884 * This function is called from the generic x86 DMA layer initialization
2887 static int __init amd_iommu_init(void)
2889 struct amd_iommu *iommu;
2892 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2893 #ifdef CONFIG_GART_IOMMU
2894 if (ret && list_empty(&amd_iommu_list)) {
2896 * We failed to initialize the AMD IOMMU - try fallback
2897 * to GART if possible.
2903 for_each_iommu(iommu)
2904 amd_iommu_debugfs_setup(iommu);
2909 static bool amd_iommu_sme_check(void)
2911 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2914 /* For Fam17h, a specific level of support is required */
2915 if (boot_cpu_data.microcode >= 0x08001205)
2918 if ((boot_cpu_data.microcode >= 0x08001126) &&
2919 (boot_cpu_data.microcode <= 0x080011ff))
2922 pr_notice("IOMMU not currently supported when SME is active\n");
2927 /****************************************************************************
2929 * Early detect code. This code runs at IOMMU detection time in the DMA
2930 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2933 ****************************************************************************/
2934 int __init amd_iommu_detect(void)
2938 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2941 if (!amd_iommu_sme_check())
2944 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2948 amd_iommu_detected = true;
2950 x86_init.iommu.iommu_init = amd_iommu_init;
2955 /****************************************************************************
2957 * Parsing functions for the AMD IOMMU specific kernel command line
2960 ****************************************************************************/
2962 static int __init parse_amd_iommu_dump(char *str)
2964 amd_iommu_dump = true;
2969 static int __init parse_amd_iommu_intr(char *str)
2971 for (; *str; ++str) {
2972 if (strncmp(str, "legacy", 6) == 0) {
2973 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
2976 if (strncmp(str, "vapic", 5) == 0) {
2977 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2984 static int __init parse_amd_iommu_options(char *str)
2986 for (; *str; ++str) {
2987 if (strncmp(str, "fullflush", 9) == 0)
2988 amd_iommu_unmap_flush = true;
2989 if (strncmp(str, "off", 3) == 0)
2990 amd_iommu_disabled = true;
2991 if (strncmp(str, "force_isolation", 15) == 0)
2992 amd_iommu_force_isolation = true;
2998 static int __init parse_ivrs_ioapic(char *str)
3000 unsigned int bus, dev, fn;
3004 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
3007 pr_err("Invalid command line: ivrs_ioapic%s\n", str);
3011 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
3012 pr_err("Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
3017 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3019 cmdline_maps = true;
3020 i = early_ioapic_map_size++;
3021 early_ioapic_map[i].id = id;
3022 early_ioapic_map[i].devid = devid;
3023 early_ioapic_map[i].cmd_line = true;
3028 static int __init parse_ivrs_hpet(char *str)
3030 unsigned int bus, dev, fn;
3034 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
3037 pr_err("Invalid command line: ivrs_hpet%s\n", str);
3041 if (early_hpet_map_size == EARLY_MAP_SIZE) {
3042 pr_err("Early HPET map overflow - ignoring ivrs_hpet%s\n",
3047 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3049 cmdline_maps = true;
3050 i = early_hpet_map_size++;
3051 early_hpet_map[i].id = id;
3052 early_hpet_map[i].devid = devid;
3053 early_hpet_map[i].cmd_line = true;
3058 static int __init parse_ivrs_acpihid(char *str)
3061 char *hid, *uid, *p;
3062 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
3065 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
3067 pr_err("Invalid command line: ivrs_acpihid(%s)\n", str);
3072 hid = strsep(&p, ":");
3075 if (!hid || !(*hid) || !uid) {
3076 pr_err("Invalid command line: hid or uid\n");
3080 i = early_acpihid_map_size++;
3081 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
3082 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
3083 early_acpihid_map[i].devid =
3084 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
3085 early_acpihid_map[i].cmd_line = true;
3090 __setup("amd_iommu_dump", parse_amd_iommu_dump);
3091 __setup("amd_iommu=", parse_amd_iommu_options);
3092 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
3093 __setup("ivrs_ioapic", parse_ivrs_ioapic);
3094 __setup("ivrs_hpet", parse_ivrs_hpet);
3095 __setup("ivrs_acpihid", parse_ivrs_acpihid);
3097 IOMMU_INIT_FINISH(amd_iommu_detect,
3098 gart_iommu_hole_init,
3102 bool amd_iommu_v2_supported(void)
3104 return amd_iommu_v2_present;
3106 EXPORT_SYMBOL(amd_iommu_v2_supported);
3108 struct amd_iommu *get_amd_iommu(unsigned int idx)
3111 struct amd_iommu *iommu;
3113 for_each_iommu(iommu)
3118 EXPORT_SYMBOL(get_amd_iommu);
3120 /****************************************************************************
3122 * IOMMU EFR Performance Counter support functionality. This code allows
3123 * access to the IOMMU PC functionality.
3125 ****************************************************************************/
3127 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
3129 struct amd_iommu *iommu = get_amd_iommu(idx);
3132 return iommu->max_banks;
3136 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
3138 bool amd_iommu_pc_supported(void)
3140 return amd_iommu_pc_present;
3142 EXPORT_SYMBOL(amd_iommu_pc_supported);
3144 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
3146 struct amd_iommu *iommu = get_amd_iommu(idx);
3149 return iommu->max_counters;
3153 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
3155 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
3156 u8 fxn, u64 *value, bool is_write)
3161 /* Make sure the IOMMU PC resource is available */
3162 if (!amd_iommu_pc_present)
3165 /* Check for valid iommu and pc register indexing */
3166 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
3169 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
3171 /* Limit the offset to the hw defined mmio region aperture */
3172 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
3173 (iommu->max_counters << 8) | 0x28);
3174 if ((offset < MMIO_CNTR_REG_OFFSET) ||
3175 (offset > max_offset_lim))
3179 u64 val = *value & GENMASK_ULL(47, 0);
3181 writel((u32)val, iommu->mmio_base + offset);
3182 writel((val >> 32), iommu->mmio_base + offset + 4);
3184 *value = readl(iommu->mmio_base + offset + 4);
3186 *value |= readl(iommu->mmio_base + offset);
3187 *value &= GENMASK_ULL(47, 0);
3193 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3198 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
3200 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
3202 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
3207 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
3209 EXPORT_SYMBOL(amd_iommu_pc_set_reg);