drivers/infiniband/hw/i40iw/i40iw_puda.c

   1 /*******************************************************************************
   2 *
   3 * Copyright (c) 2015-2016 Intel Corporation.  All rights reserved.
   4 *
   5 * This software is available to you under a choice of one of two
   6 * licenses.  You may choose to be licensed under the terms of the GNU
   7 * General Public License (GPL) Version 2, available from the file
   8 * COPYING in the main directory of this source tree, or the
   9 * OpenFabrics.org BSD license below:
  10 *
  11 *   Redistribution and use in source and binary forms, with or
  12 *   without modification, are permitted provided that the following
  13 *   conditions are met:
  14 *
  15 *    - Redistributions of source code must retain the above
  16 *       copyright notice, this list of conditions and the following
  17 *       disclaimer.
  18 *
  19 *    - Redistributions in binary form must reproduce the above
  20 *       copyright notice, this list of conditions and the following
  21 *       disclaimer in the documentation and/or other materials
  22 *       provided with the distribution.
  23 *
  24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31 * SOFTWARE.
  32 *
  33 *******************************************************************************/
  34
  35 #include "i40iw_osdep.h"
  36 #include "i40iw_register.h"
  37 #include "i40iw_status.h"
  38 #include "i40iw_hmc.h"
  39
  40 #include "i40iw_d.h"
  41 #include "i40iw_type.h"
  42 #include "i40iw_p.h"
  43 #include "i40iw_puda.h"
  44
  45 static void i40iw_ieq_receive(struct i40iw_sc_vsi *vsi,
  46                               struct i40iw_puda_buf *buf);
  47 static void i40iw_ieq_tx_compl(struct i40iw_sc_vsi *vsi, void *sqwrid);
  48 static void i40iw_ilq_putback_rcvbuf(struct i40iw_sc_qp *qp, u32 wqe_idx);
  49 static enum i40iw_status_code i40iw_puda_replenish_rq(struct i40iw_puda_rsrc
  50                                                       *rsrc, bool initial);
  51 /**
  52  * i40iw_puda_get_listbuf - get buffer from puda list
  53  * @list: list to use for buffers (ILQ or IEQ)
  54  */
  55 static struct i40iw_puda_buf *i40iw_puda_get_listbuf(struct list_head *list)
  56 {
  57         struct i40iw_puda_buf *buf = NULL;
  58
  59         if (!list_empty(list)) {
  60                 buf = (struct i40iw_puda_buf *)list->next;
  61                 list_del((struct list_head *)&buf->list);
  62         }
  63         return buf;
  64 }
  65
  66 /**
  67  * i40iw_puda_get_bufpool - return buffer from resource
  68  * @rsrc: resource to use for buffer
  69  */
  70 struct i40iw_puda_buf *i40iw_puda_get_bufpool(struct i40iw_puda_rsrc *rsrc)
  71 {
  72         struct i40iw_puda_buf *buf = NULL;
  73         struct list_head *list = &rsrc->bufpool;
  74         unsigned long   flags;
  75
  76         spin_lock_irqsave(&rsrc->bufpool_lock, flags);
  77         buf = i40iw_puda_get_listbuf(list);
  78         if (buf)
  79                 rsrc->avail_buf_count--;
  80         else
  81                 rsrc->stats_buf_alloc_fail++;
  82         spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
  83         return buf;
  84 }
  85
  86 /**
  87  * i40iw_puda_ret_bufpool - return buffer to rsrc list
  88  * @rsrc: resource to use for buffer
  89  * @buf: buffe to return to resouce
  90  */
  91 void i40iw_puda_ret_bufpool(struct i40iw_puda_rsrc *rsrc,
  92                             struct i40iw_puda_buf *buf)
  93 {
  94         unsigned long   flags;
  95
  96         spin_lock_irqsave(&rsrc->bufpool_lock, flags);
  97         list_add(&buf->list, &rsrc->bufpool);
  98         spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
  99         rsrc->avail_buf_count++;
 100 }
 101
 102 /**
 103  * i40iw_puda_post_recvbuf - set wqe for rcv buffer
 104  * @rsrc: resource ptr
 105  * @wqe_idx: wqe index to use
 106  * @buf: puda buffer for rcv q
 107  * @initial: flag if during init time
 108  */
 109 static void i40iw_puda_post_recvbuf(struct i40iw_puda_rsrc *rsrc, u32 wqe_idx,
 110                                     struct i40iw_puda_buf *buf, bool initial)
 111 {
 112         u64 *wqe;
 113         struct i40iw_sc_qp *qp = &rsrc->qp;
 114         u64 offset24 = 0;
 115
 116         qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf;
 117         wqe = qp->qp_uk.rq_base[wqe_idx].elem;
 118         i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
 119                     "%s: wqe_idx= %d buf = %p wqe = %p\n", __func__,
 120                     wqe_idx, buf, wqe);
 121         if (!initial)
 122                 get_64bit_val(wqe, 24, &offset24);
 123
 124         offset24 = (offset24) ? 0 : LS_64(1, I40IWQPSQ_VALID);
 125
 126         set_64bit_val(wqe, 0, buf->mem.pa);
 127         set_64bit_val(wqe, 8,
 128                       LS_64(buf->mem.size, I40IWQPSQ_FRAG_LEN));
 129         i40iw_insert_wqe_hdr(wqe, offset24);
 130 }
 131
 132 /**
 133  * i40iw_puda_replenish_rq - post rcv buffers
 134  * @rsrc: resource to use for buffer
 135  * @initial: flag if during init time
 136  */
 137 static enum i40iw_status_code i40iw_puda_replenish_rq(struct i40iw_puda_rsrc *rsrc,
 138                                                       bool initial)
 139 {
 140         u32 i;
 141         u32 invalid_cnt = rsrc->rxq_invalid_cnt;
 142         struct i40iw_puda_buf *buf = NULL;
 143
 144         for (i = 0; i < invalid_cnt; i++) {
 145                 buf = i40iw_puda_get_bufpool(rsrc);
 146                 if (!buf)
 147                         return I40IW_ERR_list_empty;
 148                 i40iw_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf,
 149                                         initial);
 150                 rsrc->rx_wqe_idx =
 151                     ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size);
 152                 rsrc->rxq_invalid_cnt--;
 153         }
 154         return 0;
 155 }
 156
 157 /**
 158  * i40iw_puda_alloc_buf - allocate mem for buffer
 159  * @dev: iwarp device
 160  * @length: length of buffer
 161  */
 162 static struct i40iw_puda_buf *i40iw_puda_alloc_buf(struct i40iw_sc_dev *dev,
 163                                                    u32 length)
 164 {
 165         struct i40iw_puda_buf *buf = NULL;
 166         struct i40iw_virt_mem buf_mem;
 167         enum i40iw_status_code ret;
 168
 169         ret = i40iw_allocate_virt_mem(dev->hw, &buf_mem,
 170                                       sizeof(struct i40iw_puda_buf));
 171         if (ret) {
 172                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 173                             "%s: error mem for buf\n", __func__);
 174                 return NULL;
 175         }
 176         buf = (struct i40iw_puda_buf *)buf_mem.va;
 177         ret = i40iw_allocate_dma_mem(dev->hw, &buf->mem, length, 1);
 178         if (ret) {
 179                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 180                             "%s: error dma mem for buf\n", __func__);
 181                 i40iw_free_virt_mem(dev->hw, &buf_mem);
 182                 return NULL;
 183         }
 184         buf->buf_mem.va = buf_mem.va;
 185         buf->buf_mem.size = buf_mem.size;
 186         return buf;
 187 }
 188
 189 /**
 190  * i40iw_puda_dele_buf - delete buffer back to system
 191  * @dev: iwarp device
 192  * @buf: buffer to free
 193  */
 194 static void i40iw_puda_dele_buf(struct i40iw_sc_dev *dev,
 195                                 struct i40iw_puda_buf *buf)
 196 {
 197         i40iw_free_dma_mem(dev->hw, &buf->mem);
 198         i40iw_free_virt_mem(dev->hw, &buf->buf_mem);
 199 }
 200
 201 /**
 202  * i40iw_puda_get_next_send_wqe - return next wqe for processing
 203  * @qp: puda qp for wqe
 204  * @wqe_idx: wqe index for caller
 205  */
 206 static u64 *i40iw_puda_get_next_send_wqe(struct i40iw_qp_uk *qp, u32 *wqe_idx)
 207 {
 208         u64 *wqe = NULL;
 209         enum i40iw_status_code ret_code = 0;
 210
 211         *wqe_idx = I40IW_RING_GETCURRENT_HEAD(qp->sq_ring);
 212         if (!*wqe_idx)
 213                 qp->swqe_polarity = !qp->swqe_polarity;
 214         I40IW_RING_MOVE_HEAD(qp->sq_ring, ret_code);
 215         if (ret_code)
 216                 return wqe;
 217         wqe = qp->sq_base[*wqe_idx].elem;
 218
 219         return wqe;
 220 }
 221
 222 /**
 223  * i40iw_puda_poll_info - poll cq for completion
 224  * @cq: cq for poll
 225  * @info: info return for successful completion
 226  */
 227 static enum i40iw_status_code i40iw_puda_poll_info(struct i40iw_sc_cq *cq,
 228                                                    struct i40iw_puda_completion_info *info)
 229 {
 230         u64 qword0, qword2, qword3;
 231         u64 *cqe;
 232         u64 comp_ctx;
 233         bool valid_bit;
 234         u32 major_err, minor_err;
 235         bool error;
 236
 237         cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&cq->cq_uk);
 238         get_64bit_val(cqe, 24, &qword3);
 239         valid_bit = (bool)RS_64(qword3, I40IW_CQ_VALID);
 240
 241         if (valid_bit != cq->cq_uk.polarity)
 242                 return I40IW_ERR_QUEUE_EMPTY;
 243
 244         i40iw_debug_buf(cq->dev, I40IW_DEBUG_PUDA, "PUDA CQE", cqe, 32);
 245         error = (bool)RS_64(qword3, I40IW_CQ_ERROR);
 246         if (error) {
 247                 i40iw_debug(cq->dev, I40IW_DEBUG_PUDA, "%s receive error\n", __func__);
 248                 major_err = (u32)(RS_64(qword3, I40IW_CQ_MAJERR));
 249                 minor_err = (u32)(RS_64(qword3, I40IW_CQ_MINERR));
 250                 info->compl_error = major_err << 16 | minor_err;
 251                 return I40IW_ERR_CQ_COMPL_ERROR;
 252         }
 253
 254         get_64bit_val(cqe, 0, &qword0);
 255         get_64bit_val(cqe, 16, &qword2);
 256
 257         info->q_type = (u8)RS_64(qword3, I40IW_CQ_SQ);
 258         info->qp_id = (u32)RS_64(qword2, I40IWCQ_QPID);
 259
 260         get_64bit_val(cqe, 8, &comp_ctx);
 261         info->qp = (struct i40iw_qp_uk *)(unsigned long)comp_ctx;
 262         info->wqe_idx = (u32)RS_64(qword3, I40IW_CQ_WQEIDX);
 263
 264         if (info->q_type == I40IW_CQE_QTYPE_RQ) {
 265                 info->vlan_valid = (bool)RS_64(qword3, I40IW_VLAN_TAG_VALID);
 266                 info->l4proto = (u8)RS_64(qword2, I40IW_UDA_L4PROTO);
 267                 info->l3proto = (u8)RS_64(qword2, I40IW_UDA_L3PROTO);
 268                 info->payload_len = (u16)RS_64(qword0, I40IW_UDA_PAYLOADLEN);
 269         }
 270
 271         return 0;
 272 }
 273
 274 /**
 275  * i40iw_puda_poll_completion - processes completion for cq
 276  * @dev: iwarp device
 277  * @cq: cq getting interrupt
 278  * @compl_err: return any completion err
 279  */
 280 enum i40iw_status_code i40iw_puda_poll_completion(struct i40iw_sc_dev *dev,
 281                                                   struct i40iw_sc_cq *cq, u32 *compl_err)
 282 {
 283         struct i40iw_qp_uk *qp;
 284         struct i40iw_cq_uk *cq_uk = &cq->cq_uk;
 285         struct i40iw_puda_completion_info info;
 286         enum i40iw_status_code ret = 0;
 287         struct i40iw_puda_buf *buf;
 288         struct i40iw_puda_rsrc *rsrc;
 289         void *sqwrid;
 290         u8 cq_type = cq->cq_type;
 291         unsigned long   flags;
 292
 293         if ((cq_type == I40IW_CQ_TYPE_ILQ) || (cq_type == I40IW_CQ_TYPE_IEQ)) {
 294                 rsrc = (cq_type == I40IW_CQ_TYPE_ILQ) ? cq->vsi->ilq : cq->vsi->ieq;
 295         } else {
 296                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s qp_type error\n", __func__);
 297                 return I40IW_ERR_BAD_PTR;
 298         }
 299         memset(&info, 0, sizeof(info));
 300         ret = i40iw_puda_poll_info(cq, &info);
 301         *compl_err = info.compl_error;
 302         if (ret == I40IW_ERR_QUEUE_EMPTY)
 303                 return ret;
 304         if (ret)
 305                 goto done;
 306
 307         qp = info.qp;
 308         if (!qp || !rsrc) {
 309                 ret = I40IW_ERR_BAD_PTR;
 310                 goto done;
 311         }
 312
 313         if (qp->qp_id != rsrc->qp_id) {
 314                 ret = I40IW_ERR_BAD_PTR;
 315                 goto done;
 316         }
 317
 318         if (info.q_type == I40IW_CQE_QTYPE_RQ) {
 319                 buf = (struct i40iw_puda_buf *)(uintptr_t)qp->rq_wrid_array[info.wqe_idx];
 320                 /* Get all the tcpip information in the buf header */
 321                 ret = i40iw_puda_get_tcpip_info(&info, buf);
 322                 if (ret) {
 323                         rsrc->stats_rcvd_pkt_err++;
 324                         if (cq_type == I40IW_CQ_TYPE_ILQ) {
 325                                 i40iw_ilq_putback_rcvbuf(&rsrc->qp,
 326                                                          info.wqe_idx);
 327                         } else {
 328                                 i40iw_puda_ret_bufpool(rsrc, buf);
 329                                 i40iw_puda_replenish_rq(rsrc, false);
 330                         }
 331                         goto done;
 332                 }
 333
 334                 rsrc->stats_pkt_rcvd++;
 335                 rsrc->compl_rxwqe_idx = info.wqe_idx;
 336                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s RQ completion\n", __func__);
 337                 rsrc->receive(rsrc->vsi, buf);
 338                 if (cq_type == I40IW_CQ_TYPE_ILQ)
 339                         i40iw_ilq_putback_rcvbuf(&rsrc->qp, info.wqe_idx);
 340                 else
 341                         i40iw_puda_replenish_rq(rsrc, false);
 342
 343         } else {
 344                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s SQ completion\n", __func__);
 345                 sqwrid = (void *)(uintptr_t)qp->sq_wrtrk_array[info.wqe_idx].wrid;
 346                 I40IW_RING_SET_TAIL(qp->sq_ring, info.wqe_idx);
 347                 rsrc->xmit_complete(rsrc->vsi, sqwrid);
 348                 spin_lock_irqsave(&rsrc->bufpool_lock, flags);
 349                 rsrc->tx_wqe_avail_cnt++;
 350                 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
 351                 if (!list_empty(&rsrc->txpend))
 352                         i40iw_puda_send_buf(rsrc, NULL);
 353         }
 354
 355 done:
 356         I40IW_RING_MOVE_HEAD(cq_uk->cq_ring, ret);
 357         if (I40IW_RING_GETCURRENT_HEAD(cq_uk->cq_ring) == 0)
 358                 cq_uk->polarity = !cq_uk->polarity;
 359         /* update cq tail in cq shadow memory also */
 360         I40IW_RING_MOVE_TAIL(cq_uk->cq_ring);
 361         set_64bit_val(cq_uk->shadow_area, 0,
 362                       I40IW_RING_GETCURRENT_HEAD(cq_uk->cq_ring));
 363         return 0;
 364 }
 365
 366 /**
 367  * i40iw_puda_send - complete send wqe for transmit
 368  * @qp: puda qp for send
 369  * @info: buffer information for transmit
 370  */
 371 enum i40iw_status_code i40iw_puda_send(struct i40iw_sc_qp *qp,
 372                                        struct i40iw_puda_send_info *info)
 373 {
 374         u64 *wqe;
 375         u32 iplen, l4len;
 376         u64 header[2];
 377         u32 wqe_idx;
 378         u8 iipt;
 379
 380         /* number of 32 bits DWORDS in header */
 381         l4len = info->tcplen >> 2;
 382         if (info->ipv4) {
 383                 iipt = 3;
 384                 iplen = 5;
 385         } else {
 386                 iipt = 1;
 387                 iplen = 10;
 388         }
 389
 390         wqe = i40iw_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx);
 391         if (!wqe)
 392                 return I40IW_ERR_QP_TOOMANY_WRS_POSTED;
 393         qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch;
 394         /* Third line of WQE descriptor */
 395         /* maclen is in words */
 396         header[0] = LS_64((info->maclen >> 1), I40IW_UDA_QPSQ_MACLEN) |
 397                     LS_64(iplen, I40IW_UDA_QPSQ_IPLEN) | LS_64(1, I40IW_UDA_QPSQ_L4T) |
 398                     LS_64(iipt, I40IW_UDA_QPSQ_IIPT) |
 399                     LS_64(l4len, I40IW_UDA_QPSQ_L4LEN);
 400         /* Forth line of WQE descriptor */
 401         header[1] = LS_64(I40IW_OP_TYPE_SEND, I40IW_UDA_QPSQ_OPCODE) |
 402                     LS_64(1, I40IW_UDA_QPSQ_SIGCOMPL) |
 403                     LS_64(info->doloopback, I40IW_UDA_QPSQ_DOLOOPBACK) |
 404                     LS_64(qp->qp_uk.swqe_polarity, I40IW_UDA_QPSQ_VALID);
 405
 406         set_64bit_val(wqe, 0, info->paddr);
 407         set_64bit_val(wqe, 8, LS_64(info->len, I40IWQPSQ_FRAG_LEN));
 408         set_64bit_val(wqe, 16, header[0]);
 409
 410         i40iw_insert_wqe_hdr(wqe, header[1]);
 411
 412         i40iw_debug_buf(qp->dev, I40IW_DEBUG_PUDA, "PUDA SEND WQE", wqe, 32);
 413         i40iw_qp_post_wr(&qp->qp_uk);
 414         return 0;
 415 }
 416
 417 /**
 418  * i40iw_puda_send_buf - transmit puda buffer
 419  * @rsrc: resource to use for buffer
 420  * @buf: puda buffer to transmit
 421  */
 422 void i40iw_puda_send_buf(struct i40iw_puda_rsrc *rsrc, struct i40iw_puda_buf *buf)
 423 {
 424         struct i40iw_puda_send_info info;
 425         enum i40iw_status_code ret = 0;
 426         unsigned long   flags;
 427
 428         spin_lock_irqsave(&rsrc->bufpool_lock, flags);
 429         /* if no wqe available or not from a completion and we have
 430          * pending buffers, we must queue new buffer
 431          */
 432         if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) {
 433                 list_add_tail(&buf->list, &rsrc->txpend);
 434                 spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
 435                 rsrc->stats_sent_pkt_q++;
 436                 if (rsrc->type == I40IW_PUDA_RSRC_TYPE_ILQ)
 437                         i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
 438                                     "%s: adding to txpend\n", __func__);
 439                 return;
 440         }
 441         rsrc->tx_wqe_avail_cnt--;
 442         /* if we are coming from a completion and have pending buffers
 443          * then Get one from pending list
 444          */
 445         if (!buf) {
 446                 buf = i40iw_puda_get_listbuf(&rsrc->txpend);
 447                 if (!buf)
 448                         goto done;
 449         }
 450
 451         info.scratch = (void *)buf;
 452         info.paddr = buf->mem.pa;
 453         info.len = buf->totallen;
 454         info.tcplen = buf->tcphlen;
 455         info.maclen = buf->maclen;
 456         info.ipv4 = buf->ipv4;
 457         info.doloopback = (rsrc->type == I40IW_PUDA_RSRC_TYPE_IEQ);
 458
 459         ret = i40iw_puda_send(&rsrc->qp, &info);
 460         if (ret) {
 461                 rsrc->tx_wqe_avail_cnt++;
 462                 rsrc->stats_sent_pkt_q++;
 463                 list_add(&buf->list, &rsrc->txpend);
 464                 if (rsrc->type == I40IW_PUDA_RSRC_TYPE_ILQ)
 465                         i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA,
 466                                     "%s: adding to puda_send\n", __func__);
 467         } else {
 468                 rsrc->stats_pkt_sent++;
 469         }
 470 done:
 471         spin_unlock_irqrestore(&rsrc->bufpool_lock, flags);
 472 }
 473
 474 /**
 475  * i40iw_puda_qp_setctx - during init, set qp's context
 476  * @rsrc: qp's resource
 477  */
 478 static void i40iw_puda_qp_setctx(struct i40iw_puda_rsrc *rsrc)
 479 {
 480         struct i40iw_sc_qp *qp = &rsrc->qp;
 481         u64 *qp_ctx = qp->hw_host_ctx;
 482
 483         set_64bit_val(qp_ctx, 8, qp->sq_pa);
 484         set_64bit_val(qp_ctx, 16, qp->rq_pa);
 485
 486         set_64bit_val(qp_ctx, 24,
 487                       LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
 488                       LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE));
 489
 490         set_64bit_val(qp_ctx, 48, LS_64(rsrc->buf_size, I40IW_UDA_QPC_MAXFRAMESIZE));
 491         set_64bit_val(qp_ctx, 56, 0);
 492         set_64bit_val(qp_ctx, 64, 1);
 493
 494         set_64bit_val(qp_ctx, 136,
 495                       LS_64(rsrc->cq_id, I40IWQPC_TXCQNUM) |
 496                       LS_64(rsrc->cq_id, I40IWQPC_RXCQNUM));
 497
 498         set_64bit_val(qp_ctx, 160, LS_64(1, I40IWQPC_PRIVEN));
 499
 500         set_64bit_val(qp_ctx, 168,
 501                       LS_64((uintptr_t)qp, I40IWQPC_QPCOMPCTX));
 502
 503         set_64bit_val(qp_ctx, 176,
 504                       LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
 505                       LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
 506                       LS_64(qp->qs_handle, I40IWQPC_QSHANDLE));
 507
 508         i40iw_debug_buf(rsrc->dev, I40IW_DEBUG_PUDA, "PUDA QP CONTEXT",
 509                         qp_ctx, I40IW_QP_CTX_SIZE);
 510 }
 511
 512 /**
 513  * i40iw_puda_qp_wqe - setup wqe for qp create
 514  * @dev: iwarp device
 515  * @qp: resource for qp
 516  */
 517 static enum i40iw_status_code i40iw_puda_qp_wqe(struct i40iw_sc_dev *dev, struct i40iw_sc_qp *qp)
 518 {
 519         struct i40iw_sc_cqp *cqp;
 520         u64 *wqe;
 521         u64 header;
 522         struct i40iw_ccq_cqe_info compl_info;
 523         enum i40iw_status_code status = 0;
 524
 525         cqp = dev->cqp;
 526         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, 0);
 527         if (!wqe)
 528                 return I40IW_ERR_RING_FULL;
 529
 530         set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
 531         set_64bit_val(wqe, 40, qp->shadow_area_pa);
 532         header = qp->qp_uk.qp_id |
 533                  LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) |
 534                  LS_64(I40IW_QP_TYPE_UDA, I40IW_CQPSQ_QP_QPTYPE) |
 535                  LS_64(1, I40IW_CQPSQ_QP_CQNUMVALID) |
 536                  LS_64(2, I40IW_CQPSQ_QP_NEXTIWSTATE) |
 537                  LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 538
 539         i40iw_insert_wqe_hdr(wqe, header);
 540
 541         i40iw_debug_buf(cqp->dev, I40IW_DEBUG_PUDA, "PUDA CQE", wqe, 32);
 542         i40iw_sc_cqp_post_sq(cqp);
 543         status = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 544                                                     I40IW_CQP_OP_CREATE_QP,
 545                                                     &compl_info);
 546         return status;
 547 }
 548
 549 /**
 550  * i40iw_puda_qp_create - create qp for resource
 551  * @rsrc: resource to use for buffer
 552  */
 553 static enum i40iw_status_code i40iw_puda_qp_create(struct i40iw_puda_rsrc *rsrc)
 554 {
 555         struct i40iw_sc_qp *qp = &rsrc->qp;
 556         struct i40iw_qp_uk *ukqp = &qp->qp_uk;
 557         enum i40iw_status_code ret = 0;
 558         u32 sq_size, rq_size, t_size;
 559         struct i40iw_dma_mem *mem;
 560
 561         sq_size = rsrc->sq_size * I40IW_QP_WQE_MIN_SIZE;
 562         rq_size = rsrc->rq_size * I40IW_QP_WQE_MIN_SIZE;
 563         t_size = (sq_size + rq_size + (I40IW_SHADOW_AREA_SIZE << 3) +
 564                   I40IW_QP_CTX_SIZE);
 565         /* Get page aligned memory */
 566         ret =
 567             i40iw_allocate_dma_mem(rsrc->dev->hw, &rsrc->qpmem, t_size,
 568                                    I40IW_HW_PAGE_SIZE);
 569         if (ret) {
 570                 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA, "%s: error dma mem\n", __func__);
 571                 return ret;
 572         }
 573
 574         mem = &rsrc->qpmem;
 575         memset(mem->va, 0, t_size);
 576         qp->hw_sq_size = i40iw_get_encoded_wqe_size(rsrc->sq_size, false);
 577         qp->hw_rq_size = i40iw_get_encoded_wqe_size(rsrc->rq_size, false);
 578         qp->pd = &rsrc->sc_pd;
 579         qp->qp_type = I40IW_QP_TYPE_UDA;
 580         qp->dev = rsrc->dev;
 581         qp->back_qp = (void *)rsrc;
 582         qp->sq_pa = mem->pa;
 583         qp->rq_pa = qp->sq_pa + sq_size;
 584         qp->vsi = rsrc->vsi;
 585         ukqp->sq_base = mem->va;
 586         ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size];
 587         ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem;
 588         qp->shadow_area_pa = qp->rq_pa + rq_size;
 589         qp->hw_host_ctx = ukqp->shadow_area + I40IW_SHADOW_AREA_SIZE;
 590         qp->hw_host_ctx_pa =
 591                 qp->shadow_area_pa + (I40IW_SHADOW_AREA_SIZE << 3);
 592         ukqp->qp_id = rsrc->qp_id;
 593         ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array;
 594         ukqp->rq_wrid_array = rsrc->rq_wrid_array;
 595
 596         ukqp->qp_id = rsrc->qp_id;
 597         ukqp->sq_size = rsrc->sq_size;
 598         ukqp->rq_size = rsrc->rq_size;
 599
 600         I40IW_RING_INIT(ukqp->sq_ring, ukqp->sq_size);
 601         I40IW_RING_INIT(ukqp->initial_ring, ukqp->sq_size);
 602         I40IW_RING_INIT(ukqp->rq_ring, ukqp->rq_size);
 603
 604         if (qp->pd->dev->is_pf)
 605                 ukqp->wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
 606                                                     I40E_PFPE_WQEALLOC);
 607         else
 608                 ukqp->wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
 609                                                     I40E_VFPE_WQEALLOC1);
 610
 611         qp->user_pri = 0;
 612         i40iw_qp_add_qos(qp);
 613         i40iw_puda_qp_setctx(rsrc);
 614         if (rsrc->dev->ceq_valid)
 615                 ret = i40iw_cqp_qp_create_cmd(rsrc->dev, qp);
 616         else
 617                 ret = i40iw_puda_qp_wqe(rsrc->dev, qp);
 618         if (ret) {
 619                 i40iw_qp_rem_qos(qp);
 620                 i40iw_free_dma_mem(rsrc->dev->hw, &rsrc->qpmem);
 621         }
 622         return ret;
 623 }
 624
 625 /**
 626  * i40iw_puda_cq_wqe - setup wqe for cq create
 627  * @dev: iwarp device
 628  * @cq: cq to setup
 629  */
 630 static enum i40iw_status_code i40iw_puda_cq_wqe(struct i40iw_sc_dev *dev, struct i40iw_sc_cq *cq)
 631 {
 632         u64 *wqe;
 633         struct i40iw_sc_cqp *cqp;
 634         u64 header;
 635         struct i40iw_ccq_cqe_info compl_info;
 636         enum i40iw_status_code status = 0;
 637
 638         cqp = dev->cqp;
 639         wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, 0);
 640         if (!wqe)
 641                 return I40IW_ERR_RING_FULL;
 642
 643         set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
 644         set_64bit_val(wqe, 8, RS_64_1(cq, 1));
 645         set_64bit_val(wqe, 16,
 646                       LS_64(cq->shadow_read_threshold,
 647                             I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
 648         set_64bit_val(wqe, 32, cq->cq_pa);
 649
 650         set_64bit_val(wqe, 40, cq->shadow_area_pa);
 651
 652         header = cq->cq_uk.cq_id |
 653             LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
 654             LS_64(1, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
 655             LS_64(1, I40IW_CQPSQ_CQ_ENCEQEMASK) |
 656             LS_64(1, I40IW_CQPSQ_CQ_CEQIDVALID) |
 657             LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
 658         i40iw_insert_wqe_hdr(wqe, header);
 659
 660         i40iw_debug_buf(dev, I40IW_DEBUG_PUDA, "PUDA CQE",
 661                         wqe, I40IW_CQP_WQE_SIZE * 8);
 662
 663         i40iw_sc_cqp_post_sq(dev->cqp);
 664         status = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 665                                                  I40IW_CQP_OP_CREATE_CQ,
 666                                                  &compl_info);
 667         return status;
 668 }
 669
 670 /**
 671  * i40iw_puda_cq_create - create cq for resource
 672  * @rsrc: resource for which cq to create
 673  */
 674 static enum i40iw_status_code i40iw_puda_cq_create(struct i40iw_puda_rsrc *rsrc)
 675 {
 676         struct i40iw_sc_dev *dev = rsrc->dev;
 677         struct i40iw_sc_cq *cq = &rsrc->cq;
 678         enum i40iw_status_code ret = 0;
 679         u32 tsize, cqsize;
 680         struct i40iw_dma_mem *mem;
 681         struct i40iw_cq_init_info info;
 682         struct i40iw_cq_uk_init_info *init_info = &info.cq_uk_init_info;
 683
 684         cq->vsi = rsrc->vsi;
 685         cqsize = rsrc->cq_size * (sizeof(struct i40iw_cqe));
 686         tsize = cqsize + sizeof(struct i40iw_cq_shadow_area);
 687         ret = i40iw_allocate_dma_mem(dev->hw, &rsrc->cqmem, tsize,
 688                                      I40IW_CQ0_ALIGNMENT);
 689         if (ret)
 690                 return ret;
 691
 692         mem = &rsrc->cqmem;
 693         memset(&info, 0, sizeof(info));
 694         info.dev = dev;
 695         info.type = (rsrc->type == I40IW_PUDA_RSRC_TYPE_ILQ) ?
 696                          I40IW_CQ_TYPE_ILQ : I40IW_CQ_TYPE_IEQ;
 697         info.shadow_read_threshold = rsrc->cq_size >> 2;
 698         info.ceq_id_valid = true;
 699         info.cq_base_pa = mem->pa;
 700         info.shadow_area_pa = mem->pa + cqsize;
 701         init_info->cq_base = mem->va;
 702         init_info->shadow_area = (u64 *)((u8 *)mem->va + cqsize);
 703         init_info->cq_size = rsrc->cq_size;
 704         init_info->cq_id = rsrc->cq_id;
 705         info.ceqe_mask = true;
 706         info.ceq_id_valid = true;
 707         ret = dev->iw_priv_cq_ops->cq_init(cq, &info);
 708         if (ret)
 709                 goto error;
 710         if (rsrc->dev->ceq_valid)
 711                 ret = i40iw_cqp_cq_create_cmd(dev, cq);
 712         else
 713                 ret = i40iw_puda_cq_wqe(dev, cq);
 714 error:
 715         if (ret)
 716                 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem);
 717         return ret;
 718 }
 719
 720 /**
 721  * i40iw_puda_free_qp - free qp for resource
 722  * @rsrc: resource for which qp to free
 723  */
 724 static void i40iw_puda_free_qp(struct i40iw_puda_rsrc *rsrc)
 725 {
 726         enum i40iw_status_code ret;
 727         struct i40iw_ccq_cqe_info compl_info;
 728         struct i40iw_sc_dev *dev = rsrc->dev;
 729
 730         if (rsrc->dev->ceq_valid) {
 731                 i40iw_cqp_qp_destroy_cmd(dev, &rsrc->qp);
 732                 return;
 733         }
 734
 735         ret = dev->iw_priv_qp_ops->qp_destroy(&rsrc->qp,
 736                         0, false, true, true);
 737         if (ret)
 738                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 739                             "%s error puda qp destroy wqe\n",
 740                             __func__);
 741
 742         if (!ret) {
 743                 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 744                                 I40IW_CQP_OP_DESTROY_QP,
 745                                 &compl_info);
 746                 if (ret)
 747                         i40iw_debug(dev, I40IW_DEBUG_PUDA,
 748                                     "%s error puda qp destroy failed\n",
 749                                     __func__);
 750         }
 751 }
 752
 753 /**
 754  * i40iw_puda_free_cq - free cq for resource
 755  * @rsrc: resource for which cq to free
 756  */
 757 static void i40iw_puda_free_cq(struct i40iw_puda_rsrc *rsrc)
 758 {
 759         enum i40iw_status_code ret;
 760         struct i40iw_ccq_cqe_info compl_info;
 761         struct i40iw_sc_dev *dev = rsrc->dev;
 762
 763         if (rsrc->dev->ceq_valid) {
 764                 i40iw_cqp_cq_destroy_cmd(dev, &rsrc->cq);
 765                 return;
 766         }
 767         ret = dev->iw_priv_cq_ops->cq_destroy(&rsrc->cq, 0, true);
 768
 769         if (ret)
 770                 i40iw_debug(dev, I40IW_DEBUG_PUDA,
 771                             "%s error ieq cq destroy\n",
 772                             __func__);
 773
 774         if (!ret) {
 775                 ret = dev->cqp_ops->poll_for_cqp_op_done(dev->cqp,
 776                                 I40IW_CQP_OP_DESTROY_CQ,
 777                                 &compl_info);
 778                 if (ret)
 779                         i40iw_debug(dev, I40IW_DEBUG_PUDA,
 780                                     "%s error ieq qp destroy done\n",
 781                                     __func__);
 782         }
 783 }
 784
 785 /**
 786  * i40iw_puda_dele_resources - delete all resources during close
 787  * @vsi: pointer to vsi structure
 788  * @type: type of resource to dele
 789  * @reset: true if reset chip
 790  */
 791 void i40iw_puda_dele_resources(struct i40iw_sc_vsi *vsi,
 792                                enum puda_resource_type type,
 793                                bool reset)
 794 {
 795         struct i40iw_sc_dev *dev = vsi->dev;
 796         struct i40iw_puda_rsrc *rsrc;
 797         struct i40iw_puda_buf *buf = NULL;
 798         struct i40iw_puda_buf *nextbuf = NULL;
 799         struct i40iw_virt_mem *vmem;
 800
 801         switch (type) {
 802         case I40IW_PUDA_RSRC_TYPE_ILQ:
 803                 rsrc = vsi->ilq;
 804                 vmem = &vsi->ilq_mem;
 805                 break;
 806         case I40IW_PUDA_RSRC_TYPE_IEQ:
 807                 rsrc = vsi->ieq;
 808                 vmem = &vsi->ieq_mem;
 809                 break;
 810         default:
 811                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "%s: error resource type = 0x%x\n",
 812                             __func__, type);
 813                 return;
 814         }
 815
 816         switch (rsrc->completion) {
 817         case PUDA_HASH_CRC_COMPLETE:
 818                 i40iw_free_hash_desc(rsrc->hash_desc);
 819                 fallthrough;
 820         case PUDA_QP_CREATED:
 821                 if (!reset)
 822                         i40iw_puda_free_qp(rsrc);
 823
 824                 i40iw_free_dma_mem(dev->hw, &rsrc->qpmem);
 825                 fallthrough;
 826         case PUDA_CQ_CREATED:
 827                 if (!reset)
 828                         i40iw_puda_free_cq(rsrc);
 829
 830                 i40iw_free_dma_mem(dev->hw, &rsrc->cqmem);
 831                 break;
 832         default:
 833                 i40iw_debug(rsrc->dev, I40IW_DEBUG_PUDA, "%s error no resources\n", __func__);
 834                 break;
 835         }
 836         /* Free all allocated puda buffers for both tx and rx */
 837         buf = rsrc->alloclist;
 838         while (buf) {
 839                 nextbuf = buf->next;
 840                 i40iw_puda_dele_buf(dev, buf);
 841                 buf = nextbuf;
 842                 rsrc->alloc_buf_count--;
 843         }
 844         i40iw_free_virt_mem(dev->hw, vmem);
 845 }
 846
 847 /**
 848  * i40iw_puda_allocbufs - allocate buffers for resource
 849  * @rsrc: resource for buffer allocation
 850  * @count: number of buffers to create
 851  */
 852 static enum i40iw_status_code i40iw_puda_allocbufs(struct i40iw_puda_rsrc *rsrc,
 853                                                    u32 count)
 854 {
 855         u32 i;
 856         struct i40iw_puda_buf *buf;
 857         struct i40iw_puda_buf *nextbuf;
 858
 859         for (i = 0; i < count; i++) {
 860                 buf = i40iw_puda_alloc_buf(rsrc->dev, rsrc->buf_size);
 861                 if (!buf) {
 862                         rsrc->stats_buf_alloc_fail++;
 863                         return I40IW_ERR_NO_MEMORY;
 864                 }
 865                 i40iw_puda_ret_bufpool(rsrc, buf);
 866                 rsrc->alloc_buf_count++;
 867                 if (!rsrc->alloclist) {
 868                         rsrc->alloclist = buf;
 869                 } else {
 870                         nextbuf = rsrc->alloclist;
 871                         rsrc->alloclist = buf;
 872                         buf->next = nextbuf;
 873                 }
 874         }
 875         rsrc->avail_buf_count = rsrc->alloc_buf_count;
 876         return 0;
 877 }
 878
 879 /**
 880  * i40iw_puda_create_rsrc - create resouce (ilq or ieq)
 881  * @vsi: pointer to vsi structure
 882  * @info: resource information
 883  */
 884 enum i40iw_status_code i40iw_puda_create_rsrc(struct i40iw_sc_vsi *vsi,
 885                                               struct i40iw_puda_rsrc_info *info)
 886 {
 887         struct i40iw_sc_dev *dev = vsi->dev;
 888         enum i40iw_status_code ret = 0;
 889         struct i40iw_puda_rsrc *rsrc;
 890         u32 pudasize;
 891         u32 sqwridsize, rqwridsize;
 892         struct i40iw_virt_mem *vmem;
 893
 894         info->count = 1;
 895         pudasize = sizeof(struct i40iw_puda_rsrc);
 896         sqwridsize = info->sq_size * sizeof(struct i40iw_sq_uk_wr_trk_info);
 897         rqwridsize = info->rq_size * 8;
 898         switch (info->type) {
 899         case I40IW_PUDA_RSRC_TYPE_ILQ:
 900                 vmem = &vsi->ilq_mem;
 901                 break;
 902         case I40IW_PUDA_RSRC_TYPE_IEQ:
 903                 vmem = &vsi->ieq_mem;
 904                 break;
 905         default:
 906                 return I40IW_NOT_SUPPORTED;
 907         }
 908         ret =
 909             i40iw_allocate_virt_mem(dev->hw, vmem,
 910                                     pudasize + sqwridsize + rqwridsize);
 911         if (ret)
 912                 return ret;
 913         rsrc = (struct i40iw_puda_rsrc *)vmem->va;
 914         spin_lock_init(&rsrc->bufpool_lock);
 915         if (info->type == I40IW_PUDA_RSRC_TYPE_ILQ) {
 916                 vsi->ilq = (struct i40iw_puda_rsrc *)vmem->va;
 917                 vsi->ilq_count = info->count;
 918                 rsrc->receive = info->receive;
 919                 rsrc->xmit_complete = info->xmit_complete;
 920         } else {
 921                 vmem = &vsi->ieq_mem;
 922                 vsi->ieq_count = info->count;
 923                 vsi->ieq = (struct i40iw_puda_rsrc *)vmem->va;
 924                 rsrc->receive = i40iw_ieq_receive;
 925                 rsrc->xmit_complete = i40iw_ieq_tx_compl;
 926         }
 927
 928         rsrc->type = info->type;
 929         rsrc->sq_wrtrk_array = (struct i40iw_sq_uk_wr_trk_info *)((u8 *)vmem->va + pudasize);
 930         rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize);
 931         /* Initialize all ieq lists */
 932         INIT_LIST_HEAD(&rsrc->bufpool);
 933         INIT_LIST_HEAD(&rsrc->txpend);
 934
 935         rsrc->tx_wqe_avail_cnt = info->sq_size - 1;
 936         dev->iw_pd_ops->pd_init(dev, &rsrc->sc_pd, info->pd_id, -1);
 937         rsrc->qp_id = info->qp_id;
 938         rsrc->cq_id = info->cq_id;
 939         rsrc->sq_size = info->sq_size;
 940         rsrc->rq_size = info->rq_size;
 941         rsrc->cq_size = info->rq_size + info->sq_size;
 942         rsrc->buf_size = info->buf_size;
 943         rsrc->dev = dev;
 944         rsrc->vsi = vsi;
 945
 946         ret = i40iw_puda_cq_create(rsrc);
 947         if (!ret) {
 948                 rsrc->completion = PUDA_CQ_CREATED;
 949                 ret = i40iw_puda_qp_create(rsrc);
 950         }
 951         if (ret) {
 952                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "[%s] error qp_create\n",
 953                             __func__);
 954                 goto error;
 955         }
 956         rsrc->completion = PUDA_QP_CREATED;
 957
 958         ret = i40iw_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size);
 959         if (ret) {
 960                 i40iw_debug(dev, I40IW_DEBUG_PUDA, "[%s] error alloc_buf\n",
 961                             __func__);
 962                 goto error;
 963         }
 964
 965         rsrc->rxq_invalid_cnt = info->rq_size;
 966         ret = i40iw_puda_replenish_rq(rsrc, true);
 967         if (ret)
 968                 goto error;
 969
 970         if (info->type == I40IW_PUDA_RSRC_TYPE_IEQ) {
 971                 if (!i40iw_init_hash_desc(&rsrc->hash_desc)) {
 972                         rsrc->check_crc = true;
 973                         rsrc->completion = PUDA_HASH_CRC_COMPLETE;
 974                         ret = 0;
 975                 }
 976         }
 977
 978         dev->ccq_ops->ccq_arm(&rsrc->cq);
 979         return ret;
 980  error:
 981         i40iw_puda_dele_resources(vsi, info->type, false);
 982
 983         return ret;
 984 }
 985
 986 /**
 987  * i40iw_ilq_putback_rcvbuf - ilq buffer to put back on rq
 988  * @qp: ilq's qp resource
 989  * @wqe_idx:  wqe index of completed rcvbuf
 990  */
 991 static void i40iw_ilq_putback_rcvbuf(struct i40iw_sc_qp *qp, u32 wqe_idx)
 992 {
 993         u64 *wqe;
 994         u64 offset24;
 995
 996         wqe = qp->qp_uk.rq_base[wqe_idx].elem;
 997         get_64bit_val(wqe, 24, &offset24);
 998         offset24 = (offset24) ? 0 : LS_64(1, I40IWQPSQ_VALID);
 999         set_64bit_val(wqe, 24, offset24);
1000 }
1001
1002 /**
1003  * i40iw_ieq_get_fpdu_length - given length return fpdu length
1004  * @length: length if fpdu
1005  */
1006 static u16 i40iw_ieq_get_fpdu_length(u16 length)
1007 {
1008         u16 fpdu_len;
1009
1010         fpdu_len = length + I40IW_IEQ_MPA_FRAMING;
1011         fpdu_len = (fpdu_len + 3) & 0xfffffffc;
1012         return fpdu_len;
1013 }
1014
1015 /**
1016  * i40iw_ieq_copy_to_txbuf - copydata from rcv buf to tx buf
1017  * @buf: rcv buffer with partial
1018  * @txbuf: tx buffer for sendign back
1019  * @buf_offset: rcv buffer offset to copy from
1020  * @txbuf_offset: at offset in tx buf to copy
1021  * @length: length of data to copy
1022  */
1023 static void i40iw_ieq_copy_to_txbuf(struct i40iw_puda_buf *buf,
1024                                     struct i40iw_puda_buf *txbuf,
1025                                     u16 buf_offset, u32 txbuf_offset,
1026                                     u32 length)
1027 {
1028         void *mem1 = (u8 *)buf->mem.va + buf_offset;
1029         void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset;
1030
1031         memcpy(mem2, mem1, length);
1032 }
1033
1034 /**
1035  * i40iw_ieq_setup_tx_buf - setup tx buffer for partial handling
1036  * @buf: reeive buffer with partial
1037  * @txbuf: buffer to prepare
1038  */
1039 static void i40iw_ieq_setup_tx_buf(struct i40iw_puda_buf *buf,
1040                                    struct i40iw_puda_buf *txbuf)
1041 {
1042         txbuf->maclen = buf->maclen;
1043         txbuf->tcphlen = buf->tcphlen;
1044         txbuf->ipv4 = buf->ipv4;
1045         txbuf->hdrlen = buf->hdrlen;
1046         i40iw_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen);
1047 }
1048
1049 /**
1050  * i40iw_ieq_check_first_buf - check if rcv buffer's seq is in range
1051  * @buf: receive exception buffer
1052  * @fps: first partial sequence number
1053  */
1054 static void i40iw_ieq_check_first_buf(struct i40iw_puda_buf *buf, u32 fps)
1055 {
1056         u32 offset;
1057
1058         if (buf->seqnum < fps) {
1059                 offset = fps - buf->seqnum;
1060                 if (offset > buf->datalen)
1061                         return;
1062                 buf->data += offset;
1063                 buf->datalen -= (u16)offset;
1064                 buf->seqnum = fps;
1065         }
1066 }
1067
1068 /**
1069  * i40iw_ieq_compl_pfpdu - write txbuf with full fpdu
1070  * @ieq: ieq resource
1071  * @rxlist: ieq's received buffer list
1072  * @pbufl: temporary list for buffers for fpddu
1073  * @txbuf: tx buffer for fpdu
1074  * @fpdu_len: total length of fpdu
1075  */
1076 static void  i40iw_ieq_compl_pfpdu(struct i40iw_puda_rsrc *ieq,
1077                                    struct list_head *rxlist,
1078                                    struct list_head *pbufl,
1079                                    struct i40iw_puda_buf *txbuf,
1080                                    u16 fpdu_len)
1081 {
1082         struct i40iw_puda_buf *buf;
1083         u32 nextseqnum;
1084         u16 txoffset, bufoffset;
1085
1086         buf = i40iw_puda_get_listbuf(pbufl);
1087         if (!buf)
1088                 return;
1089         nextseqnum = buf->seqnum + fpdu_len;
1090         txbuf->totallen = buf->hdrlen + fpdu_len;
1091         txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen;
1092         i40iw_ieq_setup_tx_buf(buf, txbuf);
1093
1094         txoffset = buf->hdrlen;
1095         bufoffset = (u16)(buf->data - (u8 *)buf->mem.va);
1096
1097         do {
1098                 if (buf->datalen >= fpdu_len) {
1099                         /* copied full fpdu */
1100                         i40iw_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, fpdu_len);
1101                         buf->datalen -= fpdu_len;
1102                         buf->data += fpdu_len;
1103                         buf->seqnum = nextseqnum;
1104                         break;
1105                 }
1106                 /* copy partial fpdu */
1107                 i40iw_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, buf->datalen);
1108                 txoffset += buf->datalen;
1109                 fpdu_len -= buf->datalen;
1110                 i40iw_puda_ret_bufpool(ieq, buf);
1111                 buf = i40iw_puda_get_listbuf(pbufl);
1112                 if (!buf)
1113                         return;
1114                 bufoffset = (u16)(buf->data - (u8 *)buf->mem.va);
1115         } while (1);
1116
1117         /* last buffer on the list*/
1118         if (buf->datalen)
1119                 list_add(&buf->list, rxlist);
1120         else
1121                 i40iw_puda_ret_bufpool(ieq, buf);
1122 }
1123
1124 /**
1125  * i40iw_ieq_create_pbufl - create buffer list for single fpdu
1126  * @pfpdu: partial management per user qp
1127  * @rxlist: resource list for receive ieq buffes
1128  * @pbufl: temp. list for buffers for fpddu
1129  * @buf: first receive buffer
1130  * @fpdu_len: total length of fpdu
1131  */
1132 static enum i40iw_status_code i40iw_ieq_create_pbufl(
1133                                                      struct i40iw_pfpdu *pfpdu,
1134                                                      struct list_head *rxlist,
1135                                                      struct list_head *pbufl,
1136                                                      struct i40iw_puda_buf *buf,
1137                                                      u16 fpdu_len)
1138 {
1139         enum i40iw_status_code status = 0;
1140         struct i40iw_puda_buf *nextbuf;
1141         u32     nextseqnum;
1142         u16 plen = fpdu_len - buf->datalen;
1143         bool done = false;
1144
1145         nextseqnum = buf->seqnum + buf->datalen;
1146         do {
1147                 nextbuf = i40iw_puda_get_listbuf(rxlist);
1148                 if (!nextbuf) {
1149                         status = I40IW_ERR_list_empty;
1150                         break;
1151                 }
1152                 list_add_tail(&nextbuf->list, pbufl);
1153                 if (nextbuf->seqnum != nextseqnum) {
1154                         pfpdu->bad_seq_num++;
1155                         status = I40IW_ERR_SEQ_NUM;
1156                         break;
1157                 }
1158                 if (nextbuf->datalen >= plen) {
1159                         done = true;
1160                 } else {
1161                         plen -= nextbuf->datalen;
1162                         nextseqnum = nextbuf->seqnum + nextbuf->datalen;
1163                 }
1164
1165         } while (!done);
1166
1167         return status;
1168 }
1169
1170 /**
1171  * i40iw_ieq_handle_partial - process partial fpdu buffer
1172  * @ieq: ieq resource
1173  * @pfpdu: partial management per user qp
1174  * @buf: receive buffer
1175  * @fpdu_len: fpdu len in the buffer
1176  */
1177 static enum i40iw_status_code i40iw_ieq_handle_partial(struct i40iw_puda_rsrc *ieq,
1178                                                        struct i40iw_pfpdu *pfpdu,
1179                                                        struct i40iw_puda_buf *buf,
1180                                                        u16 fpdu_len)
1181 {
1182         enum i40iw_status_code status = 0;
1183         u8 *crcptr;
1184         u32 mpacrc;
1185         u32 seqnum = buf->seqnum;
1186         struct list_head pbufl; /* partial buffer list */
1187         struct i40iw_puda_buf *txbuf = NULL;
1188         struct list_head *rxlist = &pfpdu->rxlist;
1189
1190         INIT_LIST_HEAD(&pbufl);
1191         list_add(&buf->list, &pbufl);
1192
1193         status = i40iw_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len);
1194         if (status)
1195                 goto error;
1196
1197         txbuf = i40iw_puda_get_bufpool(ieq);
1198         if (!txbuf) {
1199                 pfpdu->no_tx_bufs++;
1200                 status = I40IW_ERR_NO_TXBUFS;
1201                 goto error;
1202         }
1203
1204         i40iw_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len);
1205         i40iw_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum);
1206         crcptr = txbuf->data + fpdu_len - 4;
1207         mpacrc = *(u32 *)crcptr;
1208         if (ieq->check_crc) {
1209                 status = i40iw_ieq_check_mpacrc(ieq->hash_desc, txbuf->data,
1210                                                 (fpdu_len - 4), mpacrc);
1211                 if (status) {
1212                         i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1213                                     "%s: error bad crc\n", __func__);
1214                         goto error;
1215                 }
1216         }
1217
1218         i40iw_debug_buf(ieq->dev, I40IW_DEBUG_IEQ, "IEQ TX BUFFER",
1219                         txbuf->mem.va, txbuf->totallen);
1220         i40iw_puda_send_buf(ieq, txbuf);
1221         pfpdu->rcv_nxt = seqnum + fpdu_len;
1222         return status;
1223  error:
1224         while (!list_empty(&pbufl)) {
1225                 buf = (struct i40iw_puda_buf *)(pbufl.prev);
1226                 list_del(&buf->list);
1227                 list_add(&buf->list, rxlist);
1228         }
1229         if (txbuf)
1230                 i40iw_puda_ret_bufpool(ieq, txbuf);
1231         return status;
1232 }
1233
1234 /**
1235  * i40iw_ieq_process_buf - process buffer rcvd for ieq
1236  * @ieq: ieq resource
1237  * @pfpdu: partial management per user qp
1238  * @buf: receive buffer
1239  */
1240 static enum i40iw_status_code i40iw_ieq_process_buf(struct i40iw_puda_rsrc *ieq,
1241                                                     struct i40iw_pfpdu *pfpdu,
1242                                                     struct i40iw_puda_buf *buf)
1243 {
1244         u16 fpdu_len = 0;
1245         u16 datalen = buf->datalen;
1246         u8 *datap = buf->data;
1247         u8 *crcptr;
1248         u16 ioffset = 0;
1249         u32 mpacrc;
1250         u32 seqnum = buf->seqnum;
1251         u16 length = 0;
1252         u16 full = 0;
1253         bool partial = false;
1254         struct i40iw_puda_buf *txbuf;
1255         struct list_head *rxlist = &pfpdu->rxlist;
1256         enum i40iw_status_code ret = 0;
1257         enum i40iw_status_code status = 0;
1258
1259         ioffset = (u16)(buf->data - (u8 *)buf->mem.va);
1260         while (datalen) {
1261                 fpdu_len = i40iw_ieq_get_fpdu_length(ntohs(*(__be16 *)datap));
1262                 if (fpdu_len > pfpdu->max_fpdu_data) {
1263                         i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1264                                     "%s: error bad fpdu_len\n", __func__);
1265                         status = I40IW_ERR_MPA_CRC;
1266                         list_add(&buf->list, rxlist);
1267                         return status;
1268                 }
1269
1270                 if (datalen < fpdu_len) {
1271                         partial = true;
1272                         break;
1273                 }
1274                 crcptr = datap + fpdu_len - 4;
1275                 mpacrc = *(u32 *)crcptr;
1276                 if (ieq->check_crc)
1277                         ret = i40iw_ieq_check_mpacrc(ieq->hash_desc,
1278                                                      datap, fpdu_len - 4, mpacrc);
1279                 if (ret) {
1280                         status = I40IW_ERR_MPA_CRC;
1281                         list_add(&buf->list, rxlist);
1282                         return status;
1283                 }
1284                 full++;
1285                 pfpdu->fpdu_processed++;
1286                 datap += fpdu_len;
1287                 length += fpdu_len;
1288                 datalen -= fpdu_len;
1289         }
1290         if (full) {
1291                 /* copy full pdu's in the txbuf and send them out */
1292                 txbuf = i40iw_puda_get_bufpool(ieq);
1293                 if (!txbuf) {
1294                         pfpdu->no_tx_bufs++;
1295                         status = I40IW_ERR_NO_TXBUFS;
1296                         list_add(&buf->list, rxlist);
1297                         return status;
1298                 }
1299                 /* modify txbuf's buffer header */
1300                 i40iw_ieq_setup_tx_buf(buf, txbuf);
1301                 /* copy full fpdu's to new buffer */
1302                 i40iw_ieq_copy_to_txbuf(buf, txbuf, ioffset, buf->hdrlen,
1303                                         length);
1304                 txbuf->totallen = buf->hdrlen + length;
1305
1306                 i40iw_ieq_update_tcpip_info(txbuf, length, buf->seqnum);
1307                 i40iw_puda_send_buf(ieq, txbuf);
1308
1309                 if (!datalen) {
1310                         pfpdu->rcv_nxt = buf->seqnum + length;
1311                         i40iw_puda_ret_bufpool(ieq, buf);
1312                         return status;
1313                 }
1314                 buf->data = datap;
1315                 buf->seqnum = seqnum + length;
1316                 buf->datalen = datalen;
1317                 pfpdu->rcv_nxt = buf->seqnum;
1318         }
1319         if (partial)
1320                 status = i40iw_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len);
1321
1322         return status;
1323 }
1324
1325 /**
1326  * i40iw_ieq_process_fpdus - process fpdu's buffers on its list
1327  * @qp: qp for which partial fpdus
1328  * @ieq: ieq resource
1329  */
1330 static void i40iw_ieq_process_fpdus(struct i40iw_sc_qp *qp,
1331                                     struct i40iw_puda_rsrc *ieq)
1332 {
1333         struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1334         struct list_head *rxlist = &pfpdu->rxlist;
1335         struct i40iw_puda_buf *buf;
1336         enum i40iw_status_code status;
1337
1338         do {
1339                 if (list_empty(rxlist))
1340                         break;
1341                 buf = i40iw_puda_get_listbuf(rxlist);
1342                 if (!buf) {
1343                         i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1344                                     "%s: error no buf\n", __func__);
1345                         break;
1346                 }
1347                 if (buf->seqnum != pfpdu->rcv_nxt) {
1348                         /* This could be out of order or missing packet */
1349                         pfpdu->out_of_order++;
1350                         list_add(&buf->list, rxlist);
1351                         break;
1352                 }
1353                 /* keep processing buffers from the head of the list */
1354                 status = i40iw_ieq_process_buf(ieq, pfpdu, buf);
1355                 if (status == I40IW_ERR_MPA_CRC) {
1356                         pfpdu->mpa_crc_err = true;
1357                         while (!list_empty(rxlist)) {
1358                                 buf = i40iw_puda_get_listbuf(rxlist);
1359                                 i40iw_puda_ret_bufpool(ieq, buf);
1360                                 pfpdu->crc_err++;
1361                         }
1362                         /* create CQP for AE */
1363                         i40iw_ieq_mpa_crc_ae(ieq->dev, qp);
1364                 }
1365         } while (!status);
1366 }
1367
1368 /**
1369  * i40iw_ieq_handle_exception - handle qp's exception
1370  * @ieq: ieq resource
1371  * @qp: qp receiving excpetion
1372  * @buf: receive buffer
1373  */
1374 static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
1375                                        struct i40iw_sc_qp *qp,
1376                                        struct i40iw_puda_buf *buf)
1377 {
1378         struct i40iw_puda_buf *tmpbuf = NULL;
1379         struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1380         u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx;
1381         u32 rcv_wnd = hw_host_ctx[23];
1382         /* first partial seq # in q2 */
1383         u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET);
1384         struct list_head *rxlist = &pfpdu->rxlist;
1385         struct list_head *plist;
1386
1387         pfpdu->total_ieq_bufs++;
1388
1389         if (pfpdu->mpa_crc_err) {
1390                 pfpdu->crc_err++;
1391                 goto error;
1392         }
1393         if (pfpdu->mode && (fps != pfpdu->fps)) {
1394                 /* clean up qp as it is new partial sequence */
1395                 i40iw_ieq_cleanup_qp(ieq, qp);
1396                 i40iw_debug(ieq->dev, I40IW_DEBUG_IEQ,
1397                             "%s: restarting new partial\n", __func__);
1398                 pfpdu->mode = false;
1399         }
1400
1401         if (!pfpdu->mode) {
1402                 i40iw_debug_buf(ieq->dev, I40IW_DEBUG_IEQ, "Q2 BUFFER", (u64 *)qp->q2_buf, 128);
1403                 /* First_Partial_Sequence_Number check */
1404                 pfpdu->rcv_nxt = fps;
1405                 pfpdu->fps = fps;
1406                 pfpdu->mode = true;
1407                 pfpdu->max_fpdu_data = (buf->ipv4) ? (ieq->vsi->mtu - I40IW_MTU_TO_MSS_IPV4) :
1408                                        (ieq->vsi->mtu - I40IW_MTU_TO_MSS_IPV6);
1409                 pfpdu->pmode_count++;
1410                 INIT_LIST_HEAD(rxlist);
1411                 i40iw_ieq_check_first_buf(buf, fps);
1412         }
1413
1414         if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) {
1415                 pfpdu->bad_seq_num++;
1416                 goto error;
1417         }
1418
1419         if (!list_empty(rxlist)) {
1420                 tmpbuf = (struct i40iw_puda_buf *)rxlist->next;
1421                 while ((struct list_head *)tmpbuf != rxlist) {
1422                         if ((int)(buf->seqnum - tmpbuf->seqnum) < 0)
1423                                 break;
1424                         plist = &tmpbuf->list;
1425                         tmpbuf = (struct i40iw_puda_buf *)plist->next;
1426                 }
1427                 /* Insert buf before tmpbuf */
1428                 list_add_tail(&buf->list, &tmpbuf->list);
1429         } else {
1430                 list_add_tail(&buf->list, rxlist);
1431         }
1432         i40iw_ieq_process_fpdus(qp, ieq);
1433         return;
1434  error:
1435         i40iw_puda_ret_bufpool(ieq, buf);
1436 }
1437
1438 /**
1439  * i40iw_ieq_receive - received exception buffer
1440  * @vsi: pointer to vsi structure
1441  * @buf: exception buffer received
1442  */
1443 static void i40iw_ieq_receive(struct i40iw_sc_vsi *vsi,
1444                               struct i40iw_puda_buf *buf)
1445 {
1446         struct i40iw_puda_rsrc *ieq = vsi->ieq;
1447         struct i40iw_sc_qp *qp = NULL;
1448         u32 wqe_idx = ieq->compl_rxwqe_idx;
1449
1450         qp = i40iw_ieq_get_qp(vsi->dev, buf);
1451         if (!qp) {
1452                 ieq->stats_bad_qp_id++;
1453                 i40iw_puda_ret_bufpool(ieq, buf);
1454         } else {
1455                 i40iw_ieq_handle_exception(ieq, qp, buf);
1456         }
1457         /*
1458          * ieq->rx_wqe_idx is used by i40iw_puda_replenish_rq()
1459          * on which wqe_idx to start replenish rq
1460          */
1461         if (!ieq->rxq_invalid_cnt)
1462                 ieq->rx_wqe_idx = wqe_idx;
1463         ieq->rxq_invalid_cnt++;
1464 }
1465
1466 /**
1467  * i40iw_ieq_tx_compl - put back after sending completed exception buffer
1468  * @vsi: pointer to the vsi structure
1469  * @sqwrid: pointer to puda buffer
1470  */
1471 static void i40iw_ieq_tx_compl(struct i40iw_sc_vsi *vsi, void *sqwrid)
1472 {
1473         struct i40iw_puda_rsrc *ieq = vsi->ieq;
1474         struct i40iw_puda_buf *buf = (struct i40iw_puda_buf *)sqwrid;
1475
1476         i40iw_puda_ret_bufpool(ieq, buf);
1477 }
1478
1479 /**
1480  * i40iw_ieq_cleanup_qp - qp is being destroyed
1481  * @ieq: ieq resource
1482  * @qp: all pending fpdu buffers
1483  */
1484 void i40iw_ieq_cleanup_qp(struct i40iw_puda_rsrc *ieq, struct i40iw_sc_qp *qp)
1485 {
1486         struct i40iw_puda_buf *buf;
1487         struct i40iw_pfpdu *pfpdu = &qp->pfpdu;
1488         struct list_head *rxlist = &pfpdu->rxlist;
1489
1490         if (!pfpdu->mode)
1491                 return;
1492         while (!list_empty(rxlist)) {
1493                 buf = i40iw_puda_get_listbuf(rxlist);
1494                 i40iw_puda_ret_bufpool(ieq, buf);
1495         }
1496 }