drivers/infiniband/hw/hns/hns_roce_main.c

   1 /*
   2  * Copyright (c) 2016 Hisilicon Limited.
   3  * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
   4  *
   5  * This software is available to you under a choice of one of two
   6  * licenses.  You may choose to be licensed under the terms of the GNU
   7  * General Public License (GPL) Version 2, available from the file
   8  * COPYING in the main directory of this source tree, or the
   9  * OpenIB.org BSD license below:
  10  *
  11  *     Redistribution and use in source and binary forms, with or
  12  *     without modification, are permitted provided that the following
  13  *     conditions are met:
  14  *
  15  *      - Redistributions of source code must retain the above
  16  *        copyright notice, this list of conditions and the following
  17  *        disclaimer.
  18  *
  19  *      - Redistributions in binary form must reproduce the above
  20  *        copyright notice, this list of conditions and the following
  21  *        disclaimer in the documentation and/or other materials
  22  *        provided with the distribution.
  23  *
  24  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31  * SOFTWARE.
  32  */
  33 #include <linux/acpi.h>
  34 #include <linux/of_platform.h>
  35 #include <linux/module.h>
  36 #include <rdma/ib_addr.h>
  37 #include <rdma/ib_smi.h>
  38 #include <rdma/ib_user_verbs.h>
  39 #include <rdma/ib_cache.h>
  40 #include "hns_roce_common.h"
  41 #include "hns_roce_device.h"
  42 #include <rdma/hns-abi.h>
  43 #include "hns_roce_hem.h"
  44
  45 /**
  46  * hns_get_gid_index - Get gid index.
  47  * @hr_dev: pointer to structure hns_roce_dev.
  48  * @port:  port, value range: 0 ~ MAX
  49  * @gid_index:  gid_index, value range: 0 ~ MAX
  50  * Description:
  51  *    N ports shared gids, allocation method as follow:
  52  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  53  *              GID[0][0], GID[1][0],.....GID[N - 1][0],
  54  *              And so on
  55  */
  56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
  57 {
  58         return gid_index * hr_dev->caps.num_ports + port;
  59 }
  60 EXPORT_SYMBOL_GPL(hns_get_gid_index);
  61
  62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
  63 {
  64         u8 phy_port;
  65         u32 i = 0;
  66
  67         if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
  68                 return 0;
  69
  70         for (i = 0; i < ETH_ALEN; i++)
  71                 hr_dev->dev_addr[port][i] = addr[i];
  72
  73         phy_port = hr_dev->iboe.phy_port[port];
  74         return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
  75 }
  76
  77 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
  78 {
  79         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  80         u8 port = attr->port_num - 1;
  81         int ret;
  82
  83         if (port >= hr_dev->caps.num_ports)
  84                 return -EINVAL;
  85
  86         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
  87
  88         return ret;
  89 }
  90
  91 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
  92 {
  93         struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
  94         struct ib_gid_attr zattr = { };
  95         u8 port = attr->port_num - 1;
  96         int ret;
  97
  98         if (port >= hr_dev->caps.num_ports)
  99                 return -EINVAL;
 100
 101         ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
 102
 103         return ret;
 104 }
 105
 106 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
 107                            unsigned long event)
 108 {
 109         struct device *dev = hr_dev->dev;
 110         struct net_device *netdev;
 111         int ret = 0;
 112
 113         netdev = hr_dev->iboe.netdevs[port];
 114         if (!netdev) {
 115                 dev_err(dev, "port(%d) can't find netdev\n", port);
 116                 return -ENODEV;
 117         }
 118
 119         switch (event) {
 120         case NETDEV_UP:
 121         case NETDEV_CHANGE:
 122         case NETDEV_REGISTER:
 123         case NETDEV_CHANGEADDR:
 124                 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
 125                 break;
 126         case NETDEV_DOWN:
 127                 /*
 128                  * In v1 engine, only support all ports closed together.
 129                  */
 130                 break;
 131         default:
 132                 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
 133                 break;
 134         }
 135
 136         return ret;
 137 }
 138
 139 static int hns_roce_netdev_event(struct notifier_block *self,
 140                                  unsigned long event, void *ptr)
 141 {
 142         struct net_device *dev = netdev_notifier_info_to_dev(ptr);
 143         struct hns_roce_ib_iboe *iboe = NULL;
 144         struct hns_roce_dev *hr_dev = NULL;
 145         u8 port = 0;
 146         int ret = 0;
 147
 148         hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
 149         iboe = &hr_dev->iboe;
 150
 151         for (port = 0; port < hr_dev->caps.num_ports; port++) {
 152                 if (dev == iboe->netdevs[port]) {
 153                         ret = handle_en_event(hr_dev, port, event);
 154                         if (ret)
 155                                 return NOTIFY_DONE;
 156                         break;
 157                 }
 158         }
 159
 160         return NOTIFY_DONE;
 161 }
 162
 163 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
 164 {
 165         int ret;
 166         u8 i;
 167
 168         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 169                 if (hr_dev->hw->set_mtu)
 170                         hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
 171                                             hr_dev->caps.max_mtu);
 172                 ret = hns_roce_set_mac(hr_dev, i,
 173                                        hr_dev->iboe.netdevs[i]->dev_addr);
 174                 if (ret)
 175                         return ret;
 176         }
 177
 178         return 0;
 179 }
 180
 181 static int hns_roce_query_device(struct ib_device *ib_dev,
 182                                  struct ib_device_attr *props,
 183                                  struct ib_udata *uhw)
 184 {
 185         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 186
 187         memset(props, 0, sizeof(*props));
 188
 189         props->fw_ver = hr_dev->caps.fw_ver;
 190         props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
 191         props->max_mr_size = (u64)(~(0ULL));
 192         props->page_size_cap = hr_dev->caps.page_size_cap;
 193         props->vendor_id = hr_dev->vendor_id;
 194         props->vendor_part_id = hr_dev->vendor_part_id;
 195         props->hw_ver = hr_dev->hw_rev;
 196         props->max_qp = hr_dev->caps.num_qps;
 197         props->max_qp_wr = hr_dev->caps.max_wqes;
 198         props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
 199                                   IB_DEVICE_RC_RNR_NAK_GEN;
 200         props->max_send_sge = hr_dev->caps.max_sq_sg;
 201         props->max_recv_sge = hr_dev->caps.max_rq_sg;
 202         props->max_sge_rd = 1;
 203         props->max_cq = hr_dev->caps.num_cqs;
 204         props->max_cqe = hr_dev->caps.max_cqes;
 205         props->max_mr = hr_dev->caps.num_mtpts;
 206         props->max_pd = hr_dev->caps.num_pds;
 207         props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
 208         props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
 209         props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
 210                             IB_ATOMIC_HCA : IB_ATOMIC_NONE;
 211         props->max_pkeys = 1;
 212         props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
 213         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 214                 props->max_srq = hr_dev->caps.max_srqs;
 215                 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
 216                 props->max_srq_sge = hr_dev->caps.max_srq_sges;
 217         }
 218
 219         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR) {
 220                 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
 221                 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
 222         }
 223
 224         return 0;
 225 }
 226
 227 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
 228                                struct ib_port_attr *props)
 229 {
 230         struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
 231         struct device *dev = hr_dev->dev;
 232         struct net_device *net_dev;
 233         unsigned long flags;
 234         enum ib_mtu mtu;
 235         u8 port;
 236
 237         assert(port_num > 0);
 238         port = port_num - 1;
 239
 240         /* props being zeroed by the caller, avoid zeroing it here */
 241
 242         props->max_mtu = hr_dev->caps.max_mtu;
 243         props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
 244         props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
 245                                 IB_PORT_VENDOR_CLASS_SUP |
 246                                 IB_PORT_BOOT_MGMT_SUP;
 247         props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
 248         props->pkey_tbl_len = 1;
 249         props->active_width = IB_WIDTH_4X;
 250         props->active_speed = 1;
 251
 252         spin_lock_irqsave(&hr_dev->iboe.lock, flags);
 253
 254         net_dev = hr_dev->iboe.netdevs[port];
 255         if (!net_dev) {
 256                 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 257                 dev_err(dev, "find netdev %d failed!\r\n", port);
 258                 return -EINVAL;
 259         }
 260
 261         mtu = iboe_get_mtu(net_dev->mtu);
 262         props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
 263         props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
 264                         IB_PORT_ACTIVE : IB_PORT_DOWN;
 265         props->phys_state = (props->state == IB_PORT_ACTIVE) ?
 266                              HNS_ROCE_PHY_LINKUP : HNS_ROCE_PHY_DISABLED;
 267
 268         spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
 269
 270         return 0;
 271 }
 272
 273 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
 274                                                     u8 port_num)
 275 {
 276         return IB_LINK_LAYER_ETHERNET;
 277 }
 278
 279 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
 280                                u16 *pkey)
 281 {
 282         *pkey = PKEY_ID;
 283
 284         return 0;
 285 }
 286
 287 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
 288                                   struct ib_device_modify *props)
 289 {
 290         unsigned long flags;
 291
 292         if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
 293                 return -EOPNOTSUPP;
 294
 295         if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
 296                 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
 297                 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
 298                 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
 305                                 struct ib_port_modify *props)
 306 {
 307         return 0;
 308 }
 309
 310 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
 311                                    struct ib_udata *udata)
 312 {
 313         int ret = 0;
 314         struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
 315         struct hns_roce_ib_alloc_ucontext_resp resp = {};
 316         struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
 317
 318         if (!hr_dev->active)
 319                 return -EAGAIN;
 320
 321         resp.qp_tab_size = hr_dev->caps.num_qps;
 322
 323         ret = hns_roce_uar_alloc(hr_dev, &context->uar);
 324         if (ret)
 325                 goto error_fail_uar_alloc;
 326
 327         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
 328                 INIT_LIST_HEAD(&context->page_list);
 329                 mutex_init(&context->page_mutex);
 330         }
 331
 332         ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
 333         if (ret)
 334                 goto error_fail_copy_to_udata;
 335
 336         return 0;
 337
 338 error_fail_copy_to_udata:
 339         hns_roce_uar_free(hr_dev, &context->uar);
 340
 341 error_fail_uar_alloc:
 342         return ret;
 343 }
 344
 345 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
 346 {
 347         struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
 348
 349         hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
 350 }
 351
 352 static int hns_roce_mmap(struct ib_ucontext *context,
 353                          struct vm_area_struct *vma)
 354 {
 355         struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
 356
 357         switch (vma->vm_pgoff) {
 358         case 0:
 359                 return rdma_user_mmap_io(context, vma,
 360                                          to_hr_ucontext(context)->uar.pfn,
 361                                          PAGE_SIZE,
 362                                          pgprot_noncached(vma->vm_page_prot));
 363
 364         /* vm_pgoff: 1 -- TPTR */
 365         case 1:
 366                 if (!hr_dev->tptr_dma_addr || !hr_dev->tptr_size)
 367                         return -EINVAL;
 368                 /*
 369                  * FIXME: using io_remap_pfn_range on the dma address returned
 370                  * by dma_alloc_coherent is totally wrong.
 371                  */
 372                 return rdma_user_mmap_io(context, vma,
 373                                          hr_dev->tptr_dma_addr >> PAGE_SHIFT,
 374                                          hr_dev->tptr_size,
 375                                          vma->vm_page_prot);
 376
 377         default:
 378                 return -EINVAL;
 379         }
 380 }
 381
 382 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
 383                                    struct ib_port_immutable *immutable)
 384 {
 385         struct ib_port_attr attr;
 386         int ret;
 387
 388         ret = ib_query_port(ib_dev, port_num, &attr);
 389         if (ret)
 390                 return ret;
 391
 392         immutable->pkey_tbl_len = attr.pkey_tbl_len;
 393         immutable->gid_tbl_len = attr.gid_tbl_len;
 394
 395         immutable->max_mad_size = IB_MGMT_MAD_SIZE;
 396         immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
 397         if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
 398                 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
 399
 400         return 0;
 401 }
 402
 403 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
 404 {
 405 }
 406
 407 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
 408 {
 409         struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
 410
 411         hr_dev->active = false;
 412         unregister_netdevice_notifier(&iboe->nb);
 413         ib_unregister_device(&hr_dev->ib_dev);
 414 }
 415
 416 static const struct ib_device_ops hns_roce_dev_ops = {
 417         .driver_id = RDMA_DRIVER_HNS,
 418         .uverbs_abi_ver = 1,
 419
 420         .add_gid = hns_roce_add_gid,
 421         .alloc_pd = hns_roce_alloc_pd,
 422         .alloc_ucontext = hns_roce_alloc_ucontext,
 423         .create_ah = hns_roce_create_ah,
 424         .create_cq = hns_roce_ib_create_cq,
 425         .create_qp = hns_roce_create_qp,
 426         .dealloc_pd = hns_roce_dealloc_pd,
 427         .dealloc_ucontext = hns_roce_dealloc_ucontext,
 428         .del_gid = hns_roce_del_gid,
 429         .dereg_mr = hns_roce_dereg_mr,
 430         .destroy_ah = hns_roce_destroy_ah,
 431         .destroy_cq = hns_roce_ib_destroy_cq,
 432         .disassociate_ucontext = hns_roce_disassociate_ucontext,
 433         .fill_res_entry = hns_roce_fill_res_entry,
 434         .get_dma_mr = hns_roce_get_dma_mr,
 435         .get_link_layer = hns_roce_get_link_layer,
 436         .get_port_immutable = hns_roce_port_immutable,
 437         .mmap = hns_roce_mmap,
 438         .modify_device = hns_roce_modify_device,
 439         .modify_port = hns_roce_modify_port,
 440         .modify_qp = hns_roce_modify_qp,
 441         .query_ah = hns_roce_query_ah,
 442         .query_device = hns_roce_query_device,
 443         .query_pkey = hns_roce_query_pkey,
 444         .query_port = hns_roce_query_port,
 445         .reg_user_mr = hns_roce_reg_user_mr,
 446
 447         INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
 448         INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
 449         INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
 450 };
 451
 452 static const struct ib_device_ops hns_roce_dev_mr_ops = {
 453         .rereg_user_mr = hns_roce_rereg_user_mr,
 454 };
 455
 456 static const struct ib_device_ops hns_roce_dev_mw_ops = {
 457         .alloc_mw = hns_roce_alloc_mw,
 458         .dealloc_mw = hns_roce_dealloc_mw,
 459 };
 460
 461 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
 462         .alloc_mr = hns_roce_alloc_mr,
 463         .map_mr_sg = hns_roce_map_mr_sg,
 464 };
 465
 466 static const struct ib_device_ops hns_roce_dev_srq_ops = {
 467         .create_srq = hns_roce_create_srq,
 468         .destroy_srq = hns_roce_destroy_srq,
 469
 470         INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
 471 };
 472
 473 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
 474 {
 475         int ret;
 476         struct hns_roce_ib_iboe *iboe = NULL;
 477         struct ib_device *ib_dev = NULL;
 478         struct device *dev = hr_dev->dev;
 479         unsigned int i;
 480
 481         iboe = &hr_dev->iboe;
 482         spin_lock_init(&iboe->lock);
 483
 484         ib_dev = &hr_dev->ib_dev;
 485
 486         ib_dev->owner                   = THIS_MODULE;
 487         ib_dev->node_type               = RDMA_NODE_IB_CA;
 488         ib_dev->dev.parent              = dev;
 489
 490         ib_dev->phys_port_cnt           = hr_dev->caps.num_ports;
 491         ib_dev->local_dma_lkey          = hr_dev->caps.reserved_lkey;
 492         ib_dev->num_comp_vectors        = hr_dev->caps.num_comp_vectors;
 493         ib_dev->uverbs_cmd_mask         =
 494                 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
 495                 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
 496                 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
 497                 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
 498                 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
 499                 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
 500                 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
 501                 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
 502                 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
 503                 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
 504                 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
 505                 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
 506                 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
 507                 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
 508
 509         ib_dev->uverbs_ex_cmd_mask |=
 510                 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
 511
 512         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
 513                 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
 514                 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
 515         }
 516
 517         /* MW */
 518         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW) {
 519                 ib_dev->uverbs_cmd_mask |=
 520                                         (1ULL << IB_USER_VERBS_CMD_ALLOC_MW) |
 521                                         (1ULL << IB_USER_VERBS_CMD_DEALLOC_MW);
 522                 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
 523         }
 524
 525         /* FRMR */
 526         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
 527                 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
 528
 529         /* SRQ */
 530         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 531                 ib_dev->uverbs_cmd_mask |=
 532                                 (1ULL << IB_USER_VERBS_CMD_CREATE_SRQ) |
 533                                 (1ULL << IB_USER_VERBS_CMD_MODIFY_SRQ) |
 534                                 (1ULL << IB_USER_VERBS_CMD_QUERY_SRQ) |
 535                                 (1ULL << IB_USER_VERBS_CMD_DESTROY_SRQ) |
 536                                 (1ULL << IB_USER_VERBS_CMD_POST_SRQ_RECV);
 537                 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
 538                 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
 539         }
 540
 541         ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
 542         ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
 543         for (i = 0; i < hr_dev->caps.num_ports; i++) {
 544                 if (!hr_dev->iboe.netdevs[i])
 545                         continue;
 546
 547                 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
 548                                            i + 1);
 549                 if (ret)
 550                         return ret;
 551         }
 552         ret = ib_register_device(ib_dev, "hns_%d");
 553         if (ret) {
 554                 dev_err(dev, "ib_register_device failed!\n");
 555                 return ret;
 556         }
 557
 558         ret = hns_roce_setup_mtu_mac(hr_dev);
 559         if (ret) {
 560                 dev_err(dev, "setup_mtu_mac failed!\n");
 561                 goto error_failed_setup_mtu_mac;
 562         }
 563
 564         iboe->nb.notifier_call = hns_roce_netdev_event;
 565         ret = register_netdevice_notifier(&iboe->nb);
 566         if (ret) {
 567                 dev_err(dev, "register_netdevice_notifier failed!\n");
 568                 goto error_failed_setup_mtu_mac;
 569         }
 570
 571         hr_dev->active = true;
 572         return 0;
 573
 574 error_failed_setup_mtu_mac:
 575         ib_unregister_device(ib_dev);
 576
 577         return ret;
 578 }
 579
 580 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
 581 {
 582         int ret;
 583         struct device *dev = hr_dev->dev;
 584
 585         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
 586                                       HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
 587                                       hr_dev->caps.num_mtt_segs, 1);
 588         if (ret) {
 589                 dev_err(dev, "Failed to init MTT context memory, aborting.\n");
 590                 return ret;
 591         }
 592
 593         if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
 594                 ret = hns_roce_init_hem_table(hr_dev,
 595                                       &hr_dev->mr_table.mtt_cqe_table,
 596                                       HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
 597                                       hr_dev->caps.num_cqe_segs, 1);
 598                 if (ret) {
 599                         dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
 600                         goto err_unmap_cqe;
 601                 }
 602         }
 603
 604         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
 605                                       HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
 606                                       hr_dev->caps.num_mtpts, 1);
 607         if (ret) {
 608                 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
 609                 goto err_unmap_mtt;
 610         }
 611
 612         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
 613                                       HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
 614                                       hr_dev->caps.num_qps, 1);
 615         if (ret) {
 616                 dev_err(dev, "Failed to init QP context memory, aborting.\n");
 617                 goto err_unmap_dmpt;
 618         }
 619
 620         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
 621                                       HEM_TYPE_IRRL,
 622                                       hr_dev->caps.irrl_entry_sz *
 623                                       hr_dev->caps.max_qp_init_rdma,
 624                                       hr_dev->caps.num_qps, 1);
 625         if (ret) {
 626                 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
 627                 goto err_unmap_qp;
 628         }
 629
 630         if (hr_dev->caps.trrl_entry_sz) {
 631                 ret = hns_roce_init_hem_table(hr_dev,
 632                                               &hr_dev->qp_table.trrl_table,
 633                                               HEM_TYPE_TRRL,
 634                                               hr_dev->caps.trrl_entry_sz *
 635                                               hr_dev->caps.max_qp_dest_rdma,
 636                                               hr_dev->caps.num_qps, 1);
 637                 if (ret) {
 638                         dev_err(dev,
 639                                "Failed to init trrl_table memory, aborting.\n");
 640                         goto err_unmap_irrl;
 641                 }
 642         }
 643
 644         ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
 645                                       HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
 646                                       hr_dev->caps.num_cqs, 1);
 647         if (ret) {
 648                 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
 649                 goto err_unmap_trrl;
 650         }
 651
 652         if (hr_dev->caps.srqc_entry_sz) {
 653                 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
 654                                               HEM_TYPE_SRQC,
 655                                               hr_dev->caps.srqc_entry_sz,
 656                                               hr_dev->caps.num_srqs, 1);
 657                 if (ret) {
 658                         dev_err(dev,
 659                               "Failed to init SRQ context memory, aborting.\n");
 660                         goto err_unmap_cq;
 661                 }
 662         }
 663
 664         if (hr_dev->caps.num_srqwqe_segs) {
 665                 ret = hns_roce_init_hem_table(hr_dev,
 666                                              &hr_dev->mr_table.mtt_srqwqe_table,
 667                                              HEM_TYPE_SRQWQE,
 668                                              hr_dev->caps.mtt_entry_sz,
 669                                              hr_dev->caps.num_srqwqe_segs, 1);
 670                 if (ret) {
 671                         dev_err(dev,
 672                                 "Failed to init MTT srqwqe memory, aborting.\n");
 673                         goto err_unmap_srq;
 674                 }
 675         }
 676
 677         if (hr_dev->caps.num_idx_segs) {
 678                 ret = hns_roce_init_hem_table(hr_dev,
 679                                               &hr_dev->mr_table.mtt_idx_table,
 680                                               HEM_TYPE_IDX,
 681                                               hr_dev->caps.idx_entry_sz,
 682                                               hr_dev->caps.num_idx_segs, 1);
 683                 if (ret) {
 684                         dev_err(dev,
 685                                 "Failed to init MTT idx memory, aborting.\n");
 686                         goto err_unmap_srqwqe;
 687                 }
 688         }
 689
 690         if (hr_dev->caps.sccc_entry_sz) {
 691                 ret = hns_roce_init_hem_table(hr_dev,
 692                                               &hr_dev->qp_table.sccc_table,
 693                                               HEM_TYPE_SCCC,
 694                                               hr_dev->caps.sccc_entry_sz,
 695                                               hr_dev->caps.num_qps, 1);
 696                 if (ret) {
 697                         dev_err(dev,
 698                               "Failed to init SCC context memory, aborting.\n");
 699                         goto err_unmap_idx;
 700                 }
 701         }
 702
 703         if (hr_dev->caps.qpc_timer_entry_sz) {
 704                 ret = hns_roce_init_hem_table(hr_dev,
 705                                               &hr_dev->qpc_timer_table,
 706                                               HEM_TYPE_QPC_TIMER,
 707                                               hr_dev->caps.qpc_timer_entry_sz,
 708                                               hr_dev->caps.num_qpc_timer, 1);
 709                 if (ret) {
 710                         dev_err(dev,
 711                               "Failed to init QPC timer memory, aborting.\n");
 712                         goto err_unmap_ctx;
 713                 }
 714         }
 715
 716         if (hr_dev->caps.cqc_timer_entry_sz) {
 717                 ret = hns_roce_init_hem_table(hr_dev,
 718                                               &hr_dev->cqc_timer_table,
 719                                               HEM_TYPE_CQC_TIMER,
 720                                               hr_dev->caps.cqc_timer_entry_sz,
 721                                               hr_dev->caps.num_cqc_timer, 1);
 722                 if (ret) {
 723                         dev_err(dev,
 724                               "Failed to init CQC timer memory, aborting.\n");
 725                         goto err_unmap_qpc_timer;
 726                 }
 727         }
 728
 729         return 0;
 730
 731 err_unmap_qpc_timer:
 732         if (hr_dev->caps.qpc_timer_entry_sz)
 733                 hns_roce_cleanup_hem_table(hr_dev,
 734                                            &hr_dev->qpc_timer_table);
 735
 736 err_unmap_ctx:
 737         if (hr_dev->caps.sccc_entry_sz)
 738                 hns_roce_cleanup_hem_table(hr_dev,
 739                                            &hr_dev->qp_table.sccc_table);
 740
 741 err_unmap_idx:
 742         if (hr_dev->caps.num_idx_segs)
 743                 hns_roce_cleanup_hem_table(hr_dev,
 744                                            &hr_dev->mr_table.mtt_idx_table);
 745
 746 err_unmap_srqwqe:
 747         if (hr_dev->caps.num_srqwqe_segs)
 748                 hns_roce_cleanup_hem_table(hr_dev,
 749                                            &hr_dev->mr_table.mtt_srqwqe_table);
 750
 751 err_unmap_srq:
 752         if (hr_dev->caps.srqc_entry_sz)
 753                 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
 754
 755 err_unmap_cq:
 756         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
 757
 758 err_unmap_trrl:
 759         if (hr_dev->caps.trrl_entry_sz)
 760                 hns_roce_cleanup_hem_table(hr_dev,
 761                                            &hr_dev->qp_table.trrl_table);
 762
 763 err_unmap_irrl:
 764         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
 765
 766 err_unmap_qp:
 767         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
 768
 769 err_unmap_dmpt:
 770         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
 771
 772 err_unmap_mtt:
 773         if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
 774                 hns_roce_cleanup_hem_table(hr_dev,
 775                                            &hr_dev->mr_table.mtt_cqe_table);
 776
 777 err_unmap_cqe:
 778         hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
 779
 780         return ret;
 781 }
 782
 783 /**
 784  * hns_roce_setup_hca - setup host channel adapter
 785  * @hr_dev: pointer to hns roce device
 786  * Return : int
 787  */
 788 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
 789 {
 790         int ret;
 791         struct device *dev = hr_dev->dev;
 792
 793         spin_lock_init(&hr_dev->sm_lock);
 794         spin_lock_init(&hr_dev->bt_cmd_lock);
 795
 796         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
 797                 INIT_LIST_HEAD(&hr_dev->pgdir_list);
 798                 mutex_init(&hr_dev->pgdir_mutex);
 799         }
 800
 801         ret = hns_roce_init_uar_table(hr_dev);
 802         if (ret) {
 803                 dev_err(dev, "Failed to initialize uar table. aborting\n");
 804                 return ret;
 805         }
 806
 807         ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
 808         if (ret) {
 809                 dev_err(dev, "Failed to allocate priv_uar.\n");
 810                 goto err_uar_table_free;
 811         }
 812
 813         ret = hns_roce_init_pd_table(hr_dev);
 814         if (ret) {
 815                 dev_err(dev, "Failed to init protected domain table.\n");
 816                 goto err_uar_alloc_free;
 817         }
 818
 819         ret = hns_roce_init_mr_table(hr_dev);
 820         if (ret) {
 821                 dev_err(dev, "Failed to init memory region table.\n");
 822                 goto err_pd_table_free;
 823         }
 824
 825         ret = hns_roce_init_cq_table(hr_dev);
 826         if (ret) {
 827                 dev_err(dev, "Failed to init completion queue table.\n");
 828                 goto err_mr_table_free;
 829         }
 830
 831         ret = hns_roce_init_qp_table(hr_dev);
 832         if (ret) {
 833                 dev_err(dev, "Failed to init queue pair table.\n");
 834                 goto err_cq_table_free;
 835         }
 836
 837         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
 838                 ret = hns_roce_init_srq_table(hr_dev);
 839                 if (ret) {
 840                         dev_err(dev,
 841                                 "Failed to init share receive queue table.\n");
 842                         goto err_qp_table_free;
 843                 }
 844         }
 845
 846         return 0;
 847
 848 err_qp_table_free:
 849         if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
 850                 hns_roce_cleanup_qp_table(hr_dev);
 851
 852 err_cq_table_free:
 853         hns_roce_cleanup_cq_table(hr_dev);
 854
 855 err_mr_table_free:
 856         hns_roce_cleanup_mr_table(hr_dev);
 857
 858 err_pd_table_free:
 859         hns_roce_cleanup_pd_table(hr_dev);
 860
 861 err_uar_alloc_free:
 862         hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
 863
 864 err_uar_table_free:
 865         hns_roce_cleanup_uar_table(hr_dev);
 866         return ret;
 867 }
 868
 869 int hns_roce_init(struct hns_roce_dev *hr_dev)
 870 {
 871         int ret;
 872         struct device *dev = hr_dev->dev;
 873
 874         if (hr_dev->hw->reset) {
 875                 ret = hr_dev->hw->reset(hr_dev, true);
 876                 if (ret) {
 877                         dev_err(dev, "Reset RoCE engine failed!\n");
 878                         return ret;
 879                 }
 880         }
 881         hr_dev->is_reset = false;
 882
 883         if (hr_dev->hw->cmq_init) {
 884                 ret = hr_dev->hw->cmq_init(hr_dev);
 885                 if (ret) {
 886                         dev_err(dev, "Init RoCE Command Queue failed!\n");
 887                         goto error_failed_cmq_init;
 888                 }
 889         }
 890
 891         ret = hr_dev->hw->hw_profile(hr_dev);
 892         if (ret) {
 893                 dev_err(dev, "Get RoCE engine profile failed!\n");
 894                 goto error_failed_cmd_init;
 895         }
 896
 897         ret = hns_roce_cmd_init(hr_dev);
 898         if (ret) {
 899                 dev_err(dev, "cmd init failed!\n");
 900                 goto error_failed_cmd_init;
 901         }
 902
 903         ret = hr_dev->hw->init_eq(hr_dev);
 904         if (ret) {
 905                 dev_err(dev, "eq init failed!\n");
 906                 goto error_failed_eq_table;
 907         }
 908
 909         if (hr_dev->cmd_mod) {
 910                 ret = hns_roce_cmd_use_events(hr_dev);
 911                 if (ret) {
 912                         dev_err(dev, "Switch to event-driven cmd failed!\n");
 913                         goto error_failed_use_event;
 914                 }
 915         }
 916
 917         ret = hns_roce_init_hem(hr_dev);
 918         if (ret) {
 919                 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
 920                 goto error_failed_init_hem;
 921         }
 922
 923         ret = hns_roce_setup_hca(hr_dev);
 924         if (ret) {
 925                 dev_err(dev, "setup hca failed!\n");
 926                 goto error_failed_setup_hca;
 927         }
 928
 929         if (hr_dev->hw->hw_init) {
 930                 ret = hr_dev->hw->hw_init(hr_dev);
 931                 if (ret) {
 932                         dev_err(dev, "hw_init failed!\n");
 933                         goto error_failed_engine_init;
 934                 }
 935         }
 936
 937         ret = hns_roce_register_device(hr_dev);
 938         if (ret)
 939                 goto error_failed_register_device;
 940
 941         return 0;
 942
 943 error_failed_register_device:
 944         if (hr_dev->hw->hw_exit)
 945                 hr_dev->hw->hw_exit(hr_dev);
 946
 947 error_failed_engine_init:
 948         hns_roce_cleanup_bitmap(hr_dev);
 949
 950 error_failed_setup_hca:
 951         hns_roce_cleanup_hem(hr_dev);
 952
 953 error_failed_init_hem:
 954         if (hr_dev->cmd_mod)
 955                 hns_roce_cmd_use_polling(hr_dev);
 956
 957 error_failed_use_event:
 958         hr_dev->hw->cleanup_eq(hr_dev);
 959
 960 error_failed_eq_table:
 961         hns_roce_cmd_cleanup(hr_dev);
 962
 963 error_failed_cmd_init:
 964         if (hr_dev->hw->cmq_exit)
 965                 hr_dev->hw->cmq_exit(hr_dev);
 966
 967 error_failed_cmq_init:
 968         if (hr_dev->hw->reset) {
 969                 if (hr_dev->hw->reset(hr_dev, false))
 970                         dev_err(dev, "Dereset RoCE engine failed!\n");
 971         }
 972
 973         return ret;
 974 }
 975 EXPORT_SYMBOL_GPL(hns_roce_init);
 976
 977 void hns_roce_exit(struct hns_roce_dev *hr_dev)
 978 {
 979         hns_roce_unregister_device(hr_dev);
 980
 981         if (hr_dev->hw->hw_exit)
 982                 hr_dev->hw->hw_exit(hr_dev);
 983         hns_roce_cleanup_bitmap(hr_dev);
 984         hns_roce_cleanup_hem(hr_dev);
 985
 986         if (hr_dev->cmd_mod)
 987                 hns_roce_cmd_use_polling(hr_dev);
 988
 989         hr_dev->hw->cleanup_eq(hr_dev);
 990         hns_roce_cmd_cleanup(hr_dev);
 991         if (hr_dev->hw->cmq_exit)
 992                 hr_dev->hw->cmq_exit(hr_dev);
 993         if (hr_dev->hw->reset)
 994                 hr_dev->hw->reset(hr_dev, false);
 995 }
 996 EXPORT_SYMBOL_GPL(hns_roce_exit);
 997
 998 MODULE_LICENSE("Dual BSD/GPL");
 999 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1000 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1001 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1002 MODULE_DESCRIPTION("HNS RoCE Driver");