drivers/iio/trigger/stm32-timer-trigger.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  *
   5  * Author: Benjamin Gaignard <benjamin.gaignard@st.com>
   6  *
   7  */
   8
   9 #include <linux/iio/iio.h>
  10 #include <linux/iio/sysfs.h>
  11 #include <linux/iio/timer/stm32-timer-trigger.h>
  12 #include <linux/iio/trigger.h>
  13 #include <linux/mfd/stm32-timers.h>
  14 #include <linux/mod_devicetable.h>
  15 #include <linux/module.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/property.h>
  18
  19 #define MAX_TRIGGERS 7
  20 #define MAX_VALIDS 5
  21
  22 /* List the triggers created by each timer */
  23 static const void *triggers_table[][MAX_TRIGGERS] = {
  24         { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
  25         { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
  26         { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
  27         { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
  28         { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
  29         { TIM6_TRGO,},
  30         { TIM7_TRGO,},
  31         { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
  32         { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
  33         { TIM10_OC1,},
  34         { TIM11_OC1,},
  35         { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
  36         { TIM13_OC1,},
  37         { TIM14_OC1,},
  38         { TIM15_TRGO,},
  39         { TIM16_OC1,},
  40         { TIM17_OC1,},
  41 };
  42
  43 /* List the triggers accepted by each timer */
  44 static const void *valids_table[][MAX_VALIDS] = {
  45         { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  46         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  47         { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
  48         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  49         { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
  50         { }, /* timer 6 */
  51         { }, /* timer 7 */
  52         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  53         { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
  54         { }, /* timer 10 */
  55         { }, /* timer 11 */
  56         { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
  57 };
  58
  59 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
  60         { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  61         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  62         { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
  63         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  64         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  65         { }, /* timer 6 */
  66         { }, /* timer 7 */
  67         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  68         { }, /* timer 9 */
  69         { }, /* timer 10 */
  70         { }, /* timer 11 */
  71         { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
  72         { }, /* timer 13 */
  73         { }, /* timer 14 */
  74         { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
  75         { }, /* timer 16 */
  76         { }, /* timer 17 */
  77 };
  78
  79 struct stm32_timer_trigger_regs {
  80         u32 cr1;
  81         u32 cr2;
  82         u32 psc;
  83         u32 arr;
  84         u32 cnt;
  85         u32 smcr;
  86 };
  87
  88 struct stm32_timer_trigger {
  89         struct device *dev;
  90         struct regmap *regmap;
  91         struct clk *clk;
  92         bool enabled;
  93         u32 max_arr;
  94         const void *triggers;
  95         const void *valids;
  96         bool has_trgo2;
  97         struct mutex lock; /* concurrent sysfs configuration */
  98         struct list_head tr_list;
  99         struct stm32_timer_trigger_regs bak;
 100 };
 101
 102 struct stm32_timer_trigger_cfg {
 103         const void *(*valids_table)[MAX_VALIDS];
 104         const unsigned int num_valids_table;
 105 };
 106
 107 static bool stm32_timer_is_trgo2_name(const char *name)
 108 {
 109         return !!strstr(name, "trgo2");
 110 }
 111
 112 static bool stm32_timer_is_trgo_name(const char *name)
 113 {
 114         return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
 115 }
 116
 117 static int stm32_timer_start(struct stm32_timer_trigger *priv,
 118                              struct iio_trigger *trig,
 119                              unsigned int frequency)
 120 {
 121         unsigned long long prd, div;
 122         int prescaler = 0;
 123         u32 ccer;
 124
 125         /* Period and prescaler values depends of clock rate */
 126         div = (unsigned long long)clk_get_rate(priv->clk);
 127
 128         do_div(div, frequency);
 129
 130         prd = div;
 131
 132         /*
 133          * Increase prescaler value until we get a result that fit
 134          * with auto reload register maximum value.
 135          */
 136         while (div > priv->max_arr) {
 137                 prescaler++;
 138                 div = prd;
 139                 do_div(div, (prescaler + 1));
 140         }
 141         prd = div;
 142
 143         if (prescaler > MAX_TIM_PSC) {
 144                 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
 145                 return -EINVAL;
 146         }
 147
 148         /* Check if nobody else use the timer */
 149         regmap_read(priv->regmap, TIM_CCER, &ccer);
 150         if (ccer & TIM_CCER_CCXE)
 151                 return -EBUSY;
 152
 153         mutex_lock(&priv->lock);
 154         if (!priv->enabled) {
 155                 priv->enabled = true;
 156                 clk_enable(priv->clk);
 157         }
 158
 159         regmap_write(priv->regmap, TIM_PSC, prescaler);
 160         regmap_write(priv->regmap, TIM_ARR, prd - 1);
 161         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 162
 163         /* Force master mode to update mode */
 164         if (stm32_timer_is_trgo2_name(trig->name))
 165                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
 166                                    0x2 << TIM_CR2_MMS2_SHIFT);
 167         else
 168                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
 169                                    0x2 << TIM_CR2_MMS_SHIFT);
 170
 171         /* Make sure that registers are updated */
 172         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 173
 174         /* Enable controller */
 175         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
 176         mutex_unlock(&priv->lock);
 177
 178         return 0;
 179 }
 180
 181 static void stm32_timer_stop(struct stm32_timer_trigger *priv,
 182                              struct iio_trigger *trig)
 183 {
 184         u32 ccer;
 185
 186         regmap_read(priv->regmap, TIM_CCER, &ccer);
 187         if (ccer & TIM_CCER_CCXE)
 188                 return;
 189
 190         mutex_lock(&priv->lock);
 191         /* Stop timer */
 192         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 193         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 194         regmap_write(priv->regmap, TIM_PSC, 0);
 195         regmap_write(priv->regmap, TIM_ARR, 0);
 196
 197         /* Force disable master mode */
 198         if (stm32_timer_is_trgo2_name(trig->name))
 199                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
 200         else
 201                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0);
 202
 203         /* Make sure that registers are updated */
 204         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 205
 206         if (priv->enabled) {
 207                 priv->enabled = false;
 208                 clk_disable(priv->clk);
 209         }
 210         mutex_unlock(&priv->lock);
 211 }
 212
 213 static ssize_t stm32_tt_store_frequency(struct device *dev,
 214                                         struct device_attribute *attr,
 215                                         const char *buf, size_t len)
 216 {
 217         struct iio_trigger *trig = to_iio_trigger(dev);
 218         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 219         unsigned int freq;
 220         int ret;
 221
 222         ret = kstrtouint(buf, 10, &freq);
 223         if (ret)
 224                 return ret;
 225
 226         if (freq == 0) {
 227                 stm32_timer_stop(priv, trig);
 228         } else {
 229                 ret = stm32_timer_start(priv, trig, freq);
 230                 if (ret)
 231                         return ret;
 232         }
 233
 234         return len;
 235 }
 236
 237 static ssize_t stm32_tt_read_frequency(struct device *dev,
 238                                        struct device_attribute *attr, char *buf)
 239 {
 240         struct iio_trigger *trig = to_iio_trigger(dev);
 241         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 242         u32 psc, arr, cr1;
 243         unsigned long long freq = 0;
 244
 245         regmap_read(priv->regmap, TIM_CR1, &cr1);
 246         regmap_read(priv->regmap, TIM_PSC, &psc);
 247         regmap_read(priv->regmap, TIM_ARR, &arr);
 248
 249         if (cr1 & TIM_CR1_CEN) {
 250                 freq = (unsigned long long)clk_get_rate(priv->clk);
 251                 do_div(freq, psc + 1);
 252                 do_div(freq, arr + 1);
 253         }
 254
 255         return sprintf(buf, "%d\n", (unsigned int)freq);
 256 }
 257
 258 static IIO_DEV_ATTR_SAMP_FREQ(0660,
 259                               stm32_tt_read_frequency,
 260                               stm32_tt_store_frequency);
 261
 262 #define MASTER_MODE_MAX         7
 263 #define MASTER_MODE2_MAX        15
 264
 265 static char *master_mode_table[] = {
 266         "reset",
 267         "enable",
 268         "update",
 269         "compare_pulse",
 270         "OC1REF",
 271         "OC2REF",
 272         "OC3REF",
 273         "OC4REF",
 274         /* Master mode selection 2 only */
 275         "OC5REF",
 276         "OC6REF",
 277         "compare_pulse_OC4REF",
 278         "compare_pulse_OC6REF",
 279         "compare_pulse_OC4REF_r_or_OC6REF_r",
 280         "compare_pulse_OC4REF_r_or_OC6REF_f",
 281         "compare_pulse_OC5REF_r_or_OC6REF_r",
 282         "compare_pulse_OC5REF_r_or_OC6REF_f",
 283 };
 284
 285 static ssize_t stm32_tt_show_master_mode(struct device *dev,
 286                                          struct device_attribute *attr,
 287                                          char *buf)
 288 {
 289         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 290         struct iio_trigger *trig = to_iio_trigger(dev);
 291         u32 cr2;
 292
 293         regmap_read(priv->regmap, TIM_CR2, &cr2);
 294
 295         if (stm32_timer_is_trgo2_name(trig->name))
 296                 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
 297         else
 298                 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
 299
 300         return sysfs_emit(buf, "%s\n", master_mode_table[cr2]);
 301 }
 302
 303 static ssize_t stm32_tt_store_master_mode(struct device *dev,
 304                                           struct device_attribute *attr,
 305                                           const char *buf, size_t len)
 306 {
 307         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 308         struct iio_trigger *trig = to_iio_trigger(dev);
 309         u32 mask, shift, master_mode_max;
 310         int i;
 311
 312         if (stm32_timer_is_trgo2_name(trig->name)) {
 313                 mask = TIM_CR2_MMS2;
 314                 shift = TIM_CR2_MMS2_SHIFT;
 315                 master_mode_max = MASTER_MODE2_MAX;
 316         } else {
 317                 mask = TIM_CR2_MMS;
 318                 shift = TIM_CR2_MMS_SHIFT;
 319                 master_mode_max = MASTER_MODE_MAX;
 320         }
 321
 322         for (i = 0; i <= master_mode_max; i++) {
 323                 if (!strncmp(master_mode_table[i], buf,
 324                              strlen(master_mode_table[i]))) {
 325                         mutex_lock(&priv->lock);
 326                         if (!priv->enabled) {
 327                                 /* Clock should be enabled first */
 328                                 priv->enabled = true;
 329                                 clk_enable(priv->clk);
 330                         }
 331                         regmap_update_bits(priv->regmap, TIM_CR2, mask,
 332                                            i << shift);
 333                         mutex_unlock(&priv->lock);
 334                         return len;
 335                 }
 336         }
 337
 338         return -EINVAL;
 339 }
 340
 341 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
 342                                                struct device_attribute *attr,
 343                                                char *buf)
 344 {
 345         struct iio_trigger *trig = to_iio_trigger(dev);
 346         unsigned int i, master_mode_max;
 347         size_t len = 0;
 348
 349         if (stm32_timer_is_trgo2_name(trig->name))
 350                 master_mode_max = MASTER_MODE2_MAX;
 351         else
 352                 master_mode_max = MASTER_MODE_MAX;
 353
 354         for (i = 0; i <= master_mode_max; i++)
 355                 len += scnprintf(buf + len, PAGE_SIZE - len,
 356                         "%s ", master_mode_table[i]);
 357
 358         /* replace trailing space by newline */
 359         buf[len - 1] = '\n';
 360
 361         return len;
 362 }
 363
 364 static IIO_DEVICE_ATTR(master_mode_available, 0444,
 365                        stm32_tt_show_master_mode_avail, NULL, 0);
 366
 367 static IIO_DEVICE_ATTR(master_mode, 0660,
 368                        stm32_tt_show_master_mode,
 369                        stm32_tt_store_master_mode,
 370                        0);
 371
 372 static struct attribute *stm32_trigger_attrs[] = {
 373         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 374         &iio_dev_attr_master_mode.dev_attr.attr,
 375         &iio_dev_attr_master_mode_available.dev_attr.attr,
 376         NULL,
 377 };
 378
 379 static const struct attribute_group stm32_trigger_attr_group = {
 380         .attrs = stm32_trigger_attrs,
 381 };
 382
 383 static const struct attribute_group *stm32_trigger_attr_groups[] = {
 384         &stm32_trigger_attr_group,
 385         NULL,
 386 };
 387
 388 static const struct iio_trigger_ops timer_trigger_ops = {
 389 };
 390
 391 static void stm32_unregister_iio_triggers(struct stm32_timer_trigger *priv)
 392 {
 393         struct iio_trigger *tr;
 394
 395         list_for_each_entry(tr, &priv->tr_list, alloc_list)
 396                 iio_trigger_unregister(tr);
 397 }
 398
 399 static int stm32_register_iio_triggers(struct stm32_timer_trigger *priv)
 400 {
 401         int ret;
 402         const char * const *cur = priv->triggers;
 403
 404         INIT_LIST_HEAD(&priv->tr_list);
 405
 406         while (cur && *cur) {
 407                 struct iio_trigger *trig;
 408                 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
 409                 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
 410
 411                 if (cur_is_trgo2 && !priv->has_trgo2) {
 412                         cur++;
 413                         continue;
 414                 }
 415
 416                 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
 417                 if  (!trig)
 418                         return -ENOMEM;
 419
 420                 trig->dev.parent = priv->dev->parent;
 421                 trig->ops = &timer_trigger_ops;
 422
 423                 /*
 424                  * sampling frequency and master mode attributes
 425                  * should only be available on trgo/trgo2 triggers
 426                  */
 427                 if (cur_is_trgo || cur_is_trgo2)
 428                         trig->dev.groups = stm32_trigger_attr_groups;
 429
 430                 iio_trigger_set_drvdata(trig, priv);
 431
 432                 ret = iio_trigger_register(trig);
 433                 if (ret) {
 434                         stm32_unregister_iio_triggers(priv);
 435                         return ret;
 436                 }
 437
 438                 list_add_tail(&trig->alloc_list, &priv->tr_list);
 439                 cur++;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
 446                                   struct iio_chan_spec const *chan,
 447                                   int *val, int *val2, long mask)
 448 {
 449         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 450         u32 dat;
 451
 452         switch (mask) {
 453         case IIO_CHAN_INFO_RAW:
 454                 regmap_read(priv->regmap, TIM_CNT, &dat);
 455                 *val = dat;
 456                 return IIO_VAL_INT;
 457
 458         case IIO_CHAN_INFO_ENABLE:
 459                 regmap_read(priv->regmap, TIM_CR1, &dat);
 460                 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
 461                 return IIO_VAL_INT;
 462
 463         case IIO_CHAN_INFO_SCALE:
 464                 regmap_read(priv->regmap, TIM_SMCR, &dat);
 465                 dat &= TIM_SMCR_SMS;
 466
 467                 *val = 1;
 468                 *val2 = 0;
 469
 470                 /* in quadrature case scale = 0.25 */
 471                 if (dat == 3)
 472                         *val2 = 2;
 473
 474                 return IIO_VAL_FRACTIONAL_LOG2;
 475         }
 476
 477         return -EINVAL;
 478 }
 479
 480 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
 481                                    struct iio_chan_spec const *chan,
 482                                    int val, int val2, long mask)
 483 {
 484         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 485
 486         switch (mask) {
 487         case IIO_CHAN_INFO_RAW:
 488                 return regmap_write(priv->regmap, TIM_CNT, val);
 489
 490         case IIO_CHAN_INFO_SCALE:
 491                 /* fixed scale */
 492                 return -EINVAL;
 493
 494         case IIO_CHAN_INFO_ENABLE:
 495                 mutex_lock(&priv->lock);
 496                 if (val) {
 497                         if (!priv->enabled) {
 498                                 priv->enabled = true;
 499                                 clk_enable(priv->clk);
 500                         }
 501                         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 502                                            TIM_CR1_CEN);
 503                 } else {
 504                         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 505                                            0);
 506                         if (priv->enabled) {
 507                                 priv->enabled = false;
 508                                 clk_disable(priv->clk);
 509                         }
 510                 }
 511                 mutex_unlock(&priv->lock);
 512                 return 0;
 513         }
 514
 515         return -EINVAL;
 516 }
 517
 518 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
 519                                           struct iio_trigger *trig)
 520 {
 521         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 522         const char * const *cur = priv->valids;
 523         unsigned int i = 0;
 524
 525         if (!is_stm32_timer_trigger(trig))
 526                 return -EINVAL;
 527
 528         while (cur && *cur) {
 529                 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
 530                         regmap_update_bits(priv->regmap,
 531                                            TIM_SMCR, TIM_SMCR_TS,
 532                                            i << TIM_SMCR_TS_SHIFT);
 533                         return 0;
 534                 }
 535                 cur++;
 536                 i++;
 537         }
 538
 539         return -EINVAL;
 540 }
 541
 542 static const struct iio_info stm32_trigger_info = {
 543         .validate_trigger = stm32_counter_validate_trigger,
 544         .read_raw = stm32_counter_read_raw,
 545         .write_raw = stm32_counter_write_raw
 546 };
 547
 548 static const char *const stm32_trigger_modes[] = {
 549         "trigger",
 550 };
 551
 552 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
 553                                   const struct iio_chan_spec *chan,
 554                                   unsigned int mode)
 555 {
 556         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 557
 558         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
 559
 560         return 0;
 561 }
 562
 563 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
 564                                   const struct iio_chan_spec *chan)
 565 {
 566         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 567         u32 smcr;
 568
 569         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 570
 571         return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
 572 }
 573
 574 static const struct iio_enum stm32_trigger_mode_enum = {
 575         .items = stm32_trigger_modes,
 576         .num_items = ARRAY_SIZE(stm32_trigger_modes),
 577         .set = stm32_set_trigger_mode,
 578         .get = stm32_get_trigger_mode
 579 };
 580
 581 static const char *const stm32_enable_modes[] = {
 582         "always",
 583         "gated",
 584         "triggered",
 585 };
 586
 587 static int stm32_enable_mode2sms(int mode)
 588 {
 589         switch (mode) {
 590         case 0:
 591                 return 0;
 592         case 1:
 593                 return 5;
 594         case 2:
 595                 return 6;
 596         }
 597
 598         return -EINVAL;
 599 }
 600
 601 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
 602                                  const struct iio_chan_spec *chan,
 603                                  unsigned int mode)
 604 {
 605         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 606         int sms = stm32_enable_mode2sms(mode);
 607
 608         if (sms < 0)
 609                 return sms;
 610         /*
 611          * Triggered mode sets CEN bit automatically by hardware. So, first
 612          * enable counter clock, so it can use it. Keeps it in sync with CEN.
 613          */
 614         mutex_lock(&priv->lock);
 615         if (sms == 6 && !priv->enabled) {
 616                 clk_enable(priv->clk);
 617                 priv->enabled = true;
 618         }
 619         mutex_unlock(&priv->lock);
 620
 621         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
 622
 623         return 0;
 624 }
 625
 626 static int stm32_sms2enable_mode(int mode)
 627 {
 628         switch (mode) {
 629         case 0:
 630                 return 0;
 631         case 5:
 632                 return 1;
 633         case 6:
 634                 return 2;
 635         }
 636
 637         return -EINVAL;
 638 }
 639
 640 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
 641                                  const struct iio_chan_spec *chan)
 642 {
 643         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 644         u32 smcr;
 645
 646         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 647         smcr &= TIM_SMCR_SMS;
 648
 649         return stm32_sms2enable_mode(smcr);
 650 }
 651
 652 static const struct iio_enum stm32_enable_mode_enum = {
 653         .items = stm32_enable_modes,
 654         .num_items = ARRAY_SIZE(stm32_enable_modes),
 655         .set = stm32_set_enable_mode,
 656         .get = stm32_get_enable_mode
 657 };
 658
 659 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
 660                                       uintptr_t private,
 661                                       const struct iio_chan_spec *chan,
 662                                       char *buf)
 663 {
 664         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 665         u32 arr;
 666
 667         regmap_read(priv->regmap, TIM_ARR, &arr);
 668
 669         return snprintf(buf, PAGE_SIZE, "%u\n", arr);
 670 }
 671
 672 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
 673                                       uintptr_t private,
 674                                       const struct iio_chan_spec *chan,
 675                                       const char *buf, size_t len)
 676 {
 677         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 678         unsigned int preset;
 679         int ret;
 680
 681         ret = kstrtouint(buf, 0, &preset);
 682         if (ret)
 683                 return ret;
 684
 685         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 686         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 687         regmap_write(priv->regmap, TIM_ARR, preset);
 688
 689         return len;
 690 }
 691
 692 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
 693         {
 694                 .name = "preset",
 695                 .shared = IIO_SEPARATE,
 696                 .read = stm32_count_get_preset,
 697                 .write = stm32_count_set_preset
 698         },
 699         IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
 700         IIO_ENUM_AVAILABLE("enable_mode", IIO_SHARED_BY_TYPE, &stm32_enable_mode_enum),
 701         IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
 702         IIO_ENUM_AVAILABLE("trigger_mode", IIO_SHARED_BY_TYPE, &stm32_trigger_mode_enum),
 703         {}
 704 };
 705
 706 static const struct iio_chan_spec stm32_trigger_channel = {
 707         .type = IIO_COUNT,
 708         .channel = 0,
 709         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 710                               BIT(IIO_CHAN_INFO_ENABLE) |
 711                               BIT(IIO_CHAN_INFO_SCALE),
 712         .ext_info = stm32_trigger_count_info,
 713         .indexed = 1
 714 };
 715
 716 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
 717 {
 718         struct iio_dev *indio_dev;
 719         int ret;
 720
 721         indio_dev = devm_iio_device_alloc(dev,
 722                                           sizeof(struct stm32_timer_trigger));
 723         if (!indio_dev)
 724                 return NULL;
 725
 726         indio_dev->name = dev_name(dev);
 727         indio_dev->info = &stm32_trigger_info;
 728         indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
 729         indio_dev->num_channels = 1;
 730         indio_dev->channels = &stm32_trigger_channel;
 731
 732         ret = devm_iio_device_register(dev, indio_dev);
 733         if (ret)
 734                 return NULL;
 735
 736         return iio_priv(indio_dev);
 737 }
 738
 739 /**
 740  * is_stm32_timer_trigger
 741  * @trig: trigger to be checked
 742  *
 743  * return true if the trigger is a valid stm32 iio timer trigger
 744  * either return false
 745  */
 746 bool is_stm32_timer_trigger(struct iio_trigger *trig)
 747 {
 748         return (trig->ops == &timer_trigger_ops);
 749 }
 750 EXPORT_SYMBOL(is_stm32_timer_trigger);
 751
 752 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
 753 {
 754         u32 val;
 755
 756         /*
 757          * Master mode selection 2 bits can only be written and read back when
 758          * timer supports it.
 759          */
 760         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
 761         regmap_read(priv->regmap, TIM_CR2, &val);
 762         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
 763         priv->has_trgo2 = !!val;
 764 }
 765
 766 static int stm32_timer_trigger_probe(struct platform_device *pdev)
 767 {
 768         struct device *dev = &pdev->dev;
 769         struct stm32_timer_trigger *priv;
 770         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 771         const struct stm32_timer_trigger_cfg *cfg;
 772         unsigned int index;
 773         int ret;
 774
 775         ret = device_property_read_u32(dev, "reg", &index);
 776         if (ret)
 777                 return ret;
 778
 779         cfg = device_get_match_data(dev);
 780
 781         if (index >= ARRAY_SIZE(triggers_table) ||
 782             index >= cfg->num_valids_table)
 783                 return -EINVAL;
 784
 785         /* Create an IIO device only if we have triggers to be validated */
 786         if (*cfg->valids_table[index])
 787                 priv = stm32_setup_counter_device(dev);
 788         else
 789                 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 790
 791         if (!priv)
 792                 return -ENOMEM;
 793
 794         priv->dev = dev;
 795         priv->regmap = ddata->regmap;
 796         priv->clk = ddata->clk;
 797         priv->max_arr = ddata->max_arr;
 798         priv->triggers = triggers_table[index];
 799         priv->valids = cfg->valids_table[index];
 800         stm32_timer_detect_trgo2(priv);
 801         mutex_init(&priv->lock);
 802
 803         ret = stm32_register_iio_triggers(priv);
 804         if (ret)
 805                 return ret;
 806
 807         platform_set_drvdata(pdev, priv);
 808
 809         return 0;
 810 }
 811
 812 static int stm32_timer_trigger_remove(struct platform_device *pdev)
 813 {
 814         struct stm32_timer_trigger *priv = platform_get_drvdata(pdev);
 815         u32 val;
 816
 817         /* Unregister triggers before everything can be safely turned off */
 818         stm32_unregister_iio_triggers(priv);
 819
 820         /* Check if nobody else use the timer, then disable it */
 821         regmap_read(priv->regmap, TIM_CCER, &val);
 822         if (!(val & TIM_CCER_CCXE))
 823                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 824
 825         if (priv->enabled)
 826                 clk_disable(priv->clk);
 827
 828         return 0;
 829 }
 830
 831 static int stm32_timer_trigger_suspend(struct device *dev)
 832 {
 833         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 834
 835         /* Only take care of enabled timer: don't disturb other MFD child */
 836         if (priv->enabled) {
 837                 /* Backup registers that may get lost in low power mode */
 838                 regmap_read(priv->regmap, TIM_CR1, &priv->bak.cr1);
 839                 regmap_read(priv->regmap, TIM_CR2, &priv->bak.cr2);
 840                 regmap_read(priv->regmap, TIM_PSC, &priv->bak.psc);
 841                 regmap_read(priv->regmap, TIM_ARR, &priv->bak.arr);
 842                 regmap_read(priv->regmap, TIM_CNT, &priv->bak.cnt);
 843                 regmap_read(priv->regmap, TIM_SMCR, &priv->bak.smcr);
 844
 845                 /* Disable the timer */
 846                 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 847                 clk_disable(priv->clk);
 848         }
 849
 850         return 0;
 851 }
 852
 853 static int stm32_timer_trigger_resume(struct device *dev)
 854 {
 855         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 856         int ret;
 857
 858         if (priv->enabled) {
 859                 ret = clk_enable(priv->clk);
 860                 if (ret)
 861                         return ret;
 862
 863                 /* restore master/slave modes */
 864                 regmap_write(priv->regmap, TIM_SMCR, priv->bak.smcr);
 865                 regmap_write(priv->regmap, TIM_CR2, priv->bak.cr2);
 866
 867                 /* restore sampling_frequency (trgo / trgo2 triggers) */
 868                 regmap_write(priv->regmap, TIM_PSC, priv->bak.psc);
 869                 regmap_write(priv->regmap, TIM_ARR, priv->bak.arr);
 870                 regmap_write(priv->regmap, TIM_CNT, priv->bak.cnt);
 871
 872                 /* Also re-enables the timer */
 873                 regmap_write(priv->regmap, TIM_CR1, priv->bak.cr1);
 874         }
 875
 876         return 0;
 877 }
 878
 879 static DEFINE_SIMPLE_DEV_PM_OPS(stm32_timer_trigger_pm_ops,
 880                                 stm32_timer_trigger_suspend,
 881                                 stm32_timer_trigger_resume);
 882
 883 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
 884         .valids_table = valids_table,
 885         .num_valids_table = ARRAY_SIZE(valids_table),
 886 };
 887
 888 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
 889         .valids_table = stm32h7_valids_table,
 890         .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
 891 };
 892
 893 static const struct of_device_id stm32_trig_of_match[] = {
 894         {
 895                 .compatible = "st,stm32-timer-trigger",
 896                 .data = (void *)&stm32_timer_trg_cfg,
 897         }, {
 898                 .compatible = "st,stm32h7-timer-trigger",
 899                 .data = (void *)&stm32h7_timer_trg_cfg,
 900         },
 901         { /* end node */ },
 902 };
 903 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
 904
 905 static struct platform_driver stm32_timer_trigger_driver = {
 906         .probe = stm32_timer_trigger_probe,
 907         .remove = stm32_timer_trigger_remove,
 908         .driver = {
 909                 .name = "stm32-timer-trigger",
 910                 .of_match_table = stm32_trig_of_match,
 911                 .pm = pm_sleep_ptr(&stm32_timer_trigger_pm_ops),
 912         },
 913 };
 914 module_platform_driver(stm32_timer_trigger_driver);
 915
 916 MODULE_ALIAS("platform:stm32-timer-trigger");
 917 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
 918 MODULE_LICENSE("GPL v2");