drivers/ide/pci/serverworks.c

   1 /*
   2  * linux/drivers/ide/pci/serverworks.c          Version 0.9     Mar 4 2007
   3  *
   4  * Copyright (C) 1998-2000 Michel Aubry
   5  * Copyright (C) 1998-2000 Andrzej Krzysztofowicz
   6  * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
   7  * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
   8  * Portions copyright (c) 2001 Sun Microsystems
   9  *
  10  *
  11  * RCC/ServerWorks IDE driver for Linux
  12  *
  13  *   OSB4: `Open South Bridge' IDE Interface (fn 1)
  14  *         supports UDMA mode 2 (33 MB/s)
  15  *
  16  *   CSB5: `Champion South Bridge' IDE Interface (fn 1)
  17  *         all revisions support UDMA mode 4 (66 MB/s)
  18  *         revision A2.0 and up support UDMA mode 5 (100 MB/s)
  19  *
  20  *         *** The CSB5 does not provide ANY register ***
  21  *         *** to detect 80-conductor cable presence. ***
  22  *
  23  *   CSB6: `Champion South Bridge' IDE Interface (optional: third channel)
  24  *
  25  *   HT1000: AKA BCM5785 - Hypertransport Southbridge for Opteron systems. IDE
  26  *   controller same as the CSB6. Single channel ATA100 only.
  27  *
  28  * Documentation:
  29  *      Available under NDA only. Errata info very hard to get.
  30  *
  31  */
  32
  33 #include <linux/types.h>
  34 #include <linux/module.h>
  35 #include <linux/kernel.h>
  36 #include <linux/ioport.h>
  37 #include <linux/pci.h>
  38 #include <linux/hdreg.h>
  39 #include <linux/ide.h>
  40 #include <linux/init.h>
  41 #include <linux/delay.h>
  42
  43 #include <asm/io.h>
  44
  45 #define SVWKS_CSB5_REVISION_NEW 0x92 /* min PCI_REVISION_ID for UDMA5 (A2.0) */
  46 #define SVWKS_CSB6_REVISION     0xa0 /* min PCI_REVISION_ID for UDMA4 (A1.0) */
  47
  48 /* Seagate Barracuda ATA IV Family drives in UDMA mode 5
  49  * can overrun their FIFOs when used with the CSB5 */
  50 static const char *svwks_bad_ata100[] = {
  51         "ST320011A",
  52         "ST340016A",
  53         "ST360021A",
  54         "ST380021A",
  55         NULL
  56 };
  57
  58 static u8 svwks_revision = 0;
  59 static struct pci_dev *isa_dev;
  60
  61 static int check_in_drive_lists (ide_drive_t *drive, const char **list)
  62 {
  63         while (*list)
  64                 if (!strcmp(*list++, drive->id->model))
  65                         return 1;
  66         return 0;
  67 }
  68
  69 static u8 svwks_udma_filter(ide_drive_t *drive)
  70 {
  71         struct pci_dev *dev     = HWIF(drive)->pci_dev;
  72         u8 mask = 0;
  73
  74         if (!svwks_revision)
  75                 pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
  76
  77         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE)
  78                 return 0x1f;
  79         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
  80                 u32 reg = 0;
  81                 if (isa_dev)
  82                         pci_read_config_dword(isa_dev, 0x64, &reg);
  83
  84                 /*
  85                  *      Don't enable UDMA on disk devices for the moment
  86                  */
  87                 if(drive->media == ide_disk)
  88                         return 0;
  89                 /* Check the OSB4 DMA33 enable bit */
  90                 return ((reg & 0x00004000) == 0x00004000) ? 0x07 : 0;
  91         } else if (svwks_revision < SVWKS_CSB5_REVISION_NEW) {
  92                 return 0x07;
  93         } else if (svwks_revision >= SVWKS_CSB5_REVISION_NEW) {
  94                 u8 btr = 0, mode;
  95                 pci_read_config_byte(dev, 0x5A, &btr);
  96                 mode = btr & 0x3;
  97
  98                 /* If someone decides to do UDMA133 on CSB5 the same
  99                    issue will bite so be inclusive */
 100                 if (mode > 2 && check_in_drive_lists(drive, svwks_bad_ata100))
 101                         mode = 2;
 102
 103                 switch(mode) {
 104                 case 2:  mask = 0x1f; break;
 105                 case 1:  mask = 0x07; break;
 106                 default: mask = 0x00; break;
 107                 }
 108         }
 109         if (((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 110              (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) &&
 111             (!(PCI_FUNC(dev->devfn) & 1)))
 112                 mask = 0x1f;
 113
 114         return mask;
 115 }
 116
 117 static u8 svwks_csb_check (struct pci_dev *dev)
 118 {
 119         switch (dev->device) {
 120                 case PCI_DEVICE_ID_SERVERWORKS_CSB5IDE:
 121                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE:
 122                 case PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2:
 123                 case PCI_DEVICE_ID_SERVERWORKS_HT1000IDE:
 124                         return 1;
 125                 default:
 126                         break;
 127         }
 128         return 0;
 129 }
 130 static int svwks_tune_chipset (ide_drive_t *drive, u8 xferspeed)
 131 {
 132         static const u8 udma_modes[]            = { 0x00, 0x01, 0x02, 0x03, 0x04, 0x05 };
 133         static const u8 dma_modes[]             = { 0x77, 0x21, 0x20 };
 134         static const u8 pio_modes[]             = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
 135         static const u8 drive_pci[]             = { 0x41, 0x40, 0x43, 0x42 };
 136         static const u8 drive_pci2[]            = { 0x45, 0x44, 0x47, 0x46 };
 137
 138         ide_hwif_t *hwif        = HWIF(drive);
 139         struct pci_dev *dev     = hwif->pci_dev;
 140         u8 speed                = ide_rate_filter(drive, xferspeed);
 141         u8 pio                  = ide_get_best_pio_mode(drive, 255, 4, NULL);
 142         u8 unit                 = (drive->select.b.unit & 0x01);
 143         u8 csb5                 = svwks_csb_check(dev);
 144         u8 ultra_enable         = 0, ultra_timing = 0;
 145         u8 dma_timing           = 0, pio_timing = 0;
 146         u16 csb5_pio            = 0;
 147
 148         /* If we are about to put a disk into UDMA mode we screwed up.
 149            Our code assumes we never _ever_ do this on an OSB4 */
 150
 151         if(dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4 &&
 152                 drive->media == ide_disk && speed >= XFER_UDMA_0)
 153                         BUG();
 154
 155         pci_read_config_byte(dev, drive_pci[drive->dn], &pio_timing);
 156         pci_read_config_byte(dev, drive_pci2[drive->dn], &dma_timing);
 157         pci_read_config_byte(dev, (0x56|hwif->channel), &ultra_timing);
 158         pci_read_config_word(dev, 0x4A, &csb5_pio);
 159         pci_read_config_byte(dev, 0x54, &ultra_enable);
 160
 161         /* Per Specified Design by OEM, and ASIC Architect */
 162         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 163             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 164                 if (!drive->init_speed) {
 165                         u8 dma_stat = inb(hwif->dma_status);
 166
 167 dma_pio:
 168                         if (((ultra_enable << (7-drive->dn) & 0x80) == 0x80) &&
 169                             ((dma_stat & (1<<(5+unit))) == (1<<(5+unit)))) {
 170                                 drive->current_speed = drive->init_speed = XFER_UDMA_0 + udma_modes[(ultra_timing >> (4*unit)) & ~(0xF0)];
 171                                 return 0;
 172                         } else if ((dma_timing) &&
 173                                    ((dma_stat&(1<<(5+unit)))==(1<<(5+unit)))) {
 174                                 u8 dmaspeed = dma_timing;
 175
 176                                 dma_timing &= ~0xFF;
 177                                 if ((dmaspeed & 0x20) == 0x20)
 178                                         dmaspeed = XFER_MW_DMA_2;
 179                                 else if ((dmaspeed & 0x21) == 0x21)
 180                                         dmaspeed = XFER_MW_DMA_1;
 181                                 else if ((dmaspeed & 0x77) == 0x77)
 182                                         dmaspeed = XFER_MW_DMA_0;
 183                                 else
 184                                         goto dma_pio;
 185                                 drive->current_speed = drive->init_speed = dmaspeed;
 186                                 return 0;
 187                         } else if (pio_timing) {
 188                                 u8 piospeed = pio_timing;
 189
 190                                 pio_timing &= ~0xFF;
 191                                 if ((piospeed & 0x20) == 0x20)
 192                                         piospeed = XFER_PIO_4;
 193                                 else if ((piospeed & 0x22) == 0x22)
 194                                         piospeed = XFER_PIO_3;
 195                                 else if ((piospeed & 0x34) == 0x34)
 196                                         piospeed = XFER_PIO_2;
 197                                 else if ((piospeed & 0x47) == 0x47)
 198                                         piospeed = XFER_PIO_1;
 199                                 else if ((piospeed & 0x5d) == 0x5d)
 200                                         piospeed = XFER_PIO_0;
 201                                 else
 202                                         goto oem_setup_failed;
 203                                 drive->current_speed = drive->init_speed = piospeed;
 204                                 return 0;
 205                         }
 206                 }
 207         }
 208
 209 oem_setup_failed:
 210
 211         pio_timing      &= ~0xFF;
 212         dma_timing      &= ~0xFF;
 213         ultra_timing    &= ~(0x0F << (4*unit));
 214         ultra_enable    &= ~(0x01 << drive->dn);
 215         csb5_pio        &= ~(0x0F << (4*drive->dn));
 216
 217         switch(speed) {
 218                 case XFER_PIO_4:
 219                 case XFER_PIO_3:
 220                 case XFER_PIO_2:
 221                 case XFER_PIO_1:
 222                 case XFER_PIO_0:
 223                         pio_timing |= pio_modes[speed - XFER_PIO_0];
 224                         csb5_pio   |= ((speed - XFER_PIO_0) << (4*drive->dn));
 225                         break;
 226
 227                 case XFER_MW_DMA_2:
 228                 case XFER_MW_DMA_1:
 229                 case XFER_MW_DMA_0:
 230                         /*
 231                          * TODO: always setup PIO mode so this won't be needed
 232                          */
 233                         pio_timing |= pio_modes[pio];
 234                         csb5_pio   |= (pio << (4*drive->dn));
 235                         dma_timing |= dma_modes[speed - XFER_MW_DMA_0];
 236                         break;
 237
 238                 case XFER_UDMA_5:
 239                 case XFER_UDMA_4:
 240                 case XFER_UDMA_3:
 241                 case XFER_UDMA_2:
 242                 case XFER_UDMA_1:
 243                 case XFER_UDMA_0:
 244                         /*
 245                          * TODO: always setup PIO mode so this won't be needed
 246                          */
 247                         pio_timing   |= pio_modes[pio];
 248                         csb5_pio     |= (pio << (4*drive->dn));
 249                         dma_timing   |= dma_modes[2];
 250                         ultra_timing |= ((udma_modes[speed - XFER_UDMA_0]) << (4*unit));
 251                         ultra_enable |= (0x01 << drive->dn);
 252                 default:
 253                         break;
 254         }
 255
 256         pci_write_config_byte(dev, drive_pci[drive->dn], pio_timing);
 257         if (csb5)
 258                 pci_write_config_word(dev, 0x4A, csb5_pio);
 259
 260         pci_write_config_byte(dev, drive_pci2[drive->dn], dma_timing);
 261         pci_write_config_byte(dev, (0x56|hwif->channel), ultra_timing);
 262         pci_write_config_byte(dev, 0x54, ultra_enable);
 263
 264         return (ide_config_drive_speed(drive, speed));
 265 }
 266
 267 static void svwks_tune_drive (ide_drive_t *drive, u8 pio)
 268 {
 269         pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
 270         (void)svwks_tune_chipset(drive, XFER_PIO_0 + pio);
 271 }
 272
 273 static int svwks_config_drive_xfer_rate (ide_drive_t *drive)
 274 {
 275         drive->init_speed = 0;
 276
 277         if (ide_tune_dma(drive))
 278                 return 0;
 279
 280         if (ide_use_fast_pio(drive))
 281                 svwks_tune_drive(drive, 255);
 282
 283         return -1;
 284 }
 285
 286 static unsigned int __devinit init_chipset_svwks (struct pci_dev *dev, const char *name)
 287 {
 288         unsigned int reg;
 289         u8 btr;
 290
 291         /* save revision id to determine DMA capability */
 292         pci_read_config_byte(dev, PCI_REVISION_ID, &svwks_revision);
 293
 294         /* force Master Latency Timer value to 64 PCICLKs */
 295         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x40);
 296
 297         /* OSB4 : South Bridge and IDE */
 298         if (dev->device == PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 299                 isa_dev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 300                           PCI_DEVICE_ID_SERVERWORKS_OSB4, NULL);
 301                 if (isa_dev) {
 302                         pci_read_config_dword(isa_dev, 0x64, &reg);
 303                         reg &= ~0x00002000; /* disable 600ns interrupt mask */
 304                         if(!(reg & 0x00004000))
 305                                 printk(KERN_DEBUG "%s: UDMA not BIOS enabled.\n", name);
 306                         reg |=  0x00004000; /* enable UDMA/33 support */
 307                         pci_write_config_dword(isa_dev, 0x64, reg);
 308                 }
 309         }
 310
 311         /* setup CSB5/CSB6 : South Bridge and IDE option RAID */
 312         else if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE) ||
 313                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 314                  (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2)) {
 315
 316                 /* Third Channel Test */
 317                 if (!(PCI_FUNC(dev->devfn) & 1)) {
 318                         struct pci_dev * findev = NULL;
 319                         u32 reg4c = 0;
 320                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 321                                 PCI_DEVICE_ID_SERVERWORKS_CSB5, NULL);
 322                         if (findev) {
 323                                 pci_read_config_dword(findev, 0x4C, &reg4c);
 324                                 reg4c &= ~0x000007FF;
 325                                 reg4c |=  0x00000040;
 326                                 reg4c |=  0x00000020;
 327                                 pci_write_config_dword(findev, 0x4C, reg4c);
 328                                 pci_dev_put(findev);
 329                         }
 330                         outb_p(0x06, 0x0c00);
 331                         dev->irq = inb_p(0x0c01);
 332                 } else {
 333                         struct pci_dev * findev = NULL;
 334                         u8 reg41 = 0;
 335
 336                         findev = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
 337                                         PCI_DEVICE_ID_SERVERWORKS_CSB6, NULL);
 338                         if (findev) {
 339                                 pci_read_config_byte(findev, 0x41, &reg41);
 340                                 reg41 &= ~0x40;
 341                                 pci_write_config_byte(findev, 0x41, reg41);
 342                                 pci_dev_put(findev);
 343                         }
 344                         /*
 345                          * This is a device pin issue on CSB6.
 346                          * Since there will be a future raid mode,
 347                          * early versions of the chipset require the
 348                          * interrupt pin to be set, and it is a compatibility
 349                          * mode issue.
 350                          */
 351                         if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE)
 352                                 dev->irq = 0;
 353                 }
 354 //              pci_read_config_dword(dev, 0x40, &pioreg)
 355 //              pci_write_config_dword(dev, 0x40, 0x99999999);
 356 //              pci_read_config_dword(dev, 0x44, &dmareg);
 357 //              pci_write_config_dword(dev, 0x44, 0xFFFFFFFF);
 358                 /* setup the UDMA Control register
 359                  *
 360                  * 1. clear bit 6 to enable DMA
 361                  * 2. enable DMA modes with bits 0-1
 362                  *      00 : legacy
 363                  *      01 : udma2
 364                  *      10 : udma2/udma4
 365                  *      11 : udma2/udma4/udma5
 366                  */
 367                 pci_read_config_byte(dev, 0x5A, &btr);
 368                 btr &= ~0x40;
 369                 if (!(PCI_FUNC(dev->devfn) & 1))
 370                         btr |= 0x2;
 371                 else
 372                         btr |= (svwks_revision >= SVWKS_CSB5_REVISION_NEW) ? 0x3 : 0x2;
 373                 pci_write_config_byte(dev, 0x5A, btr);
 374         }
 375         /* Setup HT1000 SouthBridge Controller - Single Channel Only */
 376         else if (dev->device == PCI_DEVICE_ID_SERVERWORKS_HT1000IDE) {
 377                 pci_read_config_byte(dev, 0x5A, &btr);
 378                 btr &= ~0x40;
 379                 btr |= 0x3;
 380                 pci_write_config_byte(dev, 0x5A, btr);
 381         }
 382
 383         return dev->irq;
 384 }
 385
 386 static unsigned int __devinit ata66_svwks_svwks (ide_hwif_t *hwif)
 387 {
 388         return 1;
 389 }
 390
 391 /* On Dell PowerEdge servers with a CSB5/CSB6, the top two bits
 392  * of the subsystem device ID indicate presence of an 80-pin cable.
 393  * Bit 15 clear = secondary IDE channel does not have 80-pin cable.
 394  * Bit 15 set   = secondary IDE channel has 80-pin cable.
 395  * Bit 14 clear = primary IDE channel does not have 80-pin cable.
 396  * Bit 14 set   = primary IDE channel has 80-pin cable.
 397  */
 398 static unsigned int __devinit ata66_svwks_dell (ide_hwif_t *hwif)
 399 {
 400         struct pci_dev *dev = hwif->pci_dev;
 401         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
 402             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 403             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE ||
 404              dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE))
 405                 return ((1 << (hwif->channel + 14)) &
 406                         dev->subsystem_device) ? 1 : 0;
 407         return 0;
 408 }
 409
 410 /* Sun Cobalt Alpine hardware avoids the 80-pin cable
 411  * detect issue by attaching the drives directly to the board.
 412  * This check follows the Dell precedent (how scary is that?!)
 413  *
 414  * WARNING: this only works on Alpine hardware!
 415  */
 416 static unsigned int __devinit ata66_svwks_cobalt (ide_hwif_t *hwif)
 417 {
 418         struct pci_dev *dev = hwif->pci_dev;
 419         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN &&
 420             dev->vendor == PCI_VENDOR_ID_SERVERWORKS &&
 421             dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5IDE)
 422                 return ((1 << (hwif->channel + 14)) &
 423                         dev->subsystem_device) ? 1 : 0;
 424         return 0;
 425 }
 426
 427 static unsigned int __devinit ata66_svwks (ide_hwif_t *hwif)
 428 {
 429         struct pci_dev *dev = hwif->pci_dev;
 430
 431         /* Server Works */
 432         if (dev->subsystem_vendor == PCI_VENDOR_ID_SERVERWORKS)
 433                 return ata66_svwks_svwks (hwif);
 434
 435         /* Dell PowerEdge */
 436         if (dev->subsystem_vendor == PCI_VENDOR_ID_DELL)
 437                 return ata66_svwks_dell (hwif);
 438
 439         /* Cobalt Alpine */
 440         if (dev->subsystem_vendor == PCI_VENDOR_ID_SUN)
 441                 return ata66_svwks_cobalt (hwif);
 442
 443         /* Per Specified Design by OEM, and ASIC Architect */
 444         if ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE) ||
 445             (dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2))
 446                 return 1;
 447
 448         return 0;
 449 }
 450
 451 static void __devinit init_hwif_svwks (ide_hwif_t *hwif)
 452 {
 453         u8 dma_stat = 0;
 454
 455         if (!hwif->irq)
 456                 hwif->irq = hwif->channel ? 15 : 14;
 457
 458         hwif->tuneproc = &svwks_tune_drive;
 459         hwif->speedproc = &svwks_tune_chipset;
 460         hwif->udma_filter = &svwks_udma_filter;
 461
 462         hwif->atapi_dma = 1;
 463
 464         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE)
 465                 hwif->ultra_mask = 0x3f;
 466
 467         hwif->mwdma_mask = 0x07;
 468
 469         hwif->autodma = 0;
 470
 471         if (!hwif->dma_base) {
 472                 hwif->drives[0].autotune = 1;
 473                 hwif->drives[1].autotune = 1;
 474                 return;
 475         }
 476
 477         hwif->ide_dma_check = &svwks_config_drive_xfer_rate;
 478         if (hwif->pci_dev->device != PCI_DEVICE_ID_SERVERWORKS_OSB4IDE) {
 479                 if (!hwif->udma_four)
 480                         hwif->udma_four = ata66_svwks(hwif);
 481         }
 482         if (!noautodma)
 483                 hwif->autodma = 1;
 484
 485         dma_stat = inb(hwif->dma_status);
 486         hwif->drives[0].autodma = (dma_stat & 0x20);
 487         hwif->drives[1].autodma = (dma_stat & 0x40);
 488         hwif->drives[0].autotune = (!(dma_stat & 0x20));
 489         hwif->drives[1].autotune = (!(dma_stat & 0x40));
 490 }
 491
 492 static int __devinit init_setup_svwks (struct pci_dev *dev, ide_pci_device_t *d)
 493 {
 494         return ide_setup_pci_device(dev, d);
 495 }
 496
 497 static int __devinit init_setup_csb6 (struct pci_dev *dev, ide_pci_device_t *d)
 498 {
 499         if (!(PCI_FUNC(dev->devfn) & 1)) {
 500                 d->bootable = NEVER_BOARD;
 501                 if (dev->resource[0].start == 0x01f1)
 502                         d->bootable = ON_BOARD;
 503         }
 504
 505         d->channels = ((dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE ||
 506                         dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2) &&
 507                        (!(PCI_FUNC(dev->devfn) & 1))) ? 1 : 2;
 508
 509         return ide_setup_pci_device(dev, d);
 510 }
 511
 512 static ide_pci_device_t serverworks_chipsets[] __devinitdata = {
 513         {       /* 0 */
 514                 .name           = "SvrWks OSB4",
 515                 .init_setup     = init_setup_svwks,
 516                 .init_chipset   = init_chipset_svwks,
 517                 .init_hwif      = init_hwif_svwks,
 518                 .channels       = 2,
 519                 .autodma        = AUTODMA,
 520                 .bootable       = ON_BOARD,
 521         },{     /* 1 */
 522                 .name           = "SvrWks CSB5",
 523                 .init_setup     = init_setup_svwks,
 524                 .init_chipset   = init_chipset_svwks,
 525                 .init_hwif      = init_hwif_svwks,
 526                 .channels       = 2,
 527                 .autodma        = AUTODMA,
 528                 .bootable       = ON_BOARD,
 529         },{     /* 2 */
 530                 .name           = "SvrWks CSB6",
 531                 .init_setup     = init_setup_csb6,
 532                 .init_chipset   = init_chipset_svwks,
 533                 .init_hwif      = init_hwif_svwks,
 534                 .channels       = 2,
 535                 .autodma        = AUTODMA,
 536                 .bootable       = ON_BOARD,
 537         },{     /* 3 */
 538                 .name           = "SvrWks CSB6",
 539                 .init_setup     = init_setup_csb6,
 540                 .init_chipset   = init_chipset_svwks,
 541                 .init_hwif      = init_hwif_svwks,
 542                 .channels       = 1,    /* 2 */
 543                 .autodma        = AUTODMA,
 544                 .bootable       = ON_BOARD,
 545         },{     /* 4 */
 546                 .name           = "SvrWks HT1000",
 547                 .init_setup     = init_setup_svwks,
 548                 .init_chipset   = init_chipset_svwks,
 549                 .init_hwif      = init_hwif_svwks,
 550                 .channels       = 1,    /* 2 */
 551                 .autodma        = AUTODMA,
 552                 .bootable       = ON_BOARD,
 553         }
 554 };
 555
 556 /**
 557  *      svwks_init_one  -       called when a OSB/CSB is found
 558  *      @dev: the svwks device
 559  *      @id: the matching pci id
 560  *
 561  *      Called when the PCI registration layer (or the IDE initialization)
 562  *      finds a device matching our IDE device tables.
 563  */
 564
 565 static int __devinit svwks_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 566 {
 567         ide_pci_device_t *d = &serverworks_chipsets[id->driver_data];
 568
 569         return d->init_setup(dev, d);
 570 }
 571
 572 static struct pci_device_id svwks_pci_tbl[] = {
 573         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_OSB4IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
 574         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
 575         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
 576         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
 577         { PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000IDE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4},
 578         { 0, },
 579 };
 580 MODULE_DEVICE_TABLE(pci, svwks_pci_tbl);
 581
 582 static struct pci_driver driver = {
 583         .name           = "Serverworks_IDE",
 584         .id_table       = svwks_pci_tbl,
 585         .probe          = svwks_init_one,
 586 };
 587
 588 static int __init svwks_ide_init(void)
 589 {
 590         return ide_pci_register_driver(&driver);
 591 }
 592
 593 module_init(svwks_ide_init);
 594
 595 MODULE_AUTHOR("Michael Aubry. Andrzej Krzysztofowicz, Andre Hedrick");
 596 MODULE_DESCRIPTION("PCI driver module for Serverworks OSB4/CSB5/CSB6 IDE");
 597 MODULE_LICENSE("GPL");