4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly seperated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/i2c-id.h>
26 #include <linux/init.h>
27 #include <linux/time.h>
28 #include <linux/sched.h>
29 #include <linux/delay.h>
30 #include <linux/errno.h>
31 #include <linux/interrupt.h>
32 #include <linux/i2c-pxa.h>
33 #include <linux/platform_device.h>
35 #include <asm/hardware.h>
37 #include <asm/arch/i2c.h>
38 #include <asm/arch/pxa-regs.h>
42 wait_queue_head_t wait;
47 unsigned int slave_addr;
49 struct i2c_adapter adap;
50 #ifdef CONFIG_I2C_PXA_SLAVE
51 struct i2c_slave_client *slave;
54 unsigned int irqlogidx;
60 * I2C Slave mode address
62 #define I2C_PXA_SLAVE_ADDR 0x1
71 #define BIT(m, s, u) { .mask = m, .set = s, .unset = u }
74 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
76 printk("%s %08x: ", prefix, val);
78 const char *str = val & bits->mask ? bits->set : bits->unset;
85 static const struct bits isr_bits[] = {
86 BIT(ISR_RWM, "RX", "TX"),
87 BIT(ISR_ACKNAK, "NAK", "ACK"),
88 BIT(ISR_UB, "Bsy", "Rdy"),
89 BIT(ISR_IBB, "BusBsy", "BusRdy"),
90 BIT(ISR_SSD, "SlaveStop", NULL),
91 BIT(ISR_ALD, "ALD", NULL),
92 BIT(ISR_ITE, "TxEmpty", NULL),
93 BIT(ISR_IRF, "RxFull", NULL),
94 BIT(ISR_GCAD, "GenCall", NULL),
95 BIT(ISR_SAD, "SlaveAddr", NULL),
96 BIT(ISR_BED, "BusErr", NULL),
99 static void decode_ISR(unsigned int val)
101 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
105 static const struct bits icr_bits[] = {
106 BIT(ICR_START, "START", NULL),
107 BIT(ICR_STOP, "STOP", NULL),
108 BIT(ICR_ACKNAK, "ACKNAK", NULL),
109 BIT(ICR_TB, "TB", NULL),
110 BIT(ICR_MA, "MA", NULL),
111 BIT(ICR_SCLE, "SCLE", "scle"),
112 BIT(ICR_IUE, "IUE", "iue"),
113 BIT(ICR_GCD, "GCD", NULL),
114 BIT(ICR_ITEIE, "ITEIE", NULL),
115 BIT(ICR_IRFIE, "IRFIE", NULL),
116 BIT(ICR_BEIE, "BEIE", NULL),
117 BIT(ICR_SSDIE, "SSDIE", NULL),
118 BIT(ICR_ALDIE, "ALDIE", NULL),
119 BIT(ICR_SADIE, "SADIE", NULL),
120 BIT(ICR_UR, "UR", "ur"),
123 static void decode_ICR(unsigned int val)
125 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
129 static unsigned int i2c_debug = DEBUG;
131 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
133 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno, ISR, ICR, IBMR);
136 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __FUNCTION__)
140 #define show_state(i2c) do { } while (0)
141 #define decode_ISR(val) do { } while (0)
142 #define decode_ICR(val) do { } while (0)
145 #define eedbg(lvl, x...) do { if ((lvl) < 1) { printk(KERN_DEBUG "" x); } } while(0)
147 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
149 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
152 printk("i2c: error: %s\n", why);
153 printk("i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
154 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
155 printk("i2c: ICR: %08x ISR: %08x\n"
156 "i2c: log: ", ICR, ISR);
157 for (i = 0; i < i2c->irqlogidx; i++)
158 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
162 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
164 return !(ICR & ICR_SCLE);
167 static void i2c_pxa_abort(struct pxa_i2c *i2c)
169 unsigned long timeout = jiffies + HZ/4;
171 if (i2c_pxa_is_slavemode(i2c)) {
172 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
176 while (time_before(jiffies, timeout) && (IBMR & 0x1) == 0) {
177 unsigned long icr = ICR;
180 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
189 ICR &= ~(ICR_MA | ICR_START | ICR_STOP);
192 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
194 int timeout = DEF_TIMEOUT;
196 while (timeout-- && ISR & (ISR_IBB | ISR_UB)) {
197 if ((ISR & ISR_SAD) != 0)
207 return timeout <= 0 ? I2C_RETRY : 0;
210 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
212 unsigned long timeout = jiffies + HZ*4;
214 while (time_before(jiffies, timeout)) {
216 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
217 __func__, (long)jiffies, ISR, ICR, IBMR);
221 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
225 /* wait for unit and bus being not busy, and we also do a
226 * quick check of the i2c lines themselves to ensure they've
229 if ((ISR & (ISR_UB | ISR_IBB)) == 0 && IBMR == 3) {
231 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
239 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
244 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
247 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
249 if ((ISR & (ISR_UB | ISR_IBB)) != 0) {
250 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
251 if (!i2c_pxa_wait_master(i2c)) {
252 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
261 #ifdef CONFIG_I2C_PXA_SLAVE
262 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
264 unsigned long timeout = jiffies + HZ*1;
270 while (time_before(jiffies, timeout)) {
272 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
273 __func__, (long)jiffies, ISR, ICR, IBMR);
275 if ((ISR & (ISR_UB|ISR_IBB|ISR_SAD)) == ISR_SAD ||
276 (ICR & ICR_SCLE) == 0) {
278 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
286 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
291 * clear the hold on the bus, and take of anything else
292 * that has been configured
294 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
299 udelay(100); /* simple delay */
301 /* we need to wait for the stop condition to end */
303 /* if we where in stop, then clear... */
304 if (ICR & ICR_STOP) {
309 if (!i2c_pxa_wait_slave(i2c)) {
310 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
316 ICR &= ~(ICR_STOP|ICR_ACKNAK|ICR_MA);
320 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", ICR, ISR);
325 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
328 static void i2c_pxa_reset(struct pxa_i2c *i2c)
330 pr_debug("Resetting I2C Controller Unit\n");
332 /* abort any transfer currently under way */
335 /* reset according to 9.8 */
340 ISAR = i2c->slave_addr;
342 /* set control register values */
345 #ifdef CONFIG_I2C_PXA_SLAVE
346 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
347 ICR |= ICR_SADIE | ICR_ALDIE | ICR_SSDIE;
350 i2c_pxa_set_slave(i2c, 0);
358 #ifdef CONFIG_I2C_PXA_SLAVE
360 * I2C EEPROM emulation.
362 static struct i2c_eeprom_emu eeprom = {
363 .size = I2C_EEPROM_EMU_SIZE,
364 .watch = LIST_HEAD_INIT(eeprom.watch),
367 struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void)
372 int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *emu, void *data,
373 unsigned int addr, unsigned int size,
374 struct i2c_eeprom_emu_watcher *watcher)
376 struct i2c_eeprom_emu_watch *watch;
379 if (addr + size > emu->size)
382 watch = kmalloc(sizeof(struct i2c_eeprom_emu_watch), GFP_KERNEL);
385 watch->end = addr + size - 1;
386 watch->ops = watcher;
389 local_irq_save(flags);
390 list_add(&watch->node, &emu->watch);
391 local_irq_restore(flags);
394 return watch ? 0 : -ENOMEM;
397 void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *emu, void *data,
398 struct i2c_eeprom_emu_watcher *watcher)
400 struct i2c_eeprom_emu_watch *watch, *n;
403 list_for_each_entry_safe(watch, n, &emu->watch, node) {
404 if (watch->ops == watcher && watch->data == data) {
405 local_irq_save(flags);
406 list_del(&watch->node);
407 local_irq_restore(flags);
413 static void i2c_eeprom_emu_event(void *ptr, i2c_slave_event_t event)
415 struct i2c_eeprom_emu *emu = ptr;
417 eedbg(3, "i2c_eeprom_emu_event: %d\n", event);
420 case I2C_SLAVE_EVENT_START_WRITE:
422 eedbg(2, "i2c_eeprom: write initiated\n");
425 case I2C_SLAVE_EVENT_START_READ:
427 eedbg(2, "i2c_eeprom: read initiated\n");
430 case I2C_SLAVE_EVENT_STOP:
432 eedbg(2, "i2c_eeprom: received stop\n");
436 eedbg(0, "i2c_eeprom: unhandled event\n");
441 static int i2c_eeprom_emu_read(void *ptr)
443 struct i2c_eeprom_emu *emu = ptr;
446 ret = emu->bytes[emu->ptr];
447 emu->ptr = (emu->ptr + 1) % emu->size;
452 static void i2c_eeprom_emu_write(void *ptr, unsigned int val)
454 struct i2c_eeprom_emu *emu = ptr;
455 struct i2c_eeprom_emu_watch *watch;
457 if (emu->seen_start != 0) {
458 eedbg(2, "i2c_eeprom_emu_write: setting ptr %02x\n", val);
464 emu->bytes[emu->ptr] = val;
466 eedbg(1, "i2c_eeprom_emu_write: ptr=0x%02x, val=0x%02x\n",
469 list_for_each_entry(watch, &emu->watch, node) {
470 if (!watch->ops || !watch->ops->write)
472 if (watch->start <= emu->ptr && watch->end >= emu->ptr)
473 watch->ops->write(watch->data, emu->ptr, val);
476 emu->ptr = (emu->ptr + 1) % emu->size;
479 struct i2c_slave_client eeprom_client = {
481 .event = i2c_eeprom_emu_event,
482 .read = i2c_eeprom_emu_read,
483 .write = i2c_eeprom_emu_write
490 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
493 /* what should we do here? */
495 int ret = i2c->slave->read(i2c->slave->data);
498 ICR |= ICR_TB; /* allow next byte */
502 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
504 unsigned int byte = IDBR;
506 if (i2c->slave != NULL)
507 i2c->slave->write(i2c->slave->data, byte);
512 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
517 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
518 (isr & ISR_RWM) ? 'r' : 't');
520 if (i2c->slave != NULL)
521 i2c->slave->event(i2c->slave->data,
522 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
525 * slave could interrupt in the middle of us generating a
526 * start condition... if this happens, we'd better back off
527 * and stop holding the poor thing up
529 ICR &= ~(ICR_START|ICR_STOP);
541 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
549 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
552 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
554 if (i2c->slave != NULL)
555 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
558 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
561 * If we have a master-mode message waiting,
562 * kick it off now that the slave has completed.
565 i2c_pxa_master_complete(i2c, I2C_RETRY);
568 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
571 /* what should we do here? */
578 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
580 ICR |= ICR_TB | ICR_ACKNAK;
583 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
588 * slave could interrupt in the middle of us generating a
589 * start condition... if this happens, we'd better back off
590 * and stop holding the poor thing up
592 ICR &= ~(ICR_START|ICR_STOP);
593 ICR |= ICR_TB | ICR_ACKNAK;
604 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
612 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
615 i2c_pxa_master_complete(i2c, I2C_RETRY);
620 * PXA I2C Master mode
623 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
625 unsigned int addr = (msg->addr & 0x7f) << 1;
627 if (msg->flags & I2C_M_RD)
633 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
638 * Step 1: target slave address into IDBR
640 IDBR = i2c_pxa_addr_byte(i2c->msg);
643 * Step 2: initiate the write.
645 icr = ICR & ~(ICR_STOP | ICR_ALDIE);
646 ICR = icr | ICR_START | ICR_TB;
650 * We are protected by the adapter bus mutex.
652 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
658 * Wait for the bus to become free.
660 ret = i2c_pxa_wait_bus_not_busy(i2c);
662 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
669 ret = i2c_pxa_set_master(i2c);
671 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
675 spin_lock_irq(&i2c->lock);
683 i2c_pxa_start_message(i2c);
685 spin_unlock_irq(&i2c->lock);
688 * The rest of the processing occurs in the interrupt handler.
690 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
693 * We place the return code in i2c->msg_idx.
698 i2c_pxa_scream_blue_murder(i2c, "timeout");
705 * i2c_pxa_master_complete - complete the message and wake up.
707 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
718 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
720 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
724 * If ISR_ALD is set, we lost arbitration.
728 * Do we need to do anything here? The PXA docs
729 * are vague about what happens.
731 i2c_pxa_scream_blue_murder(i2c, "ALD set");
734 * We ignore this error. We seem to see spurious ALDs
735 * for seemingly no reason. If we handle them as I think
736 * they should, we end up causing an I2C error, which
737 * is painful for some systems.
746 * I2C bus error - either the device NAK'd us, or
747 * something more serious happened. If we were NAK'd
748 * on the initial address phase, we can retry.
750 if (isr & ISR_ACKNAK) {
751 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
756 i2c_pxa_master_complete(i2c, ret);
757 } else if (isr & ISR_RWM) {
759 * Read mode. We have just sent the address byte, and
760 * now we must initiate the transfer.
762 if (i2c->msg_ptr == i2c->msg->len - 1 &&
763 i2c->msg_idx == i2c->msg_num - 1)
764 icr |= ICR_STOP | ICR_ACKNAK;
766 icr |= ICR_ALDIE | ICR_TB;
767 } else if (i2c->msg_ptr < i2c->msg->len) {
769 * Write mode. Write the next data byte.
771 IDBR = i2c->msg->buf[i2c->msg_ptr++];
773 icr |= ICR_ALDIE | ICR_TB;
776 * If this is the last byte of the last message, send
779 if (i2c->msg_ptr == i2c->msg->len &&
780 i2c->msg_idx == i2c->msg_num - 1)
782 } else if (i2c->msg_idx < i2c->msg_num - 1) {
784 * Next segment of the message.
791 * If we aren't doing a repeated start and address,
792 * go back and try to send the next byte. Note that
793 * we do not support switching the R/W direction here.
795 if (i2c->msg->flags & I2C_M_NOSTART)
799 * Write the next address.
801 IDBR = i2c_pxa_addr_byte(i2c->msg);
804 * And trigger a repeated start, and send the byte.
807 icr |= ICR_START | ICR_TB;
809 if (i2c->msg->len == 0) {
811 * Device probes have a message length of zero
812 * and need the bus to be reset before it can
817 i2c_pxa_master_complete(i2c, 0);
820 i2c->icrlog[i2c->irqlogidx-1] = icr;
826 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
828 u32 icr = ICR & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
833 i2c->msg->buf[i2c->msg_ptr++] = IDBR;
835 if (i2c->msg_ptr < i2c->msg->len) {
837 * If this is the last byte of the last
838 * message, send a STOP.
840 if (i2c->msg_ptr == i2c->msg->len - 1)
841 icr |= ICR_STOP | ICR_ACKNAK;
843 icr |= ICR_ALDIE | ICR_TB;
845 i2c_pxa_master_complete(i2c, 0);
848 i2c->icrlog[i2c->irqlogidx-1] = icr;
853 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id, struct pt_regs *regs)
855 struct pxa_i2c *i2c = dev_id;
858 if (i2c_debug > 2 && 0) {
859 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
860 __func__, isr, ICR, IBMR);
864 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
865 i2c->isrlog[i2c->irqlogidx++] = isr;
870 * Always clear all pending IRQs.
872 ISR = isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED);
875 i2c_pxa_slave_start(i2c, isr);
877 i2c_pxa_slave_stop(i2c);
879 if (i2c_pxa_is_slavemode(i2c)) {
881 i2c_pxa_slave_txempty(i2c, isr);
883 i2c_pxa_slave_rxfull(i2c, isr);
884 } else if (i2c->msg) {
886 i2c_pxa_irq_txempty(i2c, isr);
888 i2c_pxa_irq_rxfull(i2c, isr);
890 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
897 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
899 struct pxa_i2c *i2c = adap->algo_data;
902 /* If the I2C controller is disabled we need to reset it (probably due
903 to a suspend/resume destroying state). We do this here as we can then
904 avoid worrying about resuming the controller before its users. */
905 if (!(ICR & ICR_IUE))
908 for (i = adap->retries; i >= 0; i--) {
909 ret = i2c_pxa_do_xfer(i2c, msgs, num);
910 if (ret != I2C_RETRY)
914 dev_dbg(&adap->dev, "Retrying transmission\n");
917 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
920 i2c_pxa_set_slave(i2c, ret);
924 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
926 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
929 static struct i2c_algorithm i2c_pxa_algorithm = {
930 .master_xfer = i2c_pxa_xfer,
931 .functionality = i2c_pxa_functionality,
934 static struct pxa_i2c i2c_pxa = {
935 .lock = SPIN_LOCK_UNLOCKED,
936 .wait = __WAIT_QUEUE_HEAD_INITIALIZER(i2c_pxa.wait),
938 .owner = THIS_MODULE,
939 .algo = &i2c_pxa_algorithm,
940 .name = "pxa2xx-i2c",
945 static int i2c_pxa_probe(struct platform_device *dev)
947 struct pxa_i2c *i2c = &i2c_pxa;
948 #ifdef CONFIG_I2C_PXA_SLAVE
949 struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
954 pxa_gpio_mode(GPIO117_I2CSCL_MD);
955 pxa_gpio_mode(GPIO118_I2CSDA_MD);
959 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
961 #ifdef CONFIG_I2C_PXA_SLAVE
962 i2c->slave = &eeprom_client;
964 i2c->slave_addr = plat->slave_addr;
966 i2c->slave = plat->slave;
970 pxa_set_cken(CKEN14_I2C, 1);
971 ret = request_irq(IRQ_I2C, i2c_pxa_handler, IRQF_DISABLED,
978 i2c->adap.algo_data = i2c;
979 i2c->adap.dev.parent = &dev->dev;
981 ret = i2c_add_adapter(&i2c->adap);
983 printk(KERN_INFO "I2C: Failed to add bus\n");
987 platform_set_drvdata(dev, i2c);
989 #ifdef CONFIG_I2C_PXA_SLAVE
990 printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
991 i2c->adap.dev.bus_id, i2c->slave_addr);
993 printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
994 i2c->adap.dev.bus_id);
999 free_irq(IRQ_I2C, i2c);
1004 static int i2c_pxa_remove(struct platform_device *dev)
1006 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1008 platform_set_drvdata(dev, NULL);
1010 i2c_del_adapter(&i2c->adap);
1011 free_irq(IRQ_I2C, i2c);
1012 pxa_set_cken(CKEN14_I2C, 0);
1017 static struct platform_driver i2c_pxa_driver = {
1018 .probe = i2c_pxa_probe,
1019 .remove = i2c_pxa_remove,
1021 .name = "pxa2xx-i2c",
1025 static int __init i2c_adap_pxa_init(void)
1027 return platform_driver_register(&i2c_pxa_driver);
1030 static void i2c_adap_pxa_exit(void)
1032 return platform_driver_unregister(&i2c_pxa_driver);
1035 MODULE_LICENSE("GPL");
1037 module_init(i2c_adap_pxa_init);
1038 module_exit(i2c_adap_pxa_exit);