drivers/i2c/busses/i2c-npcm7xx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Nuvoton NPCM7xx I2C Controller driver
   4  *
   5  * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/debugfs.h>
  10 #include <linux/errno.h>
  11 #include <linux/i2c.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/iopoll.h>
  14 #include <linux/irq.h>
  15 #include <linux/jiffies.h>
  16 #include <linux/kernel.h>
  17 #include <linux/mfd/syscon.h>
  18 #include <linux/module.h>
  19 #include <linux/of.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22
  23 enum i2c_mode {
  24         I2C_MASTER,
  25         I2C_SLAVE,
  26 };
  27
  28 /*
  29  * External I2C Interface driver xfer indication values, which indicate status
  30  * of the bus.
  31  */
  32 enum i2c_state_ind {
  33         I2C_NO_STATUS_IND = 0,
  34         I2C_SLAVE_RCV_IND,
  35         I2C_SLAVE_XMIT_IND,
  36         I2C_SLAVE_XMIT_MISSING_DATA_IND,
  37         I2C_SLAVE_RESTART_IND,
  38         I2C_SLAVE_DONE_IND,
  39         I2C_MASTER_DONE_IND,
  40         I2C_NACK_IND,
  41         I2C_BUS_ERR_IND,
  42         I2C_WAKE_UP_IND,
  43         I2C_BLOCK_BYTES_ERR_IND,
  44         I2C_SLAVE_RCV_MISSING_DATA_IND,
  45 };
  46
  47 /*
  48  * Operation type values (used to define the operation currently running)
  49  * module is interrupt driven, on each interrupt the current operation is
  50  * checked to see if the module is currently reading or writing.
  51  */
  52 enum i2c_oper {
  53         I2C_NO_OPER = 0,
  54         I2C_WRITE_OPER,
  55         I2C_READ_OPER,
  56 };
  57
  58 /* I2C Bank (module had 2 banks of registers) */
  59 enum i2c_bank {
  60         I2C_BANK_0 = 0,
  61         I2C_BANK_1,
  62 };
  63
  64 /* Internal I2C states values (for the I2C module state machine). */
  65 enum i2c_state {
  66         I2C_DISABLE = 0,
  67         I2C_IDLE,
  68         I2C_MASTER_START,
  69         I2C_SLAVE_MATCH,
  70         I2C_OPER_STARTED,
  71         I2C_STOP_PENDING,
  72 };
  73
  74 #if IS_ENABLED(CONFIG_I2C_SLAVE)
  75 /* Module supports setting multiple own slave addresses */
  76 enum i2c_addr {
  77         I2C_SLAVE_ADDR1 = 0,
  78         I2C_SLAVE_ADDR2,
  79         I2C_SLAVE_ADDR3,
  80         I2C_SLAVE_ADDR4,
  81         I2C_SLAVE_ADDR5,
  82         I2C_SLAVE_ADDR6,
  83         I2C_SLAVE_ADDR7,
  84         I2C_SLAVE_ADDR8,
  85         I2C_SLAVE_ADDR9,
  86         I2C_SLAVE_ADDR10,
  87         I2C_GC_ADDR,
  88         I2C_ARP_ADDR,
  89 };
  90 #endif
  91
  92 /* init register and default value required to enable module */
  93 #define NPCM_I2CSEGCTL                  0xE4
  94 #define NPCM_I2CSEGCTL_INIT_VAL         0x0333F000
  95
  96 /* Common regs */
  97 #define NPCM_I2CSDA                     0x00
  98 #define NPCM_I2CST                      0x02
  99 #define NPCM_I2CCST                     0x04
 100 #define NPCM_I2CCTL1                    0x06
 101 #define NPCM_I2CADDR1                   0x08
 102 #define NPCM_I2CCTL2                    0x0A
 103 #define NPCM_I2CADDR2                   0x0C
 104 #define NPCM_I2CCTL3                    0x0E
 105 #define NPCM_I2CCST2                    0x18
 106 #define NPCM_I2CCST3                    0x19
 107 #define I2C_VER                         0x1F
 108
 109 /*BANK0 regs*/
 110 #define NPCM_I2CADDR3                   0x10
 111 #define NPCM_I2CADDR7                   0x11
 112 #define NPCM_I2CADDR4                   0x12
 113 #define NPCM_I2CADDR8                   0x13
 114 #define NPCM_I2CADDR5                   0x14
 115 #define NPCM_I2CADDR9                   0x15
 116 #define NPCM_I2CADDR6                   0x16
 117 #define NPCM_I2CADDR10                  0x17
 118
 119 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 120 /*
 121  * npcm_i2caddr array:
 122  * The module supports having multiple own slave addresses.
 123  * Since the addr regs are sprinkled all over the address space,
 124  * use this array to get the address or each register.
 125  */
 126 #define I2C_NUM_OWN_ADDR 10
 127 static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = {
 128         NPCM_I2CADDR1, NPCM_I2CADDR2, NPCM_I2CADDR3, NPCM_I2CADDR4,
 129         NPCM_I2CADDR5, NPCM_I2CADDR6, NPCM_I2CADDR7, NPCM_I2CADDR8,
 130         NPCM_I2CADDR9, NPCM_I2CADDR10,
 131 };
 132 #endif
 133
 134 #define NPCM_I2CCTL4                    0x1A
 135 #define NPCM_I2CCTL5                    0x1B
 136 #define NPCM_I2CSCLLT                   0x1C /* SCL Low Time */
 137 #define NPCM_I2CFIF_CTL                 0x1D /* FIFO Control */
 138 #define NPCM_I2CSCLHT                   0x1E /* SCL High Time */
 139
 140 /* BANK 1 regs */
 141 #define NPCM_I2CFIF_CTS                 0x10 /* Both FIFOs Control and Status */
 142 #define NPCM_I2CTXF_CTL                 0x12 /* Tx-FIFO Control */
 143 #define NPCM_I2CT_OUT                   0x14 /* Bus T.O. */
 144 #define NPCM_I2CPEC                     0x16 /* PEC Data */
 145 #define NPCM_I2CTXF_STS                 0x1A /* Tx-FIFO Status */
 146 #define NPCM_I2CRXF_STS                 0x1C /* Rx-FIFO Status */
 147 #define NPCM_I2CRXF_CTL                 0x1E /* Rx-FIFO Control */
 148
 149 /* NPCM_I2CST reg fields */
 150 #define NPCM_I2CST_XMIT                 BIT(0)
 151 #define NPCM_I2CST_MASTER               BIT(1)
 152 #define NPCM_I2CST_NMATCH               BIT(2)
 153 #define NPCM_I2CST_STASTR               BIT(3)
 154 #define NPCM_I2CST_NEGACK               BIT(4)
 155 #define NPCM_I2CST_BER                  BIT(5)
 156 #define NPCM_I2CST_SDAST                BIT(6)
 157 #define NPCM_I2CST_SLVSTP               BIT(7)
 158
 159 /* NPCM_I2CCST reg fields */
 160 #define NPCM_I2CCST_BUSY                BIT(0)
 161 #define NPCM_I2CCST_BB                  BIT(1)
 162 #define NPCM_I2CCST_MATCH               BIT(2)
 163 #define NPCM_I2CCST_GCMATCH             BIT(3)
 164 #define NPCM_I2CCST_TSDA                BIT(4)
 165 #define NPCM_I2CCST_TGSCL               BIT(5)
 166 #define NPCM_I2CCST_MATCHAF             BIT(6)
 167 #define NPCM_I2CCST_ARPMATCH            BIT(7)
 168
 169 /* NPCM_I2CCTL1 reg fields */
 170 #define NPCM_I2CCTL1_START              BIT(0)
 171 #define NPCM_I2CCTL1_STOP               BIT(1)
 172 #define NPCM_I2CCTL1_INTEN              BIT(2)
 173 #define NPCM_I2CCTL1_EOBINTE            BIT(3)
 174 #define NPCM_I2CCTL1_ACK                BIT(4)
 175 #define NPCM_I2CCTL1_GCMEN              BIT(5)
 176 #define NPCM_I2CCTL1_NMINTE             BIT(6)
 177 #define NPCM_I2CCTL1_STASTRE            BIT(7)
 178
 179 /* RW1S fields (inside a RW reg): */
 180 #define NPCM_I2CCTL1_RWS   \
 181         (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK)
 182
 183 /* npcm_i2caddr reg fields */
 184 #define NPCM_I2CADDR_A                  GENMASK(6, 0)
 185 #define NPCM_I2CADDR_SAEN               BIT(7)
 186
 187 /* NPCM_I2CCTL2 reg fields */
 188 #define I2CCTL2_ENABLE                  BIT(0)
 189 #define I2CCTL2_SCLFRQ6_0               GENMASK(7, 1)
 190
 191 /* NPCM_I2CCTL3 reg fields */
 192 #define I2CCTL3_SCLFRQ8_7               GENMASK(1, 0)
 193 #define I2CCTL3_ARPMEN                  BIT(2)
 194 #define I2CCTL3_IDL_START               BIT(3)
 195 #define I2CCTL3_400K_MODE               BIT(4)
 196 #define I2CCTL3_BNK_SEL                 BIT(5)
 197 #define I2CCTL3_SDA_LVL                 BIT(6)
 198 #define I2CCTL3_SCL_LVL                 BIT(7)
 199
 200 /* NPCM_I2CCST2 reg fields */
 201 #define NPCM_I2CCST2_MATCHA1F           BIT(0)
 202 #define NPCM_I2CCST2_MATCHA2F           BIT(1)
 203 #define NPCM_I2CCST2_MATCHA3F           BIT(2)
 204 #define NPCM_I2CCST2_MATCHA4F           BIT(3)
 205 #define NPCM_I2CCST2_MATCHA5F           BIT(4)
 206 #define NPCM_I2CCST2_MATCHA6F           BIT(5)
 207 #define NPCM_I2CCST2_MATCHA7F           BIT(5)
 208 #define NPCM_I2CCST2_INTSTS             BIT(7)
 209
 210 /* NPCM_I2CCST3 reg fields */
 211 #define NPCM_I2CCST3_MATCHA8F           BIT(0)
 212 #define NPCM_I2CCST3_MATCHA9F           BIT(1)
 213 #define NPCM_I2CCST3_MATCHA10F          BIT(2)
 214 #define NPCM_I2CCST3_EO_BUSY            BIT(7)
 215
 216 /* NPCM_I2CCTL4 reg fields */
 217 #define I2CCTL4_HLDT                    GENMASK(5, 0)
 218 #define I2CCTL4_LVL_WE                  BIT(7)
 219
 220 /* NPCM_I2CCTL5 reg fields */
 221 #define I2CCTL5_DBNCT                   GENMASK(3, 0)
 222
 223 /* NPCM_I2CFIF_CTS reg fields */
 224 #define NPCM_I2CFIF_CTS_RXF_TXE         BIT(1)
 225 #define NPCM_I2CFIF_CTS_RFTE_IE         BIT(3)
 226 #define NPCM_I2CFIF_CTS_CLR_FIFO        BIT(6)
 227 #define NPCM_I2CFIF_CTS_SLVRSTR         BIT(7)
 228
 229 /* NPCM_I2CTXF_CTL reg fields */
 230 #define NPCM_I2CTXF_CTL_TX_THR          GENMASK(4, 0)
 231 #define NPCM_I2CTXF_CTL_THR_TXIE        BIT(6)
 232
 233 /* NPCM_I2CT_OUT reg fields */
 234 #define NPCM_I2CT_OUT_TO_CKDIV          GENMASK(5, 0)
 235 #define NPCM_I2CT_OUT_T_OUTIE           BIT(6)
 236 #define NPCM_I2CT_OUT_T_OUTST           BIT(7)
 237
 238 /* NPCM_I2CTXF_STS reg fields */
 239 #define NPCM_I2CTXF_STS_TX_BYTES        GENMASK(4, 0)
 240 #define NPCM_I2CTXF_STS_TX_THST         BIT(6)
 241
 242 /* NPCM_I2CRXF_STS reg fields */
 243 #define NPCM_I2CRXF_STS_RX_BYTES        GENMASK(4, 0)
 244 #define NPCM_I2CRXF_STS_RX_THST         BIT(6)
 245
 246 /* NPCM_I2CFIF_CTL reg fields */
 247 #define NPCM_I2CFIF_CTL_FIFO_EN         BIT(4)
 248
 249 /* NPCM_I2CRXF_CTL reg fields */
 250 #define NPCM_I2CRXF_CTL_RX_THR          GENMASK(4, 0)
 251 #define NPCM_I2CRXF_CTL_LAST_PEC        BIT(5)
 252 #define NPCM_I2CRXF_CTL_THR_RXIE        BIT(6)
 253
 254 #define I2C_HW_FIFO_SIZE                16
 255
 256 /* I2C_VER reg fields */
 257 #define I2C_VER_VERSION                 GENMASK(6, 0)
 258 #define I2C_VER_FIFO_EN                 BIT(7)
 259
 260 /* stall/stuck timeout in us */
 261 #define DEFAULT_STALL_COUNT             25
 262
 263 /* SCLFRQ field position */
 264 #define SCLFRQ_0_TO_6                   GENMASK(6, 0)
 265 #define SCLFRQ_7_TO_8                   GENMASK(8, 7)
 266
 267 /* supported clk settings. values in Hz. */
 268 #define I2C_FREQ_MIN_HZ                 10000
 269 #define I2C_FREQ_MAX_HZ                 I2C_MAX_FAST_MODE_PLUS_FREQ
 270
 271 /* Status of one I2C module */
 272 struct npcm_i2c {
 273         struct i2c_adapter adap;
 274         struct device *dev;
 275         unsigned char __iomem *reg;
 276         spinlock_t lock;   /* IRQ synchronization */
 277         struct completion cmd_complete;
 278         int cmd_err;
 279         struct i2c_msg *msgs;
 280         int msgs_num;
 281         int num;
 282         u32 apb_clk;
 283         struct i2c_bus_recovery_info rinfo;
 284         enum i2c_state state;
 285         enum i2c_oper operation;
 286         enum i2c_mode master_or_slave;
 287         enum i2c_state_ind stop_ind;
 288         u8 dest_addr;
 289         u8 *rd_buf;
 290         u16 rd_size;
 291         u16 rd_ind;
 292         u8 *wr_buf;
 293         u16 wr_size;
 294         u16 wr_ind;
 295         bool fifo_use;
 296         u16 PEC_mask; /* PEC bit mask per slave address */
 297         bool PEC_use;
 298         bool read_block_use;
 299         unsigned long int_time_stamp;
 300         unsigned long bus_freq; /* in Hz */
 301 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 302         u8 own_slave_addr;
 303         struct i2c_client *slave;
 304         int slv_rd_size;
 305         int slv_rd_ind;
 306         int slv_wr_size;
 307         int slv_wr_ind;
 308         u8 slv_rd_buf[I2C_HW_FIFO_SIZE];
 309         u8 slv_wr_buf[I2C_HW_FIFO_SIZE];
 310 #endif
 311         struct dentry *debugfs; /* debugfs device directory */
 312         u64 ber_cnt;
 313         u64 rec_succ_cnt;
 314         u64 rec_fail_cnt;
 315         u64 nack_cnt;
 316         u64 timeout_cnt;
 317 };
 318
 319 static inline void npcm_i2c_select_bank(struct npcm_i2c *bus,
 320                                         enum i2c_bank bank)
 321 {
 322         u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 323
 324         if (bank == I2C_BANK_0)
 325                 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL;
 326         else
 327                 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL;
 328         iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 329 }
 330
 331 static void npcm_i2c_init_params(struct npcm_i2c *bus)
 332 {
 333         bus->stop_ind = I2C_NO_STATUS_IND;
 334         bus->rd_size = 0;
 335         bus->wr_size = 0;
 336         bus->rd_ind = 0;
 337         bus->wr_ind = 0;
 338         bus->read_block_use = false;
 339         bus->int_time_stamp = 0;
 340         bus->PEC_use = false;
 341         bus->PEC_mask = 0;
 342 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 343         if (bus->slave)
 344                 bus->master_or_slave = I2C_SLAVE;
 345 #endif
 346 }
 347
 348 static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data)
 349 {
 350         iowrite8(data, bus->reg + NPCM_I2CSDA);
 351 }
 352
 353 static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus)
 354 {
 355         return ioread8(bus->reg + NPCM_I2CSDA);
 356 }
 357
 358 static int npcm_i2c_get_SCL(struct i2c_adapter *_adap)
 359 {
 360         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 361
 362         return !!(I2CCTL3_SCL_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
 363 }
 364
 365 static int npcm_i2c_get_SDA(struct i2c_adapter *_adap)
 366 {
 367         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
 368
 369         return !!(I2CCTL3_SDA_LVL & ioread32(bus->reg + NPCM_I2CCTL3));
 370 }
 371
 372 static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus)
 373 {
 374         if (bus->operation == I2C_READ_OPER)
 375                 return bus->rd_ind;
 376         if (bus->operation == I2C_WRITE_OPER)
 377                 return bus->wr_ind;
 378         return 0;
 379 }
 380
 381 /* quick protocol (just address) */
 382 static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus)
 383 {
 384         return bus->wr_size == 0 && bus->rd_size == 0;
 385 }
 386
 387 static void npcm_i2c_disable(struct npcm_i2c *bus)
 388 {
 389         u8 i2cctl2;
 390
 391 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 392         int i;
 393
 394         /* select bank 0 for I2C addresses */
 395         npcm_i2c_select_bank(bus, I2C_BANK_0);
 396
 397         /* Slave addresses removal */
 398         for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++)
 399                 iowrite8(0, bus->reg + npcm_i2caddr[i]);
 400
 401         npcm_i2c_select_bank(bus, I2C_BANK_1);
 402 #endif
 403         /* Disable module */
 404         i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 405         i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE;
 406         iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 407
 408         bus->state = I2C_DISABLE;
 409 }
 410
 411 static void npcm_i2c_enable(struct npcm_i2c *bus)
 412 {
 413         u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2);
 414
 415         i2cctl2 = i2cctl2 | I2CCTL2_ENABLE;
 416         iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2);
 417         bus->state = I2C_IDLE;
 418 }
 419
 420 /* enable\disable end of busy (EOB) interrupts */
 421 static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable)
 422 {
 423         u8 val;
 424
 425         /* Clear EO_BUSY pending bit: */
 426         val = ioread8(bus->reg + NPCM_I2CCST3);
 427         val = val | NPCM_I2CCST3_EO_BUSY;
 428         iowrite8(val, bus->reg + NPCM_I2CCST3);
 429
 430         val = ioread8(bus->reg + NPCM_I2CCTL1);
 431         val &= ~NPCM_I2CCTL1_RWS;
 432         if (enable)
 433                 val |= NPCM_I2CCTL1_EOBINTE;
 434         else
 435                 val &= ~NPCM_I2CCTL1_EOBINTE;
 436         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 437 }
 438
 439 static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus)
 440 {
 441         u8 tx_fifo_sts;
 442
 443         tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS);
 444         /* check if TX FIFO is not empty */
 445         if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0)
 446                 return false;
 447
 448         /* check if TX FIFO status bit is set: */
 449         return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts);
 450 }
 451
 452 static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus)
 453 {
 454         u8 rx_fifo_sts;
 455
 456         rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS);
 457         /* check if RX FIFO is not empty: */
 458         if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0)
 459                 return false;
 460
 461         /* check if rx fifo full status is set: */
 462         return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts);
 463 }
 464
 465 static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus)
 466 {
 467         u8 val;
 468
 469         val = ioread8(bus->reg + NPCM_I2CFIF_CTS);
 470         val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE;
 471         iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
 472 }
 473
 474 static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus)
 475 {
 476         u8 val;
 477
 478         val = ioread8(bus->reg + NPCM_I2CTXF_STS);
 479         val = val | NPCM_I2CTXF_STS_TX_THST;
 480         iowrite8(val, bus->reg + NPCM_I2CTXF_STS);
 481 }
 482
 483 static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus)
 484 {
 485         u8 val;
 486
 487         val = ioread8(bus->reg + NPCM_I2CRXF_STS);
 488         val = val | NPCM_I2CRXF_STS_RX_THST;
 489         iowrite8(val, bus->reg + NPCM_I2CRXF_STS);
 490 }
 491
 492 static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable)
 493 {
 494         u8 val;
 495
 496         val = ioread8(bus->reg + NPCM_I2CCTL1);
 497         val &= ~NPCM_I2CCTL1_RWS;
 498         if (enable)
 499                 val |= NPCM_I2CCTL1_INTEN;
 500         else
 501                 val &= ~NPCM_I2CCTL1_INTEN;
 502         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 503 }
 504
 505 static inline void npcm_i2c_master_start(struct npcm_i2c *bus)
 506 {
 507         u8 val;
 508
 509         val = ioread8(bus->reg + NPCM_I2CCTL1);
 510         val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK);
 511         val |= NPCM_I2CCTL1_START;
 512         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 513 }
 514
 515 static inline void npcm_i2c_master_stop(struct npcm_i2c *bus)
 516 {
 517         u8 val;
 518
 519         /*
 520          * override HW issue: I2C may fail to supply stop condition in Master
 521          * Write operation.
 522          * Need to delay at least 5 us from the last int, before issueing a stop
 523          */
 524         udelay(10); /* function called from interrupt, can't sleep */
 525         val = ioread8(bus->reg + NPCM_I2CCTL1);
 526         val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK);
 527         val |= NPCM_I2CCTL1_STOP;
 528         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 529
 530         if (!bus->fifo_use)
 531                 return;
 532
 533         npcm_i2c_select_bank(bus, I2C_BANK_1);
 534
 535         if (bus->operation == I2C_READ_OPER)
 536                 npcm_i2c_clear_rx_fifo(bus);
 537         else
 538                 npcm_i2c_clear_tx_fifo(bus);
 539         npcm_i2c_clear_fifo_int(bus);
 540         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 541 }
 542
 543 static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall)
 544 {
 545         u8 val;
 546
 547         val = ioread8(bus->reg + NPCM_I2CCTL1);
 548         val &= ~NPCM_I2CCTL1_RWS;
 549         if (stall)
 550                 val |= NPCM_I2CCTL1_STASTRE;
 551         else
 552                 val &= ~NPCM_I2CCTL1_STASTRE;
 553         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 554 }
 555
 556 static inline void npcm_i2c_nack(struct npcm_i2c *bus)
 557 {
 558         u8 val;
 559
 560         val = ioread8(bus->reg + NPCM_I2CCTL1);
 561         val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START);
 562         val |= NPCM_I2CCTL1_ACK;
 563         iowrite8(val, bus->reg + NPCM_I2CCTL1);
 564 }
 565
 566 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 567 static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable)
 568 {
 569         u8 i2cctl1;
 570
 571         /* enable interrupt on slave match: */
 572         i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 573         i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 574         if (enable)
 575                 i2cctl1 |= NPCM_I2CCTL1_NMINTE;
 576         else
 577                 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE;
 578         iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 579 }
 580
 581 static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type,
 582                                  u8 addr, bool enable)
 583 {
 584         u8 i2cctl1;
 585         u8 i2cctl3;
 586         u8 sa_reg;
 587
 588         sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable);
 589         if (addr_type == I2C_GC_ADDR) {
 590                 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 591                 if (enable)
 592                         i2cctl1 |= NPCM_I2CCTL1_GCMEN;
 593                 else
 594                         i2cctl1 &= ~NPCM_I2CCTL1_GCMEN;
 595                 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 596                 return 0;
 597         }
 598         if (addr_type == I2C_ARP_ADDR) {
 599                 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3);
 600                 if (enable)
 601                         i2cctl3 |= I2CCTL3_ARPMEN;
 602                 else
 603                         i2cctl3 &= ~I2CCTL3_ARPMEN;
 604                 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3);
 605                 return 0;
 606         }
 607         if (addr_type >= I2C_ARP_ADDR)
 608                 return -EFAULT;
 609         /* select bank 0 for address 3 to 10 */
 610         if (addr_type > I2C_SLAVE_ADDR2)
 611                 npcm_i2c_select_bank(bus, I2C_BANK_0);
 612         /* Set and enable the address */
 613         iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]);
 614         npcm_i2c_slave_int_enable(bus, enable);
 615         if (addr_type > I2C_SLAVE_ADDR2)
 616                 npcm_i2c_select_bank(bus, I2C_BANK_1);
 617         return 0;
 618 }
 619 #endif
 620
 621 static void npcm_i2c_reset(struct npcm_i2c *bus)
 622 {
 623         /*
 624          * Save I2CCTL1 relevant bits. It is being cleared when the module
 625          *  is disabled.
 626          */
 627         u8 i2cctl1;
 628 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 629         u8 addr;
 630 #endif
 631
 632         i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1);
 633
 634         npcm_i2c_disable(bus);
 635         npcm_i2c_enable(bus);
 636
 637         /* Restore NPCM_I2CCTL1 Status */
 638         i2cctl1 &= ~NPCM_I2CCTL1_RWS;
 639         iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1);
 640
 641         /* Clear BB (BUS BUSY) bit */
 642         iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
 643         iowrite8(0xFF, bus->reg + NPCM_I2CST);
 644
 645         /* Clear EOB bit */
 646         iowrite8(NPCM_I2CCST3_EO_BUSY, bus->reg + NPCM_I2CCST3);
 647
 648         /* Clear all fifo bits: */
 649         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
 650
 651 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 652         if (bus->slave) {
 653                 addr = bus->slave->addr;
 654                 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true);
 655         }
 656 #endif
 657
 658         bus->state = I2C_IDLE;
 659 }
 660
 661 static inline bool npcm_i2c_is_master(struct npcm_i2c *bus)
 662 {
 663         return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST));
 664 }
 665
 666 static void npcm_i2c_callback(struct npcm_i2c *bus,
 667                               enum i2c_state_ind op_status, u16 info)
 668 {
 669         struct i2c_msg *msgs;
 670         int msgs_num;
 671
 672         msgs = bus->msgs;
 673         msgs_num = bus->msgs_num;
 674         /*
 675          * check that transaction was not timed-out, and msgs still
 676          * holds a valid value.
 677          */
 678         if (!msgs)
 679                 return;
 680
 681         if (completion_done(&bus->cmd_complete))
 682                 return;
 683
 684         switch (op_status) {
 685         case I2C_MASTER_DONE_IND:
 686                 bus->cmd_err = bus->msgs_num;
 687                 fallthrough;
 688         case I2C_BLOCK_BYTES_ERR_IND:
 689                 /* Master tx finished and all transmit bytes were sent */
 690                 if (bus->msgs) {
 691                         if (msgs[0].flags & I2C_M_RD)
 692                                 msgs[0].len = info;
 693                         else if (msgs_num == 2 &&
 694                                  msgs[1].flags & I2C_M_RD)
 695                                 msgs[1].len = info;
 696                 }
 697                 if (completion_done(&bus->cmd_complete) == false)
 698                         complete(&bus->cmd_complete);
 699         break;
 700
 701         case I2C_NACK_IND:
 702                 /* MASTER transmit got a NACK before tx all bytes */
 703                 bus->cmd_err = -ENXIO;
 704                 if (bus->master_or_slave == I2C_MASTER)
 705                         complete(&bus->cmd_complete);
 706
 707                 break;
 708         case I2C_BUS_ERR_IND:
 709                 /* Bus error */
 710                 bus->cmd_err = -EAGAIN;
 711                 if (bus->master_or_slave == I2C_MASTER)
 712                         complete(&bus->cmd_complete);
 713
 714                 break;
 715         case I2C_WAKE_UP_IND:
 716                 /* I2C wake up */
 717                 break;
 718         default:
 719                 break;
 720         }
 721
 722         bus->operation = I2C_NO_OPER;
 723 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 724         if (bus->slave)
 725                 bus->master_or_slave = I2C_SLAVE;
 726 #endif
 727 }
 728
 729 static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus)
 730 {
 731         if (bus->operation == I2C_WRITE_OPER)
 732                 return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
 733                                  ioread8(bus->reg + NPCM_I2CTXF_STS));
 734         if (bus->operation == I2C_READ_OPER)
 735                 return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES,
 736                                  ioread8(bus->reg + NPCM_I2CRXF_STS));
 737         return 0;
 738 }
 739
 740 static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes)
 741 {
 742         u8 size_free_fifo;
 743
 744         /*
 745          * Fill the FIFO, while the FIFO is not full and there are more bytes
 746          * to write
 747          */
 748         size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
 749         while (max_bytes-- && size_free_fifo) {
 750                 if (bus->wr_ind < bus->wr_size)
 751                         npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
 752                 else
 753                         npcm_i2c_wr_byte(bus, 0xFF);
 754                 size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus);
 755         }
 756 }
 757
 758 /*
 759  * npcm_i2c_set_fifo:
 760  * configure the FIFO before using it. If nread is -1 RX FIFO will not be
 761  * configured. same for nwrite
 762  */
 763 static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite)
 764 {
 765         u8 rxf_ctl = 0;
 766
 767         if (!bus->fifo_use)
 768                 return;
 769         npcm_i2c_select_bank(bus, I2C_BANK_1);
 770         npcm_i2c_clear_tx_fifo(bus);
 771         npcm_i2c_clear_rx_fifo(bus);
 772
 773         /* configure RX FIFO */
 774         if (nread > 0) {
 775                 rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE);
 776
 777                 /* set LAST bit. if LAST is set next FIFO packet is nacked */
 778                 if (nread <= I2C_HW_FIFO_SIZE)
 779                         rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC;
 780
 781                 /*
 782                  * if we are about to read the first byte in blk rd mode,
 783                  * don't NACK it. If slave returns zero size HW can't NACK
 784                  * it immediately, it will read extra byte and then NACK.
 785                  */
 786                 if (bus->rd_ind == 0 && bus->read_block_use) {
 787                         /* set fifo to read one byte, no last: */
 788                         rxf_ctl = 1;
 789                 }
 790
 791                 /* set fifo size: */
 792                 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL);
 793         }
 794
 795         /* configure TX FIFO */
 796         if (nwrite > 0) {
 797                 if (nwrite > I2C_HW_FIFO_SIZE)
 798                         /* data to send is more then FIFO size. */
 799                         iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL);
 800                 else
 801                         iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL);
 802
 803                 npcm_i2c_clear_tx_fifo(bus);
 804         }
 805 }
 806
 807 static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo)
 808 {
 809         u8 data;
 810
 811         while (bytes_in_fifo--) {
 812                 data = npcm_i2c_rd_byte(bus);
 813                 if (bus->rd_ind < bus->rd_size)
 814                         bus->rd_buf[bus->rd_ind++] = data;
 815         }
 816 }
 817
 818 static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus)
 819 {
 820         u8 val;
 821
 822         /* Clear NEGACK, STASTR and BER bits */
 823         val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR;
 824         iowrite8(val, bus->reg + NPCM_I2CST);
 825 }
 826
 827 static void npcm_i2c_master_abort(struct npcm_i2c *bus)
 828 {
 829         /* Only current master is allowed to issue a stop condition */
 830         if (!npcm_i2c_is_master(bus))
 831                 return;
 832
 833         npcm_i2c_eob_int(bus, true);
 834         npcm_i2c_master_stop(bus);
 835         npcm_i2c_clear_master_status(bus);
 836 }
 837
 838 #if IS_ENABLED(CONFIG_I2C_SLAVE)
 839 static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type)
 840 {
 841         u8 slave_add;
 842
 843         /* select bank 0 for address 3 to 10 */
 844         if (addr_type > I2C_SLAVE_ADDR2)
 845                 npcm_i2c_select_bank(bus, I2C_BANK_0);
 846
 847         slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]);
 848
 849         if (addr_type > I2C_SLAVE_ADDR2)
 850                 npcm_i2c_select_bank(bus, I2C_BANK_1);
 851
 852         return slave_add;
 853 }
 854
 855 static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add)
 856 {
 857         int i;
 858
 859         /* Set the enable bit */
 860         slave_add |= 0x80;
 861         npcm_i2c_select_bank(bus, I2C_BANK_0);
 862         for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR; i++) {
 863                 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add)
 864                         iowrite8(0, bus->reg + npcm_i2caddr[i]);
 865         }
 866         npcm_i2c_select_bank(bus, I2C_BANK_1);
 867         return 0;
 868 }
 869
 870 static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes)
 871 {
 872         /*
 873          * Fill the FIFO, while the FIFO is not full and there are more bytes
 874          * to write
 875          */
 876         npcm_i2c_clear_fifo_int(bus);
 877         npcm_i2c_clear_tx_fifo(bus);
 878         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 879         while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) {
 880                 if (bus->slv_wr_size <= 0)
 881                         break;
 882                 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
 883                 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]);
 884                 bus->slv_wr_ind++;
 885                 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE;
 886                 bus->slv_wr_size--;
 887         }
 888 }
 889
 890 static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo)
 891 {
 892         u8 data;
 893
 894         if (!bus->slave)
 895                 return;
 896
 897         while (bytes_in_fifo--) {
 898                 data = npcm_i2c_rd_byte(bus);
 899
 900                 bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE;
 901                 bus->slv_rd_buf[bus->slv_rd_ind] = data;
 902                 bus->slv_rd_ind++;
 903
 904                 /* 1st byte is length in block protocol: */
 905                 if (bus->slv_rd_ind == 1 && bus->read_block_use)
 906                         bus->slv_rd_size = data + bus->PEC_use + 1;
 907         }
 908 }
 909
 910 static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus)
 911 {
 912         int i;
 913         u8 value;
 914         int ind;
 915         int ret = bus->slv_wr_ind;
 916
 917         /* fill a cyclic buffer */
 918         for (i = 0; i < I2C_HW_FIFO_SIZE; i++) {
 919                 if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
 920                         break;
 921                 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value);
 922                 ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE;
 923                 bus->slv_wr_buf[ind] = value;
 924                 bus->slv_wr_size++;
 925                 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value);
 926         }
 927         return I2C_HW_FIFO_SIZE - ret;
 928 }
 929
 930 static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus)
 931 {
 932         int i;
 933
 934         for (i = 0; i < bus->slv_rd_ind; i++)
 935                 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED,
 936                                 &bus->slv_rd_buf[i]);
 937         /*
 938          * once we send bytes up, need to reset the counter of the wr buf
 939          * got data from master (new offset in device), ignore wr fifo:
 940          */
 941         if (bus->slv_rd_ind) {
 942                 bus->slv_wr_size = 0;
 943                 bus->slv_wr_ind = 0;
 944         }
 945
 946         bus->slv_rd_ind = 0;
 947         bus->slv_rd_size = bus->adap.quirks->max_read_len;
 948
 949         npcm_i2c_clear_fifo_int(bus);
 950         npcm_i2c_clear_rx_fifo(bus);
 951 }
 952
 953 static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread,
 954                                    u8 *read_data)
 955 {
 956         bus->state = I2C_OPER_STARTED;
 957         bus->operation = I2C_READ_OPER;
 958         bus->slv_rd_size = nread;
 959         bus->slv_rd_ind = 0;
 960
 961         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
 962         iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
 963         npcm_i2c_clear_tx_fifo(bus);
 964         npcm_i2c_clear_rx_fifo(bus);
 965 }
 966
 967 static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite,
 968                                 u8 *write_data)
 969 {
 970         if (nwrite == 0)
 971                 return;
 972
 973         bus->state = I2C_OPER_STARTED;
 974         bus->operation = I2C_WRITE_OPER;
 975
 976         /* get the next buffer */
 977         npcm_i2c_slave_get_wr_buf(bus);
 978         npcm_i2c_write_fifo_slave(bus, nwrite);
 979 }
 980
 981 /*
 982  * npcm_i2c_slave_wr_buf_sync:
 983  * currently slave IF only supports single byte operations.
 984  * in order to utilize the npcm HW FIFO, the driver will ask for 16 bytes
 985  * at a time, pack them in buffer, and then transmit them all together
 986  * to the FIFO and onward to the bus.
 987  * NACK on read will be once reached to bus->adap->quirks->max_read_len.
 988  * sending a NACK wherever the backend requests for it is not supported.
 989  * the next two functions allow reading to local buffer before writing it all
 990  * to the HW FIFO.
 991  */
 992 static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus)
 993 {
 994         int left_in_fifo;
 995
 996         left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES,
 997                                  ioread8(bus->reg + NPCM_I2CTXF_STS));
 998
 999         /* fifo already full: */
1000         if (left_in_fifo >= I2C_HW_FIFO_SIZE ||
1001             bus->slv_wr_size >= I2C_HW_FIFO_SIZE)
1002                 return;
1003
1004         /* update the wr fifo index back to the untransmitted bytes: */
1005         bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo;
1006         bus->slv_wr_size = bus->slv_wr_size + left_in_fifo;
1007
1008         if (bus->slv_wr_ind < 0)
1009                 bus->slv_wr_ind += I2C_HW_FIFO_SIZE;
1010 }
1011
1012 static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus)
1013 {
1014         if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) {
1015                 /*
1016                  * Slave got an address match with direction bit 1 so it should
1017                  * transmit data. Write till the master will NACK
1018                  */
1019                 bus->operation = I2C_WRITE_OPER;
1020                 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len,
1021                                     bus->slv_wr_buf);
1022         } else {
1023                 /*
1024                  * Slave got an address match with direction bit 0 so it should
1025                  * receive data.
1026                  * this module does not support saying no to bytes.
1027                  * it will always ACK.
1028                  */
1029                 bus->operation = I2C_READ_OPER;
1030                 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1031                 bus->stop_ind = I2C_SLAVE_RCV_IND;
1032                 npcm_i2c_slave_send_rd_buf(bus);
1033                 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len,
1034                                        bus->slv_rd_buf);
1035         }
1036 }
1037
1038 static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus)
1039 {
1040         u8 val;
1041         irqreturn_t ret = IRQ_NONE;
1042         u8 i2cst = ioread8(bus->reg + NPCM_I2CST);
1043
1044         /* Slave: A NACK has occurred */
1045         if (NPCM_I2CST_NEGACK & i2cst) {
1046                 bus->stop_ind = I2C_NACK_IND;
1047                 npcm_i2c_slave_wr_buf_sync(bus);
1048                 if (bus->fifo_use)
1049                         /* clear the FIFO */
1050                         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1051                                  bus->reg + NPCM_I2CFIF_CTS);
1052
1053                 /* In slave write, NACK is OK, otherwise it is a problem */
1054                 bus->stop_ind = I2C_NO_STATUS_IND;
1055                 bus->operation = I2C_NO_OPER;
1056                 bus->own_slave_addr = 0xFF;
1057
1058                 /*
1059                  * Slave has to wait for STOP to decide this is the end
1060                  * of the transaction. tx is not yet considered as done
1061                  */
1062                 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST);
1063
1064                 ret = IRQ_HANDLED;
1065         }
1066
1067         /* Slave mode: a Bus Error (BER) has been identified */
1068         if (NPCM_I2CST_BER & i2cst) {
1069                 /*
1070                  * Check whether bus arbitration or Start or Stop during data
1071                  * xfer bus arbitration problem should not result in recovery
1072                  */
1073                 bus->stop_ind = I2C_BUS_ERR_IND;
1074
1075                 /* wait for bus busy before clear fifo */
1076                 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1077
1078                 bus->state = I2C_IDLE;
1079
1080                 /*
1081                  * in BER case we might get 2 interrupts: one for slave one for
1082                  * master ( for a channel which is master\slave switching)
1083                  */
1084                 if (completion_done(&bus->cmd_complete) == false) {
1085                         bus->cmd_err = -EIO;
1086                         complete(&bus->cmd_complete);
1087                 }
1088                 bus->own_slave_addr = 0xFF;
1089                 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST);
1090                 ret = IRQ_HANDLED;
1091         }
1092
1093         /* A Slave Stop Condition has been identified */
1094         if (NPCM_I2CST_SLVSTP & i2cst) {
1095                 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus);
1096
1097                 bus->stop_ind = I2C_SLAVE_DONE_IND;
1098
1099                 if (bus->operation == I2C_READ_OPER)
1100                         npcm_i2c_read_fifo_slave(bus, bytes_in_fifo);
1101
1102                 /* if the buffer is empty nothing will be sent */
1103                 npcm_i2c_slave_send_rd_buf(bus);
1104
1105                 /* Slave done transmitting or receiving */
1106                 bus->stop_ind = I2C_NO_STATUS_IND;
1107
1108                 /*
1109                  * Note, just because we got here, it doesn't mean we through
1110                  * away the wr buffer.
1111                  * we keep it until the next received offset.
1112                  */
1113                 bus->operation = I2C_NO_OPER;
1114                 bus->own_slave_addr = 0xFF;
1115                 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0);
1116                 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST);
1117                 if (bus->fifo_use) {
1118                         npcm_i2c_clear_fifo_int(bus);
1119                         npcm_i2c_clear_rx_fifo(bus);
1120                         npcm_i2c_clear_tx_fifo(bus);
1121
1122                         iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO,
1123                                  bus->reg + NPCM_I2CFIF_CTS);
1124                 }
1125                 bus->state = I2C_IDLE;
1126                 ret = IRQ_HANDLED;
1127         }
1128
1129         /* restart condition occurred and Rx-FIFO was not empty */
1130         if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR,
1131                                        ioread8(bus->reg + NPCM_I2CFIF_CTS))) {
1132                 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1133                 bus->master_or_slave = I2C_SLAVE;
1134                 if (bus->operation == I2C_READ_OPER)
1135                         npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus));
1136                 bus->operation = I2C_WRITE_OPER;
1137                 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1138                 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR |
1139                       NPCM_I2CFIF_CTS_RXF_TXE;
1140                 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS);
1141                 npcm_i2c_slave_rd_wr(bus);
1142                 ret = IRQ_HANDLED;
1143         }
1144
1145         /* A Slave Address Match has been identified */
1146         if (NPCM_I2CST_NMATCH & i2cst) {
1147                 u8 info = 0;
1148
1149                 /* Address match automatically implies slave mode */
1150                 bus->master_or_slave = I2C_SLAVE;
1151                 npcm_i2c_clear_fifo_int(bus);
1152                 npcm_i2c_clear_rx_fifo(bus);
1153                 npcm_i2c_clear_tx_fifo(bus);
1154                 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1155                 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL);
1156                 if (NPCM_I2CST_XMIT & i2cst) {
1157                         bus->operation = I2C_WRITE_OPER;
1158                 } else {
1159                         i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED,
1160                                         &info);
1161                         bus->operation = I2C_READ_OPER;
1162                 }
1163                 if (bus->own_slave_addr == 0xFF) {
1164                         /* Check which type of address match */
1165                         val = ioread8(bus->reg + NPCM_I2CCST);
1166                         if (NPCM_I2CCST_MATCH & val) {
1167                                 u16 addr;
1168                                 enum i2c_addr eaddr;
1169                                 u8 i2ccst2;
1170                                 u8 i2ccst3;
1171
1172                                 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3);
1173                                 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2);
1174
1175                                 /*
1176                                  * the i2c module can response to 10 own SA.
1177                                  * check which one was addressed by the master.
1178                                  * respond to the first one.
1179                                  */
1180                                 addr = ((i2ccst3 & 0x07) << 7) |
1181                                         (i2ccst2 & 0x7F);
1182                                 info = ffs(addr);
1183                                 eaddr = (enum i2c_addr)info;
1184                                 addr = npcm_i2c_get_slave_addr(bus, eaddr);
1185                                 addr &= 0x7F;
1186                                 bus->own_slave_addr = addr;
1187                                 if (bus->PEC_mask & BIT(info))
1188                                         bus->PEC_use = true;
1189                                 else
1190                                         bus->PEC_use = false;
1191                         } else {
1192                                 if (NPCM_I2CCST_GCMATCH & val)
1193                                         bus->own_slave_addr = 0;
1194                                 if (NPCM_I2CCST_ARPMATCH & val)
1195                                         bus->own_slave_addr = 0x61;
1196                         }
1197                 } else {
1198                         /*
1199                          *  Slave match can happen in two options:
1200                          *  1. Start, SA, read (slave read without further ado)
1201                          *  2. Start, SA, read, data, restart, SA, read,  ...
1202                          *     (slave read in fragmented mode)
1203                          *  3. Start, SA, write, data, restart, SA, read, ..
1204                          *     (regular write-read mode)
1205                          */
1206                         if ((bus->state == I2C_OPER_STARTED &&
1207                              bus->operation == I2C_READ_OPER &&
1208                              bus->stop_ind == I2C_SLAVE_XMIT_IND) ||
1209                              bus->stop_ind == I2C_SLAVE_RCV_IND) {
1210                                 /* slave tx after slave rx w/o STOP */
1211                                 bus->stop_ind = I2C_SLAVE_RESTART_IND;
1212                         }
1213                 }
1214
1215                 if (NPCM_I2CST_XMIT & i2cst)
1216                         bus->stop_ind = I2C_SLAVE_XMIT_IND;
1217                 else
1218                         bus->stop_ind = I2C_SLAVE_RCV_IND;
1219                 bus->state = I2C_SLAVE_MATCH;
1220                 npcm_i2c_slave_rd_wr(bus);
1221                 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1222                 ret = IRQ_HANDLED;
1223         }
1224
1225         /* Slave SDA status is set - tx or rx */
1226         if ((NPCM_I2CST_SDAST & i2cst) ||
1227             (bus->fifo_use &&
1228             (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1229                 npcm_i2c_slave_rd_wr(bus);
1230                 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST);
1231                 ret = IRQ_HANDLED;
1232         } /* SDAST */
1233
1234         return ret;
1235 }
1236
1237 static int npcm_i2c_reg_slave(struct i2c_client *client)
1238 {
1239         unsigned long lock_flags;
1240         struct npcm_i2c *bus = i2c_get_adapdata(client->adapter);
1241
1242         bus->slave = client;
1243
1244         if (!bus->slave)
1245                 return -EINVAL;
1246
1247         if (client->flags & I2C_CLIENT_TEN)
1248                 return -EAFNOSUPPORT;
1249
1250         spin_lock_irqsave(&bus->lock, lock_flags);
1251
1252         npcm_i2c_init_params(bus);
1253         bus->slv_rd_size = 0;
1254         bus->slv_wr_size = 0;
1255         bus->slv_rd_ind = 0;
1256         bus->slv_wr_ind = 0;
1257         if (client->flags & I2C_CLIENT_PEC)
1258                 bus->PEC_use = true;
1259
1260         dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num,
1261                  client->addr, bus->PEC_use);
1262
1263         npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true);
1264         npcm_i2c_clear_fifo_int(bus);
1265         npcm_i2c_clear_rx_fifo(bus);
1266         npcm_i2c_clear_tx_fifo(bus);
1267         npcm_i2c_slave_int_enable(bus, true);
1268
1269         spin_unlock_irqrestore(&bus->lock, lock_flags);
1270         return 0;
1271 }
1272
1273 static int npcm_i2c_unreg_slave(struct i2c_client *client)
1274 {
1275         struct npcm_i2c *bus = client->adapter->algo_data;
1276         unsigned long lock_flags;
1277
1278         spin_lock_irqsave(&bus->lock, lock_flags);
1279         if (!bus->slave) {
1280                 spin_unlock_irqrestore(&bus->lock, lock_flags);
1281                 return -EINVAL;
1282         }
1283         npcm_i2c_slave_int_enable(bus, false);
1284         npcm_i2c_remove_slave_addr(bus, client->addr);
1285         bus->slave = NULL;
1286         spin_unlock_irqrestore(&bus->lock, lock_flags);
1287         return 0;
1288 }
1289 #endif /* CONFIG_I2C_SLAVE */
1290
1291 static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus)
1292 {
1293         int rcount;
1294         int fifo_bytes;
1295         enum i2c_state_ind ind = I2C_MASTER_DONE_IND;
1296
1297         fifo_bytes = npcm_i2c_fifo_usage(bus);
1298         rcount = bus->rd_size - bus->rd_ind;
1299
1300         /*
1301          * In order not to change the RX_TRH during transaction (we found that
1302          * this might be problematic if it takes too much time to read the FIFO)
1303          * we read the data in the following way. If the number of bytes to
1304          * read == FIFO Size + C (where C < FIFO Size)then first read C bytes
1305          * and in the next int we read rest of the data.
1306          */
1307         if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE)
1308                 fifo_bytes = rcount - I2C_HW_FIFO_SIZE;
1309
1310         if (rcount <= fifo_bytes) {
1311                 /* last bytes are about to be read - end of tx */
1312                 bus->state = I2C_STOP_PENDING;
1313                 bus->stop_ind = ind;
1314                 npcm_i2c_eob_int(bus, true);
1315                 /* Stop should be set before reading last byte. */
1316                 npcm_i2c_master_stop(bus);
1317                 npcm_i2c_read_fifo(bus, fifo_bytes);
1318         } else {
1319                 npcm_i2c_read_fifo(bus, fifo_bytes);
1320                 rcount = bus->rd_size - bus->rd_ind;
1321                 npcm_i2c_set_fifo(bus, rcount, -1);
1322         }
1323 }
1324
1325 static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus)
1326 {
1327         u16 wcount;
1328
1329         if (bus->fifo_use)
1330                 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */
1331
1332         /* Master write operation - last byte handling */
1333         if (bus->wr_ind == bus->wr_size) {
1334                 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0)
1335                         /*
1336                          * No more bytes to send (to add to the FIFO),
1337                          * however the FIFO is not empty yet. It is
1338                          * still in the middle of tx. Currently there's nothing
1339                          * to do except for waiting to the end of the tx
1340                          * We will get an int when the FIFO will get empty.
1341                          */
1342                         return;
1343
1344                 if (bus->rd_size == 0) {
1345                         /* all bytes have been written, in wr only operation */
1346                         npcm_i2c_eob_int(bus, true);
1347                         bus->state = I2C_STOP_PENDING;
1348                         bus->stop_ind = I2C_MASTER_DONE_IND;
1349                         npcm_i2c_master_stop(bus);
1350                         /* Clear SDA Status bit (by writing dummy byte) */
1351                         npcm_i2c_wr_byte(bus, 0xFF);
1352
1353                 } else {
1354                         /* last write-byte written on previous int - restart */
1355                         npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1356                         /* Generate repeated start upon next write to SDA */
1357                         npcm_i2c_master_start(bus);
1358
1359                         /*
1360                          * Receiving one byte only - stall after successful
1361                          * completion of send address byte. If we NACK here, and
1362                          * slave doesn't ACK the address, we might
1363                          * unintentionally NACK the next multi-byte read.
1364                          */
1365                         if (bus->rd_size == 1)
1366                                 npcm_i2c_stall_after_start(bus, true);
1367
1368                         /* Next int will occur on read */
1369                         bus->operation = I2C_READ_OPER;
1370                         /* send the slave address in read direction */
1371                         npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1);
1372                 }
1373         } else {
1374                 /* write next byte not last byte and not slave address */
1375                 if (!bus->fifo_use || bus->wr_size == 1) {
1376                         npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]);
1377                 } else {
1378                         wcount = bus->wr_size - bus->wr_ind;
1379                         npcm_i2c_set_fifo(bus, -1, wcount);
1380                         if (wcount)
1381                                 npcm_i2c_write_to_fifo_master(bus, wcount);
1382                 }
1383         }
1384 }
1385
1386 static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus)
1387 {
1388         u16 block_extra_bytes_size;
1389         u8 data;
1390
1391         /* added bytes to the packet: */
1392         block_extra_bytes_size = bus->read_block_use + bus->PEC_use;
1393
1394         /*
1395          * Perform master read, distinguishing between last byte and the rest of
1396          * the bytes. The last byte should be read when the clock is stopped
1397          */
1398         if (bus->rd_ind == 0) { /* first byte handling: */
1399                 if (bus->read_block_use) {
1400                         /* first byte in block protocol is the size: */
1401                         data = npcm_i2c_rd_byte(bus);
1402                         data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX);
1403                         bus->rd_size = data + block_extra_bytes_size;
1404                         bus->rd_buf[bus->rd_ind++] = data;
1405
1406                         /* clear RX FIFO interrupt status: */
1407                         if (bus->fifo_use) {
1408                                 data = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1409                                 data = data | NPCM_I2CFIF_CTS_RXF_TXE;
1410                                 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS);
1411                         }
1412
1413                         npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1);
1414                         npcm_i2c_stall_after_start(bus, false);
1415                 } else {
1416                         npcm_i2c_clear_tx_fifo(bus);
1417                         npcm_i2c_master_fifo_read(bus);
1418                 }
1419         } else {
1420                 if (bus->rd_size == block_extra_bytes_size &&
1421                     bus->read_block_use) {
1422                         bus->state = I2C_STOP_PENDING;
1423                         bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND;
1424                         bus->cmd_err = -EIO;
1425                         npcm_i2c_eob_int(bus, true);
1426                         npcm_i2c_master_stop(bus);
1427                         npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus));
1428                 } else {
1429                         npcm_i2c_master_fifo_read(bus);
1430                 }
1431         }
1432 }
1433
1434 static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus)
1435 {
1436         iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST);
1437         npcm_i2c_nack(bus);
1438         bus->stop_ind = I2C_BUS_ERR_IND;
1439         npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1440 }
1441
1442 /* A NACK has occurred */
1443 static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus)
1444 {
1445         u8 val;
1446
1447         if (bus->nack_cnt < ULLONG_MAX)
1448                 bus->nack_cnt++;
1449
1450         if (bus->fifo_use) {
1451                 /*
1452                  * if there are still untransmitted bytes in TX FIFO
1453                  * reduce them from wr_ind
1454                  */
1455                 if (bus->operation == I2C_WRITE_OPER)
1456                         bus->wr_ind -= npcm_i2c_fifo_usage(bus);
1457
1458                 /* clear the FIFO */
1459                 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS);
1460         }
1461
1462         /* In master write operation, got unexpected NACK */
1463         bus->stop_ind = I2C_NACK_IND;
1464         /* Only current master is allowed to issue Stop Condition */
1465         if (npcm_i2c_is_master(bus)) {
1466                 /* stopping in the middle */
1467                 npcm_i2c_eob_int(bus, false);
1468                 npcm_i2c_master_stop(bus);
1469
1470                 /*
1471                  * The bus is released from stall only after the SW clears
1472                  * NEGACK bit. Then a Stop condition is sent.
1473                  */
1474                 npcm_i2c_clear_master_status(bus);
1475                 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val,
1476                                           !(val & NPCM_I2CCST_BUSY), 10, 200);
1477         }
1478         bus->state = I2C_IDLE;
1479
1480         /*
1481          * In Master mode, NACK should be cleared only after STOP.
1482          * In such case, the bus is released from stall only after the
1483          * software clears NACK bit. Then a Stop condition is sent.
1484          */
1485         npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind);
1486 }
1487
1488         /* Master mode: a Bus Error has been identified */
1489 static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus)
1490 {
1491         if (bus->ber_cnt < ULLONG_MAX)
1492                 bus->ber_cnt++;
1493         bus->stop_ind = I2C_BUS_ERR_IND;
1494         if (npcm_i2c_is_master(bus)) {
1495                 npcm_i2c_master_abort(bus);
1496         } else {
1497                 npcm_i2c_clear_master_status(bus);
1498
1499                 /* Clear BB (BUS BUSY) bit */
1500                 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1501
1502                 bus->cmd_err = -EAGAIN;
1503                 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus));
1504         }
1505         bus->state = I2C_IDLE;
1506 }
1507
1508         /* EOB: a master End Of Busy (meaning STOP completed) */
1509 static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus)
1510 {
1511         npcm_i2c_eob_int(bus, false);
1512         bus->state = I2C_IDLE;
1513         npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind);
1514 }
1515
1516 /* Address sent and requested stall occurred (Master mode) */
1517 static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus)
1518 {
1519         if (npcm_i2c_is_quick(bus)) {
1520                 bus->state = I2C_STOP_PENDING;
1521                 bus->stop_ind = I2C_MASTER_DONE_IND;
1522                 npcm_i2c_eob_int(bus, true);
1523                 npcm_i2c_master_stop(bus);
1524         } else if ((bus->rd_size == 1) && !bus->read_block_use) {
1525                 /*
1526                  * Receiving one byte only - set NACK after ensuring
1527                  * slave ACKed the address byte.
1528                  */
1529                 npcm_i2c_nack(bus);
1530         }
1531
1532         /* Reset stall-after-address-byte */
1533         npcm_i2c_stall_after_start(bus, false);
1534
1535         /* Clear stall only after setting STOP */
1536         iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST);
1537 }
1538
1539 /* SDA status is set - TX or RX, master */
1540 static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst)
1541 {
1542         u8 fif_cts;
1543
1544         if (!npcm_i2c_is_master(bus))
1545                 return;
1546
1547         if (bus->state == I2C_IDLE) {
1548                 bus->stop_ind = I2C_WAKE_UP_IND;
1549
1550                 if (npcm_i2c_is_quick(bus) || bus->read_block_use)
1551                         /*
1552                          * Need to stall after successful
1553                          * completion of sending address byte
1554                          */
1555                         npcm_i2c_stall_after_start(bus, true);
1556                 else
1557                         npcm_i2c_stall_after_start(bus, false);
1558
1559                 /*
1560                  * Receiving one byte only - stall after successful completion
1561                  * of sending address byte If we NACK here, and slave doesn't
1562                  * ACK the address, we might unintentionally NACK the next
1563                  * multi-byte read
1564                  */
1565                 if (bus->wr_size == 0 && bus->rd_size == 1)
1566                         npcm_i2c_stall_after_start(bus, true);
1567
1568                 /* Initiate I2C master tx */
1569
1570                 /* select bank 1 for FIFO regs */
1571                 npcm_i2c_select_bank(bus, I2C_BANK_1);
1572
1573                 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1574                 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR;
1575
1576                 /* clear FIFO and relevant status bits. */
1577                 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO;
1578                 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1579
1580                 /* re-enable */
1581                 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE;
1582                 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1583
1584                 /*
1585                  * Configure the FIFO threshold:
1586                  * according to the needed # of bytes to read.
1587                  * Note: due to HW limitation can't config the rx fifo before it
1588                  * got and ACK on the restart. LAST bit will not be reset unless
1589                  * RX completed. It will stay set on the next tx.
1590                  */
1591                 if (bus->wr_size)
1592                         npcm_i2c_set_fifo(bus, -1, bus->wr_size);
1593                 else
1594                         npcm_i2c_set_fifo(bus, bus->rd_size, -1);
1595
1596                 bus->state = I2C_OPER_STARTED;
1597
1598                 if (npcm_i2c_is_quick(bus) || bus->wr_size)
1599                         npcm_i2c_wr_byte(bus, bus->dest_addr);
1600                 else
1601                         npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0));
1602         /* SDA interrupt, after start\restart */
1603         } else {
1604                 if (NPCM_I2CST_XMIT & i2cst) {
1605                         bus->operation = I2C_WRITE_OPER;
1606                         npcm_i2c_irq_master_handler_write(bus);
1607                 } else {
1608                         bus->operation = I2C_READ_OPER;
1609                         npcm_i2c_irq_master_handler_read(bus);
1610                 }
1611         }
1612 }
1613
1614 static int npcm_i2c_int_master_handler(struct npcm_i2c *bus)
1615 {
1616         u8 i2cst;
1617         int ret = -EIO;
1618
1619         i2cst = ioread8(bus->reg + NPCM_I2CST);
1620
1621         if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) {
1622                 npcm_i2c_irq_handle_nmatch(bus);
1623                 return 0;
1624         }
1625         /* A NACK has occurred */
1626         if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) {
1627                 npcm_i2c_irq_handle_nack(bus);
1628                 return 0;
1629         }
1630
1631         /* Master mode: a Bus Error has been identified */
1632         if (FIELD_GET(NPCM_I2CST_BER, i2cst)) {
1633                 npcm_i2c_irq_handle_ber(bus);
1634                 return 0;
1635         }
1636
1637         /* EOB: a master End Of Busy (meaning STOP completed) */
1638         if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE,
1639                        ioread8(bus->reg + NPCM_I2CCTL1)) == 1) &&
1640             (FIELD_GET(NPCM_I2CCST3_EO_BUSY,
1641                        ioread8(bus->reg + NPCM_I2CCST3)))) {
1642                 npcm_i2c_irq_handle_eob(bus);
1643                 return 0;
1644         }
1645
1646         /* Address sent and requested stall occurred (Master mode) */
1647         if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) {
1648                 npcm_i2c_irq_handle_stall_after_start(bus);
1649                 ret = 0;
1650         }
1651
1652         /* SDA status is set - TX or RX, master */
1653         if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) ||
1654             (bus->fifo_use &&
1655             (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) {
1656                 npcm_i2c_irq_handle_sda(bus, i2cst);
1657                 ret = 0;
1658         }
1659
1660         return ret;
1661 }
1662
1663 /* recovery using TGCLK functionality of the module */
1664 static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap)
1665 {
1666         u8               val;
1667         u8               fif_cts;
1668         bool             done = false;
1669         int              status = -ENOTRECOVERABLE;
1670         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1671         /* Allow 3 bytes (27 toggles) to be read from the slave: */
1672         int              iter = 27;
1673
1674         if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) {
1675                 dev_dbg(bus->dev, "bus%d recovery skipped, bus not stuck",
1676                         bus->num);
1677                 npcm_i2c_reset(bus);
1678                 return status;
1679         }
1680
1681         npcm_i2c_int_enable(bus, false);
1682         npcm_i2c_disable(bus);
1683         npcm_i2c_enable(bus);
1684         iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
1685         npcm_i2c_clear_tx_fifo(bus);
1686         npcm_i2c_clear_rx_fifo(bus);
1687         iowrite8(0, bus->reg + NPCM_I2CRXF_CTL);
1688         iowrite8(0, bus->reg + NPCM_I2CTXF_CTL);
1689         npcm_i2c_stall_after_start(bus, false);
1690
1691         /* select bank 1 for FIFO regs */
1692         npcm_i2c_select_bank(bus, I2C_BANK_1);
1693
1694         /* clear FIFO and relevant status bits. */
1695         fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
1696         fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
1697         fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
1698         iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS);
1699         npcm_i2c_set_fifo(bus, -1, 0);
1700
1701         /* Repeat the following sequence until SDA is released */
1702         do {
1703                 /* Issue a single SCL toggle */
1704                 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST);
1705                 usleep_range(20, 30);
1706                 /* If SDA line is inactive (high), stop */
1707                 if (npcm_i2c_get_SDA(_adap)) {
1708                         done = true;
1709                         status = 0;
1710                 }
1711         } while (!done && iter--);
1712
1713         /* If SDA line is released: send start-addr-stop, to re-sync. */
1714         if (npcm_i2c_get_SDA(_adap)) {
1715                 /* Send an address byte in write direction: */
1716                 npcm_i2c_wr_byte(bus, bus->dest_addr);
1717                 npcm_i2c_master_start(bus);
1718                 /* Wait until START condition is sent */
1719                 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val,
1720                                             20, 200);
1721                 /* If START condition was sent */
1722                 if (npcm_i2c_is_master(bus) > 0) {
1723                         usleep_range(20, 30);
1724                         npcm_i2c_master_stop(bus);
1725                         usleep_range(200, 500);
1726                 }
1727         }
1728         npcm_i2c_reset(bus);
1729         npcm_i2c_int_enable(bus, true);
1730
1731         if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1))
1732                 status = 0;
1733         else
1734                 status = -ENOTRECOVERABLE;
1735         if (status) {
1736                 if (bus->rec_fail_cnt < ULLONG_MAX)
1737                         bus->rec_fail_cnt++;
1738         } else {
1739                 if (bus->rec_succ_cnt < ULLONG_MAX)
1740                         bus->rec_succ_cnt++;
1741         }
1742         return status;
1743 }
1744
1745 /* recovery using bit banging functionality of the module */
1746 static void npcm_i2c_recovery_init(struct i2c_adapter *_adap)
1747 {
1748         struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap);
1749         struct i2c_bus_recovery_info *rinfo = &bus->rinfo;
1750
1751         rinfo->recover_bus = npcm_i2c_recovery_tgclk;
1752
1753         /*
1754          * npcm i2c HW allows direct reading of SCL and SDA.
1755          * However, it does not support setting SCL and SDA directly.
1756          * The recovery function can toggle SCL when SDA is low (but not set)
1757          * Getter functions used internally, and can be used externally.
1758          */
1759         rinfo->get_scl = npcm_i2c_get_SCL;
1760         rinfo->get_sda = npcm_i2c_get_SDA;
1761         _adap->bus_recovery_info = rinfo;
1762 }
1763
1764 /* SCLFRQ min/max field values */
1765 #define SCLFRQ_MIN  10
1766 #define SCLFRQ_MAX  511
1767 #define clk_coef(freq, mul)     DIV_ROUND_UP((freq) * (mul), 1000000)
1768
1769 /*
1770  * npcm_i2c_init_clk: init HW timing parameters.
1771  * NPCM7XX i2c module timing parameters are dependent on module core clk (APB)
1772  * and bus frequency.
1773  * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are symmetric.
1774  * 400kHz bus requires asymmetric HT and LT. A different equation is recommended
1775  * by the HW designer, given core clock range (equations in comments below).
1776  *
1777  */
1778 static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz)
1779 {
1780         u32  k1 = 0;
1781         u32  k2 = 0;
1782         u8   dbnct = 0;
1783         u32  sclfrq = 0;
1784         u8   hldt = 7;
1785         u8   fast_mode = 0;
1786         u32  src_clk_khz;
1787         u32  bus_freq_khz;
1788
1789         src_clk_khz = bus->apb_clk / 1000;
1790         bus_freq_khz = bus_freq_hz / 1000;
1791         bus->bus_freq = bus_freq_hz;
1792
1793         /* 100KHz and below: */
1794         if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) {
1795                 sclfrq = src_clk_khz / (bus_freq_khz * 4);
1796
1797                 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX)
1798                         return -EDOM;
1799
1800                 if (src_clk_khz >= 40000)
1801                         hldt = 17;
1802                 else if (src_clk_khz >= 12500)
1803                         hldt = 15;
1804                 else
1805                         hldt = 7;
1806         }
1807
1808         /* 400KHz: */
1809         else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) {
1810                 sclfrq = 0;
1811                 fast_mode = I2CCTL3_400K_MODE;
1812
1813                 if (src_clk_khz < 7500)
1814                         /* 400KHZ cannot be supported for core clock < 7.5MHz */
1815                         return -EDOM;
1816
1817                 else if (src_clk_khz >= 50000) {
1818                         k1 = 80;
1819                         k2 = 48;
1820                         hldt = 12;
1821                         dbnct = 7;
1822                 }
1823
1824                 /* Master or Slave with frequency > 25MHz */
1825                 else if (src_clk_khz > 25000) {
1826                         hldt = clk_coef(src_clk_khz, 300) + 7;
1827                         k1 = clk_coef(src_clk_khz, 1600);
1828                         k2 = clk_coef(src_clk_khz, 900);
1829                 }
1830         }
1831
1832         /* 1MHz: */
1833         else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) {
1834                 sclfrq = 0;
1835                 fast_mode = I2CCTL3_400K_MODE;
1836
1837                 /* 1MHZ cannot be supported for core clock < 24 MHz */
1838                 if (src_clk_khz < 24000)
1839                         return -EDOM;
1840
1841                 k1 = clk_coef(src_clk_khz, 620);
1842                 k2 = clk_coef(src_clk_khz, 380);
1843
1844                 /* Core clk > 40 MHz */
1845                 if (src_clk_khz > 40000) {
1846                         /*
1847                          * Set HLDT:
1848                          * SDA hold time:  (HLDT-7) * T(CLK) >= 120
1849                          * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7
1850                          */
1851                         hldt = clk_coef(src_clk_khz, 120) + 7;
1852                 } else {
1853                         hldt = 7;
1854                         dbnct = 2;
1855                 }
1856         }
1857
1858         /* Frequency larger than 1 MHz is not supported */
1859         else
1860                 return -EINVAL;
1861
1862         if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1863                 k1 = round_up(k1, 2);
1864                 k2 = round_up(k2 + 1, 2);
1865                 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX ||
1866                     k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX)
1867                         return -EDOM;
1868         }
1869
1870         /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */
1871         iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F),
1872                  bus->reg + NPCM_I2CCTL2);
1873
1874         /* bits [8:7] are in I2CCTL3 reg */
1875         iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3),
1876                  bus->reg + NPCM_I2CCTL3);
1877
1878         /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */
1879         npcm_i2c_select_bank(bus, I2C_BANK_0);
1880
1881         if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) {
1882                 /*
1883                  * Set SCL Low/High Time:
1884                  * k1 = 2 * SCLLT7-0 -> Low Time  = k1 / 2
1885                  * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2
1886                  */
1887                 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT);
1888                 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT);
1889
1890                 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5);
1891         }
1892
1893         iowrite8(hldt, bus->reg + NPCM_I2CCTL4);
1894
1895         /* Return to Bank 1, and stay there by default: */
1896         npcm_i2c_select_bank(bus, I2C_BANK_1);
1897
1898         return 0;
1899 }
1900
1901 static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode,
1902                                 u32 bus_freq_hz)
1903 {
1904         u8 val;
1905         int ret;
1906
1907         /* Check whether module already enabled or frequency is out of bounds */
1908         if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) ||
1909             bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ)
1910                 return -EINVAL;
1911
1912         npcm_i2c_disable(bus);
1913
1914         /* Configure FIFO mode : */
1915         if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) {
1916                 bus->fifo_use = true;
1917                 npcm_i2c_select_bank(bus, I2C_BANK_0);
1918                 val = ioread8(bus->reg + NPCM_I2CFIF_CTL);
1919                 val |= NPCM_I2CFIF_CTL_FIFO_EN;
1920                 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL);
1921                 npcm_i2c_select_bank(bus, I2C_BANK_1);
1922         } else {
1923                 bus->fifo_use = false;
1924         }
1925
1926         /* Configure I2C module clock frequency */
1927         ret = npcm_i2c_init_clk(bus, bus_freq_hz);
1928         if (ret) {
1929                 dev_err(bus->dev, "npcm_i2c_init_clk failed\n");
1930                 return ret;
1931         }
1932
1933         /* Enable module (before configuring CTL1) */
1934         npcm_i2c_enable(bus);
1935         bus->state = I2C_IDLE;
1936         val = ioread8(bus->reg + NPCM_I2CCTL1);
1937         val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS;
1938         iowrite8(val, bus->reg + NPCM_I2CCTL1);
1939
1940         npcm_i2c_int_enable(bus, true);
1941
1942         npcm_i2c_reset(bus);
1943
1944         return 0;
1945 }
1946
1947 static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev)
1948 {
1949         u32 clk_freq_hz;
1950         int ret;
1951
1952         /* Initialize the internal data structures */
1953         bus->state = I2C_DISABLE;
1954         bus->master_or_slave = I2C_SLAVE;
1955         bus->int_time_stamp = 0;
1956 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1957         bus->slave = NULL;
1958 #endif
1959
1960         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1961                                        &clk_freq_hz);
1962         if (ret) {
1963                 dev_info(&pdev->dev, "Could not read clock-frequency property");
1964                 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
1965         }
1966
1967         ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz);
1968         if (ret) {
1969                 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n");
1970                 return ret;
1971         }
1972
1973         return 0;
1974 }
1975
1976 static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id)
1977 {
1978         struct npcm_i2c *bus = dev_id;
1979
1980         if (npcm_i2c_is_master(bus))
1981                 bus->master_or_slave = I2C_MASTER;
1982
1983         if (bus->master_or_slave == I2C_MASTER) {
1984                 bus->int_time_stamp = jiffies;
1985                 if (!npcm_i2c_int_master_handler(bus))
1986                         return IRQ_HANDLED;
1987         }
1988 #if IS_ENABLED(CONFIG_I2C_SLAVE)
1989         if (bus->slave) {
1990                 bus->master_or_slave = I2C_SLAVE;
1991                 return npcm_i2c_int_slave_handler(bus);
1992         }
1993 #endif
1994         return IRQ_NONE;
1995 }
1996
1997 static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus,
1998                                        u8 slave_addr, u16 nwrite, u16 nread,
1999                                        u8 *write_data, u8 *read_data,
2000                                        bool use_PEC, bool use_read_block)
2001 {
2002         if (bus->state != I2C_IDLE) {
2003                 bus->cmd_err = -EBUSY;
2004                 return false;
2005         }
2006         bus->dest_addr = slave_addr << 1;
2007         bus->wr_buf = write_data;
2008         bus->wr_size = nwrite;
2009         bus->wr_ind = 0;
2010         bus->rd_buf = read_data;
2011         bus->rd_size = nread;
2012         bus->rd_ind = 0;
2013         bus->PEC_use = 0;
2014
2015         /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */
2016         if (nread)
2017                 bus->PEC_use = use_PEC;
2018
2019         bus->read_block_use = use_read_block;
2020         if (nread && !nwrite)
2021                 bus->operation = I2C_READ_OPER;
2022         else
2023                 bus->operation = I2C_WRITE_OPER;
2024         if (bus->fifo_use) {
2025                 u8 i2cfif_cts;
2026
2027                 npcm_i2c_select_bank(bus, I2C_BANK_1);
2028                 /* clear FIFO and relevant status bits. */
2029                 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS);
2030                 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR;
2031                 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO;
2032                 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS);
2033         }
2034
2035         bus->state = I2C_IDLE;
2036         npcm_i2c_stall_after_start(bus, true);
2037         npcm_i2c_master_start(bus);
2038         return true;
2039 }
2040
2041 static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
2042                                 int num)
2043 {
2044         struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap);
2045         struct i2c_msg *msg0, *msg1;
2046         unsigned long time_left, flags;
2047         u16 nwrite, nread;
2048         u8 *write_data, *read_data;
2049         u8 slave_addr;
2050         int timeout;
2051         int ret = 0;
2052         bool read_block = false;
2053         bool read_PEC = false;
2054         u8 bus_busy;
2055         unsigned long timeout_usec;
2056
2057         if (bus->state == I2C_DISABLE) {
2058                 dev_err(bus->dev, "I2C%d module is disabled", bus->num);
2059                 return -EINVAL;
2060         }
2061
2062         msg0 = &msgs[0];
2063         slave_addr = msg0->addr;
2064         if (msg0->flags & I2C_M_RD) { /* read */
2065                 nwrite = 0;
2066                 write_data = NULL;
2067                 read_data = msg0->buf;
2068                 if (msg0->flags & I2C_M_RECV_LEN) {
2069                         nread = 1;
2070                         read_block = true;
2071                         if (msg0->flags & I2C_CLIENT_PEC)
2072                                 read_PEC = true;
2073                 } else {
2074                         nread = msg0->len;
2075                 }
2076         } else { /* write */
2077                 nwrite = msg0->len;
2078                 write_data = msg0->buf;
2079                 nread = 0;
2080                 read_data = NULL;
2081                 if (num == 2) {
2082                         msg1 = &msgs[1];
2083                         read_data = msg1->buf;
2084                         if (msg1->flags & I2C_M_RECV_LEN) {
2085                                 nread = 1;
2086                                 read_block = true;
2087                                 if (msg1->flags & I2C_CLIENT_PEC)
2088                                         read_PEC = true;
2089                         } else {
2090                                 nread = msg1->len;
2091                                 read_block = false;
2092                         }
2093                 }
2094         }
2095
2096         /*
2097          * Adaptive TimeOut: estimated time in usec + 100% margin:
2098          * 2: double the timeout for clock stretching case
2099          * 9: bits per transaction (including the ack/nack)
2100          */
2101         timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite);
2102         timeout = max(msecs_to_jiffies(35), usecs_to_jiffies(timeout_usec));
2103         if (nwrite >= 32 * 1024 || nread >= 32 * 1024) {
2104                 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num);
2105                 return -EINVAL;
2106         }
2107
2108         time_left = jiffies + msecs_to_jiffies(DEFAULT_STALL_COUNT) + 1;
2109         do {
2110                 /*
2111                  * we must clear slave address immediately when the bus is not
2112                  * busy, so we spinlock it, but we don't keep the lock for the
2113                  * entire while since it is too long.
2114                  */
2115                 spin_lock_irqsave(&bus->lock, flags);
2116                 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB;
2117 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2118                 if (!bus_busy && bus->slave)
2119                         iowrite8((bus->slave->addr & 0x7F),
2120                                  bus->reg + NPCM_I2CADDR1);
2121 #endif
2122                 spin_unlock_irqrestore(&bus->lock, flags);
2123
2124         } while (time_is_after_jiffies(time_left) && bus_busy);
2125
2126         if (bus_busy) {
2127                 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST);
2128                 npcm_i2c_reset(bus);
2129                 i2c_recover_bus(adap);
2130                 return -EAGAIN;
2131         }
2132
2133         npcm_i2c_init_params(bus);
2134         bus->dest_addr = slave_addr;
2135         bus->msgs = msgs;
2136         bus->msgs_num = num;
2137         bus->cmd_err = 0;
2138         bus->read_block_use = read_block;
2139
2140         reinit_completion(&bus->cmd_complete);
2141         if (!npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread,
2142                                         write_data, read_data, read_PEC,
2143                                         read_block))
2144                 ret = -EBUSY;
2145
2146         if (ret != -EBUSY) {
2147                 time_left = wait_for_completion_timeout(&bus->cmd_complete,
2148                                                         timeout);
2149
2150                 if (time_left == 0) {
2151                         if (bus->timeout_cnt < ULLONG_MAX)
2152                                 bus->timeout_cnt++;
2153                         if (bus->master_or_slave == I2C_MASTER) {
2154                                 i2c_recover_bus(adap);
2155                                 bus->cmd_err = -EIO;
2156                                 bus->state = I2C_IDLE;
2157                         }
2158                 }
2159         }
2160         ret = bus->cmd_err;
2161
2162         /* if there was BER, check if need to recover the bus: */
2163         if (bus->cmd_err == -EAGAIN)
2164                 ret = i2c_recover_bus(adap);
2165
2166         /*
2167          * After any type of error, check if LAST bit is still set,
2168          * due to a HW issue.
2169          * It cannot be cleared without resetting the module.
2170          */
2171         if (bus->cmd_err &&
2172             (NPCM_I2CRXF_CTL_LAST_PEC & ioread8(bus->reg + NPCM_I2CRXF_CTL)))
2173                 npcm_i2c_reset(bus);
2174
2175 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2176         /* reenable slave if it was enabled */
2177         if (bus->slave)
2178                 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN,
2179                          bus->reg + NPCM_I2CADDR1);
2180 #endif
2181         return bus->cmd_err;
2182 }
2183
2184 static u32 npcm_i2c_functionality(struct i2c_adapter *adap)
2185 {
2186         return I2C_FUNC_I2C |
2187                I2C_FUNC_SMBUS_EMUL |
2188                I2C_FUNC_SMBUS_BLOCK_DATA |
2189                I2C_FUNC_SMBUS_PEC |
2190                I2C_FUNC_SLAVE;
2191 }
2192
2193 static const struct i2c_adapter_quirks npcm_i2c_quirks = {
2194         .max_read_len = 32768,
2195         .max_write_len = 32768,
2196         .flags = I2C_AQ_COMB_WRITE_THEN_READ,
2197 };
2198
2199 static const struct i2c_algorithm npcm_i2c_algo = {
2200         .master_xfer = npcm_i2c_master_xfer,
2201         .functionality = npcm_i2c_functionality,
2202 #if IS_ENABLED(CONFIG_I2C_SLAVE)
2203         .reg_slave      = npcm_i2c_reg_slave,
2204         .unreg_slave    = npcm_i2c_unreg_slave,
2205 #endif
2206 };
2207
2208 /* i2c debugfs directory: used to keep health monitor of i2c devices */
2209 static struct dentry *npcm_i2c_debugfs_dir;
2210
2211 static void npcm_i2c_init_debugfs(struct platform_device *pdev,
2212                                   struct npcm_i2c *bus)
2213 {
2214         struct dentry *d;
2215
2216         if (!npcm_i2c_debugfs_dir)
2217                 return;
2218         d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir);
2219         if (IS_ERR_OR_NULL(d))
2220                 return;
2221         debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt);
2222         debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt);
2223         debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt);
2224         debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt);
2225         debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt);
2226
2227         bus->debugfs = d;
2228 }
2229
2230 static int npcm_i2c_probe_bus(struct platform_device *pdev)
2231 {
2232         struct npcm_i2c *bus;
2233         struct i2c_adapter *adap;
2234         struct clk *i2c_clk;
2235         static struct regmap *gcr_regmap;
2236         static struct regmap *clk_regmap;
2237         int irq;
2238         int ret;
2239
2240         bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
2241         if (!bus)
2242                 return -ENOMEM;
2243
2244         bus->dev = &pdev->dev;
2245
2246         bus->num = of_alias_get_id(pdev->dev.of_node, "i2c");
2247         /* core clk must be acquired to calculate module timing settings */
2248         i2c_clk = devm_clk_get(&pdev->dev, NULL);
2249         if (IS_ERR(i2c_clk))
2250                 return PTR_ERR(i2c_clk);
2251         bus->apb_clk = clk_get_rate(i2c_clk);
2252
2253         gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr");
2254         if (IS_ERR(gcr_regmap))
2255                 return PTR_ERR(gcr_regmap);
2256         regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL);
2257
2258         clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk");
2259         if (IS_ERR(clk_regmap))
2260                 return PTR_ERR(clk_regmap);
2261
2262         bus->reg = devm_platform_ioremap_resource(pdev, 0);
2263         if (IS_ERR(bus->reg))
2264                 return PTR_ERR(bus->reg);
2265
2266         spin_lock_init(&bus->lock);
2267         init_completion(&bus->cmd_complete);
2268
2269         adap = &bus->adap;
2270         adap->owner = THIS_MODULE;
2271         adap->retries = 3;
2272         adap->timeout = HZ;
2273         adap->algo = &npcm_i2c_algo;
2274         adap->quirks = &npcm_i2c_quirks;
2275         adap->algo_data = bus;
2276         adap->dev.parent = &pdev->dev;
2277         adap->dev.of_node = pdev->dev.of_node;
2278         adap->nr = pdev->id;
2279
2280         irq = platform_get_irq(pdev, 0);
2281         if (irq < 0)
2282                 return irq;
2283
2284         ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0,
2285                                dev_name(bus->dev), bus);
2286         if (ret)
2287                 return ret;
2288
2289         ret = __npcm_i2c_init(bus, pdev);
2290         if (ret)
2291                 return ret;
2292
2293         npcm_i2c_recovery_init(adap);
2294
2295         i2c_set_adapdata(adap, bus);
2296
2297         snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d",
2298                  bus->num);
2299         ret = i2c_add_numbered_adapter(&bus->adap);
2300         if (ret)
2301                 return ret;
2302
2303         platform_set_drvdata(pdev, bus);
2304         npcm_i2c_init_debugfs(pdev, bus);
2305         return 0;
2306 }
2307
2308 static int npcm_i2c_remove_bus(struct platform_device *pdev)
2309 {
2310         unsigned long lock_flags;
2311         struct npcm_i2c *bus = platform_get_drvdata(pdev);
2312
2313         debugfs_remove_recursive(bus->debugfs);
2314         spin_lock_irqsave(&bus->lock, lock_flags);
2315         npcm_i2c_disable(bus);
2316         spin_unlock_irqrestore(&bus->lock, lock_flags);
2317         i2c_del_adapter(&bus->adap);
2318         return 0;
2319 }
2320
2321 static const struct of_device_id npcm_i2c_bus_of_table[] = {
2322         { .compatible = "nuvoton,npcm750-i2c", },
2323         {}
2324 };
2325 MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table);
2326
2327 static struct platform_driver npcm_i2c_bus_driver = {
2328         .probe = npcm_i2c_probe_bus,
2329         .remove = npcm_i2c_remove_bus,
2330         .driver = {
2331                 .name = "nuvoton-i2c",
2332                 .of_match_table = npcm_i2c_bus_of_table,
2333         }
2334 };
2335
2336 static int __init npcm_i2c_init(void)
2337 {
2338         npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL);
2339         platform_driver_register(&npcm_i2c_bus_driver);
2340         return 0;
2341 }
2342 module_init(npcm_i2c_init);
2343
2344 static void __exit npcm_i2c_exit(void)
2345 {
2346         platform_driver_unregister(&npcm_i2c_bus_driver);
2347         debugfs_remove_recursive(npcm_i2c_debugfs_dir);
2348 }
2349 module_exit(npcm_i2c_exit);
2350
2351 MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>");
2352 MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>");
2353 MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>");
2354 MODULE_DESCRIPTION("Nuvoton I2C Bus Driver");
2355 MODULE_LICENSE("GPL v2");