drivers/hwtracing/coresight/coresight-stm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
   4  *
   5  * Description: CoreSight System Trace Macrocell driver
   6  *
   7  * Initial implementation by Pratik Patel
   8  * (C) 2014-2015 Pratik Patel <pratikp@codeaurora.org>
   9  *
  10  * Serious refactoring, code cleanup and upgrading to the Coresight upstream
  11  * framework by Mathieu Poirier
  12  * (C) 2015-2016 Mathieu Poirier <mathieu.poirier@linaro.org>
  13  *
  14  * Guaranteed timing and support for various packet type coming from the
  15  * generic STM API by Chunyan Zhang
  16  * (C) 2015-2016 Chunyan Zhang <zhang.chunyan@linaro.org>
  17  */
  18 #include <asm/local.h>
  19 #include <linux/acpi.h>
  20 #include <linux/amba/bus.h>
  21 #include <linux/bitmap.h>
  22 #include <linux/clk.h>
  23 #include <linux/coresight.h>
  24 #include <linux/coresight-stm.h>
  25 #include <linux/err.h>
  26 #include <linux/kernel.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/of_address.h>
  29 #include <linux/perf_event.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/stm.h>
  32
  33 #include "coresight-priv.h"
  34
  35 #define STMDMASTARTR                    0xc04
  36 #define STMDMASTOPR                     0xc08
  37 #define STMDMASTATR                     0xc0c
  38 #define STMDMACTLR                      0xc10
  39 #define STMDMAIDR                       0xcfc
  40 #define STMHEER                         0xd00
  41 #define STMHETER                        0xd20
  42 #define STMHEBSR                        0xd60
  43 #define STMHEMCR                        0xd64
  44 #define STMHEMASTR                      0xdf4
  45 #define STMHEFEAT1R                     0xdf8
  46 #define STMHEIDR                        0xdfc
  47 #define STMSPER                         0xe00
  48 #define STMSPTER                        0xe20
  49 #define STMPRIVMASKR                    0xe40
  50 #define STMSPSCR                        0xe60
  51 #define STMSPMSCR                       0xe64
  52 #define STMSPOVERRIDER                  0xe68
  53 #define STMSPMOVERRIDER                 0xe6c
  54 #define STMSPTRIGCSR                    0xe70
  55 #define STMTCSR                         0xe80
  56 #define STMTSSTIMR                      0xe84
  57 #define STMTSFREQR                      0xe8c
  58 #define STMSYNCR                        0xe90
  59 #define STMAUXCR                        0xe94
  60 #define STMSPFEAT1R                     0xea0
  61 #define STMSPFEAT2R                     0xea4
  62 #define STMSPFEAT3R                     0xea8
  63 #define STMITTRIGGER                    0xee8
  64 #define STMITATBDATA0                   0xeec
  65 #define STMITATBCTR2                    0xef0
  66 #define STMITATBID                      0xef4
  67 #define STMITATBCTR0                    0xef8
  68
  69 #define STM_32_CHANNEL                  32
  70 #define BYTES_PER_CHANNEL               256
  71 #define STM_TRACE_BUF_SIZE              4096
  72 #define STM_SW_MASTER_END               127
  73
  74 /* Register bit definition */
  75 #define STMTCSR_BUSY_BIT                23
  76 /* Reserve the first 10 channels for kernel usage */
  77 #define STM_CHANNEL_OFFSET              0
  78
  79 enum stm_pkt_type {
  80         STM_PKT_TYPE_DATA       = 0x98,
  81         STM_PKT_TYPE_FLAG       = 0xE8,
  82         STM_PKT_TYPE_TRIG       = 0xF8,
  83 };
  84
  85 #define stm_channel_addr(drvdata, ch)   (drvdata->chs.base +    \
  86                                         (ch * BYTES_PER_CHANNEL))
  87 #define stm_channel_off(type, opts)     (type & ~opts)
  88
  89 static int boot_nr_channel;
  90
  91 /*
  92  * Not really modular but using module_param is the easiest way to
  93  * remain consistent with existing use cases for now.
  94  */
  95 module_param_named(
  96         boot_nr_channel, boot_nr_channel, int, S_IRUGO
  97 );
  98
  99 /*
 100  * struct channel_space - central management entity for extended ports
 101  * @base:               memory mapped base address where channels start.
 102  * @phys:               physical base address of channel region.
 103  * @guaraneed:          is the channel delivery guaranteed.
 104  */
 105 struct channel_space {
 106         void __iomem            *base;
 107         phys_addr_t             phys;
 108         unsigned long           *guaranteed;
 109 };
 110
 111 DEFINE_CORESIGHT_DEVLIST(stm_devs, "stm");
 112
 113 /**
 114  * struct stm_drvdata - specifics associated to an STM component
 115  * @base:               memory mapped base address for this component.
 116  * @atclk:              optional clock for the core parts of the STM.
 117  * @csdev:              component vitals needed by the framework.
 118  * @spinlock:           only one at a time pls.
 119  * @chs:                the channels accociated to this STM.
 120  * @stm:                structure associated to the generic STM interface.
 121  * @mode:               this tracer's mode, i.e sysFS, or disabled.
 122  * @traceid:            value of the current ID for this component.
 123  * @write_bytes:        Maximus bytes this STM can write at a time.
 124  * @stmsper:            settings for register STMSPER.
 125  * @stmspscr:           settings for register STMSPSCR.
 126  * @numsp:              the total number of stimulus port support by this STM.
 127  * @stmheer:            settings for register STMHEER.
 128  * @stmheter:           settings for register STMHETER.
 129  * @stmhebsr:           settings for register STMHEBSR.
 130  */
 131 struct stm_drvdata {
 132         void __iomem            *base;
 133         struct clk              *atclk;
 134         struct coresight_device *csdev;
 135         spinlock_t              spinlock;
 136         struct channel_space    chs;
 137         struct stm_data         stm;
 138         local_t                 mode;
 139         u8                      traceid;
 140         u32                     write_bytes;
 141         u32                     stmsper;
 142         u32                     stmspscr;
 143         u32                     numsp;
 144         u32                     stmheer;
 145         u32                     stmheter;
 146         u32                     stmhebsr;
 147 };
 148
 149 static void stm_hwevent_enable_hw(struct stm_drvdata *drvdata)
 150 {
 151         CS_UNLOCK(drvdata->base);
 152
 153         writel_relaxed(drvdata->stmhebsr, drvdata->base + STMHEBSR);
 154         writel_relaxed(drvdata->stmheter, drvdata->base + STMHETER);
 155         writel_relaxed(drvdata->stmheer, drvdata->base + STMHEER);
 156         writel_relaxed(0x01 |   /* Enable HW event tracing */
 157                        0x04,    /* Error detection on event tracing */
 158                        drvdata->base + STMHEMCR);
 159
 160         CS_LOCK(drvdata->base);
 161 }
 162
 163 static void stm_port_enable_hw(struct stm_drvdata *drvdata)
 164 {
 165         CS_UNLOCK(drvdata->base);
 166         /* ATB trigger enable on direct writes to TRIG locations */
 167         writel_relaxed(0x10,
 168                        drvdata->base + STMSPTRIGCSR);
 169         writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 170         writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 171
 172         CS_LOCK(drvdata->base);
 173 }
 174
 175 static void stm_enable_hw(struct stm_drvdata *drvdata)
 176 {
 177         if (drvdata->stmheer)
 178                 stm_hwevent_enable_hw(drvdata);
 179
 180         stm_port_enable_hw(drvdata);
 181
 182         CS_UNLOCK(drvdata->base);
 183
 184         /* 4096 byte between synchronisation packets */
 185         writel_relaxed(0xFFF, drvdata->base + STMSYNCR);
 186         writel_relaxed((drvdata->traceid << 16 | /* trace id */
 187                         0x02 |                   /* timestamp enable */
 188                         0x01),                   /* global STM enable */
 189                         drvdata->base + STMTCSR);
 190
 191         CS_LOCK(drvdata->base);
 192 }
 193
 194 static int stm_enable(struct coresight_device *csdev,
 195                       struct perf_event *event, u32 mode)
 196 {
 197         u32 val;
 198         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 199
 200         if (mode != CS_MODE_SYSFS)
 201                 return -EINVAL;
 202
 203         val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
 204
 205         /* Someone is already using the tracer */
 206         if (val)
 207                 return -EBUSY;
 208
 209         pm_runtime_get_sync(csdev->dev.parent);
 210
 211         spin_lock(&drvdata->spinlock);
 212         stm_enable_hw(drvdata);
 213         spin_unlock(&drvdata->spinlock);
 214
 215         dev_dbg(&csdev->dev, "STM tracing enabled\n");
 216         return 0;
 217 }
 218
 219 static void stm_hwevent_disable_hw(struct stm_drvdata *drvdata)
 220 {
 221         CS_UNLOCK(drvdata->base);
 222
 223         writel_relaxed(0x0, drvdata->base + STMHEMCR);
 224         writel_relaxed(0x0, drvdata->base + STMHEER);
 225         writel_relaxed(0x0, drvdata->base + STMHETER);
 226
 227         CS_LOCK(drvdata->base);
 228 }
 229
 230 static void stm_port_disable_hw(struct stm_drvdata *drvdata)
 231 {
 232         CS_UNLOCK(drvdata->base);
 233
 234         writel_relaxed(0x0, drvdata->base + STMSPER);
 235         writel_relaxed(0x0, drvdata->base + STMSPTRIGCSR);
 236
 237         CS_LOCK(drvdata->base);
 238 }
 239
 240 static void stm_disable_hw(struct stm_drvdata *drvdata)
 241 {
 242         u32 val;
 243
 244         CS_UNLOCK(drvdata->base);
 245
 246         val = readl_relaxed(drvdata->base + STMTCSR);
 247         val &= ~0x1; /* clear global STM enable [0] */
 248         writel_relaxed(val, drvdata->base + STMTCSR);
 249
 250         CS_LOCK(drvdata->base);
 251
 252         stm_port_disable_hw(drvdata);
 253         if (drvdata->stmheer)
 254                 stm_hwevent_disable_hw(drvdata);
 255 }
 256
 257 static void stm_disable(struct coresight_device *csdev,
 258                         struct perf_event *event)
 259 {
 260         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 261         struct csdev_access *csa = &csdev->access;
 262
 263         /*
 264          * For as long as the tracer isn't disabled another entity can't
 265          * change its status.  As such we can read the status here without
 266          * fearing it will change under us.
 267          */
 268         if (local_read(&drvdata->mode) == CS_MODE_SYSFS) {
 269                 spin_lock(&drvdata->spinlock);
 270                 stm_disable_hw(drvdata);
 271                 spin_unlock(&drvdata->spinlock);
 272
 273                 /* Wait until the engine has completely stopped */
 274                 coresight_timeout(csa, STMTCSR, STMTCSR_BUSY_BIT, 0);
 275
 276                 pm_runtime_put(csdev->dev.parent);
 277
 278                 local_set(&drvdata->mode, CS_MODE_DISABLED);
 279                 dev_dbg(&csdev->dev, "STM tracing disabled\n");
 280         }
 281 }
 282
 283 static int stm_trace_id(struct coresight_device *csdev)
 284 {
 285         struct stm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 286
 287         return drvdata->traceid;
 288 }
 289
 290 static const struct coresight_ops_source stm_source_ops = {
 291         .trace_id       = stm_trace_id,
 292         .enable         = stm_enable,
 293         .disable        = stm_disable,
 294 };
 295
 296 static const struct coresight_ops stm_cs_ops = {
 297         .source_ops     = &stm_source_ops,
 298 };
 299
 300 static inline bool stm_addr_unaligned(const void *addr, u8 write_bytes)
 301 {
 302         return ((unsigned long)addr & (write_bytes - 1));
 303 }
 304
 305 static void stm_send(void __iomem *addr, const void *data,
 306                      u32 size, u8 write_bytes)
 307 {
 308         u8 paload[8];
 309
 310         if (stm_addr_unaligned(data, write_bytes)) {
 311                 memcpy(paload, data, size);
 312                 data = paload;
 313         }
 314
 315         /* now we are 64bit/32bit aligned */
 316         switch (size) {
 317 #ifdef CONFIG_64BIT
 318         case 8:
 319                 writeq_relaxed(*(u64 *)data, addr);
 320                 break;
 321 #endif
 322         case 4:
 323                 writel_relaxed(*(u32 *)data, addr);
 324                 break;
 325         case 2:
 326                 writew_relaxed(*(u16 *)data, addr);
 327                 break;
 328         case 1:
 329                 writeb_relaxed(*(u8 *)data, addr);
 330                 break;
 331         default:
 332                 break;
 333         }
 334 }
 335
 336 static int stm_generic_link(struct stm_data *stm_data,
 337                             unsigned int master,  unsigned int channel)
 338 {
 339         struct stm_drvdata *drvdata = container_of(stm_data,
 340                                                    struct stm_drvdata, stm);
 341         if (!drvdata || !drvdata->csdev)
 342                 return -EINVAL;
 343
 344         return coresight_enable(drvdata->csdev);
 345 }
 346
 347 static void stm_generic_unlink(struct stm_data *stm_data,
 348                                unsigned int master,  unsigned int channel)
 349 {
 350         struct stm_drvdata *drvdata = container_of(stm_data,
 351                                                    struct stm_drvdata, stm);
 352         if (!drvdata || !drvdata->csdev)
 353                 return;
 354
 355         coresight_disable(drvdata->csdev);
 356 }
 357
 358 static phys_addr_t
 359 stm_mmio_addr(struct stm_data *stm_data, unsigned int master,
 360               unsigned int channel, unsigned int nr_chans)
 361 {
 362         struct stm_drvdata *drvdata = container_of(stm_data,
 363                                                    struct stm_drvdata, stm);
 364         phys_addr_t addr;
 365
 366         addr = drvdata->chs.phys + channel * BYTES_PER_CHANNEL;
 367
 368         if (offset_in_page(addr) ||
 369             offset_in_page(nr_chans * BYTES_PER_CHANNEL))
 370                 return 0;
 371
 372         return addr;
 373 }
 374
 375 static long stm_generic_set_options(struct stm_data *stm_data,
 376                                     unsigned int master,
 377                                     unsigned int channel,
 378                                     unsigned int nr_chans,
 379                                     unsigned long options)
 380 {
 381         struct stm_drvdata *drvdata = container_of(stm_data,
 382                                                    struct stm_drvdata, stm);
 383         if (!(drvdata && local_read(&drvdata->mode)))
 384                 return -EINVAL;
 385
 386         if (channel >= drvdata->numsp)
 387                 return -EINVAL;
 388
 389         switch (options) {
 390         case STM_OPTION_GUARANTEED:
 391                 set_bit(channel, drvdata->chs.guaranteed);
 392                 break;
 393
 394         case STM_OPTION_INVARIANT:
 395                 clear_bit(channel, drvdata->chs.guaranteed);
 396                 break;
 397
 398         default:
 399                 return -EINVAL;
 400         }
 401
 402         return 0;
 403 }
 404
 405 static ssize_t notrace stm_generic_packet(struct stm_data *stm_data,
 406                                   unsigned int master,
 407                                   unsigned int channel,
 408                                   unsigned int packet,
 409                                   unsigned int flags,
 410                                   unsigned int size,
 411                                   const unsigned char *payload)
 412 {
 413         void __iomem *ch_addr;
 414         struct stm_drvdata *drvdata = container_of(stm_data,
 415                                                    struct stm_drvdata, stm);
 416         unsigned int stm_flags;
 417
 418         if (!(drvdata && local_read(&drvdata->mode)))
 419                 return -EACCES;
 420
 421         if (channel >= drvdata->numsp)
 422                 return -EINVAL;
 423
 424         ch_addr = stm_channel_addr(drvdata, channel);
 425
 426         stm_flags = (flags & STP_PACKET_TIMESTAMPED) ?
 427                         STM_FLAG_TIMESTAMPED : 0;
 428         stm_flags |= test_bit(channel, drvdata->chs.guaranteed) ?
 429                            STM_FLAG_GUARANTEED : 0;
 430
 431         if (size > drvdata->write_bytes)
 432                 size = drvdata->write_bytes;
 433         else
 434                 size = rounddown_pow_of_two(size);
 435
 436         switch (packet) {
 437         case STP_PACKET_FLAG:
 438                 ch_addr += stm_channel_off(STM_PKT_TYPE_FLAG, stm_flags);
 439
 440                 /*
 441                  * The generic STM core sets a size of '0' on flag packets.
 442                  * As such send a flag packet of size '1' and tell the
 443                  * core we did so.
 444                  */
 445                 stm_send(ch_addr, payload, 1, drvdata->write_bytes);
 446                 size = 1;
 447                 break;
 448
 449         case STP_PACKET_DATA:
 450                 stm_flags |= (flags & STP_PACKET_MARKED) ? STM_FLAG_MARKED : 0;
 451                 ch_addr += stm_channel_off(STM_PKT_TYPE_DATA, stm_flags);
 452                 stm_send(ch_addr, payload, size,
 453                                 drvdata->write_bytes);
 454                 break;
 455
 456         default:
 457                 return -ENOTSUPP;
 458         }
 459
 460         return size;
 461 }
 462
 463 static ssize_t hwevent_enable_show(struct device *dev,
 464                                    struct device_attribute *attr, char *buf)
 465 {
 466         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 467         unsigned long val = drvdata->stmheer;
 468
 469         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 470 }
 471
 472 static ssize_t hwevent_enable_store(struct device *dev,
 473                                     struct device_attribute *attr,
 474                                     const char *buf, size_t size)
 475 {
 476         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 477         unsigned long val;
 478         int ret = 0;
 479
 480         ret = kstrtoul(buf, 16, &val);
 481         if (ret)
 482                 return -EINVAL;
 483
 484         drvdata->stmheer = val;
 485         /* HW event enable and trigger go hand in hand */
 486         drvdata->stmheter = val;
 487
 488         return size;
 489 }
 490 static DEVICE_ATTR_RW(hwevent_enable);
 491
 492 static ssize_t hwevent_select_show(struct device *dev,
 493                                    struct device_attribute *attr, char *buf)
 494 {
 495         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 496         unsigned long val = drvdata->stmhebsr;
 497
 498         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 499 }
 500
 501 static ssize_t hwevent_select_store(struct device *dev,
 502                                     struct device_attribute *attr,
 503                                     const char *buf, size_t size)
 504 {
 505         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 506         unsigned long val;
 507         int ret = 0;
 508
 509         ret = kstrtoul(buf, 16, &val);
 510         if (ret)
 511                 return -EINVAL;
 512
 513         drvdata->stmhebsr = val;
 514
 515         return size;
 516 }
 517 static DEVICE_ATTR_RW(hwevent_select);
 518
 519 static ssize_t port_select_show(struct device *dev,
 520                                 struct device_attribute *attr, char *buf)
 521 {
 522         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 523         unsigned long val;
 524
 525         if (!local_read(&drvdata->mode)) {
 526                 val = drvdata->stmspscr;
 527         } else {
 528                 spin_lock(&drvdata->spinlock);
 529                 val = readl_relaxed(drvdata->base + STMSPSCR);
 530                 spin_unlock(&drvdata->spinlock);
 531         }
 532
 533         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 534 }
 535
 536 static ssize_t port_select_store(struct device *dev,
 537                                  struct device_attribute *attr,
 538                                  const char *buf, size_t size)
 539 {
 540         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 541         unsigned long val, stmsper;
 542         int ret = 0;
 543
 544         ret = kstrtoul(buf, 16, &val);
 545         if (ret)
 546                 return ret;
 547
 548         spin_lock(&drvdata->spinlock);
 549         drvdata->stmspscr = val;
 550
 551         if (local_read(&drvdata->mode)) {
 552                 CS_UNLOCK(drvdata->base);
 553                 /* Process as per ARM's TRM recommendation */
 554                 stmsper = readl_relaxed(drvdata->base + STMSPER);
 555                 writel_relaxed(0x0, drvdata->base + STMSPER);
 556                 writel_relaxed(drvdata->stmspscr, drvdata->base + STMSPSCR);
 557                 writel_relaxed(stmsper, drvdata->base + STMSPER);
 558                 CS_LOCK(drvdata->base);
 559         }
 560         spin_unlock(&drvdata->spinlock);
 561
 562         return size;
 563 }
 564 static DEVICE_ATTR_RW(port_select);
 565
 566 static ssize_t port_enable_show(struct device *dev,
 567                                 struct device_attribute *attr, char *buf)
 568 {
 569         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 570         unsigned long val;
 571
 572         if (!local_read(&drvdata->mode)) {
 573                 val = drvdata->stmsper;
 574         } else {
 575                 spin_lock(&drvdata->spinlock);
 576                 val = readl_relaxed(drvdata->base + STMSPER);
 577                 spin_unlock(&drvdata->spinlock);
 578         }
 579
 580         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 581 }
 582
 583 static ssize_t port_enable_store(struct device *dev,
 584                                  struct device_attribute *attr,
 585                                  const char *buf, size_t size)
 586 {
 587         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 588         unsigned long val;
 589         int ret = 0;
 590
 591         ret = kstrtoul(buf, 16, &val);
 592         if (ret)
 593                 return ret;
 594
 595         spin_lock(&drvdata->spinlock);
 596         drvdata->stmsper = val;
 597
 598         if (local_read(&drvdata->mode)) {
 599                 CS_UNLOCK(drvdata->base);
 600                 writel_relaxed(drvdata->stmsper, drvdata->base + STMSPER);
 601                 CS_LOCK(drvdata->base);
 602         }
 603         spin_unlock(&drvdata->spinlock);
 604
 605         return size;
 606 }
 607 static DEVICE_ATTR_RW(port_enable);
 608
 609 static ssize_t traceid_show(struct device *dev,
 610                             struct device_attribute *attr, char *buf)
 611 {
 612         unsigned long val;
 613         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 614
 615         val = drvdata->traceid;
 616         return sprintf(buf, "%#lx\n", val);
 617 }
 618
 619 static ssize_t traceid_store(struct device *dev,
 620                              struct device_attribute *attr,
 621                              const char *buf, size_t size)
 622 {
 623         int ret;
 624         unsigned long val;
 625         struct stm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 626
 627         ret = kstrtoul(buf, 16, &val);
 628         if (ret)
 629                 return ret;
 630
 631         /* traceid field is 7bit wide on STM32 */
 632         drvdata->traceid = val & 0x7f;
 633         return size;
 634 }
 635 static DEVICE_ATTR_RW(traceid);
 636
 637 #define coresight_stm_reg(name, offset) \
 638         coresight_simple_reg32(struct stm_drvdata, name, offset)
 639
 640 coresight_stm_reg(tcsr, STMTCSR);
 641 coresight_stm_reg(tsfreqr, STMTSFREQR);
 642 coresight_stm_reg(syncr, STMSYNCR);
 643 coresight_stm_reg(sper, STMSPER);
 644 coresight_stm_reg(spter, STMSPTER);
 645 coresight_stm_reg(privmaskr, STMPRIVMASKR);
 646 coresight_stm_reg(spscr, STMSPSCR);
 647 coresight_stm_reg(spmscr, STMSPMSCR);
 648 coresight_stm_reg(spfeat1r, STMSPFEAT1R);
 649 coresight_stm_reg(spfeat2r, STMSPFEAT2R);
 650 coresight_stm_reg(spfeat3r, STMSPFEAT3R);
 651 coresight_stm_reg(devid, CORESIGHT_DEVID);
 652
 653 static struct attribute *coresight_stm_attrs[] = {
 654         &dev_attr_hwevent_enable.attr,
 655         &dev_attr_hwevent_select.attr,
 656         &dev_attr_port_enable.attr,
 657         &dev_attr_port_select.attr,
 658         &dev_attr_traceid.attr,
 659         NULL,
 660 };
 661
 662 static struct attribute *coresight_stm_mgmt_attrs[] = {
 663         &dev_attr_tcsr.attr,
 664         &dev_attr_tsfreqr.attr,
 665         &dev_attr_syncr.attr,
 666         &dev_attr_sper.attr,
 667         &dev_attr_spter.attr,
 668         &dev_attr_privmaskr.attr,
 669         &dev_attr_spscr.attr,
 670         &dev_attr_spmscr.attr,
 671         &dev_attr_spfeat1r.attr,
 672         &dev_attr_spfeat2r.attr,
 673         &dev_attr_spfeat3r.attr,
 674         &dev_attr_devid.attr,
 675         NULL,
 676 };
 677
 678 static const struct attribute_group coresight_stm_group = {
 679         .attrs = coresight_stm_attrs,
 680 };
 681
 682 static const struct attribute_group coresight_stm_mgmt_group = {
 683         .attrs = coresight_stm_mgmt_attrs,
 684         .name = "mgmt",
 685 };
 686
 687 static const struct attribute_group *coresight_stm_groups[] = {
 688         &coresight_stm_group,
 689         &coresight_stm_mgmt_group,
 690         NULL,
 691 };
 692
 693 #ifdef CONFIG_OF
 694 static int of_stm_get_stimulus_area(struct device *dev, struct resource *res)
 695 {
 696         const char *name = NULL;
 697         int index = 0, found = 0;
 698         struct device_node *np = dev->of_node;
 699
 700         while (!of_property_read_string_index(np, "reg-names", index, &name)) {
 701                 if (strcmp("stm-stimulus-base", name)) {
 702                         index++;
 703                         continue;
 704                 }
 705
 706                 /* We have a match and @index is where it's at */
 707                 found = 1;
 708                 break;
 709         }
 710
 711         if (!found)
 712                 return -EINVAL;
 713
 714         return of_address_to_resource(np, index, res);
 715 }
 716 #else
 717 static inline int of_stm_get_stimulus_area(struct device *dev,
 718                                            struct resource *res)
 719 {
 720         return -ENOENT;
 721 }
 722 #endif
 723
 724 #ifdef CONFIG_ACPI
 725 static int acpi_stm_get_stimulus_area(struct device *dev, struct resource *res)
 726 {
 727         int rc;
 728         bool found_base = false;
 729         struct resource_entry *rent;
 730         LIST_HEAD(res_list);
 731
 732         struct acpi_device *adev = ACPI_COMPANION(dev);
 733
 734         rc = acpi_dev_get_resources(adev, &res_list, NULL, NULL);
 735         if (rc < 0)
 736                 return rc;
 737
 738         /*
 739          * The stimulus base for STM device must be listed as the second memory
 740          * resource, followed by the programming base address as described in
 741          * "Section 2.3 Resources" in ACPI for CoreSightTM 1.0 Platform Design
 742          * document (DEN0067).
 743          */
 744         rc = -ENOENT;
 745         list_for_each_entry(rent, &res_list, node) {
 746                 if (resource_type(rent->res) != IORESOURCE_MEM)
 747                         continue;
 748                 if (found_base) {
 749                         *res = *rent->res;
 750                         rc = 0;
 751                         break;
 752                 }
 753
 754                 found_base = true;
 755         }
 756
 757         acpi_dev_free_resource_list(&res_list);
 758         return rc;
 759 }
 760 #else
 761 static inline int acpi_stm_get_stimulus_area(struct device *dev,
 762                                              struct resource *res)
 763 {
 764         return -ENOENT;
 765 }
 766 #endif
 767
 768 static int stm_get_stimulus_area(struct device *dev, struct resource *res)
 769 {
 770         struct fwnode_handle *fwnode = dev_fwnode(dev);
 771
 772         if (is_of_node(fwnode))
 773                 return of_stm_get_stimulus_area(dev, res);
 774         else if (is_acpi_node(fwnode))
 775                 return acpi_stm_get_stimulus_area(dev, res);
 776         return -ENOENT;
 777 }
 778
 779 static u32 stm_fundamental_data_size(struct stm_drvdata *drvdata)
 780 {
 781         u32 stmspfeat2r;
 782
 783         if (!IS_ENABLED(CONFIG_64BIT))
 784                 return 4;
 785
 786         stmspfeat2r = readl_relaxed(drvdata->base + STMSPFEAT2R);
 787
 788         /*
 789          * bit[15:12] represents the fundamental data size
 790          * 0 - 32-bit data
 791          * 1 - 64-bit data
 792          */
 793         return BMVAL(stmspfeat2r, 12, 15) ? 8 : 4;
 794 }
 795
 796 static u32 stm_num_stimulus_port(struct stm_drvdata *drvdata)
 797 {
 798         u32 numsp;
 799
 800         numsp = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 801         /*
 802          * NUMPS in STMDEVID is 17 bit long and if equal to 0x0,
 803          * 32 stimulus ports are supported.
 804          */
 805         numsp &= 0x1ffff;
 806         if (!numsp)
 807                 numsp = STM_32_CHANNEL;
 808         return numsp;
 809 }
 810
 811 static void stm_init_default_data(struct stm_drvdata *drvdata)
 812 {
 813         /* Don't use port selection */
 814         drvdata->stmspscr = 0x0;
 815         /*
 816          * Enable all channel regardless of their number.  When port
 817          * selection isn't used (see above) STMSPER applies to all
 818          * 32 channel group available, hence setting all 32 bits to 1
 819          */
 820         drvdata->stmsper = ~0x0;
 821
 822         /*
 823          * The trace ID value for *ETM* tracers start at CPU_ID * 2 + 0x10 and
 824          * anything equal to or higher than 0x70 is reserved.  Since 0x00 is
 825          * also reserved the STM trace ID needs to be higher than 0x00 and
 826          * lowner than 0x10.
 827          */
 828         drvdata->traceid = 0x1;
 829
 830         /* Set invariant transaction timing on all channels */
 831         bitmap_clear(drvdata->chs.guaranteed, 0, drvdata->numsp);
 832 }
 833
 834 static void stm_init_generic_data(struct stm_drvdata *drvdata,
 835                                   const char *name)
 836 {
 837         drvdata->stm.name = name;
 838
 839         /*
 840          * MasterIDs are assigned at HW design phase. As such the core is
 841          * using a single master for interaction with this device.
 842          */
 843         drvdata->stm.sw_start = 1;
 844         drvdata->stm.sw_end = 1;
 845         drvdata->stm.hw_override = true;
 846         drvdata->stm.sw_nchannels = drvdata->numsp;
 847         drvdata->stm.sw_mmiosz = BYTES_PER_CHANNEL;
 848         drvdata->stm.packet = stm_generic_packet;
 849         drvdata->stm.mmio_addr = stm_mmio_addr;
 850         drvdata->stm.link = stm_generic_link;
 851         drvdata->stm.unlink = stm_generic_unlink;
 852         drvdata->stm.set_options = stm_generic_set_options;
 853 }
 854
 855 static int stm_probe(struct amba_device *adev, const struct amba_id *id)
 856 {
 857         int ret;
 858         void __iomem *base;
 859         unsigned long *guaranteed;
 860         struct device *dev = &adev->dev;
 861         struct coresight_platform_data *pdata = NULL;
 862         struct stm_drvdata *drvdata;
 863         struct resource *res = &adev->res;
 864         struct resource ch_res;
 865         size_t bitmap_size;
 866         struct coresight_desc desc = { 0 };
 867
 868         desc.name = coresight_alloc_device_name(&stm_devs, dev);
 869         if (!desc.name)
 870                 return -ENOMEM;
 871
 872         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 873         if (!drvdata)
 874                 return -ENOMEM;
 875
 876         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
 877         if (!IS_ERR(drvdata->atclk)) {
 878                 ret = clk_prepare_enable(drvdata->atclk);
 879                 if (ret)
 880                         return ret;
 881         }
 882         dev_set_drvdata(dev, drvdata);
 883
 884         base = devm_ioremap_resource(dev, res);
 885         if (IS_ERR(base))
 886                 return PTR_ERR(base);
 887         drvdata->base = base;
 888         desc.access = CSDEV_ACCESS_IOMEM(base);
 889
 890         ret = stm_get_stimulus_area(dev, &ch_res);
 891         if (ret)
 892                 return ret;
 893         drvdata->chs.phys = ch_res.start;
 894
 895         base = devm_ioremap_resource(dev, &ch_res);
 896         if (IS_ERR(base))
 897                 return PTR_ERR(base);
 898         drvdata->chs.base = base;
 899
 900         drvdata->write_bytes = stm_fundamental_data_size(drvdata);
 901
 902         if (boot_nr_channel)
 903                 drvdata->numsp = boot_nr_channel;
 904         else
 905                 drvdata->numsp = stm_num_stimulus_port(drvdata);
 906
 907         bitmap_size = BITS_TO_LONGS(drvdata->numsp) * sizeof(long);
 908
 909         guaranteed = devm_kzalloc(dev, bitmap_size, GFP_KERNEL);
 910         if (!guaranteed)
 911                 return -ENOMEM;
 912         drvdata->chs.guaranteed = guaranteed;
 913
 914         spin_lock_init(&drvdata->spinlock);
 915
 916         stm_init_default_data(drvdata);
 917         stm_init_generic_data(drvdata, desc.name);
 918
 919         if (stm_register_device(dev, &drvdata->stm, THIS_MODULE)) {
 920                 dev_info(dev,
 921                          "%s : stm_register_device failed, probing deferred\n",
 922                          desc.name);
 923                 return -EPROBE_DEFER;
 924         }
 925
 926         pdata = coresight_get_platform_data(dev);
 927         if (IS_ERR(pdata)) {
 928                 ret = PTR_ERR(pdata);
 929                 goto stm_unregister;
 930         }
 931         adev->dev.platform_data = pdata;
 932
 933         desc.type = CORESIGHT_DEV_TYPE_SOURCE;
 934         desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE;
 935         desc.ops = &stm_cs_ops;
 936         desc.pdata = pdata;
 937         desc.dev = dev;
 938         desc.groups = coresight_stm_groups;
 939         drvdata->csdev = coresight_register(&desc);
 940         if (IS_ERR(drvdata->csdev)) {
 941                 ret = PTR_ERR(drvdata->csdev);
 942                 goto stm_unregister;
 943         }
 944
 945         pm_runtime_put(&adev->dev);
 946
 947         dev_info(&drvdata->csdev->dev, "%s initialized\n",
 948                  (char *)coresight_get_uci_data(id));
 949         return 0;
 950
 951 stm_unregister:
 952         stm_unregister_device(&drvdata->stm);
 953         return ret;
 954 }
 955
 956 static void stm_remove(struct amba_device *adev)
 957 {
 958         struct stm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
 959
 960         coresight_unregister(drvdata->csdev);
 961
 962         stm_unregister_device(&drvdata->stm);
 963 }
 964
 965 #ifdef CONFIG_PM
 966 static int stm_runtime_suspend(struct device *dev)
 967 {
 968         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 969
 970         if (drvdata && !IS_ERR(drvdata->atclk))
 971                 clk_disable_unprepare(drvdata->atclk);
 972
 973         return 0;
 974 }
 975
 976 static int stm_runtime_resume(struct device *dev)
 977 {
 978         struct stm_drvdata *drvdata = dev_get_drvdata(dev);
 979
 980         if (drvdata && !IS_ERR(drvdata->atclk))
 981                 clk_prepare_enable(drvdata->atclk);
 982
 983         return 0;
 984 }
 985 #endif
 986
 987 static const struct dev_pm_ops stm_dev_pm_ops = {
 988         SET_RUNTIME_PM_OPS(stm_runtime_suspend, stm_runtime_resume, NULL)
 989 };
 990
 991 static const struct amba_id stm_ids[] = {
 992         CS_AMBA_ID_DATA(0x000bb962, "STM32"),
 993         CS_AMBA_ID_DATA(0x000bb963, "STM500"),
 994         { 0, 0},
 995 };
 996
 997 MODULE_DEVICE_TABLE(amba, stm_ids);
 998
 999 static struct amba_driver stm_driver = {
1000         .drv = {
1001                 .name   = "coresight-stm",
1002                 .owner  = THIS_MODULE,
1003                 .pm     = &stm_dev_pm_ops,
1004                 .suppress_bind_attrs = true,
1005         },
1006         .probe          = stm_probe,
1007         .remove         = stm_remove,
1008         .id_table       = stm_ids,
1009 };
1010
1011 module_amba_driver(stm_driver);
1012
1013 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1014 MODULE_DESCRIPTION("Arm CoreSight System Trace Macrocell driver");
1015 MODULE_LICENSE("GPL v2");