1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
5 * Description: CoreSight Program Flow Trace driver
8 #include <linux/kernel.h>
9 #include <linux/moduleparam.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/device.h>
14 #include <linux/err.h>
16 #include <linux/slab.h>
17 #include <linux/delay.h>
18 #include <linux/smp.h>
19 #include <linux/sysfs.h>
20 #include <linux/stat.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/cpu.h>
24 #include <linux/coresight.h>
25 #include <linux/coresight-pmu.h>
26 #include <linux/amba/bus.h>
27 #include <linux/seq_file.h>
28 #include <linux/uaccess.h>
29 #include <linux/clk.h>
30 #include <linux/perf_event.h>
31 #include <asm/sections.h>
33 #include "coresight-etm.h"
34 #include "coresight-etm-perf.h"
37 * Not really modular but using module_param is the easiest way to
38 * remain consistent with existing use cases for now.
40 static int boot_enable;
41 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
43 static struct etm_drvdata *etmdrvdata[NR_CPUS];
45 static enum cpuhp_state hp_online;
48 * Memory mapped writes to clear os lock are not supported on some processors
49 * and OS lock must be unlocked before any memory mapped access on such
50 * processors, otherwise memory mapped reads/writes will be invalid.
52 static void etm_os_unlock(struct etm_drvdata *drvdata)
54 /* Writing any value to ETMOSLAR unlocks the trace registers */
55 etm_writel(drvdata, 0x0, ETMOSLAR);
56 drvdata->os_unlock = true;
60 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
64 /* Ensure pending cp14 accesses complete before setting pwrdwn */
67 etmcr = etm_readl(drvdata, ETMCR);
68 etmcr |= ETMCR_PWD_DWN;
69 etm_writel(drvdata, etmcr, ETMCR);
72 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
76 etmcr = etm_readl(drvdata, ETMCR);
77 etmcr &= ~ETMCR_PWD_DWN;
78 etm_writel(drvdata, etmcr, ETMCR);
79 /* Ensure pwrup completes before subsequent cp14 accesses */
84 static void etm_set_pwrup(struct etm_drvdata *drvdata)
88 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
89 etmpdcr |= ETMPDCR_PWD_UP;
90 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
91 /* Ensure pwrup completes before subsequent cp14 accesses */
96 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
100 /* Ensure pending cp14 accesses complete before clearing pwrup */
103 etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
104 etmpdcr &= ~ETMPDCR_PWD_UP;
105 writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
109 * coresight_timeout_etm - loop until a bit has changed to a specific state.
110 * @drvdata: etm's private data structure.
111 * @offset: address of a register, starting from @addr.
112 * @position: the position of the bit of interest.
113 * @value: the value the bit should have.
115 * Basically the same as @coresight_timeout except for the register access
116 * method where we have to account for CP14 configurations.
118 * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
119 * TIMEOUT_US has elapsed, which ever happens first.
122 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
123 int position, int value)
128 for (i = TIMEOUT_US; i > 0; i--) {
129 val = etm_readl(drvdata, offset);
130 /* Waiting on the bit to go from 0 to 1 */
132 if (val & BIT(position))
134 /* Waiting on the bit to go from 1 to 0 */
136 if (!(val & BIT(position)))
141 * Delay is arbitrary - the specification doesn't say how long
142 * we are expected to wait. Extra check required to make sure
143 * we don't wait needlessly on the last iteration.
153 static void etm_set_prog(struct etm_drvdata *drvdata)
157 etmcr = etm_readl(drvdata, ETMCR);
158 etmcr |= ETMCR_ETM_PRG;
159 etm_writel(drvdata, etmcr, ETMCR);
161 * Recommended by spec for cp14 accesses to ensure etmcr write is
162 * complete before polling etmsr
165 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
166 dev_err(&drvdata->csdev->dev,
167 "%s: timeout observed when probing at offset %#x\n",
172 static void etm_clr_prog(struct etm_drvdata *drvdata)
176 etmcr = etm_readl(drvdata, ETMCR);
177 etmcr &= ~ETMCR_ETM_PRG;
178 etm_writel(drvdata, etmcr, ETMCR);
180 * Recommended by spec for cp14 accesses to ensure etmcr write is
181 * complete before polling etmsr
184 if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
185 dev_err(&drvdata->csdev->dev,
186 "%s: timeout observed when probing at offset %#x\n",
191 void etm_set_default(struct etm_config *config)
195 if (WARN_ON_ONCE(!config))
199 * Taken verbatim from the TRM:
201 * To trace all memory:
202 * set bit [24] in register 0x009, the ETMTECR1, to 1
203 * set all other bits in register 0x009, the ETMTECR1, to 0
204 * set all bits in register 0x007, the ETMTECR2, to 0
205 * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
207 config->enable_ctrl1 = BIT(24);
208 config->enable_ctrl2 = 0x0;
209 config->enable_event = ETM_HARD_WIRE_RES_A;
211 config->trigger_event = ETM_DEFAULT_EVENT_VAL;
212 config->enable_event = ETM_HARD_WIRE_RES_A;
214 config->seq_12_event = ETM_DEFAULT_EVENT_VAL;
215 config->seq_21_event = ETM_DEFAULT_EVENT_VAL;
216 config->seq_23_event = ETM_DEFAULT_EVENT_VAL;
217 config->seq_31_event = ETM_DEFAULT_EVENT_VAL;
218 config->seq_32_event = ETM_DEFAULT_EVENT_VAL;
219 config->seq_13_event = ETM_DEFAULT_EVENT_VAL;
220 config->timestamp_event = ETM_DEFAULT_EVENT_VAL;
222 for (i = 0; i < ETM_MAX_CNTR; i++) {
223 config->cntr_rld_val[i] = 0x0;
224 config->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
225 config->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
226 config->cntr_val[i] = 0x0;
229 config->seq_curr_state = 0x0;
230 config->ctxid_idx = 0x0;
231 for (i = 0; i < ETM_MAX_CTXID_CMP; i++)
232 config->ctxid_pid[i] = 0x0;
234 config->ctxid_mask = 0x0;
235 /* Setting default to 1024 as per TRM recommendation */
236 config->sync_freq = 0x400;
239 void etm_config_trace_mode(struct etm_config *config)
245 mode &= (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER);
247 /* excluding kernel AND user space doesn't make sense */
248 if (mode == (ETM_MODE_EXCL_KERN | ETM_MODE_EXCL_USER))
251 /* nothing to do if neither flags are set */
252 if (!(mode & ETM_MODE_EXCL_KERN) && !(mode & ETM_MODE_EXCL_USER))
255 flags = (1 << 0 | /* instruction execute */
256 3 << 3 | /* ARM instruction */
257 0 << 5 | /* No data value comparison */
258 0 << 7 | /* No exact mach */
259 0 << 8); /* Ignore context ID */
261 /* No need to worry about single address comparators. */
262 config->enable_ctrl2 = 0x0;
264 /* Bit 0 is address range comparator 1 */
265 config->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
269 * ETMACTRn[13,11] == Non-secure state comparison control
270 * ETMACTRn[12,10] == Secure state comparison control
272 * b00 == Match in all modes in this state
273 * b01 == Do not match in any more in this state
274 * b10 == Match in all modes excepts user mode in this state
275 * b11 == Match only in user mode in this state
278 /* Tracing in secure mode is not supported at this time */
279 flags |= (0 << 12 | 1 << 10);
281 if (mode & ETM_MODE_EXCL_USER) {
282 /* exclude user, match all modes except user mode */
283 flags |= (1 << 13 | 0 << 11);
285 /* exclude kernel, match only in user mode */
286 flags |= (1 << 13 | 1 << 11);
290 * The ETMEEVR register is already set to "hard wire A". As such
291 * all there is to do is setup an address comparator that spans
292 * the entire address range and configure the state and mode bits.
294 config->addr_val[0] = (u32) 0x0;
295 config->addr_val[1] = (u32) ~0x0;
296 config->addr_acctype[0] = flags;
297 config->addr_acctype[1] = flags;
298 config->addr_type[0] = ETM_ADDR_TYPE_RANGE;
299 config->addr_type[1] = ETM_ADDR_TYPE_RANGE;
302 #define ETM3X_SUPPORTED_OPTIONS (ETMCR_CYC_ACC | \
303 ETMCR_TIMESTAMP_EN | \
306 static int etm_parse_event_config(struct etm_drvdata *drvdata,
307 struct perf_event *event)
309 struct etm_config *config = &drvdata->config;
310 struct perf_event_attr *attr = &event->attr;
315 /* Clear configuration from previous run */
316 memset(config, 0, sizeof(struct etm_config));
318 if (attr->exclude_kernel)
319 config->mode = ETM_MODE_EXCL_KERN;
321 if (attr->exclude_user)
322 config->mode = ETM_MODE_EXCL_USER;
324 /* Always start from the default config */
325 etm_set_default(config);
328 * By default the tracers are configured to trace the whole address
329 * range. Narrow the field only if requested by user space.
332 etm_config_trace_mode(config);
335 * At this time only cycle accurate, return stack and timestamp
336 * options are available.
338 if (attr->config & ~ETM3X_SUPPORTED_OPTIONS)
341 config->ctrl = attr->config;
344 * Possible to have cores with PTM (supports ret stack) and ETM
345 * (never has ret stack) on the same SoC. So if we have a request
346 * for return stack that can't be honoured on this core then
347 * clear the bit - trace will still continue normally
349 if ((config->ctrl & ETMCR_RETURN_STACK) &&
350 !(drvdata->etmccer & ETMCCER_RETSTACK))
351 config->ctrl &= ~ETMCR_RETURN_STACK;
356 static int etm_enable_hw(struct etm_drvdata *drvdata)
360 struct etm_config *config = &drvdata->config;
361 struct coresight_device *csdev = drvdata->csdev;
363 CS_UNLOCK(drvdata->base);
365 rc = coresight_claim_device_unlocked(csdev);
370 etm_clr_pwrdwn(drvdata);
371 /* Apply power to trace registers */
372 etm_set_pwrup(drvdata);
373 /* Make sure all registers are accessible */
374 etm_os_unlock(drvdata);
376 etm_set_prog(drvdata);
378 etmcr = etm_readl(drvdata, ETMCR);
379 /* Clear setting from a previous run if need be */
380 etmcr &= ~ETM3X_SUPPORTED_OPTIONS;
381 etmcr |= drvdata->port_size;
382 etmcr |= ETMCR_ETM_EN;
383 etm_writel(drvdata, config->ctrl | etmcr, ETMCR);
384 etm_writel(drvdata, config->trigger_event, ETMTRIGGER);
385 etm_writel(drvdata, config->startstop_ctrl, ETMTSSCR);
386 etm_writel(drvdata, config->enable_event, ETMTEEVR);
387 etm_writel(drvdata, config->enable_ctrl1, ETMTECR1);
388 etm_writel(drvdata, config->fifofull_level, ETMFFLR);
389 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
390 etm_writel(drvdata, config->addr_val[i], ETMACVRn(i));
391 etm_writel(drvdata, config->addr_acctype[i], ETMACTRn(i));
393 for (i = 0; i < drvdata->nr_cntr; i++) {
394 etm_writel(drvdata, config->cntr_rld_val[i], ETMCNTRLDVRn(i));
395 etm_writel(drvdata, config->cntr_event[i], ETMCNTENRn(i));
396 etm_writel(drvdata, config->cntr_rld_event[i],
398 etm_writel(drvdata, config->cntr_val[i], ETMCNTVRn(i));
400 etm_writel(drvdata, config->seq_12_event, ETMSQ12EVR);
401 etm_writel(drvdata, config->seq_21_event, ETMSQ21EVR);
402 etm_writel(drvdata, config->seq_23_event, ETMSQ23EVR);
403 etm_writel(drvdata, config->seq_31_event, ETMSQ31EVR);
404 etm_writel(drvdata, config->seq_32_event, ETMSQ32EVR);
405 etm_writel(drvdata, config->seq_13_event, ETMSQ13EVR);
406 etm_writel(drvdata, config->seq_curr_state, ETMSQR);
407 for (i = 0; i < drvdata->nr_ext_out; i++)
408 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
409 for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
410 etm_writel(drvdata, config->ctxid_pid[i], ETMCIDCVRn(i));
411 etm_writel(drvdata, config->ctxid_mask, ETMCIDCMR);
412 etm_writel(drvdata, config->sync_freq, ETMSYNCFR);
413 /* No external input selected */
414 etm_writel(drvdata, 0x0, ETMEXTINSELR);
415 etm_writel(drvdata, config->timestamp_event, ETMTSEVR);
416 /* No auxiliary control selected */
417 etm_writel(drvdata, 0x0, ETMAUXCR);
418 etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
419 /* No VMID comparator value selected */
420 etm_writel(drvdata, 0x0, ETMVMIDCVR);
422 etm_clr_prog(drvdata);
425 CS_LOCK(drvdata->base);
427 dev_dbg(&drvdata->csdev->dev, "cpu: %d enable smp call done: %d\n",
432 struct etm_enable_arg {
433 struct etm_drvdata *drvdata;
437 static void etm_enable_hw_smp_call(void *info)
439 struct etm_enable_arg *arg = info;
443 arg->rc = etm_enable_hw(arg->drvdata);
446 static int etm_cpu_id(struct coresight_device *csdev)
448 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
453 int etm_get_trace_id(struct etm_drvdata *drvdata)
457 struct device *etm_dev;
462 etm_dev = drvdata->csdev->dev.parent;
463 if (!local_read(&drvdata->mode))
464 return drvdata->traceid;
466 pm_runtime_get_sync(etm_dev);
468 spin_lock_irqsave(&drvdata->spinlock, flags);
470 CS_UNLOCK(drvdata->base);
471 trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
472 CS_LOCK(drvdata->base);
474 spin_unlock_irqrestore(&drvdata->spinlock, flags);
475 pm_runtime_put(etm_dev);
482 static int etm_trace_id(struct coresight_device *csdev)
484 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
486 return etm_get_trace_id(drvdata);
489 static int etm_enable_perf(struct coresight_device *csdev,
490 struct perf_event *event)
492 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
494 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
497 /* Configure the tracer based on the session's specifics */
498 etm_parse_event_config(drvdata, event);
500 return etm_enable_hw(drvdata);
503 static int etm_enable_sysfs(struct coresight_device *csdev)
505 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
506 struct etm_enable_arg arg = { };
509 spin_lock(&drvdata->spinlock);
512 * Configure the ETM only if the CPU is online. If it isn't online
513 * hw configuration will take place on the local CPU during bring up.
515 if (cpu_online(drvdata->cpu)) {
516 arg.drvdata = drvdata;
517 ret = smp_call_function_single(drvdata->cpu,
518 etm_enable_hw_smp_call, &arg, 1);
522 drvdata->sticky_enable = true;
527 spin_unlock(&drvdata->spinlock);
530 dev_dbg(&csdev->dev, "ETM tracing enabled\n");
534 static int etm_enable(struct coresight_device *csdev,
535 struct perf_event *event, u32 mode)
539 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
541 val = local_cmpxchg(&drvdata->mode, CS_MODE_DISABLED, mode);
543 /* Someone is already using the tracer */
549 ret = etm_enable_sysfs(csdev);
552 ret = etm_enable_perf(csdev, event);
558 /* The tracer didn't start */
560 local_set(&drvdata->mode, CS_MODE_DISABLED);
565 static void etm_disable_hw(void *info)
568 struct etm_drvdata *drvdata = info;
569 struct etm_config *config = &drvdata->config;
570 struct coresight_device *csdev = drvdata->csdev;
572 CS_UNLOCK(drvdata->base);
573 etm_set_prog(drvdata);
575 /* Read back sequencer and counters for post trace analysis */
576 config->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
578 for (i = 0; i < drvdata->nr_cntr; i++)
579 config->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
581 etm_set_pwrdwn(drvdata);
582 coresight_disclaim_device_unlocked(csdev);
584 CS_LOCK(drvdata->base);
586 dev_dbg(&drvdata->csdev->dev,
587 "cpu: %d disable smp call done\n", drvdata->cpu);
590 static void etm_disable_perf(struct coresight_device *csdev)
592 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
594 if (WARN_ON_ONCE(drvdata->cpu != smp_processor_id()))
597 CS_UNLOCK(drvdata->base);
599 /* Setting the prog bit disables tracing immediately */
600 etm_set_prog(drvdata);
603 * There is no way to know when the tracer will be used again so
604 * power down the tracer.
606 etm_set_pwrdwn(drvdata);
607 coresight_disclaim_device_unlocked(csdev);
609 CS_LOCK(drvdata->base);
612 static void etm_disable_sysfs(struct coresight_device *csdev)
614 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
617 * Taking hotplug lock here protects from clocks getting disabled
618 * with tracing being left on (crash scenario) if user disable occurs
619 * after cpu online mask indicates the cpu is offline but before the
620 * DYING hotplug callback is serviced by the ETM driver.
623 spin_lock(&drvdata->spinlock);
626 * Executing etm_disable_hw on the cpu whose ETM is being disabled
627 * ensures that register writes occur when cpu is powered.
629 smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
631 spin_unlock(&drvdata->spinlock);
634 dev_dbg(&csdev->dev, "ETM tracing disabled\n");
637 static void etm_disable(struct coresight_device *csdev,
638 struct perf_event *event)
641 struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
644 * For as long as the tracer isn't disabled another entity can't
645 * change its status. As such we can read the status here without
646 * fearing it will change under us.
648 mode = local_read(&drvdata->mode);
651 case CS_MODE_DISABLED:
654 etm_disable_sysfs(csdev);
657 etm_disable_perf(csdev);
665 local_set(&drvdata->mode, CS_MODE_DISABLED);
668 static const struct coresight_ops_source etm_source_ops = {
669 .cpu_id = etm_cpu_id,
670 .trace_id = etm_trace_id,
671 .enable = etm_enable,
672 .disable = etm_disable,
675 static const struct coresight_ops etm_cs_ops = {
676 .source_ops = &etm_source_ops,
679 static int etm_online_cpu(unsigned int cpu)
681 if (!etmdrvdata[cpu])
684 if (etmdrvdata[cpu]->boot_enable && !etmdrvdata[cpu]->sticky_enable)
685 coresight_enable(etmdrvdata[cpu]->csdev);
689 static int etm_starting_cpu(unsigned int cpu)
691 if (!etmdrvdata[cpu])
694 spin_lock(&etmdrvdata[cpu]->spinlock);
695 if (!etmdrvdata[cpu]->os_unlock) {
696 etm_os_unlock(etmdrvdata[cpu]);
697 etmdrvdata[cpu]->os_unlock = true;
700 if (local_read(&etmdrvdata[cpu]->mode))
701 etm_enable_hw(etmdrvdata[cpu]);
702 spin_unlock(&etmdrvdata[cpu]->spinlock);
706 static int etm_dying_cpu(unsigned int cpu)
708 if (!etmdrvdata[cpu])
711 spin_lock(&etmdrvdata[cpu]->spinlock);
712 if (local_read(&etmdrvdata[cpu]->mode))
713 etm_disable_hw(etmdrvdata[cpu]);
714 spin_unlock(&etmdrvdata[cpu]->spinlock);
718 static bool etm_arch_supported(u8 arch)
735 static void etm_init_arch_data(void *info)
739 struct etm_drvdata *drvdata = info;
741 /* Make sure all registers are accessible */
742 etm_os_unlock(drvdata);
744 CS_UNLOCK(drvdata->base);
746 /* First dummy read */
747 (void)etm_readl(drvdata, ETMPDSR);
748 /* Provide power to ETM: ETMPDCR[3] == 1 */
749 etm_set_pwrup(drvdata);
751 * Clear power down bit since when this bit is set writes to
752 * certain registers might be ignored.
754 etm_clr_pwrdwn(drvdata);
756 * Set prog bit. It will be set from reset but this is included to
759 etm_set_prog(drvdata);
761 /* Find all capabilities */
762 etmidr = etm_readl(drvdata, ETMIDR);
763 drvdata->arch = BMVAL(etmidr, 4, 11);
764 drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
766 drvdata->etmccer = etm_readl(drvdata, ETMCCER);
767 etmccr = etm_readl(drvdata, ETMCCR);
768 drvdata->etmccr = etmccr;
769 drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
770 drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
771 drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
772 drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
773 drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
775 etm_set_pwrdwn(drvdata);
776 etm_clr_pwrup(drvdata);
777 CS_LOCK(drvdata->base);
780 static void etm_init_trace_id(struct etm_drvdata *drvdata)
782 drvdata->traceid = coresight_get_trace_id(drvdata->cpu);
785 static int __init etm_hp_setup(void)
789 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ARM_CORESIGHT_STARTING,
790 "arm/coresight:starting",
791 etm_starting_cpu, etm_dying_cpu);
796 ret = cpuhp_setup_state_nocalls_cpuslocked(CPUHP_AP_ONLINE_DYN,
797 "arm/coresight:online",
798 etm_online_cpu, NULL);
800 /* HP dyn state ID returned in ret on success */
806 /* failed dyn state - remove others */
807 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
812 static void etm_hp_clear(void)
814 cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CORESIGHT_STARTING);
816 cpuhp_remove_state_nocalls(hp_online);
821 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
825 struct device *dev = &adev->dev;
826 struct coresight_platform_data *pdata = NULL;
827 struct etm_drvdata *drvdata;
828 struct resource *res = &adev->res;
829 struct coresight_desc desc = { 0 };
831 drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
835 drvdata->use_cp14 = fwnode_property_read_bool(dev->fwnode, "arm,cp14");
836 dev_set_drvdata(dev, drvdata);
838 /* Validity for the resource is already checked by the AMBA core */
839 base = devm_ioremap_resource(dev, res);
841 return PTR_ERR(base);
843 drvdata->base = base;
844 desc.access = CSDEV_ACCESS_IOMEM(base);
846 spin_lock_init(&drvdata->spinlock);
848 drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
849 if (!IS_ERR(drvdata->atclk)) {
850 ret = clk_prepare_enable(drvdata->atclk);
855 drvdata->cpu = coresight_get_cpu(dev);
856 if (drvdata->cpu < 0)
859 desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
863 if (smp_call_function_single(drvdata->cpu,
864 etm_init_arch_data, drvdata, 1))
865 dev_err(dev, "ETM arch init failed\n");
867 if (etm_arch_supported(drvdata->arch) == false)
870 etm_init_trace_id(drvdata);
871 etm_set_default(&drvdata->config);
873 pdata = coresight_get_platform_data(dev);
875 return PTR_ERR(pdata);
877 adev->dev.platform_data = pdata;
879 desc.type = CORESIGHT_DEV_TYPE_SOURCE;
880 desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
881 desc.ops = &etm_cs_ops;
884 desc.groups = coresight_etm_groups;
885 drvdata->csdev = coresight_register(&desc);
886 if (IS_ERR(drvdata->csdev))
887 return PTR_ERR(drvdata->csdev);
889 ret = etm_perf_symlink(drvdata->csdev, true);
891 coresight_unregister(drvdata->csdev);
895 etmdrvdata[drvdata->cpu] = drvdata;
897 pm_runtime_put(&adev->dev);
898 dev_info(&drvdata->csdev->dev,
899 "%s initialized\n", (char *)coresight_get_uci_data(id));
901 coresight_enable(drvdata->csdev);
902 drvdata->boot_enable = true;
908 static void clear_etmdrvdata(void *info)
910 int cpu = *(int *)info;
912 etmdrvdata[cpu] = NULL;
915 static void etm_remove(struct amba_device *adev)
917 struct etm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
919 etm_perf_symlink(drvdata->csdev, false);
922 * Taking hotplug lock here to avoid racing between etm_remove and
923 * CPU hotplug call backs.
927 * The readers for etmdrvdata[] are CPU hotplug call backs
928 * and PM notification call backs. Change etmdrvdata[i] on
929 * CPU i ensures these call backs has consistent view
930 * inside one call back function.
932 if (smp_call_function_single(drvdata->cpu, clear_etmdrvdata, &drvdata->cpu, 1))
933 etmdrvdata[drvdata->cpu] = NULL;
937 coresight_unregister(drvdata->csdev);
941 static int etm_runtime_suspend(struct device *dev)
943 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
945 if (drvdata && !IS_ERR(drvdata->atclk))
946 clk_disable_unprepare(drvdata->atclk);
951 static int etm_runtime_resume(struct device *dev)
953 struct etm_drvdata *drvdata = dev_get_drvdata(dev);
955 if (drvdata && !IS_ERR(drvdata->atclk))
956 clk_prepare_enable(drvdata->atclk);
962 static const struct dev_pm_ops etm_dev_pm_ops = {
963 SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
966 static const struct amba_id etm_ids[] = {
968 CS_AMBA_ID_DATA(0x000bb921, "ETM 3.3"),
969 /* ETM 3.5 - Cortex-A5 */
970 CS_AMBA_ID_DATA(0x000bb955, "ETM 3.5"),
972 CS_AMBA_ID_DATA(0x000bb956, "ETM 3.5"),
974 CS_AMBA_ID_DATA(0x000bb950, "PTM 1.0"),
976 CS_AMBA_ID_DATA(0x000bb95f, "PTM 1.1"),
977 /* PTM 1.1 Qualcomm */
978 CS_AMBA_ID_DATA(0x000b006f, "PTM 1.1"),
982 MODULE_DEVICE_TABLE(amba, etm_ids);
984 static struct amba_driver etm_driver = {
986 .name = "coresight-etm3x",
987 .owner = THIS_MODULE,
988 .pm = &etm_dev_pm_ops,
989 .suppress_bind_attrs = true,
992 .remove = etm_remove,
996 static int __init etm_init(void)
1000 ret = etm_hp_setup();
1002 /* etm_hp_setup() does its own cleanup - exit on error */
1006 ret = amba_driver_register(&etm_driver);
1008 pr_err("Error registering etm3x driver\n");
1015 static void __exit etm_exit(void)
1017 amba_driver_unregister(&etm_driver);
1021 module_init(etm_init);
1022 module_exit(etm_exit);
1024 MODULE_AUTHOR("Pratik Patel <pratikp@codeaurora.org>");
1025 MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
1026 MODULE_DESCRIPTION("Arm CoreSight Program Flow Trace driver");
1027 MODULE_LICENSE("GPL v2");