2 * Tegra host1x Syncpoints
4 * Copyright (c) 2010-2013, NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include "../syncpt.h"
25 * Write the current syncpoint value back to hw.
27 static void syncpt_restore(struct host1x_syncpt *sp)
29 u32 min = host1x_syncpt_read_min(sp);
30 struct host1x *host = sp->host;
32 host1x_sync_writel(host, min, HOST1X_SYNC_SYNCPT(sp->id));
36 * Write the current waitbase value back to hw.
38 static void syncpt_restore_wait_base(struct host1x_syncpt *sp)
41 struct host1x *host = sp->host;
43 host1x_sync_writel(host, sp->base_val,
44 HOST1X_SYNC_SYNCPT_BASE(sp->id));
49 * Read waitbase value from hw.
51 static void syncpt_read_wait_base(struct host1x_syncpt *sp)
54 struct host1x *host = sp->host;
57 host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(sp->id));
62 * Updates the last value read from hardware.
64 static u32 syncpt_load(struct host1x_syncpt *sp)
66 struct host1x *host = sp->host;
69 /* Loop in case there's a race writing to min_val */
71 old = host1x_syncpt_read_min(sp);
72 live = host1x_sync_readl(host, HOST1X_SYNC_SYNCPT(sp->id));
73 } while ((u32)atomic_cmpxchg(&sp->min_val, old, live) != old);
75 if (!host1x_syncpt_check_max(sp, live))
76 dev_err(host->dev, "%s failed: id=%u, min=%d, max=%d\n",
77 __func__, sp->id, host1x_syncpt_read_min(sp),
78 host1x_syncpt_read_max(sp));
84 * Write a cpu syncpoint increment to the hardware, without touching
87 static int syncpt_cpu_incr(struct host1x_syncpt *sp)
89 struct host1x *host = sp->host;
90 u32 reg_offset = sp->id / 32;
92 if (!host1x_syncpt_client_managed(sp) &&
93 host1x_syncpt_idle(sp))
96 host1x_sync_writel(host, BIT(sp->id % 32),
97 HOST1X_SYNC_SYNCPT_CPU_INCR(reg_offset));
104 * syncpt_assign_to_channel() - Assign syncpoint to channel
108 * On chips with the syncpoint protection feature (Tegra186+), assign @sp to
109 * @ch, preventing other channels from incrementing the syncpoints. If @ch is
110 * NULL, unassigns the syncpoint.
112 * On older chips, do nothing.
114 static void syncpt_assign_to_channel(struct host1x_syncpt *sp,
115 struct host1x_channel *ch)
118 struct host1x *host = sp->host;
123 host1x_sync_writel(host,
124 HOST1X_SYNC_SYNCPT_CH_APP_CH(ch ? ch->id : 0xff),
125 HOST1X_SYNC_SYNCPT_CH_APP(sp->id));
130 * syncpt_enable_protection() - Enable syncpoint protection
131 * @host: host1x instance
133 * On chips with the syncpoint protection feature (Tegra186+), enable this
134 * feature. On older chips, do nothing.
136 static void syncpt_enable_protection(struct host1x *host)
142 host1x_hypervisor_writel(host, HOST1X_HV_SYNCPT_PROT_EN_CH_EN,
143 HOST1X_HV_SYNCPT_PROT_EN);
147 static const struct host1x_syncpt_ops host1x_syncpt_ops = {
148 .restore = syncpt_restore,
149 .restore_wait_base = syncpt_restore_wait_base,
150 .load_wait_base = syncpt_read_wait_base,
152 .cpu_incr = syncpt_cpu_incr,
153 .assign_to_channel = syncpt_assign_to_channel,
154 .enable_protection = syncpt_enable_protection,