2 * Tegra host1x Register Offsets for Tegra186
4 * Copyright (c) 2017 NVIDIA Corporation.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 #ifndef __HOST1X_HOST1X06_HARDWARE_H
20 #define __HOST1X_HOST1X06_HARDWARE_H
22 #include <linux/types.h>
23 #include <linux/bitops.h>
25 #include "hw_host1x06_channel.h"
26 #include "hw_host1x06_uclass.h"
27 #include "hw_host1x06_vm.h"
28 #include "hw_host1x06_hypervisor.h"
30 static inline u32 host1x_class_host_wait_syncpt(
31 unsigned indx, unsigned threshold)
33 return host1x_uclass_wait_syncpt_indx_f(indx)
34 | host1x_uclass_wait_syncpt_thresh_f(threshold);
37 static inline u32 host1x_class_host_load_syncpt_base(
38 unsigned indx, unsigned threshold)
40 return host1x_uclass_load_syncpt_base_base_indx_f(indx)
41 | host1x_uclass_load_syncpt_base_value_f(threshold);
44 static inline u32 host1x_class_host_wait_syncpt_base(
45 unsigned indx, unsigned base_indx, unsigned offset)
47 return host1x_uclass_wait_syncpt_base_indx_f(indx)
48 | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
49 | host1x_uclass_wait_syncpt_base_offset_f(offset);
52 static inline u32 host1x_class_host_incr_syncpt_base(
53 unsigned base_indx, unsigned offset)
55 return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
56 | host1x_uclass_incr_syncpt_base_offset_f(offset);
59 static inline u32 host1x_class_host_incr_syncpt(
60 unsigned cond, unsigned indx)
62 return host1x_uclass_incr_syncpt_cond_f(cond)
63 | host1x_uclass_incr_syncpt_indx_f(indx);
66 static inline u32 host1x_class_host_indoff_reg_write(
67 unsigned mod_id, unsigned offset, bool auto_inc)
69 u32 v = host1x_uclass_indoff_indbe_f(0xf)
70 | host1x_uclass_indoff_indmodid_f(mod_id)
71 | host1x_uclass_indoff_indroffset_f(offset);
73 v |= host1x_uclass_indoff_autoinc_f(1);
77 static inline u32 host1x_class_host_indoff_reg_read(
78 unsigned mod_id, unsigned offset, bool auto_inc)
80 u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
81 | host1x_uclass_indoff_indroffset_f(offset)
82 | host1x_uclass_indoff_rwn_read_v();
84 v |= host1x_uclass_indoff_autoinc_f(1);
89 static inline u32 host1x_opcode_setclass(
90 unsigned class_id, unsigned offset, unsigned mask)
92 return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
95 static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
97 return (1 << 28) | (offset << 16) | count;
100 static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
102 return (2 << 28) | (offset << 16) | count;
105 static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
107 return (3 << 28) | (offset << 16) | mask;
110 static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
112 return (4 << 28) | (offset << 16) | value;
115 static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
117 return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
118 host1x_class_host_incr_syncpt(cond, indx));
121 static inline u32 host1x_opcode_restart(unsigned address)
123 return (5 << 28) | (address >> 4);
126 static inline u32 host1x_opcode_gather(unsigned count)
128 return (6 << 28) | count;
131 static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
133 return (6 << 28) | (offset << 16) | BIT(15) | count;
136 static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
138 return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
141 static inline u32 host1x_opcode_gather_wide(unsigned count)
143 return (12 << 28) | count;
146 #define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)