drivers/gpu/drm/vc4/vc4_plane.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  */
   5
   6 /**
   7  * DOC: VC4 plane module
   8  *
   9  * Each DRM plane is a layer of pixels being scanned out by the HVS.
  10  *
  11  * At atomic modeset check time, we compute the HVS display element
  12  * state that would be necessary for displaying the plane (giving us a
  13  * chance to figure out if a plane configuration is invalid), then at
  14  * atomic flush time the CRTC will ask us to write our element state
  15  * into the region of the HVS that it has allocated for us.
  16  */
  17
  18 #include <drm/drm_atomic.h>
  19 #include <drm/drm_atomic_helper.h>
  20 #include <drm/drm_fb_cma_helper.h>
  21 #include <drm/drm_plane_helper.h>
  22 #include <drm/drm_atomic_uapi.h>
  23
  24 #include "uapi/drm/vc4_drm.h"
  25 #include "vc4_drv.h"
  26 #include "vc4_regs.h"
  27
  28 static const struct hvs_format {
  29         u32 drm; /* DRM_FORMAT_* */
  30         u32 hvs; /* HVS_FORMAT_* */
  31         u32 pixel_order;
  32 } hvs_formats[] = {
  33         {
  34                 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  35                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  36         },
  37         {
  38                 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  39                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  40         },
  41         {
  42                 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  43                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  44         },
  45         {
  46                 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888,
  47                 .pixel_order = HVS_PIXEL_ORDER_ARGB,
  48         },
  49         {
  50                 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  51                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  52         },
  53         {
  54                 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565,
  55                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  56         },
  57         {
  58                 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  59                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  60         },
  61         {
  62                 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551,
  63                 .pixel_order = HVS_PIXEL_ORDER_ABGR,
  64         },
  65         {
  66                 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  67                 .pixel_order = HVS_PIXEL_ORDER_XRGB,
  68         },
  69         {
  70                 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888,
  71                 .pixel_order = HVS_PIXEL_ORDER_XBGR,
  72         },
  73         {
  74                 .drm = DRM_FORMAT_YUV422,
  75                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  76                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  77         },
  78         {
  79                 .drm = DRM_FORMAT_YVU422,
  80                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE,
  81                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  82         },
  83         {
  84                 .drm = DRM_FORMAT_YUV420,
  85                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  86                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  87         },
  88         {
  89                 .drm = DRM_FORMAT_YVU420,
  90                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE,
  91                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
  92         },
  93         {
  94                 .drm = DRM_FORMAT_NV12,
  95                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
  96                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
  97         },
  98         {
  99                 .drm = DRM_FORMAT_NV21,
 100                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE,
 101                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 102         },
 103         {
 104                 .drm = DRM_FORMAT_NV16,
 105                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 106                 .pixel_order = HVS_PIXEL_ORDER_XYCBCR,
 107         },
 108         {
 109                 .drm = DRM_FORMAT_NV61,
 110                 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE,
 111                 .pixel_order = HVS_PIXEL_ORDER_XYCRCB,
 112         },
 113 };
 114
 115 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format)
 116 {
 117         unsigned i;
 118
 119         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) {
 120                 if (hvs_formats[i].drm == drm_format)
 121                         return &hvs_formats[i];
 122         }
 123
 124         return NULL;
 125 }
 126
 127 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst)
 128 {
 129         if (dst == src)
 130                 return VC4_SCALING_NONE;
 131         if (3 * dst >= 2 * src)
 132                 return VC4_SCALING_PPF;
 133         else
 134                 return VC4_SCALING_TPZ;
 135 }
 136
 137 static bool plane_enabled(struct drm_plane_state *state)
 138 {
 139         return state->fb && state->crtc;
 140 }
 141
 142 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane)
 143 {
 144         struct vc4_plane_state *vc4_state;
 145
 146         if (WARN_ON(!plane->state))
 147                 return NULL;
 148
 149         vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL);
 150         if (!vc4_state)
 151                 return NULL;
 152
 153         memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm));
 154         vc4_state->dlist_initialized = 0;
 155
 156         __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base);
 157
 158         if (vc4_state->dlist) {
 159                 vc4_state->dlist = kmemdup(vc4_state->dlist,
 160                                            vc4_state->dlist_count * 4,
 161                                            GFP_KERNEL);
 162                 if (!vc4_state->dlist) {
 163                         kfree(vc4_state);
 164                         return NULL;
 165                 }
 166                 vc4_state->dlist_size = vc4_state->dlist_count;
 167         }
 168
 169         return &vc4_state->base;
 170 }
 171
 172 static void vc4_plane_destroy_state(struct drm_plane *plane,
 173                                     struct drm_plane_state *state)
 174 {
 175         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 176         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 177
 178         if (vc4_state->lbm.allocated) {
 179                 unsigned long irqflags;
 180
 181                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 182                 drm_mm_remove_node(&vc4_state->lbm);
 183                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 184         }
 185
 186         kfree(vc4_state->dlist);
 187         __drm_atomic_helper_plane_destroy_state(&vc4_state->base);
 188         kfree(state);
 189 }
 190
 191 /* Called during init to allocate the plane's atomic state. */
 192 static void vc4_plane_reset(struct drm_plane *plane)
 193 {
 194         struct vc4_plane_state *vc4_state;
 195
 196         WARN_ON(plane->state);
 197
 198         vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
 199         if (!vc4_state)
 200                 return;
 201
 202         __drm_atomic_helper_plane_reset(plane, &vc4_state->base);
 203 }
 204
 205 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val)
 206 {
 207         if (vc4_state->dlist_count == vc4_state->dlist_size) {
 208                 u32 new_size = max(4u, vc4_state->dlist_count * 2);
 209                 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL);
 210
 211                 if (!new_dlist)
 212                         return;
 213                 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4);
 214
 215                 kfree(vc4_state->dlist);
 216                 vc4_state->dlist = new_dlist;
 217                 vc4_state->dlist_size = new_size;
 218         }
 219
 220         vc4_state->dlist[vc4_state->dlist_count++] = val;
 221 }
 222
 223 /* Returns the scl0/scl1 field based on whether the dimensions need to
 224  * be up/down/non-scaled.
 225  *
 226  * This is a replication of a table from the spec.
 227  */
 228 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane)
 229 {
 230         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 231
 232         switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) {
 233         case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF:
 234                 return SCALER_CTL0_SCL_H_PPF_V_PPF;
 235         case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF:
 236                 return SCALER_CTL0_SCL_H_TPZ_V_PPF;
 237         case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ:
 238                 return SCALER_CTL0_SCL_H_PPF_V_TPZ;
 239         case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ:
 240                 return SCALER_CTL0_SCL_H_TPZ_V_TPZ;
 241         case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE:
 242                 return SCALER_CTL0_SCL_H_PPF_V_NONE;
 243         case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF:
 244                 return SCALER_CTL0_SCL_H_NONE_V_PPF;
 245         case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ:
 246                 return SCALER_CTL0_SCL_H_NONE_V_TPZ;
 247         case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE:
 248                 return SCALER_CTL0_SCL_H_TPZ_V_NONE;
 249         default:
 250         case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE:
 251                 /* The unity case is independently handled by
 252                  * SCALER_CTL0_UNITY.
 253                  */
 254                 return 0;
 255         }
 256 }
 257
 258 static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
 259 {
 260         struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
 261         unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay;
 262         struct drm_crtc_state *crtc_state;
 263
 264         crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
 265                                                    pstate->crtc);
 266
 267         vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom);
 268         if (!left && !right && !top && !bottom)
 269                 return 0;
 270
 271         if (left + right >= crtc_state->mode.hdisplay ||
 272             top + bottom >= crtc_state->mode.vdisplay)
 273                 return -EINVAL;
 274
 275         adjhdisplay = crtc_state->mode.hdisplay - (left + right);
 276         vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x *
 277                                                adjhdisplay,
 278                                                crtc_state->mode.hdisplay);
 279         vc4_pstate->crtc_x += left;
 280         if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - left)
 281                 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - left;
 282
 283         adjvdisplay = crtc_state->mode.vdisplay - (top + bottom);
 284         vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y *
 285                                                adjvdisplay,
 286                                                crtc_state->mode.vdisplay);
 287         vc4_pstate->crtc_y += top;
 288         if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - top)
 289                 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - top;
 290
 291         vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w *
 292                                                adjhdisplay,
 293                                                crtc_state->mode.hdisplay);
 294         vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h *
 295                                                adjvdisplay,
 296                                                crtc_state->mode.vdisplay);
 297
 298         if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h)
 299                 return -EINVAL;
 300
 301         return 0;
 302 }
 303
 304 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
 305 {
 306         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 307         struct drm_framebuffer *fb = state->fb;
 308         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 309         u32 subpixel_src_mask = (1 << 16) - 1;
 310         u32 format = fb->format->format;
 311         int num_planes = fb->format->num_planes;
 312         struct drm_crtc_state *crtc_state;
 313         u32 h_subsample, v_subsample;
 314         int i, ret;
 315
 316         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 317                                                         state->crtc);
 318         if (!crtc_state) {
 319                 DRM_DEBUG_KMS("Invalid crtc state\n");
 320                 return -EINVAL;
 321         }
 322
 323         ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1,
 324                                                   INT_MAX, true, true);
 325         if (ret)
 326                 return ret;
 327
 328         h_subsample = drm_format_horz_chroma_subsampling(format);
 329         v_subsample = drm_format_vert_chroma_subsampling(format);
 330
 331         for (i = 0; i < num_planes; i++)
 332                 vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
 333
 334         /* We don't support subpixel source positioning for scaling. */
 335         if ((state->src.x1 & subpixel_src_mask) ||
 336             (state->src.x2 & subpixel_src_mask) ||
 337             (state->src.y1 & subpixel_src_mask) ||
 338             (state->src.y2 & subpixel_src_mask)) {
 339                 return -EINVAL;
 340         }
 341
 342         vc4_state->src_x = state->src.x1 >> 16;
 343         vc4_state->src_y = state->src.y1 >> 16;
 344         vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
 345         vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
 346
 347         vc4_state->crtc_x = state->dst.x1;
 348         vc4_state->crtc_y = state->dst.y1;
 349         vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
 350         vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
 351
 352         ret = vc4_plane_margins_adj(state);
 353         if (ret)
 354                 return ret;
 355
 356         vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
 357                                                        vc4_state->crtc_w);
 358         vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0],
 359                                                        vc4_state->crtc_h);
 360
 361         vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE &&
 362                                vc4_state->y_scaling[0] == VC4_SCALING_NONE);
 363
 364         if (num_planes > 1) {
 365                 vc4_state->is_yuv = true;
 366
 367                 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
 368                 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
 369
 370                 vc4_state->x_scaling[1] =
 371                         vc4_get_scaling_mode(vc4_state->src_w[1],
 372                                              vc4_state->crtc_w);
 373                 vc4_state->y_scaling[1] =
 374                         vc4_get_scaling_mode(vc4_state->src_h[1],
 375                                              vc4_state->crtc_h);
 376
 377                 /* YUV conversion requires that horizontal scaling be enabled
 378                  * on the UV plane even if vc4_get_scaling_mode() returned
 379                  * VC4_SCALING_NONE (which can happen when the down-scaling
 380                  * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this
 381                  * case.
 382                  */
 383                 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE)
 384                         vc4_state->x_scaling[1] = VC4_SCALING_PPF;
 385         } else {
 386                 vc4_state->is_yuv = false;
 387                 vc4_state->x_scaling[1] = VC4_SCALING_NONE;
 388                 vc4_state->y_scaling[1] = VC4_SCALING_NONE;
 389         }
 390
 391         return 0;
 392 }
 393
 394 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 395 {
 396         u32 scale, recip;
 397
 398         scale = (1 << 16) * src / dst;
 399
 400         /* The specs note that while the reciprocal would be defined
 401          * as (1<<32)/scale, ~0 is close enough.
 402          */
 403         recip = ~0 / scale;
 404
 405         vc4_dlist_write(vc4_state,
 406                         VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) |
 407                         VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE));
 408         vc4_dlist_write(vc4_state,
 409                         VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP));
 410 }
 411
 412 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst)
 413 {
 414         u32 scale = (1 << 16) * src / dst;
 415
 416         vc4_dlist_write(vc4_state,
 417                         SCALER_PPF_AGC |
 418                         VC4_SET_FIELD(scale, SCALER_PPF_SCALE) |
 419                         VC4_SET_FIELD(0, SCALER_PPF_IPHASE));
 420 }
 421
 422 static u32 vc4_lbm_size(struct drm_plane_state *state)
 423 {
 424         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 425         /* This is the worst case number.  One of the two sizes will
 426          * be used depending on the scaling configuration.
 427          */
 428         u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w);
 429         u32 lbm;
 430
 431         /* LBM is not needed when there's no vertical scaling. */
 432         if (vc4_state->y_scaling[0] == VC4_SCALING_NONE &&
 433             vc4_state->y_scaling[1] == VC4_SCALING_NONE)
 434                 return 0;
 435
 436         if (!vc4_state->is_yuv) {
 437                 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ)
 438                         lbm = pix_per_line * 8;
 439                 else {
 440                         /* In special cases, this multiplier might be 12. */
 441                         lbm = pix_per_line * 16;
 442                 }
 443         } else {
 444                 /* There are cases for this going down to a multiplier
 445                  * of 2, but according to the firmware source, the
 446                  * table in the docs is somewhat wrong.
 447                  */
 448                 lbm = pix_per_line * 16;
 449         }
 450
 451         lbm = roundup(lbm, 32);
 452
 453         return lbm;
 454 }
 455
 456 static void vc4_write_scaling_parameters(struct drm_plane_state *state,
 457                                          int channel)
 458 {
 459         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 460
 461         /* Ch0 H-PPF Word 0: Scaling Parameters */
 462         if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) {
 463                 vc4_write_ppf(vc4_state,
 464                               vc4_state->src_w[channel], vc4_state->crtc_w);
 465         }
 466
 467         /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */
 468         if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) {
 469                 vc4_write_ppf(vc4_state,
 470                               vc4_state->src_h[channel], vc4_state->crtc_h);
 471                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 472         }
 473
 474         /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */
 475         if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) {
 476                 vc4_write_tpz(vc4_state,
 477                               vc4_state->src_w[channel], vc4_state->crtc_w);
 478         }
 479
 480         /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */
 481         if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) {
 482                 vc4_write_tpz(vc4_state,
 483                               vc4_state->src_h[channel], vc4_state->crtc_h);
 484                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 485         }
 486 }
 487
 488 static void vc4_plane_calc_load(struct drm_plane_state *state)
 489 {
 490         unsigned int hvs_load_shift, vrefresh, i;
 491         struct drm_framebuffer *fb = state->fb;
 492         struct vc4_plane_state *vc4_state;
 493         struct drm_crtc_state *crtc_state;
 494         unsigned int vscale_factor;
 495
 496         vc4_state = to_vc4_plane_state(state);
 497         crtc_state = drm_atomic_get_existing_crtc_state(state->state,
 498                                                         state->crtc);
 499         vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode);
 500
 501         /* The HVS is able to process 2 pixels/cycle when scaling the source,
 502          * 4 pixels/cycle otherwise.
 503          * Alpha blending step seems to be pipelined and it's always operating
 504          * at 4 pixels/cycle, so the limiting aspect here seems to be the
 505          * scaler block.
 506          * HVS load is expressed in clk-cycles/sec (AKA Hz).
 507          */
 508         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 509             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 510             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 511             vc4_state->y_scaling[1] != VC4_SCALING_NONE)
 512                 hvs_load_shift = 1;
 513         else
 514                 hvs_load_shift = 2;
 515
 516         vc4_state->membus_load = 0;
 517         vc4_state->hvs_load = 0;
 518         for (i = 0; i < fb->format->num_planes; i++) {
 519                 /* Even if the bandwidth/plane required for a single frame is
 520                  *
 521                  * vc4_state->src_w[i] * vc4_state->src_h[i] * cpp * vrefresh
 522                  *
 523                  * when downscaling, we have to read more pixels per line in
 524                  * the time frame reserved for a single line, so the bandwidth
 525                  * demand can be punctually higher. To account for that, we
 526                  * calculate the down-scaling factor and multiply the plane
 527                  * load by this number. We're likely over-estimating the read
 528                  * demand, but that's better than under-estimating it.
 529                  */
 530                 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i],
 531                                              vc4_state->crtc_h);
 532                 vc4_state->membus_load += vc4_state->src_w[i] *
 533                                           vc4_state->src_h[i] * vscale_factor *
 534                                           fb->format->cpp[i];
 535                 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w;
 536         }
 537
 538         vc4_state->hvs_load *= vrefresh;
 539         vc4_state->hvs_load >>= hvs_load_shift;
 540         vc4_state->membus_load *= vrefresh;
 541 }
 542
 543 static int vc4_plane_allocate_lbm(struct drm_plane_state *state)
 544 {
 545         struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev);
 546         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 547         unsigned long irqflags;
 548         u32 lbm_size;
 549
 550         lbm_size = vc4_lbm_size(state);
 551         if (!lbm_size)
 552                 return 0;
 553
 554         if (WARN_ON(!vc4_state->lbm_offset))
 555                 return -EINVAL;
 556
 557         /* Allocate the LBM memory that the HVS will use for temporary
 558          * storage due to our scaling/format conversion.
 559          */
 560         if (!vc4_state->lbm.allocated) {
 561                 int ret;
 562
 563                 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags);
 564                 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm,
 565                                                  &vc4_state->lbm,
 566                                                  lbm_size, 32, 0, 0);
 567                 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags);
 568
 569                 if (ret)
 570                         return ret;
 571         } else {
 572                 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size);
 573         }
 574
 575         vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start;
 576
 577         return 0;
 578 }
 579
 580 /* Writes out a full display list for an active plane to the plane's
 581  * private dlist state.
 582  */
 583 static int vc4_plane_mode_set(struct drm_plane *plane,
 584                               struct drm_plane_state *state)
 585 {
 586         struct vc4_dev *vc4 = to_vc4_dev(plane->dev);
 587         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 588         struct drm_framebuffer *fb = state->fb;
 589         u32 ctl0_offset = vc4_state->dlist_count;
 590         const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
 591         u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
 592         int num_planes = drm_format_num_planes(format->drm);
 593         u32 h_subsample, v_subsample;
 594         bool mix_plane_alpha;
 595         bool covers_screen;
 596         u32 scl0, scl1, pitch0;
 597         u32 tiling, src_y;
 598         u32 hvs_format = format->hvs;
 599         unsigned int rotation;
 600         int ret, i;
 601
 602         if (vc4_state->dlist_initialized)
 603                 return 0;
 604
 605         ret = vc4_plane_setup_clipping_and_scaling(state);
 606         if (ret)
 607                 return ret;
 608
 609         /* SCL1 is used for Cb/Cr scaling of planar formats.  For RGB
 610          * and 4:4:4, scl1 should be set to scl0 so both channels of
 611          * the scaler do the same thing.  For YUV, the Y plane needs
 612          * to be put in channel 1 and Cb/Cr in channel 0, so we swap
 613          * the scl fields here.
 614          */
 615         if (num_planes == 1) {
 616                 scl0 = vc4_get_scl_field(state, 0);
 617                 scl1 = scl0;
 618         } else {
 619                 scl0 = vc4_get_scl_field(state, 1);
 620                 scl1 = vc4_get_scl_field(state, 0);
 621         }
 622
 623         h_subsample = drm_format_horz_chroma_subsampling(format->drm);
 624         v_subsample = drm_format_vert_chroma_subsampling(format->drm);
 625
 626         rotation = drm_rotation_simplify(state->rotation,
 627                                          DRM_MODE_ROTATE_0 |
 628                                          DRM_MODE_REFLECT_X |
 629                                          DRM_MODE_REFLECT_Y);
 630
 631         /* We must point to the last line when Y reflection is enabled. */
 632         src_y = vc4_state->src_y;
 633         if (rotation & DRM_MODE_REFLECT_Y)
 634                 src_y += vc4_state->src_h[0] - 1;
 635
 636         switch (base_format_mod) {
 637         case DRM_FORMAT_MOD_LINEAR:
 638                 tiling = SCALER_CTL0_TILING_LINEAR;
 639                 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
 640
 641                 /* Adjust the base pointer to the first pixel to be scanned
 642                  * out.
 643                  */
 644                 for (i = 0; i < num_planes; i++) {
 645                         vc4_state->offsets[i] += src_y /
 646                                                  (i ? v_subsample : 1) *
 647                                                  fb->pitches[i];
 648
 649                         vc4_state->offsets[i] += vc4_state->src_x /
 650                                                  (i ? h_subsample : 1) *
 651                                                  fb->format->cpp[i];
 652                 }
 653
 654                 break;
 655
 656         case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
 657                 u32 tile_size_shift = 12; /* T tiles are 4kb */
 658                 /* Whole-tile offsets, mostly for setting the pitch. */
 659                 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
 660                 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
 661                 u32 tile_w_mask = (1 << tile_w_shift) - 1;
 662                 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
 663                  * the height (in pixels) of a 4k tile.
 664                  */
 665                 u32 tile_h_mask = (2 << tile_h_shift) - 1;
 666                 /* For T-tiled, the FB pitch is "how many bytes from one row to
 667                  * the next, such that
 668                  *
 669                  *      pitch * tile_h == tile_size * tiles_per_row
 670                  */
 671                 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
 672                 u32 tiles_l = vc4_state->src_x >> tile_w_shift;
 673                 u32 tiles_r = tiles_w - tiles_l;
 674                 u32 tiles_t = src_y >> tile_h_shift;
 675                 /* Intra-tile offsets, which modify the base address (the
 676                  * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
 677                  * base address).
 678                  */
 679                 u32 tile_y = (src_y >> 4) & 1;
 680                 u32 subtile_y = (src_y >> 2) & 3;
 681                 u32 utile_y = src_y & 3;
 682                 u32 x_off = vc4_state->src_x & tile_w_mask;
 683                 u32 y_off = src_y & tile_h_mask;
 684
 685                 /* When Y reflection is requested we must set the
 686                  * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines
 687                  * after the initial one should be fetched in descending order,
 688                  * which makes sense since we start from the last line and go
 689                  * backward.
 690                  * Don't know why we need y_off = max_y_off - y_off, but it's
 691                  * definitely required (I guess it's also related to the "going
 692                  * backward" situation).
 693                  */
 694                 if (rotation & DRM_MODE_REFLECT_Y) {
 695                         y_off = tile_h_mask - y_off;
 696                         pitch0 = SCALER_PITCH0_TILE_LINE_DIR;
 697                 } else {
 698                         pitch0 = 0;
 699                 }
 700
 701                 tiling = SCALER_CTL0_TILING_256B_OR_T;
 702                 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
 703                            VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
 704                            VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
 705                            VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
 706                 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
 707                 vc4_state->offsets[0] += subtile_y << 8;
 708                 vc4_state->offsets[0] += utile_y << 4;
 709
 710                 /* Rows of tiles alternate left-to-right and right-to-left. */
 711                 if (tiles_t & 1) {
 712                         pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
 713                         vc4_state->offsets[0] += (tiles_w - tiles_l) <<
 714                                                  tile_size_shift;
 715                         vc4_state->offsets[0] -= (1 + !tile_y) << 10;
 716                 } else {
 717                         vc4_state->offsets[0] += tiles_l << tile_size_shift;
 718                         vc4_state->offsets[0] += tile_y << 10;
 719                 }
 720
 721                 break;
 722         }
 723
 724         case DRM_FORMAT_MOD_BROADCOM_SAND64:
 725         case DRM_FORMAT_MOD_BROADCOM_SAND128:
 726         case DRM_FORMAT_MOD_BROADCOM_SAND256: {
 727                 uint32_t param = fourcc_mod_broadcom_param(fb->modifier);
 728                 u32 tile_w, tile, x_off, pix_per_tile;
 729
 730                 hvs_format = HVS_PIXEL_FORMAT_H264;
 731
 732                 switch (base_format_mod) {
 733                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
 734                         tiling = SCALER_CTL0_TILING_64B;
 735                         tile_w = 64;
 736                         break;
 737                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
 738                         tiling = SCALER_CTL0_TILING_128B;
 739                         tile_w = 128;
 740                         break;
 741                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
 742                         tiling = SCALER_CTL0_TILING_256B_OR_T;
 743                         tile_w = 256;
 744                         break;
 745                 default:
 746                         break;
 747                 }
 748
 749                 if (param > SCALER_TILE_HEIGHT_MASK) {
 750                         DRM_DEBUG_KMS("SAND height too large (%d)\n", param);
 751                         return -EINVAL;
 752                 }
 753
 754                 pix_per_tile = tile_w / fb->format->cpp[0];
 755                 tile = vc4_state->src_x / pix_per_tile;
 756                 x_off = vc4_state->src_x % pix_per_tile;
 757
 758                 /* Adjust the base pointer to the first pixel to be scanned
 759                  * out.
 760                  */
 761                 for (i = 0; i < num_planes; i++) {
 762                         vc4_state->offsets[i] += param * tile_w * tile;
 763                         vc4_state->offsets[i] += src_y /
 764                                                  (i ? v_subsample : 1) *
 765                                                  tile_w;
 766                         vc4_state->offsets[i] += x_off /
 767                                                  (i ? h_subsample : 1) *
 768                                                  fb->format->cpp[i];
 769                 }
 770
 771                 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
 772                 break;
 773         }
 774
 775         default:
 776                 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
 777                               (long long)fb->modifier);
 778                 return -EINVAL;
 779         }
 780
 781         /* Control word */
 782         vc4_dlist_write(vc4_state,
 783                         SCALER_CTL0_VALID |
 784                         (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) |
 785                         (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) |
 786                         VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) |
 787                         (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) |
 788                         (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) |
 789                         VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) |
 790                         (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) |
 791                         VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) |
 792                         VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1));
 793
 794         /* Position Word 0: Image Positions and Alpha Value */
 795         vc4_state->pos0_offset = vc4_state->dlist_count;
 796         vc4_dlist_write(vc4_state,
 797                         VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) |
 798                         VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) |
 799                         VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y));
 800
 801         /* Position Word 1: Scaled Image Dimensions. */
 802         if (!vc4_state->is_unity) {
 803                 vc4_dlist_write(vc4_state,
 804                                 VC4_SET_FIELD(vc4_state->crtc_w,
 805                                               SCALER_POS1_SCL_WIDTH) |
 806                                 VC4_SET_FIELD(vc4_state->crtc_h,
 807                                               SCALER_POS1_SCL_HEIGHT));
 808         }
 809
 810         /* Don't waste cycles mixing with plane alpha if the set alpha
 811          * is opaque or there is no per-pixel alpha information.
 812          * In any case we use the alpha property value as the fixed alpha.
 813          */
 814         mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE &&
 815                           fb->format->has_alpha;
 816
 817         /* Position Word 2: Source Image Size, Alpha */
 818         vc4_state->pos2_offset = vc4_state->dlist_count;
 819         vc4_dlist_write(vc4_state,
 820                         VC4_SET_FIELD(fb->format->has_alpha ?
 821                                       SCALER_POS2_ALPHA_MODE_PIPELINE :
 822                                       SCALER_POS2_ALPHA_MODE_FIXED,
 823                                       SCALER_POS2_ALPHA_MODE) |
 824                         (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) |
 825                         (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) |
 826                         VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) |
 827                         VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT));
 828
 829         /* Position Word 3: Context.  Written by the HVS. */
 830         vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 831
 832
 833         /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers
 834          *
 835          * The pointers may be any byte address.
 836          */
 837         vc4_state->ptr0_offset = vc4_state->dlist_count;
 838         for (i = 0; i < num_planes; i++)
 839                 vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
 840
 841         /* Pointer Context Word 0/1/2: Written by the HVS */
 842         for (i = 0; i < num_planes; i++)
 843                 vc4_dlist_write(vc4_state, 0xc0c0c0c0);
 844
 845         /* Pitch word 0 */
 846         vc4_dlist_write(vc4_state, pitch0);
 847
 848         /* Pitch word 1/2 */
 849         for (i = 1; i < num_planes; i++) {
 850                 if (hvs_format != HVS_PIXEL_FORMAT_H264) {
 851                         vc4_dlist_write(vc4_state,
 852                                         VC4_SET_FIELD(fb->pitches[i],
 853                                                       SCALER_SRC_PITCH));
 854                 } else {
 855                         vc4_dlist_write(vc4_state, pitch0);
 856                 }
 857         }
 858
 859         /* Colorspace conversion words */
 860         if (vc4_state->is_yuv) {
 861                 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5);
 862                 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5);
 863                 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5);
 864         }
 865
 866         vc4_state->lbm_offset = 0;
 867
 868         if (vc4_state->x_scaling[0] != VC4_SCALING_NONE ||
 869             vc4_state->x_scaling[1] != VC4_SCALING_NONE ||
 870             vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 871             vc4_state->y_scaling[1] != VC4_SCALING_NONE) {
 872                 /* Reserve a slot for the LBM Base Address. The real value will
 873                  * be set when calling vc4_plane_allocate_lbm().
 874                  */
 875                 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE ||
 876                     vc4_state->y_scaling[1] != VC4_SCALING_NONE)
 877                         vc4_state->lbm_offset = vc4_state->dlist_count++;
 878
 879                 if (num_planes > 1) {
 880                         /* Emit Cb/Cr as channel 0 and Y as channel
 881                          * 1. This matches how we set up scl0/scl1
 882                          * above.
 883                          */
 884                         vc4_write_scaling_parameters(state, 1);
 885                 }
 886                 vc4_write_scaling_parameters(state, 0);
 887
 888                 /* If any PPF setup was done, then all the kernel
 889                  * pointers get uploaded.
 890                  */
 891                 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF ||
 892                     vc4_state->y_scaling[0] == VC4_SCALING_PPF ||
 893                     vc4_state->x_scaling[1] == VC4_SCALING_PPF ||
 894                     vc4_state->y_scaling[1] == VC4_SCALING_PPF) {
 895                         u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start,
 896                                                    SCALER_PPF_KERNEL_OFFSET);
 897
 898                         /* HPPF plane 0 */
 899                         vc4_dlist_write(vc4_state, kernel);
 900                         /* VPPF plane 0 */
 901                         vc4_dlist_write(vc4_state, kernel);
 902                         /* HPPF plane 1 */
 903                         vc4_dlist_write(vc4_state, kernel);
 904                         /* VPPF plane 1 */
 905                         vc4_dlist_write(vc4_state, kernel);
 906                 }
 907         }
 908
 909         vc4_state->dlist[ctl0_offset] |=
 910                 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE);
 911
 912         /* crtc_* are already clipped coordinates. */
 913         covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 &&
 914                         vc4_state->crtc_w == state->crtc->mode.hdisplay &&
 915                         vc4_state->crtc_h == state->crtc->mode.vdisplay;
 916         /* Background fill might be necessary when the plane has per-pixel
 917          * alpha content or a non-opaque plane alpha and could blend from the
 918          * background or does not cover the entire screen.
 919          */
 920         vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen ||
 921                                    state->alpha != DRM_BLEND_ALPHA_OPAQUE;
 922
 923         /* Flag the dlist as initialized to avoid checking it twice in case
 924          * the async update check already called vc4_plane_mode_set() and
 925          * decided to fallback to sync update because async update was not
 926          * possible.
 927          */
 928         vc4_state->dlist_initialized = 1;
 929
 930         vc4_plane_calc_load(state);
 931
 932         return 0;
 933 }
 934
 935 /* If a modeset involves changing the setup of a plane, the atomic
 936  * infrastructure will call this to validate a proposed plane setup.
 937  * However, if a plane isn't getting updated, this (and the
 938  * corresponding vc4_plane_atomic_update) won't get called.  Thus, we
 939  * compute the dlist here and have all active plane dlists get updated
 940  * in the CRTC's flush.
 941  */
 942 static int vc4_plane_atomic_check(struct drm_plane *plane,
 943                                   struct drm_plane_state *state)
 944 {
 945         struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
 946         int ret;
 947
 948         vc4_state->dlist_count = 0;
 949
 950         if (!plane_enabled(state))
 951                 return 0;
 952
 953         ret = vc4_plane_mode_set(plane, state);
 954         if (ret)
 955                 return ret;
 956
 957         return vc4_plane_allocate_lbm(state);
 958 }
 959
 960 static void vc4_plane_atomic_update(struct drm_plane *plane,
 961                                     struct drm_plane_state *old_state)
 962 {
 963         /* No contents here.  Since we don't know where in the CRTC's
 964          * dlist we should be stored, our dlist is uploaded to the
 965          * hardware with vc4_plane_write_dlist() at CRTC atomic_flush
 966          * time.
 967          */
 968 }
 969
 970 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist)
 971 {
 972         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 973         int i;
 974
 975         vc4_state->hw_dlist = dlist;
 976
 977         /* Can't memcpy_toio() because it needs to be 32-bit writes. */
 978         for (i = 0; i < vc4_state->dlist_count; i++)
 979                 writel(vc4_state->dlist[i], &dlist[i]);
 980
 981         return vc4_state->dlist_count;
 982 }
 983
 984 u32 vc4_plane_dlist_size(const struct drm_plane_state *state)
 985 {
 986         const struct vc4_plane_state *vc4_state =
 987                 container_of(state, typeof(*vc4_state), base);
 988
 989         return vc4_state->dlist_count;
 990 }
 991
 992 /* Updates the plane to immediately (well, once the FIFO needs
 993  * refilling) scan out from at a new framebuffer.
 994  */
 995 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb)
 996 {
 997         struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state);
 998         struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0);
 999         uint32_t addr;
1000
1001         /* We're skipping the address adjustment for negative origin,
1002          * because this is only called on the primary plane.
1003          */
1004         WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0);
1005         addr = bo->paddr + fb->offsets[0];
1006
1007         /* Write the new address into the hardware immediately.  The
1008          * scanout will start from this address as soon as the FIFO
1009          * needs to refill with pixels.
1010          */
1011         writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1012
1013         /* Also update the CPU-side dlist copy, so that any later
1014          * atomic updates that don't do a new modeset on our plane
1015          * also use our updated address.
1016          */
1017         vc4_state->dlist[vc4_state->ptr0_offset] = addr;
1018 }
1019
1020 static void vc4_plane_atomic_async_update(struct drm_plane *plane,
1021                                           struct drm_plane_state *state)
1022 {
1023         struct vc4_plane_state *vc4_state, *new_vc4_state;
1024
1025         swap(plane->state->fb, state->fb);
1026         plane->state->crtc_x = state->crtc_x;
1027         plane->state->crtc_y = state->crtc_y;
1028         plane->state->crtc_w = state->crtc_w;
1029         plane->state->crtc_h = state->crtc_h;
1030         plane->state->src_x = state->src_x;
1031         plane->state->src_y = state->src_y;
1032         plane->state->src_w = state->src_w;
1033         plane->state->src_h = state->src_h;
1034         plane->state->src_h = state->src_h;
1035         plane->state->alpha = state->alpha;
1036         plane->state->pixel_blend_mode = state->pixel_blend_mode;
1037         plane->state->rotation = state->rotation;
1038         plane->state->zpos = state->zpos;
1039         plane->state->normalized_zpos = state->normalized_zpos;
1040         plane->state->color_encoding = state->color_encoding;
1041         plane->state->color_range = state->color_range;
1042         plane->state->src = state->src;
1043         plane->state->dst = state->dst;
1044         plane->state->visible = state->visible;
1045
1046         new_vc4_state = to_vc4_plane_state(state);
1047         vc4_state = to_vc4_plane_state(plane->state);
1048
1049         vc4_state->crtc_x = new_vc4_state->crtc_x;
1050         vc4_state->crtc_y = new_vc4_state->crtc_y;
1051         vc4_state->crtc_h = new_vc4_state->crtc_h;
1052         vc4_state->crtc_w = new_vc4_state->crtc_w;
1053         vc4_state->src_x = new_vc4_state->src_x;
1054         vc4_state->src_y = new_vc4_state->src_y;
1055         memcpy(vc4_state->src_w, new_vc4_state->src_w,
1056                sizeof(vc4_state->src_w));
1057         memcpy(vc4_state->src_h, new_vc4_state->src_h,
1058                sizeof(vc4_state->src_h));
1059         memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling,
1060                sizeof(vc4_state->x_scaling));
1061         memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling,
1062                sizeof(vc4_state->y_scaling));
1063         vc4_state->is_unity = new_vc4_state->is_unity;
1064         vc4_state->is_yuv = new_vc4_state->is_yuv;
1065         memcpy(vc4_state->offsets, new_vc4_state->offsets,
1066                sizeof(vc4_state->offsets));
1067         vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
1068
1069         /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
1070         vc4_state->dlist[vc4_state->pos0_offset] =
1071                 new_vc4_state->dlist[vc4_state->pos0_offset];
1072         vc4_state->dlist[vc4_state->pos2_offset] =
1073                 new_vc4_state->dlist[vc4_state->pos2_offset];
1074         vc4_state->dlist[vc4_state->ptr0_offset] =
1075                 new_vc4_state->dlist[vc4_state->ptr0_offset];
1076
1077         /* Note that we can't just call vc4_plane_write_dlist()
1078          * because that would smash the context data that the HVS is
1079          * currently using.
1080          */
1081         writel(vc4_state->dlist[vc4_state->pos0_offset],
1082                &vc4_state->hw_dlist[vc4_state->pos0_offset]);
1083         writel(vc4_state->dlist[vc4_state->pos2_offset],
1084                &vc4_state->hw_dlist[vc4_state->pos2_offset]);
1085         writel(vc4_state->dlist[vc4_state->ptr0_offset],
1086                &vc4_state->hw_dlist[vc4_state->ptr0_offset]);
1087 }
1088
1089 static int vc4_plane_atomic_async_check(struct drm_plane *plane,
1090                                         struct drm_plane_state *state)
1091 {
1092         struct vc4_plane_state *old_vc4_state, *new_vc4_state;
1093         int ret;
1094         u32 i;
1095
1096         ret = vc4_plane_mode_set(plane, state);
1097         if (ret)
1098                 return ret;
1099
1100         old_vc4_state = to_vc4_plane_state(plane->state);
1101         new_vc4_state = to_vc4_plane_state(state);
1102         if (old_vc4_state->dlist_count != new_vc4_state->dlist_count ||
1103             old_vc4_state->pos0_offset != new_vc4_state->pos0_offset ||
1104             old_vc4_state->pos2_offset != new_vc4_state->pos2_offset ||
1105             old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset ||
1106             vc4_lbm_size(plane->state) != vc4_lbm_size(state))
1107                 return -EINVAL;
1108
1109         /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update
1110          * if anything else has changed, fallback to a sync update.
1111          */
1112         for (i = 0; i < new_vc4_state->dlist_count; i++) {
1113                 if (i == new_vc4_state->pos0_offset ||
1114                     i == new_vc4_state->pos2_offset ||
1115                     i == new_vc4_state->ptr0_offset ||
1116                     (new_vc4_state->lbm_offset &&
1117                      i == new_vc4_state->lbm_offset))
1118                         continue;
1119
1120                 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i])
1121                         return -EINVAL;
1122         }
1123
1124         return 0;
1125 }
1126
1127 static int vc4_prepare_fb(struct drm_plane *plane,
1128                           struct drm_plane_state *state)
1129 {
1130         struct vc4_bo *bo;
1131         struct dma_fence *fence;
1132         int ret;
1133
1134         if (!state->fb)
1135                 return 0;
1136
1137         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1138
1139         fence = reservation_object_get_excl_rcu(bo->base.base.resv);
1140         drm_atomic_set_fence_for_plane(state, fence);
1141
1142         if (plane->state->fb == state->fb)
1143                 return 0;
1144
1145         ret = vc4_bo_inc_usecnt(bo);
1146         if (ret)
1147                 return ret;
1148
1149         return 0;
1150 }
1151
1152 static void vc4_cleanup_fb(struct drm_plane *plane,
1153                            struct drm_plane_state *state)
1154 {
1155         struct vc4_bo *bo;
1156
1157         if (plane->state->fb == state->fb || !state->fb)
1158                 return;
1159
1160         bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base);
1161         vc4_bo_dec_usecnt(bo);
1162 }
1163
1164 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = {
1165         .atomic_check = vc4_plane_atomic_check,
1166         .atomic_update = vc4_plane_atomic_update,
1167         .prepare_fb = vc4_prepare_fb,
1168         .cleanup_fb = vc4_cleanup_fb,
1169         .atomic_async_check = vc4_plane_atomic_async_check,
1170         .atomic_async_update = vc4_plane_atomic_async_update,
1171 };
1172
1173 static void vc4_plane_destroy(struct drm_plane *plane)
1174 {
1175         drm_plane_cleanup(plane);
1176 }
1177
1178 static bool vc4_format_mod_supported(struct drm_plane *plane,
1179                                      uint32_t format,
1180                                      uint64_t modifier)
1181 {
1182         /* Support T_TILING for RGB formats only. */
1183         switch (format) {
1184         case DRM_FORMAT_XRGB8888:
1185         case DRM_FORMAT_ARGB8888:
1186         case DRM_FORMAT_ABGR8888:
1187         case DRM_FORMAT_XBGR8888:
1188         case DRM_FORMAT_RGB565:
1189         case DRM_FORMAT_BGR565:
1190         case DRM_FORMAT_ARGB1555:
1191         case DRM_FORMAT_XRGB1555:
1192                 switch (fourcc_mod_broadcom_mod(modifier)) {
1193                 case DRM_FORMAT_MOD_LINEAR:
1194                 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
1195                         return true;
1196                 default:
1197                         return false;
1198                 }
1199         case DRM_FORMAT_NV12:
1200         case DRM_FORMAT_NV21:
1201                 switch (fourcc_mod_broadcom_mod(modifier)) {
1202                 case DRM_FORMAT_MOD_LINEAR:
1203                 case DRM_FORMAT_MOD_BROADCOM_SAND64:
1204                 case DRM_FORMAT_MOD_BROADCOM_SAND128:
1205                 case DRM_FORMAT_MOD_BROADCOM_SAND256:
1206                         return true;
1207                 default:
1208                         return false;
1209                 }
1210         case DRM_FORMAT_YUV422:
1211         case DRM_FORMAT_YVU422:
1212         case DRM_FORMAT_YUV420:
1213         case DRM_FORMAT_YVU420:
1214         case DRM_FORMAT_NV16:
1215         case DRM_FORMAT_NV61:
1216         default:
1217                 return (modifier == DRM_FORMAT_MOD_LINEAR);
1218         }
1219 }
1220
1221 static const struct drm_plane_funcs vc4_plane_funcs = {
1222         .update_plane = drm_atomic_helper_update_plane,
1223         .disable_plane = drm_atomic_helper_disable_plane,
1224         .destroy = vc4_plane_destroy,
1225         .set_property = NULL,
1226         .reset = vc4_plane_reset,
1227         .atomic_duplicate_state = vc4_plane_duplicate_state,
1228         .atomic_destroy_state = vc4_plane_destroy_state,
1229         .format_mod_supported = vc4_format_mod_supported,
1230 };
1231
1232 struct drm_plane *vc4_plane_init(struct drm_device *dev,
1233                                  enum drm_plane_type type)
1234 {
1235         struct drm_plane *plane = NULL;
1236         struct vc4_plane *vc4_plane;
1237         u32 formats[ARRAY_SIZE(hvs_formats)];
1238         int ret = 0;
1239         unsigned i;
1240         static const uint64_t modifiers[] = {
1241                 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED,
1242                 DRM_FORMAT_MOD_BROADCOM_SAND128,
1243                 DRM_FORMAT_MOD_BROADCOM_SAND64,
1244                 DRM_FORMAT_MOD_BROADCOM_SAND256,
1245                 DRM_FORMAT_MOD_LINEAR,
1246                 DRM_FORMAT_MOD_INVALID
1247         };
1248
1249         vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane),
1250                                  GFP_KERNEL);
1251         if (!vc4_plane)
1252                 return ERR_PTR(-ENOMEM);
1253
1254         for (i = 0; i < ARRAY_SIZE(hvs_formats); i++)
1255                 formats[i] = hvs_formats[i].drm;
1256
1257         plane = &vc4_plane->base;
1258         ret = drm_universal_plane_init(dev, plane, 0,
1259                                        &vc4_plane_funcs,
1260                                        formats, ARRAY_SIZE(formats),
1261                                        modifiers, type, NULL);
1262
1263         drm_plane_helper_add(plane, &vc4_plane_helper_funcs);
1264
1265         drm_plane_create_alpha_property(plane);
1266         drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0,
1267                                            DRM_MODE_ROTATE_0 |
1268                                            DRM_MODE_ROTATE_180 |
1269                                            DRM_MODE_REFLECT_X |
1270                                            DRM_MODE_REFLECT_Y);
1271
1272         return plane;
1273 }