drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <linux/clk.h>
  39 #include <linux/component.h>
  40 #include <linux/i2c.h>
  41 #include <linux/of_address.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/of_platform.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/rational.h>
  46 #include <linux/reset.h>
  47 #include <sound/dmaengine_pcm.h>
  48 #include <sound/pcm_drm_eld.h>
  49 #include <sound/pcm_params.h>
  50 #include <sound/soc.h>
  51 #include "media/cec.h"
  52 #include "vc4_drv.h"
  53 #include "vc4_hdmi.h"
  54 #include "vc4_hdmi_regs.h"
  55 #include "vc4_regs.h"
  56
  57 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  58 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  59 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  60 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  61 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  62 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  63
  64 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  65 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  66 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  67 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  68
  69 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  70 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  71 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  72 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  73 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  74 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  75
  76 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  77 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  78
  79 # define VC4_HD_M_SW_RST                        BIT(2)
  80 # define VC4_HD_M_ENABLE                        BIT(0)
  81
  82 #define CEC_CLOCK_FREQ 40000
  83 #define VC4_HSM_MID_CLOCK 149985000
  84
  85 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
  86 {
  87         struct drm_info_node *node = (struct drm_info_node *)m->private;
  88         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
  89         struct drm_printer p = drm_seq_file_printer(m);
  90
  91         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
  92         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
  93
  94         return 0;
  95 }
  96
  97 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
  98 {
  99         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 100         udelay(1);
 101         HDMI_WRITE(HDMI_M_CTL, 0);
 102
 103         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 104
 105         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 106                    VC4_HDMI_SW_RESET_HDMI |
 107                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 108
 109         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 110 }
 111
 112 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 113 {
 114         reset_control_reset(vc4_hdmi->reset);
 115
 116         HDMI_WRITE(HDMI_DVP_CTL, 0);
 117
 118         HDMI_WRITE(HDMI_CLOCK_STOP,
 119                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 120 }
 121
 122 static enum drm_connector_status
 123 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 124 {
 125         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 126
 127         if (vc4_hdmi->hpd_gpio) {
 128                 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
 129                     vc4_hdmi->hpd_active_low)
 130                         return connector_status_connected;
 131                 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 132                 return connector_status_disconnected;
 133         }
 134
 135         if (drm_probe_ddc(vc4_hdmi->ddc))
 136                 return connector_status_connected;
 137
 138         if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 139                 return connector_status_connected;
 140         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 141         return connector_status_disconnected;
 142 }
 143
 144 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 145 {
 146         drm_connector_unregister(connector);
 147         drm_connector_cleanup(connector);
 148 }
 149
 150 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 151 {
 152         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 153         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 154         int ret = 0;
 155         struct edid *edid;
 156
 157         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 158         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 159         if (!edid)
 160                 return -ENODEV;
 161
 162         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 163
 164         drm_connector_update_edid_property(connector, edid);
 165         ret = drm_add_edid_modes(connector, edid);
 166         kfree(edid);
 167
 168         return ret;
 169 }
 170
 171 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 172 {
 173         drm_atomic_helper_connector_reset(connector);
 174         drm_atomic_helper_connector_tv_reset(connector);
 175 }
 176
 177 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 178         .detect = vc4_hdmi_connector_detect,
 179         .fill_modes = drm_helper_probe_single_connector_modes,
 180         .destroy = vc4_hdmi_connector_destroy,
 181         .reset = vc4_hdmi_connector_reset,
 182         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 183         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 184 };
 185
 186 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 187         .get_modes = vc4_hdmi_connector_get_modes,
 188 };
 189
 190 static int vc4_hdmi_connector_init(struct drm_device *dev,
 191                                    struct vc4_hdmi *vc4_hdmi)
 192 {
 193         struct drm_connector *connector = &vc4_hdmi->connector;
 194         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 195         int ret;
 196
 197         drm_connector_init_with_ddc(dev, connector,
 198                                     &vc4_hdmi_connector_funcs,
 199                                     DRM_MODE_CONNECTOR_HDMIA,
 200                                     vc4_hdmi->ddc);
 201         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 202
 203         /* Create and attach TV margin props to this connector. */
 204         ret = drm_mode_create_tv_margin_properties(dev);
 205         if (ret)
 206                 return ret;
 207
 208         drm_connector_attach_tv_margin_properties(connector);
 209
 210         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 211                              DRM_CONNECTOR_POLL_DISCONNECT);
 212
 213         connector->interlace_allowed = 1;
 214         connector->doublescan_allowed = 0;
 215
 216         drm_connector_attach_encoder(connector, encoder);
 217
 218         return 0;
 219 }
 220
 221 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 222                                 enum hdmi_infoframe_type type)
 223 {
 224         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 225         u32 packet_id = type - 0x80;
 226
 227         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 228                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 229
 230         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 231                           BIT(packet_id)), 100);
 232 }
 233
 234 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 235                                      union hdmi_infoframe *frame)
 236 {
 237         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 238         u32 packet_id = frame->any.type - 0x80;
 239         const struct vc4_hdmi_register *ram_packet_start =
 240                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 241         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 242         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 243                                                        ram_packet_start->reg);
 244         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 245         ssize_t len, i;
 246         int ret;
 247
 248         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 249                     VC4_HDMI_RAM_PACKET_ENABLE),
 250                   "Packet RAM has to be on to store the packet.");
 251
 252         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 253         if (len < 0)
 254                 return;
 255
 256         ret = vc4_hdmi_stop_packet(encoder, frame->any.type);
 257         if (ret) {
 258                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 259                 return;
 260         }
 261
 262         for (i = 0; i < len; i += 7) {
 263                 writel(buffer[i + 0] << 0 |
 264                        buffer[i + 1] << 8 |
 265                        buffer[i + 2] << 16,
 266                        base + packet_reg);
 267                 packet_reg += 4;
 268
 269                 writel(buffer[i + 3] << 0 |
 270                        buffer[i + 4] << 8 |
 271                        buffer[i + 5] << 16 |
 272                        buffer[i + 6] << 24,
 273                        base + packet_reg);
 274                 packet_reg += 4;
 275         }
 276
 277         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 278                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 279         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 280                         BIT(packet_id)), 100);
 281         if (ret)
 282                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 283 }
 284
 285 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 286 {
 287         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 288         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 289         struct drm_connector *connector = &vc4_hdmi->connector;
 290         struct drm_connector_state *cstate = connector->state;
 291         struct drm_crtc *crtc = encoder->crtc;
 292         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 293         union hdmi_infoframe frame;
 294         int ret;
 295
 296         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 297                                                        connector, mode);
 298         if (ret < 0) {
 299                 DRM_ERROR("couldn't fill AVI infoframe\n");
 300                 return;
 301         }
 302
 303         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 304                                            connector, mode,
 305                                            vc4_encoder->limited_rgb_range ?
 306                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 307                                            HDMI_QUANTIZATION_RANGE_FULL);
 308
 309         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 310
 311         vc4_hdmi_write_infoframe(encoder, &frame);
 312 }
 313
 314 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 315 {
 316         union hdmi_infoframe frame;
 317         int ret;
 318
 319         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 320         if (ret < 0) {
 321                 DRM_ERROR("couldn't fill SPD infoframe\n");
 322                 return;
 323         }
 324
 325         frame.spd.sdi = HDMI_SPD_SDI_PC;
 326
 327         vc4_hdmi_write_infoframe(encoder, &frame);
 328 }
 329
 330 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 331 {
 332         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 333         union hdmi_infoframe frame;
 334         int ret;
 335
 336         ret = hdmi_audio_infoframe_init(&frame.audio);
 337
 338         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 339         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 340         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 341         frame.audio.channels = vc4_hdmi->audio.channels;
 342
 343         vc4_hdmi_write_infoframe(encoder, &frame);
 344 }
 345
 346 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 347 {
 348         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 349
 350         vc4_hdmi_set_avi_infoframe(encoder);
 351         vc4_hdmi_set_spd_infoframe(encoder);
 352         /*
 353          * If audio was streaming, then we need to reenabled the audio
 354          * infoframe here during encoder_enable.
 355          */
 356         if (vc4_hdmi->audio.streaming)
 357                 vc4_hdmi_set_audio_infoframe(encoder);
 358 }
 359
 360 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
 361 {
 362         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 363
 364         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 365
 366         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
 367                    VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
 368
 369         HDMI_WRITE(HDMI_VID_CTL,
 370                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 371 }
 372
 373 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)
 374 {
 375         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 376         int ret;
 377
 378         if (vc4_hdmi->variant->phy_disable)
 379                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 380
 381         HDMI_WRITE(HDMI_VID_CTL,
 382                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 383
 384         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 385         clk_disable_unprepare(vc4_hdmi->hsm_clock);
 386         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 387
 388         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 389         if (ret < 0)
 390                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 391 }
 392
 393 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 394 {
 395 }
 396
 397 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 398 {
 399         u32 csc_ctl;
 400
 401         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 402                                 VC4_HD_CSC_CTL_ORDER);
 403
 404         if (enable) {
 405                 /* CEA VICs other than #1 requre limited range RGB
 406                  * output unless overridden by an AVI infoframe.
 407                  * Apply a colorspace conversion to squash 0-255 down
 408                  * to 16-235.  The matrix here is:
 409                  *
 410                  * [ 0      0      0.8594 16]
 411                  * [ 0      0.8594 0      16]
 412                  * [ 0.8594 0      0      16]
 413                  * [ 0      0      0       1]
 414                  */
 415                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 416                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 417                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 418                                          VC4_HD_CSC_CTL_MODE);
 419
 420                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 421                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 422                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 423                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 424                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 425                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 426         }
 427
 428         /* The RGB order applies even when CSC is disabled. */
 429         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 430 }
 431
 432 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 433 {
 434         u32 csc_ctl;
 435
 436         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 437
 438         if (enable) {
 439                 /* CEA VICs other than #1 requre limited range RGB
 440                  * output unless overridden by an AVI infoframe.
 441                  * Apply a colorspace conversion to squash 0-255 down
 442                  * to 16-235.  The matrix here is:
 443                  *
 444                  * [ 0.8594 0      0      16]
 445                  * [ 0      0.8594 0      16]
 446                  * [ 0      0      0.8594 16]
 447                  * [ 0      0      0       1]
 448                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 449                  */
 450                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 451                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 452                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 453                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 454                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 455                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 456         } else {
 457                 /* Still use the matrix for full range, but make it unity.
 458                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 459                  */
 460                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 461                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 462                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 463                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 464                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 465                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 466         }
 467
 468         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 469 }
 470
 471 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 472                                  struct drm_display_mode *mode)
 473 {
 474         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 475         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 476         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 477         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 478         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 479                                    VC4_HDMI_VERTA_VSP) |
 480                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 481                                    VC4_HDMI_VERTA_VFP) |
 482                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 483         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 484                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 485                                    VC4_HDMI_VERTB_VBP));
 486         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 487                           VC4_SET_FIELD(mode->crtc_vtotal -
 488                                         mode->crtc_vsync_end -
 489                                         interlaced,
 490                                         VC4_HDMI_VERTB_VBP));
 491
 492         HDMI_WRITE(HDMI_HORZA,
 493                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 494                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 495                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 496                                  VC4_HDMI_HORZA_HAP));
 497
 498         HDMI_WRITE(HDMI_HORZB,
 499                    VC4_SET_FIELD((mode->htotal -
 500                                   mode->hsync_end) * pixel_rep,
 501                                  VC4_HDMI_HORZB_HBP) |
 502                    VC4_SET_FIELD((mode->hsync_end -
 503                                   mode->hsync_start) * pixel_rep,
 504                                  VC4_HDMI_HORZB_HSP) |
 505                    VC4_SET_FIELD((mode->hsync_start -
 506                                   mode->hdisplay) * pixel_rep,
 507                                  VC4_HDMI_HORZB_HFP));
 508
 509         HDMI_WRITE(HDMI_VERTA0, verta);
 510         HDMI_WRITE(HDMI_VERTA1, verta);
 511
 512         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 513         HDMI_WRITE(HDMI_VERTB1, vertb);
 514 }
 515 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 516                                  struct drm_display_mode *mode)
 517 {
 518         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 519         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 520         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 521         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 522         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 523                                    VC5_HDMI_VERTA_VSP) |
 524                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 525                                    VC5_HDMI_VERTA_VFP) |
 526                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 527         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 528                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 529                                    VC4_HDMI_VERTB_VBP));
 530         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 531                           VC4_SET_FIELD(mode->crtc_vtotal -
 532                                         mode->crtc_vsync_end -
 533                                         interlaced,
 534                                         VC4_HDMI_VERTB_VBP));
 535
 536         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 537         HDMI_WRITE(HDMI_HORZA,
 538                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 539                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 540                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 541                                  VC5_HDMI_HORZA_HAP) |
 542                    VC4_SET_FIELD((mode->hsync_start -
 543                                   mode->hdisplay) * pixel_rep,
 544                                  VC5_HDMI_HORZA_HFP));
 545
 546         HDMI_WRITE(HDMI_HORZB,
 547                    VC4_SET_FIELD((mode->htotal -
 548                                   mode->hsync_end) * pixel_rep,
 549                                  VC5_HDMI_HORZB_HBP) |
 550                    VC4_SET_FIELD((mode->hsync_end -
 551                                   mode->hsync_start) * pixel_rep,
 552                                  VC5_HDMI_HORZB_HSP));
 553
 554         HDMI_WRITE(HDMI_VERTA0, verta);
 555         HDMI_WRITE(HDMI_VERTA1, verta);
 556
 557         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 558         HDMI_WRITE(HDMI_VERTB1, vertb);
 559
 560         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 561 }
 562
 563 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 564 {
 565         u32 drift;
 566         int ret;
 567
 568         drift = HDMI_READ(HDMI_FIFO_CTL);
 569         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 570
 571         HDMI_WRITE(HDMI_FIFO_CTL,
 572                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 573         HDMI_WRITE(HDMI_FIFO_CTL,
 574                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 575         usleep_range(1000, 1100);
 576         HDMI_WRITE(HDMI_FIFO_CTL,
 577                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 578         HDMI_WRITE(HDMI_FIFO_CTL,
 579                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 580
 581         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 582                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 583         WARN_ONCE(ret, "Timeout waiting for "
 584                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 585 }
 586
 587 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder)
 588 {
 589         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 590         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 591         unsigned long pixel_rate, hsm_rate;
 592         int ret;
 593
 594         ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
 595         if (ret < 0) {
 596                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 597                 return;
 598         }
 599
 600         pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1);
 601         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 602         if (ret) {
 603                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 604                 return;
 605         }
 606
 607         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 608         if (ret) {
 609                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 610                 return;
 611         }
 612
 613         /*
 614          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 615          * be faster than pixel clock, infinitesimally faster, tested in
 616          * simulation. Otherwise, exact value is unimportant for HDMI
 617          * operation." This conflicts with bcm2835's vc4 documentation, which
 618          * states HSM's clock has to be at least 108% of the pixel clock.
 619          *
 620          * Real life tests reveal that vc4's firmware statement holds up, and
 621          * users are able to use pixel clocks closer to HSM's, namely for
 622          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 623          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 624          * 162MHz.
 625          *
 626          * Additionally, the AXI clock needs to be at least 25% of
 627          * pixel clock, but HSM ends up being the limiting factor.
 628          */
 629         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 630         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 631         if (ret) {
 632                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 633                 return;
 634         }
 635
 636         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
 637         if (ret) {
 638                 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret);
 639                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 640                 return;
 641         }
 642
 643         /*
 644          * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
 645          * at 300MHz.
 646          */
 647         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
 648                                (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
 649         if (ret) {
 650                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 651                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 652                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 653                 return;
 654         }
 655
 656         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 657         if (ret) {
 658                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 659                 clk_disable_unprepare(vc4_hdmi->hsm_clock);
 660                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 661                 return;
 662         }
 663
 664         if (vc4_hdmi->variant->reset)
 665                 vc4_hdmi->variant->reset(vc4_hdmi);
 666
 667         if (vc4_hdmi->variant->phy_init)
 668                 vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
 669
 670         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 671                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 672                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 673                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 674
 675         if (vc4_hdmi->variant->set_timings)
 676                 vc4_hdmi->variant->set_timings(vc4_hdmi, mode);
 677 }
 678
 679 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder)
 680 {
 681         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 682         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 683         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 684
 685         if (vc4_encoder->hdmi_monitor &&
 686             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 687                 if (vc4_hdmi->variant->csc_setup)
 688                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 689
 690                 vc4_encoder->limited_rgb_range = true;
 691         } else {
 692                 if (vc4_hdmi->variant->csc_setup)
 693                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
 694
 695                 vc4_encoder->limited_rgb_range = false;
 696         }
 697
 698         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 699 }
 700
 701 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
 702 {
 703         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 704         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 705         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 706         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 707         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 708         int ret;
 709
 710         HDMI_WRITE(HDMI_VID_CTL,
 711                    VC4_HD_VID_CTL_ENABLE |
 712                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 713                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
 714                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 715                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 716
 717         HDMI_WRITE(HDMI_VID_CTL,
 718                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
 719
 720         if (vc4_encoder->hdmi_monitor) {
 721                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 722                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 723                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 724
 725                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 726                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 727                 WARN_ONCE(ret, "Timeout waiting for "
 728                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 729         } else {
 730                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 731                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 732                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 733                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 734                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 735                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 736
 737                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 738                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 739                 WARN_ONCE(ret, "Timeout waiting for "
 740                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 741         }
 742
 743         if (vc4_encoder->hdmi_monitor) {
 744                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 745                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 746                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 747                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 748                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 749
 750                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 751                            VC4_HDMI_RAM_PACKET_ENABLE);
 752
 753                 vc4_hdmi_set_infoframes(encoder);
 754         }
 755
 756         vc4_hdmi_recenter_fifo(vc4_hdmi);
 757 }
 758
 759 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 760 {
 761 }
 762
 763 static enum drm_mode_status
 764 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 765                             const struct drm_display_mode *mode)
 766 {
 767         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 768
 769         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
 770                 return MODE_CLOCK_HIGH;
 771
 772         return MODE_OK;
 773 }
 774
 775 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 776         .mode_valid = vc4_hdmi_encoder_mode_valid,
 777         .disable = vc4_hdmi_encoder_disable,
 778         .enable = vc4_hdmi_encoder_enable,
 779 };
 780
 781 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 782 {
 783         int i;
 784         u32 channel_map = 0;
 785
 786         for (i = 0; i < 8; i++) {
 787                 if (channel_mask & BIT(i))
 788                         channel_map |= i << (3 * i);
 789         }
 790         return channel_map;
 791 }
 792
 793 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 794 {
 795         int i;
 796         u32 channel_map = 0;
 797
 798         for (i = 0; i < 8; i++) {
 799                 if (channel_mask & BIT(i))
 800                         channel_map |= i << (4 * i);
 801         }
 802         return channel_map;
 803 }
 804
 805 /* HDMI audio codec callbacks */
 806 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
 807 {
 808         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
 809         unsigned long n, m;
 810
 811         rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
 812                                     VC4_HD_MAI_SMP_N_MASK >>
 813                                     VC4_HD_MAI_SMP_N_SHIFT,
 814                                     (VC4_HD_MAI_SMP_M_MASK >>
 815                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
 816                                     &n, &m);
 817
 818         HDMI_WRITE(HDMI_MAI_SMP,
 819                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
 820                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
 821 }
 822
 823 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
 824 {
 825         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 826         struct drm_crtc *crtc = encoder->crtc;
 827         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 828         u32 samplerate = vc4_hdmi->audio.samplerate;
 829         u32 n, cts;
 830         u64 tmp;
 831
 832         n = 128 * samplerate / 1000;
 833         tmp = (u64)(mode->clock * 1000) * n;
 834         do_div(tmp, 128 * samplerate);
 835         cts = tmp;
 836
 837         HDMI_WRITE(HDMI_CRP_CFG,
 838                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
 839                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
 840
 841         /*
 842          * We could get slightly more accurate clocks in some cases by
 843          * providing a CTS_1 value.  The two CTS values are alternated
 844          * between based on the period fields
 845          */
 846         HDMI_WRITE(HDMI_CTS_0, cts);
 847         HDMI_WRITE(HDMI_CTS_1, cts);
 848 }
 849
 850 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
 851 {
 852         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
 853
 854         return snd_soc_card_get_drvdata(card);
 855 }
 856
 857 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
 858                                   struct snd_soc_dai *dai)
 859 {
 860         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 861         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 862         struct drm_connector *connector = &vc4_hdmi->connector;
 863         int ret;
 864
 865         if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
 866                 return -EINVAL;
 867
 868         vc4_hdmi->audio.substream = substream;
 869
 870         /*
 871          * If the HDMI encoder hasn't probed, or the encoder is
 872          * currently in DVI mode, treat the codec dai as missing.
 873          */
 874         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 875                                 VC4_HDMI_RAM_PACKET_ENABLE))
 876                 return -ENODEV;
 877
 878         ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
 879         if (ret)
 880                 return ret;
 881
 882         return 0;
 883 }
 884
 885 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 886 {
 887         return 0;
 888 }
 889
 890 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
 891 {
 892         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 893         struct device *dev = &vc4_hdmi->pdev->dev;
 894         int ret;
 895
 896         vc4_hdmi->audio.streaming = false;
 897         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO);
 898         if (ret)
 899                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
 900
 901         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
 902         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
 903         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
 904 }
 905
 906 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
 907                                     struct snd_soc_dai *dai)
 908 {
 909         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 910
 911         if (substream != vc4_hdmi->audio.substream)
 912                 return;
 913
 914         vc4_hdmi_audio_reset(vc4_hdmi);
 915
 916         vc4_hdmi->audio.substream = NULL;
 917 }
 918
 919 /* HDMI audio codec callbacks */
 920 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
 921                                     struct snd_pcm_hw_params *params,
 922                                     struct snd_soc_dai *dai)
 923 {
 924         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 925         struct device *dev = &vc4_hdmi->pdev->dev;
 926         u32 audio_packet_config, channel_mask;
 927         u32 channel_map;
 928
 929         if (substream != vc4_hdmi->audio.substream)
 930                 return -EINVAL;
 931
 932         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
 933                 params_rate(params), params_width(params),
 934                 params_channels(params));
 935
 936         vc4_hdmi->audio.channels = params_channels(params);
 937         vc4_hdmi->audio.samplerate = params_rate(params);
 938
 939         HDMI_WRITE(HDMI_MAI_CTL,
 940                    VC4_HD_MAI_CTL_RESET |
 941                    VC4_HD_MAI_CTL_FLUSH |
 942                    VC4_HD_MAI_CTL_DLATE |
 943                    VC4_HD_MAI_CTL_ERRORE |
 944                    VC4_HD_MAI_CTL_ERRORF);
 945
 946         vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
 947
 948         /* The B frame identifier should match the value used by alsa-lib (8) */
 949         audio_packet_config =
 950                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
 951                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
 952                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
 953
 954         channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
 955         audio_packet_config |= VC4_SET_FIELD(channel_mask,
 956                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
 957
 958         /* Set the MAI threshold.  This logic mimics the firmware's. */
 959         if (vc4_hdmi->audio.samplerate > 96000) {
 960                 HDMI_WRITE(HDMI_MAI_THR,
 961                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
 962                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 963         } else if (vc4_hdmi->audio.samplerate > 48000) {
 964                 HDMI_WRITE(HDMI_MAI_THR,
 965                            VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
 966                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
 967         } else {
 968                 HDMI_WRITE(HDMI_MAI_THR,
 969                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
 970                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
 971                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
 972                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
 973         }
 974
 975         HDMI_WRITE(HDMI_MAI_CONFIG,
 976                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
 977                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
 978
 979         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
 980         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
 981         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
 982         vc4_hdmi_set_n_cts(vc4_hdmi);
 983
 984         return 0;
 985 }
 986
 987 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
 988                                   struct snd_soc_dai *dai)
 989 {
 990         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
 991         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 992
 993         switch (cmd) {
 994         case SNDRV_PCM_TRIGGER_START:
 995                 vc4_hdmi_set_audio_infoframe(encoder);
 996                 vc4_hdmi->audio.streaming = true;
 997
 998                 if (vc4_hdmi->variant->phy_rng_enable)
 999                         vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1000
1001                 HDMI_WRITE(HDMI_MAI_CTL,
1002                            VC4_SET_FIELD(vc4_hdmi->audio.channels,
1003                                          VC4_HD_MAI_CTL_CHNUM) |
1004                            VC4_HD_MAI_CTL_ENABLE);
1005                 break;
1006         case SNDRV_PCM_TRIGGER_STOP:
1007                 HDMI_WRITE(HDMI_MAI_CTL,
1008                            VC4_HD_MAI_CTL_DLATE |
1009                            VC4_HD_MAI_CTL_ERRORE |
1010                            VC4_HD_MAI_CTL_ERRORF);
1011
1012                 if (vc4_hdmi->variant->phy_rng_disable)
1013                         vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1014
1015                 vc4_hdmi->audio.streaming = false;
1016
1017                 break;
1018         default:
1019                 break;
1020         }
1021
1022         return 0;
1023 }
1024
1025 static inline struct vc4_hdmi *
1026 snd_component_to_hdmi(struct snd_soc_component *component)
1027 {
1028         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1029
1030         return snd_soc_card_get_drvdata(card);
1031 }
1032
1033 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1034                                        struct snd_ctl_elem_info *uinfo)
1035 {
1036         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1037         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1038         struct drm_connector *connector = &vc4_hdmi->connector;
1039
1040         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1041         uinfo->count = sizeof(connector->eld);
1042
1043         return 0;
1044 }
1045
1046 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1047                                       struct snd_ctl_elem_value *ucontrol)
1048 {
1049         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1050         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1051         struct drm_connector *connector = &vc4_hdmi->connector;
1052
1053         memcpy(ucontrol->value.bytes.data, connector->eld,
1054                sizeof(connector->eld));
1055
1056         return 0;
1057 }
1058
1059 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1060         {
1061                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1062                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1063                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1064                 .name = "ELD",
1065                 .info = vc4_hdmi_audio_eld_ctl_info,
1066                 .get = vc4_hdmi_audio_eld_ctl_get,
1067         },
1068 };
1069
1070 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1071         SND_SOC_DAPM_OUTPUT("TX"),
1072 };
1073
1074 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1075         { "TX", NULL, "Playback" },
1076 };
1077
1078 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1079         .controls               = vc4_hdmi_audio_controls,
1080         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
1081         .dapm_widgets           = vc4_hdmi_audio_widgets,
1082         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1083         .dapm_routes            = vc4_hdmi_audio_routes,
1084         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1085         .idle_bias_on           = 1,
1086         .use_pmdown_time        = 1,
1087         .endianness             = 1,
1088         .non_legacy_dai_naming  = 1,
1089 };
1090
1091 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1092         .startup = vc4_hdmi_audio_startup,
1093         .shutdown = vc4_hdmi_audio_shutdown,
1094         .hw_params = vc4_hdmi_audio_hw_params,
1095         .set_fmt = vc4_hdmi_audio_set_fmt,
1096         .trigger = vc4_hdmi_audio_trigger,
1097 };
1098
1099 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1100         .name = "vc4-hdmi-hifi",
1101         .playback = {
1102                 .stream_name = "Playback",
1103                 .channels_min = 2,
1104                 .channels_max = 8,
1105                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1106                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1107                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1108                          SNDRV_PCM_RATE_192000,
1109                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1110         },
1111 };
1112
1113 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1114         .name = "vc4-hdmi-cpu-dai-component",
1115 };
1116
1117 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1118 {
1119         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1120
1121         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1122
1123         return 0;
1124 }
1125
1126 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1127         .name = "vc4-hdmi-cpu-dai",
1128         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1129         .playback = {
1130                 .stream_name = "Playback",
1131                 .channels_min = 1,
1132                 .channels_max = 8,
1133                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1134                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1135                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1136                          SNDRV_PCM_RATE_192000,
1137                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1138         },
1139         .ops = &vc4_hdmi_audio_dai_ops,
1140 };
1141
1142 static const struct snd_dmaengine_pcm_config pcm_conf = {
1143         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1144         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1145 };
1146
1147 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1148 {
1149         const struct vc4_hdmi_register *mai_data =
1150                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1151         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1152         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1153         struct device *dev = &vc4_hdmi->pdev->dev;
1154         const __be32 *addr;
1155         int index;
1156         int ret;
1157
1158         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1159                 dev_warn(dev,
1160                          "'dmas' DT property is missing, no HDMI audio\n");
1161                 return 0;
1162         }
1163
1164         if (mai_data->reg != VC4_HD) {
1165                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1166                 return -EINVAL;
1167         }
1168
1169         /*
1170          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1171          * the bus address specified in the DT, because the physical address
1172          * (the one returned by platform_get_resource()) is not appropriate
1173          * for DMA transfers.
1174          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1175          */
1176         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1177         /* Before BCM2711, we don't have a named register range */
1178         if (index < 0)
1179                 index = 1;
1180
1181         addr = of_get_address(dev->of_node, index, NULL, NULL);
1182
1183         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1184         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1185         vc4_hdmi->audio.dma_data.maxburst = 2;
1186
1187         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1188         if (ret) {
1189                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1190                 return ret;
1191         }
1192
1193         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1194                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1195         if (ret) {
1196                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1197                 return ret;
1198         }
1199
1200         /* register component and codec dai */
1201         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1202                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1203         if (ret) {
1204                 dev_err(dev, "Could not register component: %d\n", ret);
1205                 return ret;
1206         }
1207
1208         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1209         dai_link->codecs        = &vc4_hdmi->audio.codec;
1210         dai_link->platforms     = &vc4_hdmi->audio.platform;
1211
1212         dai_link->num_cpus      = 1;
1213         dai_link->num_codecs    = 1;
1214         dai_link->num_platforms = 1;
1215
1216         dai_link->name = "MAI";
1217         dai_link->stream_name = "MAI PCM";
1218         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1219         dai_link->cpus->dai_name = dev_name(dev);
1220         dai_link->codecs->name = dev_name(dev);
1221         dai_link->platforms->name = dev_name(dev);
1222
1223         card->dai_link = dai_link;
1224         card->num_links = 1;
1225         card->name = vc4_hdmi->variant->card_name;
1226         card->dev = dev;
1227         card->owner = THIS_MODULE;
1228
1229         /*
1230          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1231          * stores a pointer to the snd card object in dev->driver_data. This
1232          * means we cannot use it for something else. The hdmi back-pointer is
1233          * now stored in card->drvdata and should be retrieved with
1234          * snd_soc_card_get_drvdata() if needed.
1235          */
1236         snd_soc_card_set_drvdata(card, vc4_hdmi);
1237         ret = devm_snd_soc_register_card(dev, card);
1238         if (ret)
1239                 dev_err(dev, "Could not register sound card: %d\n", ret);
1240
1241         return ret;
1242
1243 }
1244
1245 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1246 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1247 {
1248         struct vc4_hdmi *vc4_hdmi = priv;
1249
1250         if (vc4_hdmi->cec_irq_was_rx) {
1251                 if (vc4_hdmi->cec_rx_msg.len)
1252                         cec_received_msg(vc4_hdmi->cec_adap,
1253                                          &vc4_hdmi->cec_rx_msg);
1254         } else if (vc4_hdmi->cec_tx_ok) {
1255                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1256                                   0, 0, 0, 0);
1257         } else {
1258                 /*
1259                  * This CEC implementation makes 1 retry, so if we
1260                  * get a NACK, then that means it made 2 attempts.
1261                  */
1262                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1263                                   0, 2, 0, 0);
1264         }
1265         return IRQ_HANDLED;
1266 }
1267
1268 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1269 {
1270         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1271         unsigned int i;
1272
1273         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1274                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1275         for (i = 0; i < msg->len; i += 4) {
1276                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + i);
1277
1278                 msg->msg[i] = val & 0xff;
1279                 msg->msg[i + 1] = (val >> 8) & 0xff;
1280                 msg->msg[i + 2] = (val >> 16) & 0xff;
1281                 msg->msg[i + 3] = (val >> 24) & 0xff;
1282         }
1283 }
1284
1285 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1286 {
1287         struct vc4_hdmi *vc4_hdmi = priv;
1288         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1289         u32 cntrl1, cntrl5;
1290
1291         if (!(stat & VC4_HDMI_CPU_CEC))
1292                 return IRQ_NONE;
1293         vc4_hdmi->cec_rx_msg.len = 0;
1294         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1295         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1296         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1297         if (vc4_hdmi->cec_irq_was_rx) {
1298                 vc4_cec_read_msg(vc4_hdmi, cntrl1);
1299                 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1300                 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1301                 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1302         } else {
1303                 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1304                 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1305         }
1306         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1307         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1308
1309         return IRQ_WAKE_THREAD;
1310 }
1311
1312 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1313 {
1314         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1315         /* clock period in microseconds */
1316         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1317         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1318
1319         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1320                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1321                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1322         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1323                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1324
1325         if (enable) {
1326                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1327                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1328                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1329                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1330                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1331                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1332                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1333                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1334                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1335                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1336                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1337                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1338                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1339                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1340                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1341                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1342                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1343                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1344                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1345
1346                 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1347         } else {
1348                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1349                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1350                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1351         }
1352         return 0;
1353 }
1354
1355 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1356 {
1357         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1358
1359         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1360                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1361                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1362         return 0;
1363 }
1364
1365 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1366                                       u32 signal_free_time, struct cec_msg *msg)
1367 {
1368         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1369         u32 val;
1370         unsigned int i;
1371
1372         for (i = 0; i < msg->len; i += 4)
1373                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + i,
1374                            (msg->msg[i]) |
1375                            (msg->msg[i + 1] << 8) |
1376                            (msg->msg[i + 2] << 16) |
1377                            (msg->msg[i + 3] << 24));
1378
1379         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1380         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1381         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1382         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1383         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1384         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1385
1386         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1387         return 0;
1388 }
1389
1390 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1391         .adap_enable = vc4_hdmi_cec_adap_enable,
1392         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1393         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1394 };
1395
1396 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1397 {
1398         struct cec_connector_info conn_info;
1399         struct platform_device *pdev = vc4_hdmi->pdev;
1400         u32 value;
1401         int ret;
1402
1403         if (!vc4_hdmi->variant->cec_available)
1404                 return 0;
1405
1406         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1407                                                   vc4_hdmi, "vc4",
1408                                                   CEC_CAP_DEFAULTS |
1409                                                   CEC_CAP_CONNECTOR_INFO, 1);
1410         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1411         if (ret < 0)
1412                 return ret;
1413
1414         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1415         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1416
1417         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1418         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1419         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
1420         /*
1421          * Set the logical address to Unregistered and set the clock
1422          * divider: the hsm_clock rate and this divider setting will
1423          * give a 40 kHz CEC clock.
1424          */
1425         value |= VC4_HDMI_CEC_ADDR_MASK |
1426                  (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT);
1427         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1428         ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1429                                         vc4_cec_irq_handler,
1430                                         vc4_cec_irq_handler_thread, 0,
1431                                         "vc4 hdmi cec", vc4_hdmi);
1432         if (ret)
1433                 goto err_delete_cec_adap;
1434
1435         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1436         if (ret < 0)
1437                 goto err_delete_cec_adap;
1438
1439         return 0;
1440
1441 err_delete_cec_adap:
1442         cec_delete_adapter(vc4_hdmi->cec_adap);
1443
1444         return ret;
1445 }
1446
1447 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1448 {
1449         cec_unregister_adapter(vc4_hdmi->cec_adap);
1450 }
1451 #else
1452 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1453 {
1454         return 0;
1455 }
1456
1457 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1458
1459 #endif
1460
1461 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1462                                  struct debugfs_regset32 *regset,
1463                                  enum vc4_hdmi_regs reg)
1464 {
1465         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1466         struct debugfs_reg32 *regs, *new_regs;
1467         unsigned int count = 0;
1468         unsigned int i;
1469
1470         regs = kcalloc(variant->num_registers, sizeof(*regs),
1471                        GFP_KERNEL);
1472         if (!regs)
1473                 return -ENOMEM;
1474
1475         for (i = 0; i < variant->num_registers; i++) {
1476                 const struct vc4_hdmi_register *field = &variant->registers[i];
1477
1478                 if (field->reg != reg)
1479                         continue;
1480
1481                 regs[count].name = field->name;
1482                 regs[count].offset = field->offset;
1483                 count++;
1484         }
1485
1486         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1487         if (!new_regs)
1488                 return -ENOMEM;
1489
1490         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1491         regset->regs = new_regs;
1492         regset->nregs = count;
1493
1494         return 0;
1495 }
1496
1497 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1498 {
1499         struct platform_device *pdev = vc4_hdmi->pdev;
1500         struct device *dev = &pdev->dev;
1501         int ret;
1502
1503         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1504         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1505                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1506
1507         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1508         if (IS_ERR(vc4_hdmi->hd_regs))
1509                 return PTR_ERR(vc4_hdmi->hd_regs);
1510
1511         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1512         if (ret)
1513                 return ret;
1514
1515         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1516         if (ret)
1517                 return ret;
1518
1519         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1520         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1521                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1522                 if (ret != -EPROBE_DEFER)
1523                         DRM_ERROR("Failed to get pixel clock\n");
1524                 return ret;
1525         }
1526
1527         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1528         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1529                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1530                 return PTR_ERR(vc4_hdmi->hsm_clock);
1531         }
1532         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1533
1534         return 0;
1535 }
1536
1537 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1538 {
1539         struct platform_device *pdev = vc4_hdmi->pdev;
1540         struct device *dev = &pdev->dev;
1541         struct resource *res;
1542
1543         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1544         if (!res)
1545                 return -ENODEV;
1546
1547         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1548                                                resource_size(res));
1549         if (!vc4_hdmi->hdmicore_regs)
1550                 return -ENOMEM;
1551
1552         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1553         if (!res)
1554                 return -ENODEV;
1555
1556         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1557         if (!vc4_hdmi->hd_regs)
1558                 return -ENOMEM;
1559
1560         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1561         if (!res)
1562                 return -ENODEV;
1563
1564         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1565         if (!vc4_hdmi->cec_regs)
1566                 return -ENOMEM;
1567
1568         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1569         if (!res)
1570                 return -ENODEV;
1571
1572         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1573         if (!vc4_hdmi->csc_regs)
1574                 return -ENOMEM;
1575
1576         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1577         if (!res)
1578                 return -ENODEV;
1579
1580         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1581         if (!vc4_hdmi->dvp_regs)
1582                 return -ENOMEM;
1583
1584         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1585         if (!res)
1586                 return -ENODEV;
1587
1588         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1589         if (!vc4_hdmi->phy_regs)
1590                 return -ENOMEM;
1591
1592         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1593         if (!res)
1594                 return -ENODEV;
1595
1596         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1597         if (!vc4_hdmi->ram_regs)
1598                 return -ENOMEM;
1599
1600         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1601         if (!res)
1602                 return -ENODEV;
1603
1604         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1605         if (!vc4_hdmi->rm_regs)
1606                 return -ENOMEM;
1607
1608         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1609         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1610                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1611                 return PTR_ERR(vc4_hdmi->hsm_clock);
1612         }
1613
1614         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1615         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1616                 DRM_ERROR("Failed to get pixel bvb clock\n");
1617                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1618         }
1619
1620         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1621         if (IS_ERR(vc4_hdmi->audio_clock)) {
1622                 DRM_ERROR("Failed to get audio clock\n");
1623                 return PTR_ERR(vc4_hdmi->audio_clock);
1624         }
1625
1626         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1627         if (IS_ERR(vc4_hdmi->reset)) {
1628                 DRM_ERROR("Failed to get HDMI reset line\n");
1629                 return PTR_ERR(vc4_hdmi->reset);
1630         }
1631
1632         return 0;
1633 }
1634
1635 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1636 {
1637         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1638         struct platform_device *pdev = to_platform_device(dev);
1639         struct drm_device *drm = dev_get_drvdata(master);
1640         struct vc4_hdmi *vc4_hdmi;
1641         struct drm_encoder *encoder;
1642         struct device_node *ddc_node;
1643         u32 value;
1644         int ret;
1645
1646         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1647         if (!vc4_hdmi)
1648                 return -ENOMEM;
1649
1650         dev_set_drvdata(dev, vc4_hdmi);
1651         encoder = &vc4_hdmi->encoder.base.base;
1652         vc4_hdmi->encoder.base.type = variant->encoder_type;
1653         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1654         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1655         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1656         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1657         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1658         vc4_hdmi->pdev = pdev;
1659         vc4_hdmi->variant = variant;
1660
1661         ret = variant->init_resources(vc4_hdmi);
1662         if (ret)
1663                 return ret;
1664
1665         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1666         if (!ddc_node) {
1667                 DRM_ERROR("Failed to find ddc node in device tree\n");
1668                 return -ENODEV;
1669         }
1670
1671         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1672         of_node_put(ddc_node);
1673         if (!vc4_hdmi->ddc) {
1674                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1675                 return -EPROBE_DEFER;
1676         }
1677
1678         /* Only use the GPIO HPD pin if present in the DT, otherwise
1679          * we'll use the HDMI core's register.
1680          */
1681         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1682                 enum of_gpio_flags hpd_gpio_flags;
1683
1684                 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1685                                                              "hpd-gpios", 0,
1686                                                              &hpd_gpio_flags);
1687                 if (vc4_hdmi->hpd_gpio < 0) {
1688                         ret = vc4_hdmi->hpd_gpio;
1689                         goto err_unprepare_hsm;
1690                 }
1691
1692                 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
1693         }
1694
1695         pm_runtime_enable(dev);
1696
1697         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
1698         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
1699
1700         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
1701         if (ret)
1702                 goto err_destroy_encoder;
1703
1704         ret = vc4_hdmi_cec_init(vc4_hdmi);
1705         if (ret)
1706                 goto err_destroy_conn;
1707
1708         ret = vc4_hdmi_audio_init(vc4_hdmi);
1709         if (ret)
1710                 goto err_free_cec;
1711
1712         vc4_debugfs_add_file(drm, variant->debugfs_name,
1713                              vc4_hdmi_debugfs_regs,
1714                              vc4_hdmi);
1715
1716         return 0;
1717
1718 err_free_cec:
1719         vc4_hdmi_cec_exit(vc4_hdmi);
1720 err_destroy_conn:
1721         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1722 err_destroy_encoder:
1723         drm_encoder_cleanup(encoder);
1724 err_unprepare_hsm:
1725         pm_runtime_disable(dev);
1726         put_device(&vc4_hdmi->ddc->dev);
1727
1728         return ret;
1729 }
1730
1731 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
1732                             void *data)
1733 {
1734         struct vc4_hdmi *vc4_hdmi;
1735
1736         /*
1737          * ASoC makes it a bit hard to retrieve a pointer to the
1738          * vc4_hdmi structure. Registering the card will overwrite our
1739          * device drvdata with a pointer to the snd_soc_card structure,
1740          * which can then be used to retrieve whatever drvdata we want
1741          * to associate.
1742          *
1743          * However, that doesn't fly in the case where we wouldn't
1744          * register an ASoC card (because of an old DT that is missing
1745          * the dmas properties for example), then the card isn't
1746          * registered and the device drvdata wouldn't be set.
1747          *
1748          * We can deal with both cases by making sure a snd_soc_card
1749          * pointer and a vc4_hdmi structure are pointing to the same
1750          * memory address, so we can treat them indistinctly without any
1751          * issue.
1752          */
1753         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
1754         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
1755         vc4_hdmi = dev_get_drvdata(dev);
1756
1757         kfree(vc4_hdmi->hdmi_regset.regs);
1758         kfree(vc4_hdmi->hd_regset.regs);
1759
1760         vc4_hdmi_cec_exit(vc4_hdmi);
1761         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
1762         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
1763
1764         pm_runtime_disable(dev);
1765
1766         put_device(&vc4_hdmi->ddc->dev);
1767 }
1768
1769 static const struct component_ops vc4_hdmi_ops = {
1770         .bind   = vc4_hdmi_bind,
1771         .unbind = vc4_hdmi_unbind,
1772 };
1773
1774 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
1775 {
1776         return component_add(&pdev->dev, &vc4_hdmi_ops);
1777 }
1778
1779 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
1780 {
1781         component_del(&pdev->dev, &vc4_hdmi_ops);
1782         return 0;
1783 }
1784
1785 static const struct vc4_hdmi_variant bcm2835_variant = {
1786         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
1787         .debugfs_name           = "hdmi_regs",
1788         .card_name              = "vc4-hdmi",
1789         .max_pixel_clock        = 162000000,
1790         .cec_available          = true,
1791         .registers              = vc4_hdmi_fields,
1792         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
1793
1794         .init_resources         = vc4_hdmi_init_resources,
1795         .csc_setup              = vc4_hdmi_csc_setup,
1796         .reset                  = vc4_hdmi_reset,
1797         .set_timings            = vc4_hdmi_set_timings,
1798         .phy_init               = vc4_hdmi_phy_init,
1799         .phy_disable            = vc4_hdmi_phy_disable,
1800         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
1801         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
1802         .channel_map            = vc4_hdmi_channel_map,
1803 };
1804
1805 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
1806         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
1807         .debugfs_name           = "hdmi0_regs",
1808         .card_name              = "vc4-hdmi-0",
1809         .max_pixel_clock        = 297000000,
1810         .registers              = vc5_hdmi_hdmi0_fields,
1811         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
1812         .phy_lane_mapping       = {
1813                 PHY_LANE_0,
1814                 PHY_LANE_1,
1815                 PHY_LANE_2,
1816                 PHY_LANE_CK,
1817         },
1818
1819         .init_resources         = vc5_hdmi_init_resources,
1820         .csc_setup              = vc5_hdmi_csc_setup,
1821         .reset                  = vc5_hdmi_reset,
1822         .set_timings            = vc5_hdmi_set_timings,
1823         .phy_init               = vc5_hdmi_phy_init,
1824         .phy_disable            = vc5_hdmi_phy_disable,
1825         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
1826         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
1827         .channel_map            = vc5_hdmi_channel_map,
1828 };
1829
1830 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
1831         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
1832         .debugfs_name           = "hdmi1_regs",
1833         .card_name              = "vc4-hdmi-1",
1834         .max_pixel_clock        = 297000000,
1835         .registers              = vc5_hdmi_hdmi1_fields,
1836         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
1837         .phy_lane_mapping       = {
1838                 PHY_LANE_1,
1839                 PHY_LANE_0,
1840                 PHY_LANE_CK,
1841                 PHY_LANE_2,
1842         },
1843
1844         .init_resources         = vc5_hdmi_init_resources,
1845         .csc_setup              = vc5_hdmi_csc_setup,
1846         .reset                  = vc5_hdmi_reset,
1847         .set_timings            = vc5_hdmi_set_timings,
1848         .phy_init               = vc5_hdmi_phy_init,
1849         .phy_disable            = vc5_hdmi_phy_disable,
1850         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
1851         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
1852         .channel_map            = vc5_hdmi_channel_map,
1853 };
1854
1855 static const struct of_device_id vc4_hdmi_dt_match[] = {
1856         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
1857         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
1858         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
1859         {}
1860 };
1861
1862 struct platform_driver vc4_hdmi_driver = {
1863         .probe = vc4_hdmi_dev_probe,
1864         .remove = vc4_hdmi_dev_remove,
1865         .driver = {
1866                 .name = "vc4_hdmi",
1867                 .of_match_table = vc4_hdmi_dt_match,
1868         },
1869 };