drivers/gpu/drm/vc4/vc4_hdmi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Broadcom
   4  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   5  * Copyright (C) 2013 Red Hat
   6  * Author: Rob Clark <robdclark@gmail.com>
   7  */
   8
   9 /**
  10  * DOC: VC4 Falcon HDMI module
  11  *
  12  * The HDMI core has a state machine and a PHY.  On BCM2835, most of
  13  * the unit operates off of the HSM clock from CPRMAN.  It also
  14  * internally uses the PLLH_PIX clock for the PHY.
  15  *
  16  * HDMI infoframes are kept within a small packet ram, where each
  17  * packet can be individually enabled for including in a frame.
  18  *
  19  * HDMI audio is implemented entirely within the HDMI IP block.  A
  20  * register in the HDMI encoder takes SPDIF frames from the DMA engine
  21  * and transfers them over an internal MAI (multi-channel audio
  22  * interconnect) bus to the encoder side for insertion into the video
  23  * blank regions.
  24  *
  25  * The driver's HDMI encoder does not yet support power management.
  26  * The HDMI encoder's power domain and the HSM/pixel clocks are kept
  27  * continuously running, and only the HDMI logic and packet ram are
  28  * powered off/on at disable/enable time.
  29  *
  30  * The driver does not yet support CEC control, though the HDMI
  31  * encoder block has CEC support.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_edid.h>
  36 #include <drm/drm_probe_helper.h>
  37 #include <drm/drm_simple_kms_helper.h>
  38 #include <linux/clk.h>
  39 #include <linux/component.h>
  40 #include <linux/i2c.h>
  41 #include <linux/of_address.h>
  42 #include <linux/of_gpio.h>
  43 #include <linux/of_platform.h>
  44 #include <linux/pm_runtime.h>
  45 #include <linux/rational.h>
  46 #include <linux/reset.h>
  47 #include <sound/dmaengine_pcm.h>
  48 #include <sound/pcm_drm_eld.h>
  49 #include <sound/pcm_params.h>
  50 #include <sound/soc.h>
  51 #include "media/cec.h"
  52 #include "vc4_drv.h"
  53 #include "vc4_hdmi.h"
  54 #include "vc4_hdmi_regs.h"
  55 #include "vc4_regs.h"
  56
  57 #define VC5_HDMI_HORZA_HFP_SHIFT                16
  58 #define VC5_HDMI_HORZA_HFP_MASK                 VC4_MASK(28, 16)
  59 #define VC5_HDMI_HORZA_VPOS                     BIT(15)
  60 #define VC5_HDMI_HORZA_HPOS                     BIT(14)
  61 #define VC5_HDMI_HORZA_HAP_SHIFT                0
  62 #define VC5_HDMI_HORZA_HAP_MASK                 VC4_MASK(13, 0)
  63
  64 #define VC5_HDMI_HORZB_HBP_SHIFT                16
  65 #define VC5_HDMI_HORZB_HBP_MASK                 VC4_MASK(26, 16)
  66 #define VC5_HDMI_HORZB_HSP_SHIFT                0
  67 #define VC5_HDMI_HORZB_HSP_MASK                 VC4_MASK(10, 0)
  68
  69 #define VC5_HDMI_VERTA_VSP_SHIFT                24
  70 #define VC5_HDMI_VERTA_VSP_MASK                 VC4_MASK(28, 24)
  71 #define VC5_HDMI_VERTA_VFP_SHIFT                16
  72 #define VC5_HDMI_VERTA_VFP_MASK                 VC4_MASK(22, 16)
  73 #define VC5_HDMI_VERTA_VAL_SHIFT                0
  74 #define VC5_HDMI_VERTA_VAL_MASK                 VC4_MASK(12, 0)
  75
  76 #define VC5_HDMI_VERTB_VSPO_SHIFT               16
  77 #define VC5_HDMI_VERTB_VSPO_MASK                VC4_MASK(29, 16)
  78
  79 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT      8
  80 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK       VC4_MASK(10, 8)
  81
  82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT          0
  83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK           VC4_MASK(3, 0)
  84
  85 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE          BIT(31)
  86
  87 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT  8
  88 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK   VC4_MASK(15, 8)
  89
  90 # define VC4_HD_M_SW_RST                        BIT(2)
  91 # define VC4_HD_M_ENABLE                        BIT(0)
  92
  93 #define CEC_CLOCK_FREQ 40000
  94 #define VC4_HSM_MID_CLOCK 149985000
  95
  96 #define HDMI_14_MAX_TMDS_CLK   (340 * 1000 * 1000)
  97
  98 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
  99 {
 100         struct drm_info_node *node = (struct drm_info_node *)m->private;
 101         struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
 102         struct drm_printer p = drm_seq_file_printer(m);
 103
 104         drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
 105         drm_print_regset32(&p, &vc4_hdmi->hd_regset);
 106
 107         return 0;
 108 }
 109
 110 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 111 {
 112         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
 113         udelay(1);
 114         HDMI_WRITE(HDMI_M_CTL, 0);
 115
 116         HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
 117
 118         HDMI_WRITE(HDMI_SW_RESET_CONTROL,
 119                    VC4_HDMI_SW_RESET_HDMI |
 120                    VC4_HDMI_SW_RESET_FORMAT_DETECT);
 121
 122         HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
 123 }
 124
 125 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
 126 {
 127         reset_control_reset(vc4_hdmi->reset);
 128
 129         HDMI_WRITE(HDMI_DVP_CTL, 0);
 130
 131         HDMI_WRITE(HDMI_CLOCK_STOP,
 132                    HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
 133 }
 134
 135 #ifdef CONFIG_DRM_VC4_HDMI_CEC
 136 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
 137 {
 138         u16 clk_cnt;
 139         u32 value;
 140
 141         value = HDMI_READ(HDMI_CEC_CNTRL_1);
 142         value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
 143
 144         /*
 145          * Set the clock divider: the hsm_clock rate and this divider
 146          * setting will give a 40 kHz CEC clock.
 147          */
 148         clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ;
 149         value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
 150         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
 151 }
 152 #else
 153 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
 154 #endif
 155
 156 static enum drm_connector_status
 157 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 158 {
 159         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 160         bool connected = false;
 161
 162         WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
 163
 164         if (vc4_hdmi->hpd_gpio) {
 165                 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^
 166                     vc4_hdmi->hpd_active_low)
 167                         connected = true;
 168         } else if (drm_probe_ddc(vc4_hdmi->ddc)) {
 169                 connected = true;
 170         } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) {
 171                 connected = true;
 172         }
 173
 174         if (connected) {
 175                 if (connector->status != connector_status_connected) {
 176                         struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
 177
 178                         if (edid) {
 179                                 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 180                                 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid);
 181                                 kfree(edid);
 182                         }
 183                 }
 184
 185                 pm_runtime_put(&vc4_hdmi->pdev->dev);
 186                 return connector_status_connected;
 187         }
 188
 189         cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
 190         pm_runtime_put(&vc4_hdmi->pdev->dev);
 191         return connector_status_disconnected;
 192 }
 193
 194 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 195 {
 196         drm_connector_unregister(connector);
 197         drm_connector_cleanup(connector);
 198 }
 199
 200 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 201 {
 202         struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
 203         struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder;
 204         int ret = 0;
 205         struct edid *edid;
 206
 207         edid = drm_get_edid(connector, vc4_hdmi->ddc);
 208         cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
 209         if (!edid)
 210                 return -ENODEV;
 211
 212         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 213
 214         drm_connector_update_edid_property(connector, edid);
 215         ret = drm_add_edid_modes(connector, edid);
 216         kfree(edid);
 217
 218         return ret;
 219 }
 220
 221 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
 222 {
 223         struct vc4_hdmi_connector_state *old_state =
 224                 conn_state_to_vc4_hdmi_conn_state(connector->state);
 225         struct vc4_hdmi_connector_state *new_state =
 226                 kzalloc(sizeof(*new_state), GFP_KERNEL);
 227
 228         if (connector->state)
 229                 __drm_atomic_helper_connector_destroy_state(connector->state);
 230
 231         kfree(old_state);
 232         __drm_atomic_helper_connector_reset(connector, &new_state->base);
 233
 234         if (!new_state)
 235                 return;
 236
 237         new_state->base.max_bpc = 8;
 238         new_state->base.max_requested_bpc = 8;
 239         drm_atomic_helper_connector_tv_reset(connector);
 240 }
 241
 242 static struct drm_connector_state *
 243 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
 244 {
 245         struct drm_connector_state *conn_state = connector->state;
 246         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 247         struct vc4_hdmi_connector_state *new_state;
 248
 249         new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
 250         if (!new_state)
 251                 return NULL;
 252
 253         new_state->pixel_rate = vc4_state->pixel_rate;
 254         __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
 255
 256         return &new_state->base;
 257 }
 258
 259 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 260         .detect = vc4_hdmi_connector_detect,
 261         .fill_modes = drm_helper_probe_single_connector_modes,
 262         .destroy = vc4_hdmi_connector_destroy,
 263         .reset = vc4_hdmi_connector_reset,
 264         .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
 265         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 266 };
 267
 268 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 269         .get_modes = vc4_hdmi_connector_get_modes,
 270 };
 271
 272 static int vc4_hdmi_connector_init(struct drm_device *dev,
 273                                    struct vc4_hdmi *vc4_hdmi)
 274 {
 275         struct drm_connector *connector = &vc4_hdmi->connector;
 276         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
 277         int ret;
 278
 279         drm_connector_init_with_ddc(dev, connector,
 280                                     &vc4_hdmi_connector_funcs,
 281                                     DRM_MODE_CONNECTOR_HDMIA,
 282                                     vc4_hdmi->ddc);
 283         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 284
 285         /*
 286          * Some of the properties below require access to state, like bpc.
 287          * Allocate some default initial connector state with our reset helper.
 288          */
 289         if (connector->funcs->reset)
 290                 connector->funcs->reset(connector);
 291
 292         /* Create and attach TV margin props to this connector. */
 293         ret = drm_mode_create_tv_margin_properties(dev);
 294         if (ret)
 295                 return ret;
 296
 297         drm_connector_attach_tv_margin_properties(connector);
 298         drm_connector_attach_max_bpc_property(connector, 8, 12);
 299
 300         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 301                              DRM_CONNECTOR_POLL_DISCONNECT);
 302
 303         connector->interlace_allowed = 1;
 304         connector->doublescan_allowed = 0;
 305
 306         drm_connector_attach_encoder(connector, encoder);
 307
 308         return 0;
 309 }
 310
 311 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
 312                                 enum hdmi_infoframe_type type,
 313                                 bool poll)
 314 {
 315         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 316         u32 packet_id = type - 0x80;
 317
 318         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 319                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
 320
 321         if (!poll)
 322                 return 0;
 323
 324         return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 325                           BIT(packet_id)), 100);
 326 }
 327
 328 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
 329                                      union hdmi_infoframe *frame)
 330 {
 331         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 332         u32 packet_id = frame->any.type - 0x80;
 333         const struct vc4_hdmi_register *ram_packet_start =
 334                 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
 335         u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
 336         void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
 337                                                        ram_packet_start->reg);
 338         uint8_t buffer[VC4_HDMI_PACKET_STRIDE];
 339         ssize_t len, i;
 340         int ret;
 341
 342         WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 343                     VC4_HDMI_RAM_PACKET_ENABLE),
 344                   "Packet RAM has to be on to store the packet.");
 345
 346         len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
 347         if (len < 0)
 348                 return;
 349
 350         ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
 351         if (ret) {
 352                 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
 353                 return;
 354         }
 355
 356         for (i = 0; i < len; i += 7) {
 357                 writel(buffer[i + 0] << 0 |
 358                        buffer[i + 1] << 8 |
 359                        buffer[i + 2] << 16,
 360                        base + packet_reg);
 361                 packet_reg += 4;
 362
 363                 writel(buffer[i + 3] << 0 |
 364                        buffer[i + 4] << 8 |
 365                        buffer[i + 5] << 16 |
 366                        buffer[i + 6] << 24,
 367                        base + packet_reg);
 368                 packet_reg += 4;
 369         }
 370
 371         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 372                    HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
 373         ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
 374                         BIT(packet_id)), 100);
 375         if (ret)
 376                 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
 377 }
 378
 379 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
 380 {
 381         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 382         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 383         struct drm_connector *connector = &vc4_hdmi->connector;
 384         struct drm_connector_state *cstate = connector->state;
 385         struct drm_crtc *crtc = encoder->crtc;
 386         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 387         union hdmi_infoframe frame;
 388         int ret;
 389
 390         ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
 391                                                        connector, mode);
 392         if (ret < 0) {
 393                 DRM_ERROR("couldn't fill AVI infoframe\n");
 394                 return;
 395         }
 396
 397         drm_hdmi_avi_infoframe_quant_range(&frame.avi,
 398                                            connector, mode,
 399                                            vc4_encoder->limited_rgb_range ?
 400                                            HDMI_QUANTIZATION_RANGE_LIMITED :
 401                                            HDMI_QUANTIZATION_RANGE_FULL);
 402
 403         drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
 404
 405         vc4_hdmi_write_infoframe(encoder, &frame);
 406 }
 407
 408 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
 409 {
 410         union hdmi_infoframe frame;
 411         int ret;
 412
 413         ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
 414         if (ret < 0) {
 415                 DRM_ERROR("couldn't fill SPD infoframe\n");
 416                 return;
 417         }
 418
 419         frame.spd.sdi = HDMI_SPD_SDI_PC;
 420
 421         vc4_hdmi_write_infoframe(encoder, &frame);
 422 }
 423
 424 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
 425 {
 426         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 427         union hdmi_infoframe frame;
 428
 429         hdmi_audio_infoframe_init(&frame.audio);
 430
 431         frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM;
 432         frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM;
 433         frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM;
 434         frame.audio.channels = vc4_hdmi->audio.channels;
 435
 436         vc4_hdmi_write_infoframe(encoder, &frame);
 437 }
 438
 439 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
 440 {
 441         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 442
 443         vc4_hdmi_set_avi_infoframe(encoder);
 444         vc4_hdmi_set_spd_infoframe(encoder);
 445         /*
 446          * If audio was streaming, then we need to reenabled the audio
 447          * infoframe here during encoder_enable.
 448          */
 449         if (vc4_hdmi->audio.streaming)
 450                 vc4_hdmi_set_audio_infoframe(encoder);
 451 }
 452
 453 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
 454                                                struct drm_atomic_state *state)
 455 {
 456         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 457
 458         HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
 459
 460         HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
 461                    VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
 462
 463         HDMI_WRITE(HDMI_VID_CTL,
 464                    HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 465 }
 466
 467 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
 468                                                  struct drm_atomic_state *state)
 469 {
 470         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 471         int ret;
 472
 473         if (vc4_hdmi->variant->phy_disable)
 474                 vc4_hdmi->variant->phy_disable(vc4_hdmi);
 475
 476         HDMI_WRITE(HDMI_VID_CTL,
 477                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 478
 479         clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
 480         clk_disable_unprepare(vc4_hdmi->pixel_clock);
 481
 482         ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
 483         if (ret < 0)
 484                 DRM_ERROR("Failed to release power domain: %d\n", ret);
 485 }
 486
 487 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 488 {
 489 }
 490
 491 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 492 {
 493         u32 csc_ctl;
 494
 495         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 496                                 VC4_HD_CSC_CTL_ORDER);
 497
 498         if (enable) {
 499                 /* CEA VICs other than #1 requre limited range RGB
 500                  * output unless overridden by an AVI infoframe.
 501                  * Apply a colorspace conversion to squash 0-255 down
 502                  * to 16-235.  The matrix here is:
 503                  *
 504                  * [ 0      0      0.8594 16]
 505                  * [ 0      0.8594 0      16]
 506                  * [ 0.8594 0      0      16]
 507                  * [ 0      0      0       1]
 508                  */
 509                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 510                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 511                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 512                                          VC4_HD_CSC_CTL_MODE);
 513
 514                 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
 515                 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
 516                 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
 517                 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
 518                 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
 519                 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
 520         }
 521
 522         /* The RGB order applies even when CSC is disabled. */
 523         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 524 }
 525
 526 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable)
 527 {
 528         u32 csc_ctl;
 529
 530         csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */
 531
 532         if (enable) {
 533                 /* CEA VICs other than #1 requre limited range RGB
 534                  * output unless overridden by an AVI infoframe.
 535                  * Apply a colorspace conversion to squash 0-255 down
 536                  * to 16-235.  The matrix here is:
 537                  *
 538                  * [ 0.8594 0      0      16]
 539                  * [ 0      0.8594 0      16]
 540                  * [ 0      0      0.8594 16]
 541                  * [ 0      0      0       1]
 542                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 543                  */
 544                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80);
 545                 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000);
 546                 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000);
 547                 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000);
 548                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 549                 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80);
 550         } else {
 551                 /* Still use the matrix for full range, but make it unity.
 552                  * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
 553                  */
 554                 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000);
 555                 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000);
 556                 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000);
 557                 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000);
 558                 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000);
 559                 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000);
 560         }
 561
 562         HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
 563 }
 564
 565 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 566                                  struct drm_connector_state *state,
 567                                  struct drm_display_mode *mode)
 568 {
 569         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 570         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 571         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 572         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 573         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 574                                    VC4_HDMI_VERTA_VSP) |
 575                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 576                                    VC4_HDMI_VERTA_VFP) |
 577                      VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
 578         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 579                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 580                                    VC4_HDMI_VERTB_VBP));
 581         u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 582                           VC4_SET_FIELD(mode->crtc_vtotal -
 583                                         mode->crtc_vsync_end -
 584                                         interlaced,
 585                                         VC4_HDMI_VERTB_VBP));
 586
 587         HDMI_WRITE(HDMI_HORZA,
 588                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 589                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 590                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 591                                  VC4_HDMI_HORZA_HAP));
 592
 593         HDMI_WRITE(HDMI_HORZB,
 594                    VC4_SET_FIELD((mode->htotal -
 595                                   mode->hsync_end) * pixel_rep,
 596                                  VC4_HDMI_HORZB_HBP) |
 597                    VC4_SET_FIELD((mode->hsync_end -
 598                                   mode->hsync_start) * pixel_rep,
 599                                  VC4_HDMI_HORZB_HSP) |
 600                    VC4_SET_FIELD((mode->hsync_start -
 601                                   mode->hdisplay) * pixel_rep,
 602                                  VC4_HDMI_HORZB_HFP));
 603
 604         HDMI_WRITE(HDMI_VERTA0, verta);
 605         HDMI_WRITE(HDMI_VERTA1, verta);
 606
 607         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 608         HDMI_WRITE(HDMI_VERTB1, vertb);
 609 }
 610
 611 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
 612                                  struct drm_connector_state *state,
 613                                  struct drm_display_mode *mode)
 614 {
 615         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 616         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 617         bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
 618         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
 619         u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
 620                                    VC5_HDMI_VERTA_VSP) |
 621                      VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
 622                                    VC5_HDMI_VERTA_VFP) |
 623                      VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
 624         u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 625                      VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
 626                                    VC4_HDMI_VERTB_VBP));
 627         u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
 628                           VC4_SET_FIELD(mode->crtc_vtotal -
 629                                         mode->crtc_vsync_end -
 630                                         interlaced,
 631                                         VC4_HDMI_VERTB_VBP));
 632         unsigned char gcp;
 633         bool gcp_en;
 634         u32 reg;
 635
 636         HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021);
 637         HDMI_WRITE(HDMI_HORZA,
 638                    (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
 639                    (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
 640                    VC4_SET_FIELD(mode->hdisplay * pixel_rep,
 641                                  VC5_HDMI_HORZA_HAP) |
 642                    VC4_SET_FIELD((mode->hsync_start -
 643                                   mode->hdisplay) * pixel_rep,
 644                                  VC5_HDMI_HORZA_HFP));
 645
 646         HDMI_WRITE(HDMI_HORZB,
 647                    VC4_SET_FIELD((mode->htotal -
 648                                   mode->hsync_end) * pixel_rep,
 649                                  VC5_HDMI_HORZB_HBP) |
 650                    VC4_SET_FIELD((mode->hsync_end -
 651                                   mode->hsync_start) * pixel_rep,
 652                                  VC5_HDMI_HORZB_HSP));
 653
 654         HDMI_WRITE(HDMI_VERTA0, verta);
 655         HDMI_WRITE(HDMI_VERTA1, verta);
 656
 657         HDMI_WRITE(HDMI_VERTB0, vertb_even);
 658         HDMI_WRITE(HDMI_VERTB1, vertb);
 659
 660         switch (state->max_bpc) {
 661         case 12:
 662                 gcp = 6;
 663                 gcp_en = true;
 664                 break;
 665         case 10:
 666                 gcp = 5;
 667                 gcp_en = true;
 668                 break;
 669         case 8:
 670         default:
 671                 gcp = 4;
 672                 gcp_en = false;
 673                 break;
 674         }
 675
 676         reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
 677         reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
 678                  VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
 679         reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
 680                VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
 681         HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
 682
 683         reg = HDMI_READ(HDMI_GCP_WORD_1);
 684         reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
 685         reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
 686         HDMI_WRITE(HDMI_GCP_WORD_1, reg);
 687
 688         reg = HDMI_READ(HDMI_GCP_CONFIG);
 689         reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
 690         reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
 691         HDMI_WRITE(HDMI_GCP_CONFIG, reg);
 692
 693         HDMI_WRITE(HDMI_CLOCK_STOP, 0);
 694 }
 695
 696 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
 697 {
 698         u32 drift;
 699         int ret;
 700
 701         drift = HDMI_READ(HDMI_FIFO_CTL);
 702         drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 703
 704         HDMI_WRITE(HDMI_FIFO_CTL,
 705                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 706         HDMI_WRITE(HDMI_FIFO_CTL,
 707                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 708         usleep_range(1000, 1100);
 709         HDMI_WRITE(HDMI_FIFO_CTL,
 710                    drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 711         HDMI_WRITE(HDMI_FIFO_CTL,
 712                    drift | VC4_HDMI_FIFO_CTL_RECENTER);
 713
 714         ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
 715                        VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 716         WARN_ONCE(ret, "Timeout waiting for "
 717                   "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 718 }
 719
 720 static struct drm_connector_state *
 721 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder,
 722                                      struct drm_atomic_state *state)
 723 {
 724         struct drm_connector_state *conn_state;
 725         struct drm_connector *connector;
 726         unsigned int i;
 727
 728         for_each_new_connector_in_state(state, connector, conn_state, i) {
 729                 if (conn_state->best_encoder == encoder)
 730                         return conn_state;
 731         }
 732
 733         return NULL;
 734 }
 735
 736 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
 737                                                 struct drm_atomic_state *state)
 738 {
 739         struct drm_connector_state *conn_state =
 740                 vc4_hdmi_encoder_get_connector_state(encoder, state);
 741         struct vc4_hdmi_connector_state *vc4_conn_state =
 742                 conn_state_to_vc4_hdmi_conn_state(conn_state);
 743         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 744         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 745         unsigned long pixel_rate, hsm_rate;
 746         int ret;
 747
 748         ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev);
 749         if (ret < 0) {
 750                 DRM_ERROR("Failed to retain power domain: %d\n", ret);
 751                 return;
 752         }
 753
 754         pixel_rate = vc4_conn_state->pixel_rate;
 755         ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate);
 756         if (ret) {
 757                 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
 758                 return;
 759         }
 760
 761         ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
 762         if (ret) {
 763                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 764                 return;
 765         }
 766
 767         /*
 768          * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
 769          * be faster than pixel clock, infinitesimally faster, tested in
 770          * simulation. Otherwise, exact value is unimportant for HDMI
 771          * operation." This conflicts with bcm2835's vc4 documentation, which
 772          * states HSM's clock has to be at least 108% of the pixel clock.
 773          *
 774          * Real life tests reveal that vc4's firmware statement holds up, and
 775          * users are able to use pixel clocks closer to HSM's, namely for
 776          * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
 777          * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
 778          * 162MHz.
 779          *
 780          * Additionally, the AXI clock needs to be at least 25% of
 781          * pixel clock, but HSM ends up being the limiting factor.
 782          */
 783         hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101);
 784         ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
 785         if (ret) {
 786                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 787                 return;
 788         }
 789
 790         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
 791
 792         /*
 793          * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup
 794          * at 300MHz.
 795          */
 796         ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock,
 797                                (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000));
 798         if (ret) {
 799                 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
 800                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 801                 return;
 802         }
 803
 804         ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
 805         if (ret) {
 806                 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
 807                 clk_disable_unprepare(vc4_hdmi->pixel_clock);
 808                 return;
 809         }
 810
 811         if (vc4_hdmi->variant->phy_init)
 812                 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
 813
 814         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 815                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 816                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 817                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 818
 819         if (vc4_hdmi->variant->set_timings)
 820                 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
 821 }
 822
 823 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
 824                                              struct drm_atomic_state *state)
 825 {
 826         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 827         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 828         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 829
 830         if (vc4_encoder->hdmi_monitor &&
 831             drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) {
 832                 if (vc4_hdmi->variant->csc_setup)
 833                         vc4_hdmi->variant->csc_setup(vc4_hdmi, true);
 834
 835                 vc4_encoder->limited_rgb_range = true;
 836         } else {
 837                 if (vc4_hdmi->variant->csc_setup)
 838                         vc4_hdmi->variant->csc_setup(vc4_hdmi, false);
 839
 840                 vc4_encoder->limited_rgb_range = false;
 841         }
 842
 843         HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 844 }
 845
 846 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
 847                                               struct drm_atomic_state *state)
 848 {
 849         struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
 850         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 851         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 852         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 853         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 854         int ret;
 855
 856         HDMI_WRITE(HDMI_VID_CTL,
 857                    VC4_HD_VID_CTL_ENABLE |
 858                    VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 859                    VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
 860                    (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 861                    (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 862
 863         HDMI_WRITE(HDMI_VID_CTL,
 864                    HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
 865
 866         if (vc4_encoder->hdmi_monitor) {
 867                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 868                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 869                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 870
 871                 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 872                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
 873                 WARN_ONCE(ret, "Timeout waiting for "
 874                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 875         } else {
 876                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 877                            HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
 878                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 879                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 880                            HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 881                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 882
 883                 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 884                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
 885                 WARN_ONCE(ret, "Timeout waiting for "
 886                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 887         }
 888
 889         if (vc4_encoder->hdmi_monitor) {
 890                 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
 891                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 892                 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
 893                            HDMI_READ(HDMI_SCHEDULER_CONTROL) |
 894                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 895
 896                 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
 897                            VC4_HDMI_RAM_PACKET_ENABLE);
 898
 899                 vc4_hdmi_set_infoframes(encoder);
 900         }
 901
 902         vc4_hdmi_recenter_fifo(vc4_hdmi);
 903 }
 904
 905 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 906 {
 907 }
 908
 909 #define WIFI_2_4GHz_CH1_MIN_FREQ        2400000000ULL
 910 #define WIFI_2_4GHz_CH1_MAX_FREQ        2422000000ULL
 911
 912 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
 913                                          struct drm_crtc_state *crtc_state,
 914                                          struct drm_connector_state *conn_state)
 915 {
 916         struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
 917         struct drm_display_mode *mode = &crtc_state->adjusted_mode;
 918         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 919         unsigned long long pixel_rate = mode->clock * 1000;
 920         unsigned long long tmds_rate;
 921
 922         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
 923             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
 924              (mode->hsync_end % 2) || (mode->htotal % 2)))
 925                 return -EINVAL;
 926
 927         /*
 928          * The 1440p@60 pixel rate is in the same range than the first
 929          * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
 930          * bandwidth). Slightly lower the frequency to bring it out of
 931          * the WiFi range.
 932          */
 933         tmds_rate = pixel_rate * 10;
 934         if (vc4_hdmi->disable_wifi_frequencies &&
 935             (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
 936              tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
 937                 mode->clock = 238560;
 938                 pixel_rate = mode->clock * 1000;
 939         }
 940
 941         if (conn_state->max_bpc == 12) {
 942                 pixel_rate = pixel_rate * 150;
 943                 do_div(pixel_rate, 100);
 944         } else if (conn_state->max_bpc == 10) {
 945                 pixel_rate = pixel_rate * 125;
 946                 do_div(pixel_rate, 100);
 947         }
 948
 949         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 950                 pixel_rate = pixel_rate * 2;
 951
 952         if (pixel_rate > vc4_hdmi->variant->max_pixel_clock)
 953                 return -EINVAL;
 954
 955         vc4_state->pixel_rate = pixel_rate;
 956
 957         return 0;
 958 }
 959
 960 static enum drm_mode_status
 961 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
 962                             const struct drm_display_mode *mode)
 963 {
 964         struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
 965
 966         if (vc4_hdmi->variant->unsupported_odd_h_timings &&
 967             ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
 968              (mode->hsync_end % 2) || (mode->htotal % 2)))
 969                 return MODE_H_ILLEGAL;
 970
 971         if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock)
 972                 return MODE_CLOCK_HIGH;
 973
 974         return MODE_OK;
 975 }
 976
 977 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 978         .atomic_check = vc4_hdmi_encoder_atomic_check,
 979         .mode_valid = vc4_hdmi_encoder_mode_valid,
 980         .disable = vc4_hdmi_encoder_disable,
 981         .enable = vc4_hdmi_encoder_enable,
 982 };
 983
 984 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 985 {
 986         int i;
 987         u32 channel_map = 0;
 988
 989         for (i = 0; i < 8; i++) {
 990                 if (channel_mask & BIT(i))
 991                         channel_map |= i << (3 * i);
 992         }
 993         return channel_map;
 994 }
 995
 996 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
 997 {
 998         int i;
 999         u32 channel_map = 0;
1000
1001         for (i = 0; i < 8; i++) {
1002                 if (channel_mask & BIT(i))
1003                         channel_map |= i << (4 * i);
1004         }
1005         return channel_map;
1006 }
1007
1008 /* HDMI audio codec callbacks */
1009 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi)
1010 {
1011         u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1012         unsigned long n, m;
1013
1014         rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate,
1015                                     VC4_HD_MAI_SMP_N_MASK >>
1016                                     VC4_HD_MAI_SMP_N_SHIFT,
1017                                     (VC4_HD_MAI_SMP_M_MASK >>
1018                                      VC4_HD_MAI_SMP_M_SHIFT) + 1,
1019                                     &n, &m);
1020
1021         HDMI_WRITE(HDMI_MAI_SMP,
1022                    VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1023                    VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1024 }
1025
1026 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi)
1027 {
1028         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1029         struct drm_crtc *crtc = encoder->crtc;
1030         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1031         u32 samplerate = vc4_hdmi->audio.samplerate;
1032         u32 n, cts;
1033         u64 tmp;
1034
1035         n = 128 * samplerate / 1000;
1036         tmp = (u64)(mode->clock * 1000) * n;
1037         do_div(tmp, 128 * samplerate);
1038         cts = tmp;
1039
1040         HDMI_WRITE(HDMI_CRP_CFG,
1041                    VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1042                    VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1043
1044         /*
1045          * We could get slightly more accurate clocks in some cases by
1046          * providing a CTS_1 value.  The two CTS values are alternated
1047          * between based on the period fields
1048          */
1049         HDMI_WRITE(HDMI_CTS_0, cts);
1050         HDMI_WRITE(HDMI_CTS_1, cts);
1051 }
1052
1053 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1054 {
1055         struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1056
1057         return snd_soc_card_get_drvdata(card);
1058 }
1059
1060 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream,
1061                                   struct snd_soc_dai *dai)
1062 {
1063         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1064         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1065         struct drm_connector *connector = &vc4_hdmi->connector;
1066         int ret;
1067
1068         if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream)
1069                 return -EINVAL;
1070
1071         vc4_hdmi->audio.substream = substream;
1072
1073         /*
1074          * If the HDMI encoder hasn't probed, or the encoder is
1075          * currently in DVI mode, treat the codec dai as missing.
1076          */
1077         if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1078                                 VC4_HDMI_RAM_PACKET_ENABLE))
1079                 return -ENODEV;
1080
1081         ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld);
1082         if (ret)
1083                 return ret;
1084
1085         return 0;
1086 }
1087
1088 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
1089 {
1090         return 0;
1091 }
1092
1093 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
1094 {
1095         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1096         struct device *dev = &vc4_hdmi->pdev->dev;
1097         int ret;
1098
1099         vc4_hdmi->audio.streaming = false;
1100         ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
1101         if (ret)
1102                 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
1103
1104         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
1105         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
1106         HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
1107 }
1108
1109 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream,
1110                                     struct snd_soc_dai *dai)
1111 {
1112         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1113
1114         if (substream != vc4_hdmi->audio.substream)
1115                 return;
1116
1117         vc4_hdmi_audio_reset(vc4_hdmi);
1118
1119         vc4_hdmi->audio.substream = NULL;
1120 }
1121
1122 /* HDMI audio codec callbacks */
1123 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream,
1124                                     struct snd_pcm_hw_params *params,
1125                                     struct snd_soc_dai *dai)
1126 {
1127         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1128         struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base;
1129         struct device *dev = &vc4_hdmi->pdev->dev;
1130         u32 audio_packet_config, channel_mask;
1131         u32 channel_map;
1132
1133         if (substream != vc4_hdmi->audio.substream)
1134                 return -EINVAL;
1135
1136         dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
1137                 params_rate(params), params_width(params),
1138                 params_channels(params));
1139
1140         vc4_hdmi->audio.channels = params_channels(params);
1141         vc4_hdmi->audio.samplerate = params_rate(params);
1142
1143         HDMI_WRITE(HDMI_MAI_CTL,
1144                    VC4_HD_MAI_CTL_RESET |
1145                    VC4_HD_MAI_CTL_FLUSH |
1146                    VC4_HD_MAI_CTL_DLATE |
1147                    VC4_HD_MAI_CTL_ERRORE |
1148                    VC4_HD_MAI_CTL_ERRORF);
1149
1150         vc4_hdmi_audio_set_mai_clock(vc4_hdmi);
1151
1152         /* The B frame identifier should match the value used by alsa-lib (8) */
1153         audio_packet_config =
1154                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
1155                 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
1156                 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
1157
1158         channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0);
1159         audio_packet_config |= VC4_SET_FIELD(channel_mask,
1160                                              VC4_HDMI_AUDIO_PACKET_CEA_MASK);
1161
1162         /* Set the MAI threshold.  This logic mimics the firmware's. */
1163         if (vc4_hdmi->audio.samplerate > 96000) {
1164                 HDMI_WRITE(HDMI_MAI_THR,
1165                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) |
1166                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1167         } else if (vc4_hdmi->audio.samplerate > 48000) {
1168                 HDMI_WRITE(HDMI_MAI_THR,
1169                            VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) |
1170                            VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW));
1171         } else {
1172                 HDMI_WRITE(HDMI_MAI_THR,
1173                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) |
1174                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) |
1175                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) |
1176                            VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW));
1177         }
1178
1179         HDMI_WRITE(HDMI_MAI_CONFIG,
1180                    VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
1181                    VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
1182
1183         channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
1184         HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
1185         HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
1186         vc4_hdmi_set_n_cts(vc4_hdmi);
1187
1188         vc4_hdmi_set_audio_infoframe(encoder);
1189
1190         return 0;
1191 }
1192
1193 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
1194                                   struct snd_soc_dai *dai)
1195 {
1196         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1197
1198         switch (cmd) {
1199         case SNDRV_PCM_TRIGGER_START:
1200                 vc4_hdmi->audio.streaming = true;
1201
1202                 if (vc4_hdmi->variant->phy_rng_enable)
1203                         vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
1204
1205                 HDMI_WRITE(HDMI_MAI_CTL,
1206                            VC4_SET_FIELD(vc4_hdmi->audio.channels,
1207                                          VC4_HD_MAI_CTL_CHNUM) |
1208                            VC4_HD_MAI_CTL_ENABLE);
1209                 break;
1210         case SNDRV_PCM_TRIGGER_STOP:
1211                 HDMI_WRITE(HDMI_MAI_CTL,
1212                            VC4_HD_MAI_CTL_DLATE |
1213                            VC4_HD_MAI_CTL_ERRORE |
1214                            VC4_HD_MAI_CTL_ERRORF);
1215
1216                 if (vc4_hdmi->variant->phy_rng_disable)
1217                         vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
1218
1219                 vc4_hdmi->audio.streaming = false;
1220
1221                 break;
1222         default:
1223                 break;
1224         }
1225
1226         return 0;
1227 }
1228
1229 static inline struct vc4_hdmi *
1230 snd_component_to_hdmi(struct snd_soc_component *component)
1231 {
1232         struct snd_soc_card *card = snd_soc_component_get_drvdata(component);
1233
1234         return snd_soc_card_get_drvdata(card);
1235 }
1236
1237 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol,
1238                                        struct snd_ctl_elem_info *uinfo)
1239 {
1240         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1241         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1242         struct drm_connector *connector = &vc4_hdmi->connector;
1243
1244         uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1245         uinfo->count = sizeof(connector->eld);
1246
1247         return 0;
1248 }
1249
1250 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol,
1251                                       struct snd_ctl_elem_value *ucontrol)
1252 {
1253         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1254         struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component);
1255         struct drm_connector *connector = &vc4_hdmi->connector;
1256
1257         memcpy(ucontrol->value.bytes.data, connector->eld,
1258                sizeof(connector->eld));
1259
1260         return 0;
1261 }
1262
1263 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = {
1264         {
1265                 .access = SNDRV_CTL_ELEM_ACCESS_READ |
1266                           SNDRV_CTL_ELEM_ACCESS_VOLATILE,
1267                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1268                 .name = "ELD",
1269                 .info = vc4_hdmi_audio_eld_ctl_info,
1270                 .get = vc4_hdmi_audio_eld_ctl_get,
1271         },
1272 };
1273
1274 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = {
1275         SND_SOC_DAPM_OUTPUT("TX"),
1276 };
1277
1278 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = {
1279         { "TX", NULL, "Playback" },
1280 };
1281
1282 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = {
1283         .name                   = "vc4-hdmi-codec-dai-component",
1284         .controls               = vc4_hdmi_audio_controls,
1285         .num_controls           = ARRAY_SIZE(vc4_hdmi_audio_controls),
1286         .dapm_widgets           = vc4_hdmi_audio_widgets,
1287         .num_dapm_widgets       = ARRAY_SIZE(vc4_hdmi_audio_widgets),
1288         .dapm_routes            = vc4_hdmi_audio_routes,
1289         .num_dapm_routes        = ARRAY_SIZE(vc4_hdmi_audio_routes),
1290         .idle_bias_on           = 1,
1291         .use_pmdown_time        = 1,
1292         .endianness             = 1,
1293         .non_legacy_dai_naming  = 1,
1294 };
1295
1296 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = {
1297         .startup = vc4_hdmi_audio_startup,
1298         .shutdown = vc4_hdmi_audio_shutdown,
1299         .hw_params = vc4_hdmi_audio_hw_params,
1300         .set_fmt = vc4_hdmi_audio_set_fmt,
1301         .trigger = vc4_hdmi_audio_trigger,
1302 };
1303
1304 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = {
1305         .name = "vc4-hdmi-hifi",
1306         .playback = {
1307                 .stream_name = "Playback",
1308                 .channels_min = 2,
1309                 .channels_max = 8,
1310                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1311                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1312                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1313                          SNDRV_PCM_RATE_192000,
1314                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1315         },
1316 };
1317
1318 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
1319         .name = "vc4-hdmi-cpu-dai-component",
1320 };
1321
1322 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
1323 {
1324         struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
1325
1326         snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
1327
1328         return 0;
1329 }
1330
1331 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
1332         .name = "vc4-hdmi-cpu-dai",
1333         .probe  = vc4_hdmi_audio_cpu_dai_probe,
1334         .playback = {
1335                 .stream_name = "Playback",
1336                 .channels_min = 1,
1337                 .channels_max = 8,
1338                 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
1339                          SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
1340                          SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
1341                          SNDRV_PCM_RATE_192000,
1342                 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
1343         },
1344         .ops = &vc4_hdmi_audio_dai_ops,
1345 };
1346
1347 static const struct snd_dmaengine_pcm_config pcm_conf = {
1348         .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
1349         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
1350 };
1351
1352 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
1353 {
1354         const struct vc4_hdmi_register *mai_data =
1355                 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
1356         struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
1357         struct snd_soc_card *card = &vc4_hdmi->audio.card;
1358         struct device *dev = &vc4_hdmi->pdev->dev;
1359         const __be32 *addr;
1360         int index;
1361         int ret;
1362
1363         if (!of_find_property(dev->of_node, "dmas", NULL)) {
1364                 dev_warn(dev,
1365                          "'dmas' DT property is missing, no HDMI audio\n");
1366                 return 0;
1367         }
1368
1369         if (mai_data->reg != VC4_HD) {
1370                 WARN_ONCE(true, "MAI isn't in the HD block\n");
1371                 return -EINVAL;
1372         }
1373
1374         /*
1375          * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
1376          * the bus address specified in the DT, because the physical address
1377          * (the one returned by platform_get_resource()) is not appropriate
1378          * for DMA transfers.
1379          * This VC/MMU should probably be exposed to avoid this kind of hacks.
1380          */
1381         index = of_property_match_string(dev->of_node, "reg-names", "hd");
1382         /* Before BCM2711, we don't have a named register range */
1383         if (index < 0)
1384                 index = 1;
1385
1386         addr = of_get_address(dev->of_node, index, NULL, NULL);
1387
1388         vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
1389         vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1390         vc4_hdmi->audio.dma_data.maxburst = 2;
1391
1392         ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
1393         if (ret) {
1394                 dev_err(dev, "Could not register PCM component: %d\n", ret);
1395                 return ret;
1396         }
1397
1398         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
1399                                               &vc4_hdmi_audio_cpu_dai_drv, 1);
1400         if (ret) {
1401                 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
1402                 return ret;
1403         }
1404
1405         /* register component and codec dai */
1406         ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv,
1407                                      &vc4_hdmi_audio_codec_dai_drv, 1);
1408         if (ret) {
1409                 dev_err(dev, "Could not register component: %d\n", ret);
1410                 return ret;
1411         }
1412
1413         dai_link->cpus          = &vc4_hdmi->audio.cpu;
1414         dai_link->codecs        = &vc4_hdmi->audio.codec;
1415         dai_link->platforms     = &vc4_hdmi->audio.platform;
1416
1417         dai_link->num_cpus      = 1;
1418         dai_link->num_codecs    = 1;
1419         dai_link->num_platforms = 1;
1420
1421         dai_link->name = "MAI";
1422         dai_link->stream_name = "MAI PCM";
1423         dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name;
1424         dai_link->cpus->dai_name = dev_name(dev);
1425         dai_link->codecs->name = dev_name(dev);
1426         dai_link->platforms->name = dev_name(dev);
1427
1428         card->dai_link = dai_link;
1429         card->num_links = 1;
1430         card->name = vc4_hdmi->variant->card_name;
1431         card->driver_name = "vc4-hdmi";
1432         card->dev = dev;
1433         card->owner = THIS_MODULE;
1434
1435         /*
1436          * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
1437          * stores a pointer to the snd card object in dev->driver_data. This
1438          * means we cannot use it for something else. The hdmi back-pointer is
1439          * now stored in card->drvdata and should be retrieved with
1440          * snd_soc_card_get_drvdata() if needed.
1441          */
1442         snd_soc_card_set_drvdata(card, vc4_hdmi);
1443         ret = devm_snd_soc_register_card(dev, card);
1444         if (ret)
1445                 dev_err(dev, "Could not register sound card: %d\n", ret);
1446
1447         return ret;
1448
1449 }
1450
1451 #ifdef CONFIG_DRM_VC4_HDMI_CEC
1452 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
1453 {
1454         struct vc4_hdmi *vc4_hdmi = priv;
1455
1456         if (vc4_hdmi->cec_rx_msg.len)
1457                 cec_received_msg(vc4_hdmi->cec_adap,
1458                                  &vc4_hdmi->cec_rx_msg);
1459
1460         return IRQ_HANDLED;
1461 }
1462
1463 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
1464 {
1465         struct vc4_hdmi *vc4_hdmi = priv;
1466
1467         if (vc4_hdmi->cec_tx_ok) {
1468                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
1469                                   0, 0, 0, 0);
1470         } else {
1471                 /*
1472                  * This CEC implementation makes 1 retry, so if we
1473                  * get a NACK, then that means it made 2 attempts.
1474                  */
1475                 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
1476                                   0, 2, 0, 0);
1477         }
1478         return IRQ_HANDLED;
1479 }
1480
1481 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
1482 {
1483         struct vc4_hdmi *vc4_hdmi = priv;
1484         irqreturn_t ret;
1485
1486         if (vc4_hdmi->cec_irq_was_rx)
1487                 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
1488         else
1489                 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
1490
1491         return ret;
1492 }
1493
1494 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
1495 {
1496         struct drm_device *dev = vc4_hdmi->connector.dev;
1497         struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
1498         unsigned int i;
1499
1500         msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
1501                                         VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
1502
1503         if (msg->len > 16) {
1504                 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
1505                 return;
1506         }
1507
1508         for (i = 0; i < msg->len; i += 4) {
1509                 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
1510
1511                 msg->msg[i] = val & 0xff;
1512                 msg->msg[i + 1] = (val >> 8) & 0xff;
1513                 msg->msg[i + 2] = (val >> 16) & 0xff;
1514                 msg->msg[i + 3] = (val >> 24) & 0xff;
1515         }
1516 }
1517
1518 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
1519 {
1520         struct vc4_hdmi *vc4_hdmi = priv;
1521         u32 cntrl1;
1522
1523         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1524         vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
1525         cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1526         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1527
1528         return IRQ_WAKE_THREAD;
1529 }
1530
1531 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
1532 {
1533         struct vc4_hdmi *vc4_hdmi = priv;
1534         u32 cntrl1;
1535
1536         vc4_hdmi->cec_rx_msg.len = 0;
1537         cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
1538         vc4_cec_read_msg(vc4_hdmi, cntrl1);
1539         cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1540         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1541         cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
1542
1543         HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
1544
1545         return IRQ_WAKE_THREAD;
1546 }
1547
1548 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
1549 {
1550         struct vc4_hdmi *vc4_hdmi = priv;
1551         u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
1552         irqreturn_t ret;
1553         u32 cntrl5;
1554
1555         if (!(stat & VC4_HDMI_CPU_CEC))
1556                 return IRQ_NONE;
1557
1558         cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
1559         vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
1560         if (vc4_hdmi->cec_irq_was_rx)
1561                 ret = vc4_cec_irq_handler_rx_bare(irq, priv);
1562         else
1563                 ret = vc4_cec_irq_handler_tx_bare(irq, priv);
1564
1565         HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
1566         return ret;
1567 }
1568
1569 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
1570 {
1571         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1572         /* clock period in microseconds */
1573         const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
1574         u32 val = HDMI_READ(HDMI_CEC_CNTRL_5);
1575
1576         val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
1577                  VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
1578                  VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
1579         val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
1580                ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
1581
1582         if (enable) {
1583                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1584                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1585                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
1586                 HDMI_WRITE(HDMI_CEC_CNTRL_2,
1587                            ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
1588                            ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
1589                            ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
1590                            ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
1591                            ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
1592                 HDMI_WRITE(HDMI_CEC_CNTRL_3,
1593                            ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
1594                            ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
1595                            ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
1596                            ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
1597                 HDMI_WRITE(HDMI_CEC_CNTRL_4,
1598                            ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
1599                            ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
1600                            ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
1601                            ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
1602
1603                 if (!vc4_hdmi->variant->external_irq_controller)
1604                         HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
1605         } else {
1606                 if (!vc4_hdmi->variant->external_irq_controller)
1607                         HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
1608                 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
1609                            VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
1610         }
1611         return 0;
1612 }
1613
1614 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
1615 {
1616         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1617
1618         HDMI_WRITE(HDMI_CEC_CNTRL_1,
1619                    (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
1620                    (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
1621         return 0;
1622 }
1623
1624 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
1625                                       u32 signal_free_time, struct cec_msg *msg)
1626 {
1627         struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
1628         struct drm_device *dev = vc4_hdmi->connector.dev;
1629         u32 val;
1630         unsigned int i;
1631
1632         if (msg->len > 16) {
1633                 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
1634                 return -ENOMEM;
1635         }
1636
1637         for (i = 0; i < msg->len; i += 4)
1638                 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
1639                            (msg->msg[i]) |
1640                            (msg->msg[i + 1] << 8) |
1641                            (msg->msg[i + 2] << 16) |
1642                            (msg->msg[i + 3] << 24));
1643
1644         val = HDMI_READ(HDMI_CEC_CNTRL_1);
1645         val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
1646         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1647         val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
1648         val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
1649         val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
1650
1651         HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
1652         return 0;
1653 }
1654
1655 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
1656         .adap_enable = vc4_hdmi_cec_adap_enable,
1657         .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
1658         .adap_transmit = vc4_hdmi_cec_adap_transmit,
1659 };
1660
1661 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1662 {
1663         struct cec_connector_info conn_info;
1664         struct platform_device *pdev = vc4_hdmi->pdev;
1665         struct device *dev = &pdev->dev;
1666         u32 value;
1667         int ret;
1668
1669         if (!of_find_property(dev->of_node, "interrupts", NULL)) {
1670                 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
1671                 return 0;
1672         }
1673
1674         vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
1675                                                   vc4_hdmi, "vc4",
1676                                                   CEC_CAP_DEFAULTS |
1677                                                   CEC_CAP_CONNECTOR_INFO, 1);
1678         ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
1679         if (ret < 0)
1680                 return ret;
1681
1682         cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
1683         cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
1684
1685         value = HDMI_READ(HDMI_CEC_CNTRL_1);
1686         /* Set the logical address to Unregistered */
1687         value |= VC4_HDMI_CEC_ADDR_MASK;
1688         HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
1689
1690         vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1691
1692         if (vc4_hdmi->variant->external_irq_controller) {
1693                 ret = devm_request_threaded_irq(&pdev->dev,
1694                                                 platform_get_irq_byname(pdev, "cec-rx"),
1695                                                 vc4_cec_irq_handler_rx_bare,
1696                                                 vc4_cec_irq_handler_rx_thread, 0,
1697                                                 "vc4 hdmi cec rx", vc4_hdmi);
1698                 if (ret)
1699                         goto err_delete_cec_adap;
1700
1701                 ret = devm_request_threaded_irq(&pdev->dev,
1702                                                 platform_get_irq_byname(pdev, "cec-tx"),
1703                                                 vc4_cec_irq_handler_tx_bare,
1704                                                 vc4_cec_irq_handler_tx_thread, 0,
1705                                                 "vc4 hdmi cec tx", vc4_hdmi);
1706                 if (ret)
1707                         goto err_delete_cec_adap;
1708         } else {
1709                 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
1710
1711                 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0),
1712                                                 vc4_cec_irq_handler,
1713                                                 vc4_cec_irq_handler_thread, 0,
1714                                                 "vc4 hdmi cec", vc4_hdmi);
1715                 if (ret)
1716                         goto err_delete_cec_adap;
1717         }
1718
1719         ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
1720         if (ret < 0)
1721                 goto err_delete_cec_adap;
1722
1723         return 0;
1724
1725 err_delete_cec_adap:
1726         cec_delete_adapter(vc4_hdmi->cec_adap);
1727
1728         return ret;
1729 }
1730
1731 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi)
1732 {
1733         cec_unregister_adapter(vc4_hdmi->cec_adap);
1734 }
1735 #else
1736 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
1737 {
1738         return 0;
1739 }
1740
1741 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {};
1742
1743 #endif
1744
1745 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi,
1746                                  struct debugfs_regset32 *regset,
1747                                  enum vc4_hdmi_regs reg)
1748 {
1749         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1750         struct debugfs_reg32 *regs, *new_regs;
1751         unsigned int count = 0;
1752         unsigned int i;
1753
1754         regs = kcalloc(variant->num_registers, sizeof(*regs),
1755                        GFP_KERNEL);
1756         if (!regs)
1757                 return -ENOMEM;
1758
1759         for (i = 0; i < variant->num_registers; i++) {
1760                 const struct vc4_hdmi_register *field = &variant->registers[i];
1761
1762                 if (field->reg != reg)
1763                         continue;
1764
1765                 regs[count].name = field->name;
1766                 regs[count].offset = field->offset;
1767                 count++;
1768         }
1769
1770         new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
1771         if (!new_regs)
1772                 return -ENOMEM;
1773
1774         regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
1775         regset->regs = new_regs;
1776         regset->nregs = count;
1777
1778         return 0;
1779 }
1780
1781 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1782 {
1783         struct platform_device *pdev = vc4_hdmi->pdev;
1784         struct device *dev = &pdev->dev;
1785         int ret;
1786
1787         vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
1788         if (IS_ERR(vc4_hdmi->hdmicore_regs))
1789                 return PTR_ERR(vc4_hdmi->hdmicore_regs);
1790
1791         vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
1792         if (IS_ERR(vc4_hdmi->hd_regs))
1793                 return PTR_ERR(vc4_hdmi->hd_regs);
1794
1795         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
1796         if (ret)
1797                 return ret;
1798
1799         ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
1800         if (ret)
1801                 return ret;
1802
1803         vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
1804         if (IS_ERR(vc4_hdmi->pixel_clock)) {
1805                 ret = PTR_ERR(vc4_hdmi->pixel_clock);
1806                 if (ret != -EPROBE_DEFER)
1807                         DRM_ERROR("Failed to get pixel clock\n");
1808                 return ret;
1809         }
1810
1811         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1812         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1813                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1814                 return PTR_ERR(vc4_hdmi->hsm_clock);
1815         }
1816         vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
1817         vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
1818
1819         return 0;
1820 }
1821
1822 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi)
1823 {
1824         struct platform_device *pdev = vc4_hdmi->pdev;
1825         struct device *dev = &pdev->dev;
1826         struct resource *res;
1827
1828         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
1829         if (!res)
1830                 return -ENODEV;
1831
1832         vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
1833                                                resource_size(res));
1834         if (!vc4_hdmi->hdmicore_regs)
1835                 return -ENOMEM;
1836
1837         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
1838         if (!res)
1839                 return -ENODEV;
1840
1841         vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
1842         if (!vc4_hdmi->hd_regs)
1843                 return -ENOMEM;
1844
1845         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
1846         if (!res)
1847                 return -ENODEV;
1848
1849         vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
1850         if (!vc4_hdmi->cec_regs)
1851                 return -ENOMEM;
1852
1853         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
1854         if (!res)
1855                 return -ENODEV;
1856
1857         vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
1858         if (!vc4_hdmi->csc_regs)
1859                 return -ENOMEM;
1860
1861         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
1862         if (!res)
1863                 return -ENODEV;
1864
1865         vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
1866         if (!vc4_hdmi->dvp_regs)
1867                 return -ENOMEM;
1868
1869         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
1870         if (!res)
1871                 return -ENODEV;
1872
1873         vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
1874         if (!vc4_hdmi->phy_regs)
1875                 return -ENOMEM;
1876
1877         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
1878         if (!res)
1879                 return -ENODEV;
1880
1881         vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
1882         if (!vc4_hdmi->ram_regs)
1883                 return -ENOMEM;
1884
1885         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
1886         if (!res)
1887                 return -ENODEV;
1888
1889         vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
1890         if (!vc4_hdmi->rm_regs)
1891                 return -ENOMEM;
1892
1893         vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
1894         if (IS_ERR(vc4_hdmi->hsm_clock)) {
1895                 DRM_ERROR("Failed to get HDMI state machine clock\n");
1896                 return PTR_ERR(vc4_hdmi->hsm_clock);
1897         }
1898
1899         vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
1900         if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
1901                 DRM_ERROR("Failed to get pixel bvb clock\n");
1902                 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
1903         }
1904
1905         vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
1906         if (IS_ERR(vc4_hdmi->audio_clock)) {
1907                 DRM_ERROR("Failed to get audio clock\n");
1908                 return PTR_ERR(vc4_hdmi->audio_clock);
1909         }
1910
1911         vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
1912         if (IS_ERR(vc4_hdmi->cec_clock)) {
1913                 DRM_ERROR("Failed to get CEC clock\n");
1914                 return PTR_ERR(vc4_hdmi->cec_clock);
1915         }
1916
1917         vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
1918         if (IS_ERR(vc4_hdmi->reset)) {
1919                 DRM_ERROR("Failed to get HDMI reset line\n");
1920                 return PTR_ERR(vc4_hdmi->reset);
1921         }
1922
1923         return 0;
1924 }
1925
1926 #ifdef CONFIG_PM
1927 static int vc4_hdmi_runtime_suspend(struct device *dev)
1928 {
1929         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1930
1931         clk_disable_unprepare(vc4_hdmi->hsm_clock);
1932
1933         return 0;
1934 }
1935
1936 static int vc4_hdmi_runtime_resume(struct device *dev)
1937 {
1938         struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1939         int ret;
1940
1941         ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
1942         if (ret)
1943                 return ret;
1944
1945         return 0;
1946 }
1947 #endif
1948
1949 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
1950 {
1951         const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
1952         struct platform_device *pdev = to_platform_device(dev);
1953         struct drm_device *drm = dev_get_drvdata(master);
1954         struct vc4_hdmi *vc4_hdmi;
1955         struct drm_encoder *encoder;
1956         struct device_node *ddc_node;
1957         u32 value;
1958         int ret;
1959
1960         vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL);
1961         if (!vc4_hdmi)
1962                 return -ENOMEM;
1963
1964         dev_set_drvdata(dev, vc4_hdmi);
1965         encoder = &vc4_hdmi->encoder.base.base;
1966         vc4_hdmi->encoder.base.type = variant->encoder_type;
1967         vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
1968         vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
1969         vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
1970         vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
1971         vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
1972         vc4_hdmi->pdev = pdev;
1973         vc4_hdmi->variant = variant;
1974
1975         ret = variant->init_resources(vc4_hdmi);
1976         if (ret)
1977                 return ret;
1978
1979         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
1980         if (!ddc_node) {
1981                 DRM_ERROR("Failed to find ddc node in device tree\n");
1982                 return -ENODEV;
1983         }
1984
1985         vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
1986         of_node_put(ddc_node);
1987         if (!vc4_hdmi->ddc) {
1988                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
1989                 return -EPROBE_DEFER;
1990         }
1991
1992         /* Only use the GPIO HPD pin if present in the DT, otherwise
1993          * we'll use the HDMI core's register.
1994          */
1995         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
1996                 enum of_gpio_flags hpd_gpio_flags;
1997
1998                 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
1999                                                              "hpd-gpios", 0,
2000                                                              &hpd_gpio_flags);
2001                 if (vc4_hdmi->hpd_gpio < 0) {
2002                         ret = vc4_hdmi->hpd_gpio;
2003                         goto err_unprepare_hsm;
2004                 }
2005
2006                 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
2007         }
2008
2009         vc4_hdmi->disable_wifi_frequencies =
2010                 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
2011
2012         if (vc4_hdmi->variant->reset)
2013                 vc4_hdmi->variant->reset(vc4_hdmi);
2014
2015         pm_runtime_enable(dev);
2016
2017         drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
2018         drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
2019
2020         ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
2021         if (ret)
2022                 goto err_destroy_encoder;
2023
2024         ret = vc4_hdmi_cec_init(vc4_hdmi);
2025         if (ret)
2026                 goto err_destroy_conn;
2027
2028         ret = vc4_hdmi_audio_init(vc4_hdmi);
2029         if (ret)
2030                 goto err_free_cec;
2031
2032         vc4_debugfs_add_file(drm, variant->debugfs_name,
2033                              vc4_hdmi_debugfs_regs,
2034                              vc4_hdmi);
2035
2036         return 0;
2037
2038 err_free_cec:
2039         vc4_hdmi_cec_exit(vc4_hdmi);
2040 err_destroy_conn:
2041         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2042 err_destroy_encoder:
2043         drm_encoder_cleanup(encoder);
2044 err_unprepare_hsm:
2045         pm_runtime_disable(dev);
2046         put_device(&vc4_hdmi->ddc->dev);
2047
2048         return ret;
2049 }
2050
2051 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
2052                             void *data)
2053 {
2054         struct vc4_hdmi *vc4_hdmi;
2055
2056         /*
2057          * ASoC makes it a bit hard to retrieve a pointer to the
2058          * vc4_hdmi structure. Registering the card will overwrite our
2059          * device drvdata with a pointer to the snd_soc_card structure,
2060          * which can then be used to retrieve whatever drvdata we want
2061          * to associate.
2062          *
2063          * However, that doesn't fly in the case where we wouldn't
2064          * register an ASoC card (because of an old DT that is missing
2065          * the dmas properties for example), then the card isn't
2066          * registered and the device drvdata wouldn't be set.
2067          *
2068          * We can deal with both cases by making sure a snd_soc_card
2069          * pointer and a vc4_hdmi structure are pointing to the same
2070          * memory address, so we can treat them indistinctly without any
2071          * issue.
2072          */
2073         BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2074         BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2075         vc4_hdmi = dev_get_drvdata(dev);
2076
2077         kfree(vc4_hdmi->hdmi_regset.regs);
2078         kfree(vc4_hdmi->hd_regset.regs);
2079
2080         vc4_hdmi_cec_exit(vc4_hdmi);
2081         vc4_hdmi_connector_destroy(&vc4_hdmi->connector);
2082         drm_encoder_cleanup(&vc4_hdmi->encoder.base.base);
2083
2084         pm_runtime_disable(dev);
2085
2086         put_device(&vc4_hdmi->ddc->dev);
2087 }
2088
2089 static const struct component_ops vc4_hdmi_ops = {
2090         .bind   = vc4_hdmi_bind,
2091         .unbind = vc4_hdmi_unbind,
2092 };
2093
2094 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
2095 {
2096         return component_add(&pdev->dev, &vc4_hdmi_ops);
2097 }
2098
2099 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
2100 {
2101         component_del(&pdev->dev, &vc4_hdmi_ops);
2102         return 0;
2103 }
2104
2105 static const struct vc4_hdmi_variant bcm2835_variant = {
2106         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2107         .debugfs_name           = "hdmi_regs",
2108         .card_name              = "vc4-hdmi",
2109         .max_pixel_clock        = 162000000,
2110         .registers              = vc4_hdmi_fields,
2111         .num_registers          = ARRAY_SIZE(vc4_hdmi_fields),
2112
2113         .init_resources         = vc4_hdmi_init_resources,
2114         .csc_setup              = vc4_hdmi_csc_setup,
2115         .reset                  = vc4_hdmi_reset,
2116         .set_timings            = vc4_hdmi_set_timings,
2117         .phy_init               = vc4_hdmi_phy_init,
2118         .phy_disable            = vc4_hdmi_phy_disable,
2119         .phy_rng_enable         = vc4_hdmi_phy_rng_enable,
2120         .phy_rng_disable        = vc4_hdmi_phy_rng_disable,
2121         .channel_map            = vc4_hdmi_channel_map,
2122 };
2123
2124 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
2125         .encoder_type           = VC4_ENCODER_TYPE_HDMI0,
2126         .debugfs_name           = "hdmi0_regs",
2127         .card_name              = "vc4-hdmi-0",
2128         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2129         .registers              = vc5_hdmi_hdmi0_fields,
2130         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
2131         .phy_lane_mapping       = {
2132                 PHY_LANE_0,
2133                 PHY_LANE_1,
2134                 PHY_LANE_2,
2135                 PHY_LANE_CK,
2136         },
2137         .unsupported_odd_h_timings      = true,
2138         .external_irq_controller        = true,
2139
2140         .init_resources         = vc5_hdmi_init_resources,
2141         .csc_setup              = vc5_hdmi_csc_setup,
2142         .reset                  = vc5_hdmi_reset,
2143         .set_timings            = vc5_hdmi_set_timings,
2144         .phy_init               = vc5_hdmi_phy_init,
2145         .phy_disable            = vc5_hdmi_phy_disable,
2146         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2147         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2148         .channel_map            = vc5_hdmi_channel_map,
2149 };
2150
2151 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
2152         .encoder_type           = VC4_ENCODER_TYPE_HDMI1,
2153         .debugfs_name           = "hdmi1_regs",
2154         .card_name              = "vc4-hdmi-1",
2155         .max_pixel_clock        = HDMI_14_MAX_TMDS_CLK,
2156         .registers              = vc5_hdmi_hdmi1_fields,
2157         .num_registers          = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
2158         .phy_lane_mapping       = {
2159                 PHY_LANE_1,
2160                 PHY_LANE_0,
2161                 PHY_LANE_CK,
2162                 PHY_LANE_2,
2163         },
2164         .unsupported_odd_h_timings      = true,
2165         .external_irq_controller        = true,
2166
2167         .init_resources         = vc5_hdmi_init_resources,
2168         .csc_setup              = vc5_hdmi_csc_setup,
2169         .reset                  = vc5_hdmi_reset,
2170         .set_timings            = vc5_hdmi_set_timings,
2171         .phy_init               = vc5_hdmi_phy_init,
2172         .phy_disable            = vc5_hdmi_phy_disable,
2173         .phy_rng_enable         = vc5_hdmi_phy_rng_enable,
2174         .phy_rng_disable        = vc5_hdmi_phy_rng_disable,
2175         .channel_map            = vc5_hdmi_channel_map,
2176 };
2177
2178 static const struct of_device_id vc4_hdmi_dt_match[] = {
2179         { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
2180         { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
2181         { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
2182         {}
2183 };
2184
2185 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
2186         SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
2187                            vc4_hdmi_runtime_resume,
2188                            NULL)
2189 };
2190
2191 struct platform_driver vc4_hdmi_driver = {
2192         .probe = vc4_hdmi_dev_probe,
2193         .remove = vc4_hdmi_dev_remove,
2194         .driver = {
2195                 .name = "vc4_hdmi",
2196                 .of_match_table = vc4_hdmi_dt_match,
2197                 .pm = &vc4_hdmi_pm_ops,
2198         },
2199 };