1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2015 Broadcom
4 * Copyright (c) 2014 The Linux Foundation. All rights reserved.
5 * Copyright (C) 2013 Red Hat
6 * Author: Rob Clark <robdclark@gmail.com>
10 * DOC: VC4 Falcon HDMI module
12 * The HDMI core has a state machine and a PHY. On BCM2835, most of
13 * the unit operates off of the HSM clock from CPRMAN. It also
14 * internally uses the PLLH_PIX clock for the PHY.
16 * HDMI infoframes are kept within a small packet ram, where each
17 * packet can be individually enabled for including in a frame.
19 * HDMI audio is implemented entirely within the HDMI IP block. A
20 * register in the HDMI encoder takes SPDIF frames from the DMA engine
21 * and transfers them over an internal MAI (multi-channel audio
22 * interconnect) bus to the encoder side for insertion into the video
25 * The driver's HDMI encoder does not yet support power management.
26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept
27 * continuously running, and only the HDMI logic and packet ram are
28 * powered off/on at disable/enable time.
30 * The driver does not yet support CEC control, though the HDMI
31 * encoder block has CEC support.
34 #include <drm/display/drm_hdmi_helper.h>
35 #include <drm/display/drm_scdc_helper.h>
36 #include <drm/drm_atomic_helper.h>
37 #include <drm/drm_drv.h>
38 #include <drm/drm_probe_helper.h>
39 #include <drm/drm_simple_kms_helper.h>
40 #include <linux/clk.h>
41 #include <linux/component.h>
42 #include <linux/gpio/consumer.h>
43 #include <linux/i2c.h>
44 #include <linux/of_address.h>
45 #include <linux/of_platform.h>
46 #include <linux/pm_runtime.h>
47 #include <linux/rational.h>
48 #include <linux/reset.h>
49 #include <sound/dmaengine_pcm.h>
50 #include <sound/hdmi-codec.h>
51 #include <sound/pcm_drm_eld.h>
52 #include <sound/pcm_params.h>
53 #include <sound/soc.h>
54 #include "media/cec.h"
57 #include "vc4_hdmi_regs.h"
60 #define VC5_HDMI_HORZA_HFP_SHIFT 16
61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16)
62 #define VC5_HDMI_HORZA_VPOS BIT(15)
63 #define VC5_HDMI_HORZA_HPOS BIT(14)
64 #define VC5_HDMI_HORZA_HAP_SHIFT 0
65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0)
67 #define VC5_HDMI_HORZB_HBP_SHIFT 16
68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16)
69 #define VC5_HDMI_HORZB_HSP_SHIFT 0
70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0)
72 #define VC5_HDMI_VERTA_VSP_SHIFT 24
73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24)
74 #define VC5_HDMI_VERTA_VFP_SHIFT 16
75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16)
76 #define VC5_HDMI_VERTA_VAL_SHIFT 0
77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0)
79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16
80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16)
82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0
85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0)
87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0)
89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8
90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8)
92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0
93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0)
95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31)
97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8
98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8)
100 # define VC4_HD_M_SW_RST BIT(2)
101 # define VC4_HD_M_ENABLE BIT(0)
103 #define HSM_MIN_CLOCK_FREQ 120000000
104 #define CEC_CLOCK_FREQ 40000
106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000)
108 static const char * const output_format_str[] = {
109 [VC4_HDMI_OUTPUT_RGB] = "RGB",
110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0",
111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2",
112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4",
115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt)
117 if (fmt >= ARRAY_SIZE(output_format_str))
120 return output_format_str[fmt];
123 static unsigned long long
124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
125 unsigned int bpc, enum vc4_hdmi_output_format fmt);
127 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode,
129 enum vc4_hdmi_output_format fmt)
131 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
133 return clock > HDMI_14_MAX_TMDS_CLK;
136 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi,
137 const struct drm_display_mode *mode)
139 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
141 return !display->is_hdmi ||
142 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL;
145 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
147 struct drm_info_node *node = (struct drm_info_node *)m->private;
148 struct vc4_hdmi *vc4_hdmi = node->info_ent->data;
149 struct drm_device *drm = vc4_hdmi->connector.dev;
150 struct drm_printer p = drm_seq_file_printer(m);
153 if (!drm_dev_enter(drm, &idx))
156 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset);
157 drm_print_regset32(&p, &vc4_hdmi->hd_regset);
158 drm_print_regset32(&p, &vc4_hdmi->cec_regset);
159 drm_print_regset32(&p, &vc4_hdmi->csc_regset);
160 drm_print_regset32(&p, &vc4_hdmi->dvp_regset);
161 drm_print_regset32(&p, &vc4_hdmi->phy_regset);
162 drm_print_regset32(&p, &vc4_hdmi->ram_regset);
163 drm_print_regset32(&p, &vc4_hdmi->rm_regset);
170 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
172 struct drm_device *drm = vc4_hdmi->connector.dev;
177 * We can be called by our bind callback, when the
178 * connector->dev pointer might not be initialised yet.
180 if (drm && !drm_dev_enter(drm, &idx))
183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
185 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST);
187 HDMI_WRITE(HDMI_M_CTL, 0);
189 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE);
191 HDMI_WRITE(HDMI_SW_RESET_CONTROL,
192 VC4_HDMI_SW_RESET_HDMI |
193 VC4_HDMI_SW_RESET_FORMAT_DETECT);
195 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0);
197 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
203 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi)
205 struct drm_device *drm = vc4_hdmi->connector.dev;
210 * We can be called by our bind callback, when the
211 * connector->dev pointer might not be initialised yet.
213 if (drm && !drm_dev_enter(drm, &idx))
216 reset_control_reset(vc4_hdmi->reset);
218 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
220 HDMI_WRITE(HDMI_DVP_CTL, 0);
222 HDMI_WRITE(HDMI_CLOCK_STOP,
223 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL);
225 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
231 #ifdef CONFIG_DRM_VC4_HDMI_CEC
232 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi)
234 struct drm_device *drm = vc4_hdmi->connector.dev;
235 unsigned long cec_rate;
242 * This function is called by our runtime_resume implementation
243 * and thus at bind time, when we haven't registered our
244 * connector yet and thus don't have a pointer to the DRM
247 if (drm && !drm_dev_enter(drm, &idx))
250 cec_rate = clk_get_rate(vc4_hdmi->cec_clock);
252 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
254 value = HDMI_READ(HDMI_CEC_CNTRL_1);
255 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK;
258 * Set the clock divider: the hsm_clock rate and this divider
259 * setting will give a 40 kHz CEC clock.
261 clk_cnt = cec_rate / CEC_CLOCK_FREQ;
262 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT;
263 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
265 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
271 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {}
274 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder);
276 static enum drm_connector_status
277 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
279 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
280 bool connected = false;
282 mutex_lock(&vc4_hdmi->mutex);
284 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev));
286 if (vc4_hdmi->hpd_gpio) {
287 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio))
290 if (vc4_hdmi->variant->hp_detect &&
291 vc4_hdmi->variant->hp_detect(vc4_hdmi))
296 if (connector->status != connector_status_connected) {
297 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc);
300 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
305 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base);
306 pm_runtime_put(&vc4_hdmi->pdev->dev);
307 mutex_unlock(&vc4_hdmi->mutex);
308 return connector_status_connected;
311 cec_phys_addr_invalidate(vc4_hdmi->cec_adap);
312 pm_runtime_put(&vc4_hdmi->pdev->dev);
313 mutex_unlock(&vc4_hdmi->mutex);
314 return connector_status_disconnected;
317 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
319 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector);
323 mutex_lock(&vc4_hdmi->mutex);
325 edid = drm_get_edid(connector, vc4_hdmi->ddc);
326 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid);
332 drm_connector_update_edid_property(connector, edid);
333 ret = drm_add_edid_modes(connector, edid);
336 if (vc4_hdmi->disable_4kp60) {
337 struct drm_device *drm = connector->dev;
338 struct drm_display_mode *mode;
340 list_for_each_entry(mode, &connector->probed_modes, head) {
341 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) {
342 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz.");
343 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60.");
349 mutex_unlock(&vc4_hdmi->mutex);
354 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector,
355 struct drm_atomic_state *state)
357 struct drm_connector_state *old_state =
358 drm_atomic_get_old_connector_state(state, connector);
359 struct drm_connector_state *new_state =
360 drm_atomic_get_new_connector_state(state, connector);
361 struct drm_crtc *crtc = new_state->crtc;
366 if (old_state->colorspace != new_state->colorspace ||
367 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) {
368 struct drm_crtc_state *crtc_state;
370 crtc_state = drm_atomic_get_crtc_state(state, crtc);
371 if (IS_ERR(crtc_state))
372 return PTR_ERR(crtc_state);
374 crtc_state->mode_changed = true;
380 static void vc4_hdmi_connector_reset(struct drm_connector *connector)
382 struct vc4_hdmi_connector_state *old_state =
383 conn_state_to_vc4_hdmi_conn_state(connector->state);
384 struct vc4_hdmi_connector_state *new_state =
385 kzalloc(sizeof(*new_state), GFP_KERNEL);
387 if (connector->state)
388 __drm_atomic_helper_connector_destroy_state(connector->state);
391 __drm_atomic_helper_connector_reset(connector, &new_state->base);
396 new_state->base.max_bpc = 8;
397 new_state->base.max_requested_bpc = 8;
398 new_state->output_format = VC4_HDMI_OUTPUT_RGB;
399 drm_atomic_helper_connector_tv_reset(connector);
402 static struct drm_connector_state *
403 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector)
405 struct drm_connector_state *conn_state = connector->state;
406 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
407 struct vc4_hdmi_connector_state *new_state;
409 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
413 new_state->tmds_char_rate = vc4_state->tmds_char_rate;
414 new_state->output_bpc = vc4_state->output_bpc;
415 new_state->output_format = vc4_state->output_format;
416 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
418 return &new_state->base;
421 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
422 .detect = vc4_hdmi_connector_detect,
423 .fill_modes = drm_helper_probe_single_connector_modes,
424 .reset = vc4_hdmi_connector_reset,
425 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state,
426 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
429 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
430 .get_modes = vc4_hdmi_connector_get_modes,
431 .atomic_check = vc4_hdmi_connector_atomic_check,
434 static int vc4_hdmi_connector_init(struct drm_device *dev,
435 struct vc4_hdmi *vc4_hdmi)
437 struct drm_connector *connector = &vc4_hdmi->connector;
438 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
441 ret = drmm_connector_init(dev, connector,
442 &vc4_hdmi_connector_funcs,
443 DRM_MODE_CONNECTOR_HDMIA,
448 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
451 * Some of the properties below require access to state, like bpc.
452 * Allocate some default initial connector state with our reset helper.
454 if (connector->funcs->reset)
455 connector->funcs->reset(connector);
457 /* Create and attach TV margin props to this connector. */
458 ret = drm_mode_create_tv_margin_properties(dev);
462 ret = drm_mode_create_hdmi_colorspace_property(connector);
466 drm_connector_attach_colorspace_property(connector);
467 drm_connector_attach_tv_margin_properties(connector);
468 drm_connector_attach_max_bpc_property(connector, 8, 12);
470 connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
471 DRM_CONNECTOR_POLL_DISCONNECT);
473 connector->interlace_allowed = 1;
474 connector->doublescan_allowed = 0;
475 connector->stereo_allowed = 1;
477 if (vc4_hdmi->variant->supports_hdr)
478 drm_connector_attach_hdr_output_metadata_property(connector);
480 drm_connector_attach_encoder(connector, encoder);
485 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder,
486 enum hdmi_infoframe_type type,
489 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
490 struct drm_device *drm = vc4_hdmi->connector.dev;
491 u32 packet_id = type - 0x80;
496 if (!drm_dev_enter(drm, &idx))
499 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
500 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
501 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id));
502 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
505 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) &
506 BIT(packet_id)), 100);
513 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder,
514 union hdmi_infoframe *frame)
516 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
517 struct drm_device *drm = vc4_hdmi->connector.dev;
518 u32 packet_id = frame->any.type - 0x80;
519 const struct vc4_hdmi_register *ram_packet_start =
520 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START];
521 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id;
522 u32 packet_reg_next = ram_packet_start->offset +
523 VC4_HDMI_PACKET_STRIDE * (packet_id + 1);
524 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi,
525 ram_packet_start->reg);
526 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {};
532 if (!drm_dev_enter(drm, &idx))
535 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
536 VC4_HDMI_RAM_PACKET_ENABLE),
537 "Packet RAM has to be on to store the packet.");
539 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer));
543 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true);
545 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret);
549 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
551 for (i = 0; i < len; i += 7) {
552 writel(buffer[i + 0] << 0 |
558 writel(buffer[i + 3] << 0 |
560 buffer[i + 5] << 16 |
567 * clear remainder of packet ram as it's included in the
568 * infoframe and triggers a checksum error on hdmi analyser
570 for (; packet_reg < packet_reg_next; packet_reg += 4)
571 writel(0, base + packet_reg);
573 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
574 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id));
576 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
578 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) &
579 BIT(packet_id)), 100);
581 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret);
587 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame,
588 enum vc4_hdmi_output_format fmt)
591 case VC4_HDMI_OUTPUT_RGB:
592 frame->colorspace = HDMI_COLORSPACE_RGB;
595 case VC4_HDMI_OUTPUT_YUV420:
596 frame->colorspace = HDMI_COLORSPACE_YUV420;
599 case VC4_HDMI_OUTPUT_YUV422:
600 frame->colorspace = HDMI_COLORSPACE_YUV422;
603 case VC4_HDMI_OUTPUT_YUV444:
604 frame->colorspace = HDMI_COLORSPACE_YUV444;
612 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder)
614 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
615 struct drm_connector *connector = &vc4_hdmi->connector;
616 struct drm_connector_state *cstate = connector->state;
617 struct vc4_hdmi_connector_state *vc4_state =
618 conn_state_to_vc4_hdmi_conn_state(cstate);
619 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
620 union hdmi_infoframe frame;
623 lockdep_assert_held(&vc4_hdmi->mutex);
625 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
628 DRM_ERROR("couldn't fill AVI infoframe\n");
632 drm_hdmi_avi_infoframe_quant_range(&frame.avi,
634 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ?
635 HDMI_QUANTIZATION_RANGE_FULL :
636 HDMI_QUANTIZATION_RANGE_LIMITED);
637 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate);
638 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format);
639 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate);
641 vc4_hdmi_write_infoframe(encoder, &frame);
644 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder)
646 union hdmi_infoframe frame;
649 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore");
651 DRM_ERROR("couldn't fill SPD infoframe\n");
655 frame.spd.sdi = HDMI_SPD_SDI_PC;
657 vc4_hdmi_write_infoframe(encoder, &frame);
660 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder)
662 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
663 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe;
664 union hdmi_infoframe frame;
666 memcpy(&frame.audio, audio, sizeof(*audio));
668 if (vc4_hdmi->packet_ram_enabled)
669 vc4_hdmi_write_infoframe(encoder, &frame);
672 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder)
674 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
675 struct drm_connector *connector = &vc4_hdmi->connector;
676 struct drm_connector_state *conn_state = connector->state;
677 union hdmi_infoframe frame;
679 lockdep_assert_held(&vc4_hdmi->mutex);
681 if (!vc4_hdmi->variant->supports_hdr)
684 if (!conn_state->hdr_output_metadata)
687 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state))
690 vc4_hdmi_write_infoframe(encoder, &frame);
693 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder)
695 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
697 lockdep_assert_held(&vc4_hdmi->mutex);
699 vc4_hdmi_set_avi_infoframe(encoder);
700 vc4_hdmi_set_spd_infoframe(encoder);
702 * If audio was streaming, then we need to reenabled the audio
703 * infoframe here during encoder_enable.
705 if (vc4_hdmi->audio.streaming)
706 vc4_hdmi_set_audio_infoframe(encoder);
708 vc4_hdmi_set_hdr_infoframe(encoder);
711 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder,
712 struct drm_display_mode *mode)
714 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
715 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
717 lockdep_assert_held(&vc4_hdmi->mutex);
719 if (!display->is_hdmi)
722 if (!display->hdmi.scdc.supported ||
723 !display->hdmi.scdc.scrambling.supported)
729 #define SCRAMBLING_POLLING_DELAY_MS 1000
731 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder)
733 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
734 struct drm_device *drm = vc4_hdmi->connector.dev;
735 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
739 lockdep_assert_held(&vc4_hdmi->mutex);
741 if (!vc4_hdmi_supports_scrambling(encoder, mode))
744 if (!vc4_hdmi_mode_needs_scrambling(mode,
745 vc4_hdmi->output_bpc,
746 vc4_hdmi->output_format))
749 if (!drm_dev_enter(drm, &idx))
752 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
753 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
755 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
756 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) |
757 VC5_HDMI_SCRAMBLER_CTL_ENABLE);
758 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
762 vc4_hdmi->scdc_enabled = true;
764 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
765 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
768 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder)
770 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
771 struct drm_device *drm = vc4_hdmi->connector.dev;
775 lockdep_assert_held(&vc4_hdmi->mutex);
777 if (!vc4_hdmi->scdc_enabled)
780 vc4_hdmi->scdc_enabled = false;
782 if (delayed_work_pending(&vc4_hdmi->scrambling_work))
783 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work);
785 if (!drm_dev_enter(drm, &idx))
788 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
789 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) &
790 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE);
791 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
793 drm_scdc_set_scrambling(vc4_hdmi->ddc, false);
794 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false);
799 static void vc4_hdmi_scrambling_wq(struct work_struct *work)
801 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work),
805 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc))
808 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true);
809 drm_scdc_set_scrambling(vc4_hdmi->ddc, true);
811 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work,
812 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS));
815 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder,
816 struct drm_atomic_state *state)
818 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
819 struct drm_device *drm = vc4_hdmi->connector.dev;
823 mutex_lock(&vc4_hdmi->mutex);
825 vc4_hdmi->packet_ram_enabled = false;
827 if (!drm_dev_enter(drm, &idx))
830 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
832 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
834 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB);
836 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
840 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
841 HDMI_WRITE(HDMI_VID_CTL,
842 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
843 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
845 vc4_hdmi_disable_scrambling(encoder);
850 mutex_unlock(&vc4_hdmi->mutex);
853 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder,
854 struct drm_atomic_state *state)
856 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
857 struct drm_device *drm = vc4_hdmi->connector.dev;
862 mutex_lock(&vc4_hdmi->mutex);
864 if (!drm_dev_enter(drm, &idx))
867 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
868 HDMI_WRITE(HDMI_VID_CTL,
869 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
870 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
872 if (vc4_hdmi->variant->phy_disable)
873 vc4_hdmi->variant->phy_disable(vc4_hdmi);
875 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock);
876 clk_disable_unprepare(vc4_hdmi->pixel_clock);
878 ret = pm_runtime_put(&vc4_hdmi->pdev->dev);
880 DRM_ERROR("Failed to release power domain: %d\n", ret);
885 mutex_unlock(&vc4_hdmi->mutex);
888 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
889 struct drm_connector_state *state,
890 const struct drm_display_mode *mode)
892 struct drm_device *drm = vc4_hdmi->connector.dev;
897 if (!drm_dev_enter(drm, &idx))
900 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
902 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
903 VC4_HD_CSC_CTL_ORDER);
905 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) {
906 /* CEA VICs other than #1 requre limited range RGB
907 * output unless overridden by an AVI infoframe.
908 * Apply a colorspace conversion to squash 0-255 down
909 * to 16-235. The matrix here is:
916 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
917 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
918 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
919 VC4_HD_CSC_CTL_MODE);
921 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000);
922 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0);
923 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000);
924 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000);
925 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0);
926 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000);
929 /* The RGB order applies even when CSC is disabled. */
930 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
932 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
938 * If we need to output Full Range RGB, then use the unity matrix
944 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
946 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = {
947 { 0x2000, 0x0000, 0x0000, 0x0000 },
948 { 0x0000, 0x2000, 0x0000, 0x0000 },
949 { 0x0000, 0x0000, 0x2000, 0x0000 },
953 * CEA VICs other than #1 require limited range RGB output unless
954 * overridden by an AVI infoframe. Apply a colorspace conversion to
955 * squash 0-255 down to 16-235. The matrix here is:
961 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
963 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = {
964 { 0x1b80, 0x0000, 0x0000, 0x0400 },
965 { 0x0000, 0x1b80, 0x0000, 0x0400 },
966 { 0x0000, 0x0000, 0x1b80, 0x0400 },
970 * Conversion between Full Range RGB and Full Range YUV422 using the
974 * [ 0.181906 0.611804 0.061758 16 ]
975 * [ -0.100268 -0.337232 0.437500 128 ]
976 * [ 0.437500 -0.397386 -0.040114 128 ]
978 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
980 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = {
981 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
982 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
983 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
987 * Conversion between Full Range RGB and Full Range YUV444 using the
990 * [ -0.100268 -0.337232 0.437500 128 ]
991 * [ 0.437500 -0.397386 -0.040114 128 ]
992 * [ 0.181906 0.611804 0.061758 16 ]
994 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets
996 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = {
997 { 0xfccc, 0xf536, 0x0e00, 0x2000 },
998 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 },
999 { 0x05d2, 0x1394, 0x01fa, 0x0400 },
1002 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi,
1003 const u16 coeffs[3][4])
1005 lockdep_assert_held(&vc4_hdmi->hw_lock);
1007 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]);
1008 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]);
1009 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]);
1010 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]);
1011 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]);
1012 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]);
1015 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi,
1016 struct drm_connector_state *state,
1017 const struct drm_display_mode *mode)
1019 struct drm_device *drm = vc4_hdmi->connector.dev;
1020 struct vc4_hdmi_connector_state *vc4_state =
1021 conn_state_to_vc4_hdmi_conn_state(state);
1022 unsigned long flags;
1024 u32 if_xbar = 0x543210;
1025 u32 csc_chan_ctl = 0;
1026 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
1027 VC5_MT_CP_CSC_CTL_MODE);
1030 if (!drm_dev_enter(drm, &idx))
1033 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1035 switch (vc4_state->output_format) {
1036 case VC4_HDMI_OUTPUT_YUV444:
1037 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709);
1040 case VC4_HDMI_OUTPUT_YUV422:
1041 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD,
1042 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) |
1043 VC5_MT_CP_CSC_CTL_USE_444_TO_422 |
1044 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION;
1046 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE,
1047 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP);
1049 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY,
1050 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422);
1052 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709);
1055 case VC4_HDMI_OUTPUT_RGB:
1058 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode))
1059 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb);
1061 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity);
1068 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg);
1069 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar);
1070 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl);
1071 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl);
1073 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1078 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1079 struct drm_connector_state *state,
1080 struct drm_display_mode *mode)
1082 struct drm_device *drm = vc4_hdmi->connector.dev;
1083 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1084 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1085 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1086 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1087 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1088 VC4_HDMI_VERTA_VSP) |
1089 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1090 VC4_HDMI_VERTA_VFP) |
1091 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
1092 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1093 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end +
1095 VC4_HDMI_VERTB_VBP));
1096 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
1097 VC4_SET_FIELD(mode->crtc_vtotal -
1098 mode->crtc_vsync_end,
1099 VC4_HDMI_VERTB_VBP));
1100 unsigned long flags;
1104 if (!drm_dev_enter(drm, &idx))
1107 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1109 HDMI_WRITE(HDMI_HORZA,
1110 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
1111 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
1112 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1113 VC4_HDMI_HORZA_HAP));
1115 HDMI_WRITE(HDMI_HORZB,
1116 VC4_SET_FIELD((mode->htotal -
1117 mode->hsync_end) * pixel_rep,
1118 VC4_HDMI_HORZB_HBP) |
1119 VC4_SET_FIELD((mode->hsync_end -
1120 mode->hsync_start) * pixel_rep,
1121 VC4_HDMI_HORZB_HSP) |
1122 VC4_SET_FIELD((mode->hsync_start -
1123 mode->hdisplay) * pixel_rep,
1124 VC4_HDMI_HORZB_HFP));
1126 HDMI_WRITE(HDMI_VERTA0, verta);
1127 HDMI_WRITE(HDMI_VERTA1, verta);
1129 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1130 HDMI_WRITE(HDMI_VERTB1, vertb);
1132 reg = HDMI_READ(HDMI_MISC_CONTROL);
1133 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1134 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP);
1135 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1142 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi,
1143 struct drm_connector_state *state,
1144 struct drm_display_mode *mode)
1146 struct drm_device *drm = vc4_hdmi->connector.dev;
1147 const struct vc4_hdmi_connector_state *vc4_state =
1148 conn_state_to_vc4_hdmi_conn_state(state);
1149 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1150 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1151 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
1152 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
1153 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
1154 VC5_HDMI_VERTA_VSP) |
1155 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
1156 VC5_HDMI_VERTA_VFP) |
1157 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL));
1158 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep),
1159 VC5_HDMI_VERTB_VSPO) |
1160 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
1161 VC4_HDMI_VERTB_VBP));
1162 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) |
1163 VC4_SET_FIELD(mode->crtc_vtotal -
1164 mode->crtc_vsync_end - interlaced,
1165 VC4_HDMI_VERTB_VBP));
1166 unsigned long flags;
1172 if (!drm_dev_enter(drm, &idx))
1175 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1177 HDMI_WRITE(HDMI_HORZA,
1178 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) |
1179 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) |
1180 VC4_SET_FIELD(mode->hdisplay * pixel_rep,
1181 VC5_HDMI_HORZA_HAP) |
1182 VC4_SET_FIELD((mode->hsync_start -
1183 mode->hdisplay) * pixel_rep,
1184 VC5_HDMI_HORZA_HFP));
1186 HDMI_WRITE(HDMI_HORZB,
1187 VC4_SET_FIELD((mode->htotal -
1188 mode->hsync_end) * pixel_rep,
1189 VC5_HDMI_HORZB_HBP) |
1190 VC4_SET_FIELD((mode->hsync_end -
1191 mode->hsync_start) * pixel_rep,
1192 VC5_HDMI_HORZB_HSP));
1194 HDMI_WRITE(HDMI_VERTA0, verta);
1195 HDMI_WRITE(HDMI_VERTA1, verta);
1197 HDMI_WRITE(HDMI_VERTB0, vertb_even);
1198 HDMI_WRITE(HDMI_VERTB1, vertb);
1200 switch (vc4_state->output_bpc) {
1217 * YCC422 is always 36-bit and not considered deep colour so
1218 * doesn't signal in GCP.
1220 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) {
1225 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1);
1226 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK |
1227 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK);
1228 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) |
1229 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH);
1230 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg);
1232 reg = HDMI_READ(HDMI_GCP_WORD_1);
1233 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK;
1234 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1);
1235 HDMI_WRITE(HDMI_GCP_WORD_1, reg);
1237 reg = HDMI_READ(HDMI_GCP_CONFIG);
1238 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE;
1239 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0;
1240 HDMI_WRITE(HDMI_GCP_CONFIG, reg);
1242 reg = HDMI_READ(HDMI_MISC_CONTROL);
1243 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK;
1244 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP);
1245 HDMI_WRITE(HDMI_MISC_CONTROL, reg);
1247 HDMI_WRITE(HDMI_CLOCK_STOP, 0);
1249 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1254 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi)
1256 struct drm_device *drm = vc4_hdmi->connector.dev;
1257 unsigned long flags;
1262 if (!drm_dev_enter(drm, &idx))
1265 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1267 drift = HDMI_READ(HDMI_FIFO_CTL);
1268 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
1270 HDMI_WRITE(HDMI_FIFO_CTL,
1271 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1272 HDMI_WRITE(HDMI_FIFO_CTL,
1273 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1275 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1277 usleep_range(1000, 1100);
1279 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1281 HDMI_WRITE(HDMI_FIFO_CTL,
1282 drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
1283 HDMI_WRITE(HDMI_FIFO_CTL,
1284 drift | VC4_HDMI_FIFO_CTL_RECENTER);
1286 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1288 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) &
1289 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
1290 WARN_ONCE(ret, "Timeout waiting for "
1291 "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
1296 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder,
1297 struct drm_atomic_state *state)
1299 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1300 struct drm_device *drm = vc4_hdmi->connector.dev;
1301 struct drm_connector *connector = &vc4_hdmi->connector;
1302 struct drm_connector_state *conn_state =
1303 drm_atomic_get_new_connector_state(state, connector);
1304 struct vc4_hdmi_connector_state *vc4_conn_state =
1305 conn_state_to_vc4_hdmi_conn_state(conn_state);
1306 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1307 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate;
1308 unsigned long bvb_rate, hsm_rate;
1309 unsigned long flags;
1313 mutex_lock(&vc4_hdmi->mutex);
1315 if (!drm_dev_enter(drm, &idx))
1319 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must
1320 * be faster than pixel clock, infinitesimally faster, tested in
1321 * simulation. Otherwise, exact value is unimportant for HDMI
1322 * operation." This conflicts with bcm2835's vc4 documentation, which
1323 * states HSM's clock has to be at least 108% of the pixel clock.
1325 * Real life tests reveal that vc4's firmware statement holds up, and
1326 * users are able to use pixel clocks closer to HSM's, namely for
1327 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between
1328 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of
1331 * Additionally, the AXI clock needs to be at least 25% of
1332 * pixel clock, but HSM ends up being the limiting factor.
1334 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101);
1335 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate);
1337 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
1341 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
1343 DRM_ERROR("Failed to retain power domain: %d\n", ret);
1347 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate);
1349 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret);
1350 goto err_put_runtime_pm;
1353 ret = clk_prepare_enable(vc4_hdmi->pixel_clock);
1355 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
1356 goto err_put_runtime_pm;
1360 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
1362 if (tmds_char_rate > 297000000)
1363 bvb_rate = 300000000;
1364 else if (tmds_char_rate > 148500000)
1365 bvb_rate = 150000000;
1367 bvb_rate = 75000000;
1369 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate);
1371 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret);
1372 goto err_disable_pixel_clock;
1375 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
1377 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret);
1378 goto err_disable_pixel_clock;
1381 if (vc4_hdmi->variant->phy_init)
1382 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
1384 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1386 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1387 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1388 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
1389 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
1391 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1393 if (vc4_hdmi->variant->set_timings)
1394 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode);
1398 mutex_unlock(&vc4_hdmi->mutex);
1402 err_disable_pixel_clock:
1403 clk_disable_unprepare(vc4_hdmi->pixel_clock);
1405 pm_runtime_put(&vc4_hdmi->pdev->dev);
1409 mutex_unlock(&vc4_hdmi->mutex);
1413 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder,
1414 struct drm_atomic_state *state)
1416 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1417 struct drm_device *drm = vc4_hdmi->connector.dev;
1418 struct drm_connector *connector = &vc4_hdmi->connector;
1419 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1420 struct drm_connector_state *conn_state =
1421 drm_atomic_get_new_connector_state(state, connector);
1422 unsigned long flags;
1425 mutex_lock(&vc4_hdmi->mutex);
1427 if (!drm_dev_enter(drm, &idx))
1430 if (vc4_hdmi->variant->csc_setup)
1431 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode);
1433 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1434 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
1435 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1440 mutex_unlock(&vc4_hdmi->mutex);
1443 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder,
1444 struct drm_atomic_state *state)
1446 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1447 struct drm_device *drm = vc4_hdmi->connector.dev;
1448 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1449 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1450 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
1451 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
1452 unsigned long flags;
1456 mutex_lock(&vc4_hdmi->mutex);
1458 if (!drm_dev_enter(drm, &idx))
1461 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1463 HDMI_WRITE(HDMI_VID_CTL,
1464 VC4_HD_VID_CTL_ENABLE |
1465 VC4_HD_VID_CTL_CLRRGB |
1466 VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
1467 VC4_HD_VID_CTL_FRAME_COUNTER_RESET |
1468 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
1469 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
1471 HDMI_WRITE(HDMI_VID_CTL,
1472 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
1474 if (display->is_hdmi) {
1475 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1476 HDMI_READ(HDMI_SCHEDULER_CONTROL) |
1477 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1479 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1481 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1482 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000);
1483 WARN_ONCE(ret, "Timeout waiting for "
1484 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1486 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1487 HDMI_READ(HDMI_RAM_PACKET_CONFIG) &
1488 ~(VC4_HDMI_RAM_PACKET_ENABLE));
1489 HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
1490 HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1491 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
1493 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1495 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1496 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000);
1497 WARN_ONCE(ret, "Timeout waiting for "
1498 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
1501 if (display->is_hdmi) {
1502 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1504 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) &
1505 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
1507 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG,
1508 VC4_HDMI_RAM_PACKET_ENABLE);
1510 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1511 vc4_hdmi->packet_ram_enabled = true;
1513 vc4_hdmi_set_infoframes(encoder);
1516 vc4_hdmi_recenter_fifo(vc4_hdmi);
1517 vc4_hdmi_enable_scrambling(encoder);
1522 mutex_unlock(&vc4_hdmi->mutex);
1525 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder,
1526 struct drm_crtc_state *crtc_state,
1527 struct drm_connector_state *conn_state)
1529 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1530 struct vc4_hdmi_connector_state *vc4_state =
1531 conn_state_to_vc4_hdmi_conn_state(conn_state);
1533 mutex_lock(&vc4_hdmi->mutex);
1534 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode,
1535 &crtc_state->adjusted_mode);
1536 vc4_hdmi->output_bpc = vc4_state->output_bpc;
1537 vc4_hdmi->output_format = vc4_state->output_format;
1538 mutex_unlock(&vc4_hdmi->mutex);
1542 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi,
1543 const struct drm_display_info *info,
1544 const struct drm_display_mode *mode,
1545 unsigned int format, unsigned int bpc)
1547 struct drm_device *dev = vc4_hdmi->connector.dev;
1548 u8 vic = drm_match_cea_mode(mode);
1550 if (vic == 1 && bpc != 8) {
1551 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc);
1555 if (!info->is_hdmi &&
1556 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) {
1557 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n");
1562 case VC4_HDMI_OUTPUT_RGB:
1563 drm_dbg(dev, "RGB Format, checking the constraints.\n");
1565 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444))
1568 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1569 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1573 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1574 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1578 drm_dbg(dev, "RGB format supported in that configuration.\n");
1582 case VC4_HDMI_OUTPUT_YUV422:
1583 drm_dbg(dev, "YUV422 format, checking the constraints.\n");
1585 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) {
1586 drm_dbg(dev, "Sink doesn't support YUV422.\n");
1591 drm_dbg(dev, "YUV422 only supports 12 bpc.\n");
1595 drm_dbg(dev, "YUV422 format supported in that configuration.\n");
1599 case VC4_HDMI_OUTPUT_YUV444:
1600 drm_dbg(dev, "YUV444 format, checking the constraints.\n");
1602 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) {
1603 drm_dbg(dev, "Sink doesn't support YUV444.\n");
1607 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) {
1608 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n");
1612 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) {
1613 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n");
1617 drm_dbg(dev, "YUV444 format supported in that configuration.\n");
1625 static enum drm_mode_status
1626 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi,
1627 unsigned long long clock)
1629 const struct drm_connector *connector = &vc4_hdmi->connector;
1630 const struct drm_display_info *info = &connector->display_info;
1632 if (clock > vc4_hdmi->variant->max_pixel_clock)
1633 return MODE_CLOCK_HIGH;
1635 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK)
1636 return MODE_CLOCK_HIGH;
1638 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000))
1639 return MODE_CLOCK_HIGH;
1644 static unsigned long long
1645 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode,
1647 enum vc4_hdmi_output_format fmt)
1649 unsigned long long clock = mode->clock * 1000ULL;
1651 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1654 if (fmt == VC4_HDMI_OUTPUT_YUV422)
1657 clock = clock * bpc;
1664 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi,
1665 struct vc4_hdmi_connector_state *vc4_state,
1666 const struct drm_display_mode *mode,
1667 unsigned int bpc, unsigned int fmt)
1669 unsigned long long clock;
1671 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt);
1672 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK)
1675 vc4_state->tmds_char_rate = clock;
1681 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi,
1682 struct vc4_hdmi_connector_state *vc4_state,
1683 const struct drm_display_mode *mode,
1686 struct drm_device *dev = vc4_hdmi->connector.dev;
1687 const struct drm_connector *connector = &vc4_hdmi->connector;
1688 const struct drm_display_info *info = &connector->display_info;
1689 unsigned int format;
1691 drm_dbg(dev, "Trying with an RGB output\n");
1693 format = VC4_HDMI_OUTPUT_RGB;
1694 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1697 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1700 vc4_state->output_format = format;
1705 drm_dbg(dev, "Failed, Trying with an YUV422 output\n");
1707 format = VC4_HDMI_OUTPUT_YUV422;
1708 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) {
1711 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state,
1714 vc4_state->output_format = format;
1719 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n");
1725 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi,
1726 struct vc4_hdmi_connector_state *vc4_state,
1727 const struct drm_display_mode *mode)
1729 struct drm_device *dev = vc4_hdmi->connector.dev;
1730 struct drm_connector_state *conn_state = &vc4_state->base;
1731 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12);
1735 for (bpc = max_bpc; bpc >= 8; bpc -= 2) {
1736 drm_dbg(dev, "Trying with a %d bpc output\n", bpc);
1738 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state,
1743 vc4_state->output_bpc = bpc;
1746 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n",
1747 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode),
1748 vc4_state->output_bpc,
1749 vc4_hdmi_output_fmt_str(vc4_state->output_format),
1750 vc4_state->tmds_char_rate);
1758 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL
1759 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL
1761 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1762 struct drm_crtc_state *crtc_state,
1763 struct drm_connector_state *conn_state)
1765 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1766 struct drm_connector *connector = &vc4_hdmi->connector;
1767 struct drm_connector_state *old_conn_state =
1768 drm_atomic_get_old_connector_state(conn_state->state, connector);
1769 struct vc4_hdmi_connector_state *old_vc4_state =
1770 conn_state_to_vc4_hdmi_conn_state(old_conn_state);
1771 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state);
1772 struct drm_display_mode *mode = &crtc_state->adjusted_mode;
1773 unsigned long long tmds_char_rate = mode->clock * 1000;
1774 unsigned long long tmds_bit_rate;
1777 if (vc4_hdmi->variant->unsupported_odd_h_timings) {
1778 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1779 /* Only try to fixup DBLCLK modes to get 480i and 576i
1781 * A generic solution for all modes with odd horizontal
1782 * timing values seems impossible based on trying to
1783 * solve it for 1366x768 monitors.
1785 if ((mode->hsync_start - mode->hdisplay) & 1)
1786 mode->hsync_start--;
1787 if ((mode->hsync_end - mode->hsync_start) & 1)
1791 /* Now check whether we still have odd values remaining */
1792 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1793 (mode->hsync_end % 2) || (mode->htotal % 2))
1798 * The 1440p@60 pixel rate is in the same range than the first
1799 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz
1800 * bandwidth). Slightly lower the frequency to bring it out of
1803 tmds_bit_rate = tmds_char_rate * 10;
1804 if (vc4_hdmi->disable_wifi_frequencies &&
1805 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ &&
1806 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) {
1807 mode->clock = 238560;
1808 tmds_char_rate = mode->clock * 1000;
1811 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode);
1815 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */
1816 if (vc4_state->output_bpc != old_vc4_state->output_bpc ||
1817 vc4_state->output_format != old_vc4_state->output_format)
1818 crtc_state->mode_changed = true;
1823 static enum drm_mode_status
1824 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder,
1825 const struct drm_display_mode *mode)
1827 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1829 if (vc4_hdmi->variant->unsupported_odd_h_timings &&
1830 !(mode->flags & DRM_MODE_FLAG_DBLCLK) &&
1831 ((mode->hdisplay % 2) || (mode->hsync_start % 2) ||
1832 (mode->hsync_end % 2) || (mode->htotal % 2)))
1833 return MODE_H_ILLEGAL;
1835 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000);
1838 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
1839 .atomic_check = vc4_hdmi_encoder_atomic_check,
1840 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set,
1841 .mode_valid = vc4_hdmi_encoder_mode_valid,
1844 static int vc4_hdmi_late_register(struct drm_encoder *encoder)
1846 struct drm_device *drm = encoder->dev;
1847 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);
1848 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
1851 ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name,
1852 vc4_hdmi_debugfs_regs,
1860 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
1861 .late_register = vc4_hdmi_late_register,
1864 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1867 u32 channel_map = 0;
1869 for (i = 0; i < 8; i++) {
1870 if (channel_mask & BIT(i))
1871 channel_map |= i << (3 * i);
1876 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask)
1879 u32 channel_map = 0;
1881 for (i = 0; i < 8; i++) {
1882 if (channel_mask & BIT(i))
1883 channel_map |= i << (4 * i);
1888 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi)
1890 struct drm_device *drm = vc4_hdmi->connector.dev;
1891 unsigned long flags;
1895 if (!drm_dev_enter(drm, &idx))
1898 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1899 hotplug = HDMI_READ(HDMI_HOTPLUG);
1900 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1904 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED);
1907 /* HDMI audio codec callbacks */
1908 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi,
1909 unsigned int samplerate)
1911 struct drm_device *drm = vc4_hdmi->connector.dev;
1913 unsigned long flags;
1917 if (!drm_dev_enter(drm, &idx))
1920 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock);
1921 rational_best_approximation(hsm_clock, samplerate,
1922 VC4_HD_MAI_SMP_N_MASK >>
1923 VC4_HD_MAI_SMP_N_SHIFT,
1924 (VC4_HD_MAI_SMP_M_MASK >>
1925 VC4_HD_MAI_SMP_M_SHIFT) + 1,
1928 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
1929 HDMI_WRITE(HDMI_MAI_SMP,
1930 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) |
1931 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M));
1932 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
1937 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate)
1939 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode;
1943 lockdep_assert_held(&vc4_hdmi->mutex);
1944 lockdep_assert_held(&vc4_hdmi->hw_lock);
1946 n = 128 * samplerate / 1000;
1947 tmp = (u64)(mode->clock * 1000) * n;
1948 do_div(tmp, 128 * samplerate);
1951 HDMI_WRITE(HDMI_CRP_CFG,
1952 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN |
1953 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N));
1956 * We could get slightly more accurate clocks in some cases by
1957 * providing a CTS_1 value. The two CTS values are alternated
1958 * between based on the period fields
1960 HDMI_WRITE(HDMI_CTS_0, cts);
1961 HDMI_WRITE(HDMI_CTS_1, cts);
1964 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai)
1966 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai);
1968 return snd_soc_card_get_drvdata(card);
1971 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi)
1973 struct drm_display_info *display = &vc4_hdmi->connector.display_info;
1975 lockdep_assert_held(&vc4_hdmi->mutex);
1978 * If the encoder is currently in DVI mode, treat the codec DAI
1981 if (!display->is_hdmi)
1987 static int vc4_hdmi_audio_startup(struct device *dev, void *data)
1989 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
1990 struct drm_device *drm = vc4_hdmi->connector.dev;
1991 unsigned long flags;
1995 mutex_lock(&vc4_hdmi->mutex);
1997 if (!drm_dev_enter(drm, &idx)) {
2002 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2007 vc4_hdmi->audio.streaming = true;
2009 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2010 HDMI_WRITE(HDMI_MAI_CTL,
2011 VC4_HD_MAI_CTL_RESET |
2012 VC4_HD_MAI_CTL_FLUSH |
2013 VC4_HD_MAI_CTL_DLATE |
2014 VC4_HD_MAI_CTL_ERRORE |
2015 VC4_HD_MAI_CTL_ERRORF);
2016 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2018 if (vc4_hdmi->variant->phy_rng_enable)
2019 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi);
2024 mutex_unlock(&vc4_hdmi->mutex);
2029 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi)
2031 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2032 struct device *dev = &vc4_hdmi->pdev->dev;
2033 unsigned long flags;
2036 lockdep_assert_held(&vc4_hdmi->mutex);
2038 vc4_hdmi->audio.streaming = false;
2039 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false);
2041 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret);
2043 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2045 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET);
2046 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF);
2047 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH);
2049 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2052 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data)
2054 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2055 struct drm_device *drm = vc4_hdmi->connector.dev;
2056 unsigned long flags;
2059 mutex_lock(&vc4_hdmi->mutex);
2061 if (!drm_dev_enter(drm, &idx))
2064 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2066 HDMI_WRITE(HDMI_MAI_CTL,
2067 VC4_HD_MAI_CTL_DLATE |
2068 VC4_HD_MAI_CTL_ERRORE |
2069 VC4_HD_MAI_CTL_ERRORF);
2071 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2073 if (vc4_hdmi->variant->phy_rng_disable)
2074 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi);
2076 vc4_hdmi->audio.streaming = false;
2077 vc4_hdmi_audio_reset(vc4_hdmi);
2082 mutex_unlock(&vc4_hdmi->mutex);
2085 static int sample_rate_to_mai_fmt(int samplerate)
2087 switch (samplerate) {
2089 return VC4_HDMI_MAI_SAMPLE_RATE_8000;
2091 return VC4_HDMI_MAI_SAMPLE_RATE_11025;
2093 return VC4_HDMI_MAI_SAMPLE_RATE_12000;
2095 return VC4_HDMI_MAI_SAMPLE_RATE_16000;
2097 return VC4_HDMI_MAI_SAMPLE_RATE_22050;
2099 return VC4_HDMI_MAI_SAMPLE_RATE_24000;
2101 return VC4_HDMI_MAI_SAMPLE_RATE_32000;
2103 return VC4_HDMI_MAI_SAMPLE_RATE_44100;
2105 return VC4_HDMI_MAI_SAMPLE_RATE_48000;
2107 return VC4_HDMI_MAI_SAMPLE_RATE_64000;
2109 return VC4_HDMI_MAI_SAMPLE_RATE_88200;
2111 return VC4_HDMI_MAI_SAMPLE_RATE_96000;
2113 return VC4_HDMI_MAI_SAMPLE_RATE_128000;
2115 return VC4_HDMI_MAI_SAMPLE_RATE_176400;
2117 return VC4_HDMI_MAI_SAMPLE_RATE_192000;
2119 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED;
2123 /* HDMI audio codec callbacks */
2124 static int vc4_hdmi_audio_prepare(struct device *dev, void *data,
2125 struct hdmi_codec_daifmt *daifmt,
2126 struct hdmi_codec_params *params)
2128 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2129 struct drm_device *drm = vc4_hdmi->connector.dev;
2130 struct drm_encoder *encoder = &vc4_hdmi->encoder.base;
2131 unsigned int sample_rate = params->sample_rate;
2132 unsigned int channels = params->channels;
2133 unsigned long flags;
2134 u32 audio_packet_config, channel_mask;
2136 u32 mai_audio_format;
2137 u32 mai_sample_rate;
2141 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__,
2142 sample_rate, params->sample_width, channels);
2144 mutex_lock(&vc4_hdmi->mutex);
2146 if (!drm_dev_enter(drm, &idx)) {
2151 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) {
2156 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate);
2158 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2159 HDMI_WRITE(HDMI_MAI_CTL,
2160 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) |
2161 VC4_HD_MAI_CTL_WHOLSMP |
2162 VC4_HD_MAI_CTL_CHALIGN |
2163 VC4_HD_MAI_CTL_ENABLE);
2165 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate);
2166 if (params->iec.status[0] & IEC958_AES0_NONAUDIO &&
2167 params->channels == 8)
2168 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR;
2170 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM;
2171 HDMI_WRITE(HDMI_MAI_FMT,
2172 VC4_SET_FIELD(mai_sample_rate,
2173 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) |
2174 VC4_SET_FIELD(mai_audio_format,
2175 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT));
2177 /* The B frame identifier should match the value used by alsa-lib (8) */
2178 audio_packet_config =
2179 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT |
2180 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS |
2181 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER);
2183 channel_mask = GENMASK(channels - 1, 0);
2184 audio_packet_config |= VC4_SET_FIELD(channel_mask,
2185 VC4_HDMI_AUDIO_PACKET_CEA_MASK);
2187 /* Set the MAI threshold */
2188 HDMI_WRITE(HDMI_MAI_THR,
2189 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) |
2190 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) |
2191 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) |
2192 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW));
2194 HDMI_WRITE(HDMI_MAI_CONFIG,
2195 VC4_HDMI_MAI_CONFIG_BIT_REVERSE |
2196 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE |
2197 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK));
2199 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask);
2200 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map);
2201 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config);
2203 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate);
2205 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2207 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea));
2208 vc4_hdmi_set_audio_infoframe(encoder);
2213 mutex_unlock(&vc4_hdmi->mutex);
2218 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = {
2219 .name = "vc4-hdmi-cpu-dai-component",
2220 .legacy_dai_naming = 1,
2223 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai)
2225 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai);
2227 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL);
2232 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = {
2233 .name = "vc4-hdmi-cpu-dai",
2234 .probe = vc4_hdmi_audio_cpu_dai_probe,
2236 .stream_name = "Playback",
2239 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 |
2240 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 |
2241 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 |
2242 SNDRV_PCM_RATE_192000,
2243 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE,
2247 static const struct snd_dmaengine_pcm_config pcm_conf = {
2248 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx",
2249 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
2252 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data,
2253 uint8_t *buf, size_t len)
2255 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
2256 struct drm_connector *connector = &vc4_hdmi->connector;
2258 mutex_lock(&vc4_hdmi->mutex);
2259 memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
2260 mutex_unlock(&vc4_hdmi->mutex);
2265 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = {
2266 .get_eld = vc4_hdmi_audio_get_eld,
2267 .prepare = vc4_hdmi_audio_prepare,
2268 .audio_shutdown = vc4_hdmi_audio_shutdown,
2269 .audio_startup = vc4_hdmi_audio_startup,
2272 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = {
2273 .ops = &vc4_hdmi_codec_ops,
2274 .max_i2s_channels = 8,
2278 static void vc4_hdmi_audio_codec_release(void *ptr)
2280 struct vc4_hdmi *vc4_hdmi = ptr;
2282 platform_device_unregister(vc4_hdmi->audio.codec_pdev);
2283 vc4_hdmi->audio.codec_pdev = NULL;
2286 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi)
2288 const struct vc4_hdmi_register *mai_data =
2289 &vc4_hdmi->variant->registers[HDMI_MAI_DATA];
2290 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link;
2291 struct snd_soc_card *card = &vc4_hdmi->audio.card;
2292 struct device *dev = &vc4_hdmi->pdev->dev;
2293 struct platform_device *codec_pdev;
2299 * ASoC makes it a bit hard to retrieve a pointer to the
2300 * vc4_hdmi structure. Registering the card will overwrite our
2301 * device drvdata with a pointer to the snd_soc_card structure,
2302 * which can then be used to retrieve whatever drvdata we want
2305 * However, that doesn't fly in the case where we wouldn't
2306 * register an ASoC card (because of an old DT that is missing
2307 * the dmas properties for example), then the card isn't
2308 * registered and the device drvdata wouldn't be set.
2310 * We can deal with both cases by making sure a snd_soc_card
2311 * pointer and a vc4_hdmi structure are pointing to the same
2312 * memory address, so we can treat them indistinctly without any
2315 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0);
2316 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0);
2318 if (!of_find_property(dev->of_node, "dmas", &len) || !len) {
2320 "'dmas' DT property is missing or empty, no HDMI audio\n");
2324 if (mai_data->reg != VC4_HD) {
2325 WARN_ONCE(true, "MAI isn't in the HD block\n");
2330 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve
2331 * the bus address specified in the DT, because the physical address
2332 * (the one returned by platform_get_resource()) is not appropriate
2333 * for DMA transfers.
2334 * This VC/MMU should probably be exposed to avoid this kind of hacks.
2336 index = of_property_match_string(dev->of_node, "reg-names", "hd");
2337 /* Before BCM2711, we don't have a named register range */
2341 addr = of_get_address(dev->of_node, index, NULL, NULL);
2343 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset;
2344 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
2345 vc4_hdmi->audio.dma_data.maxburst = 2;
2348 * NOTE: Strictly speaking, we should probably use a DRM-managed
2349 * registration there to avoid removing all the audio components
2350 * by the time the driver doesn't have any user anymore.
2352 * However, the ASoC core uses a number of devm_kzalloc calls
2353 * when registering, even when using non-device-managed
2354 * functions (such as in snd_soc_register_component()).
2356 * If we call snd_soc_unregister_component() in a DRM-managed
2357 * action, the device-managed actions have already been executed
2358 * and thus we would access memory that has been freed.
2360 * Using device-managed hooks here probably leaves us open to a
2361 * bunch of issues if userspace still has a handle on the ALSA
2362 * device when the device is removed. However, this is mitigated
2363 * by the use of drm_dev_enter()/drm_dev_exit() in the audio
2364 * path to prevent the access to the device resources if it
2365 * isn't there anymore.
2367 * Then, the vc4_hdmi structure is DRM-managed and thus only
2368 * freed whenever the last user has closed the DRM device file.
2369 * It should thus outlive ALSA in most situations.
2371 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0);
2373 dev_err(dev, "Could not register PCM component: %d\n", ret);
2377 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp,
2378 &vc4_hdmi_audio_cpu_dai_drv, 1);
2380 dev_err(dev, "Could not register CPU DAI: %d\n", ret);
2384 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME,
2385 PLATFORM_DEVID_AUTO,
2386 &vc4_hdmi_codec_pdata,
2387 sizeof(vc4_hdmi_codec_pdata));
2388 if (IS_ERR(codec_pdev)) {
2389 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev));
2390 return PTR_ERR(codec_pdev);
2392 vc4_hdmi->audio.codec_pdev = codec_pdev;
2394 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi);
2398 dai_link->cpus = &vc4_hdmi->audio.cpu;
2399 dai_link->codecs = &vc4_hdmi->audio.codec;
2400 dai_link->platforms = &vc4_hdmi->audio.platform;
2402 dai_link->num_cpus = 1;
2403 dai_link->num_codecs = 1;
2404 dai_link->num_platforms = 1;
2406 dai_link->name = "MAI";
2407 dai_link->stream_name = "MAI PCM";
2408 dai_link->codecs->dai_name = "i2s-hifi";
2409 dai_link->cpus->dai_name = dev_name(dev);
2410 dai_link->codecs->name = dev_name(&codec_pdev->dev);
2411 dai_link->platforms->name = dev_name(dev);
2413 card->dai_link = dai_link;
2414 card->num_links = 1;
2415 card->name = vc4_hdmi->variant->card_name;
2416 card->driver_name = "vc4-hdmi";
2418 card->owner = THIS_MODULE;
2421 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and
2422 * stores a pointer to the snd card object in dev->driver_data. This
2423 * means we cannot use it for something else. The hdmi back-pointer is
2424 * now stored in card->drvdata and should be retrieved with
2425 * snd_soc_card_get_drvdata() if needed.
2427 snd_soc_card_set_drvdata(card, vc4_hdmi);
2428 ret = devm_snd_soc_register_card(dev, card);
2430 dev_err_probe(dev, ret, "Could not register sound card\n");
2436 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv)
2438 struct vc4_hdmi *vc4_hdmi = priv;
2439 struct drm_connector *connector = &vc4_hdmi->connector;
2440 struct drm_device *dev = connector->dev;
2442 if (dev && dev->registered)
2443 drm_connector_helper_hpd_irq_event(connector);
2448 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi)
2450 struct drm_connector *connector = &vc4_hdmi->connector;
2451 struct platform_device *pdev = vc4_hdmi->pdev;
2454 if (vc4_hdmi->variant->external_irq_controller) {
2455 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected");
2456 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed");
2458 ret = devm_request_threaded_irq(&pdev->dev, hpd_con,
2460 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2461 "vc4 hdmi hpd connected", vc4_hdmi);
2465 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm,
2467 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT,
2468 "vc4 hdmi hpd disconnected", vc4_hdmi);
2472 connector->polled = DRM_CONNECTOR_POLL_HPD;
2478 #ifdef CONFIG_DRM_VC4_HDMI_CEC
2479 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv)
2481 struct vc4_hdmi *vc4_hdmi = priv;
2483 if (vc4_hdmi->cec_rx_msg.len)
2484 cec_received_msg(vc4_hdmi->cec_adap,
2485 &vc4_hdmi->cec_rx_msg);
2490 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv)
2492 struct vc4_hdmi *vc4_hdmi = priv;
2494 if (vc4_hdmi->cec_tx_ok) {
2495 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK,
2499 * This CEC implementation makes 1 retry, so if we
2500 * get a NACK, then that means it made 2 attempts.
2502 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK,
2508 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv)
2510 struct vc4_hdmi *vc4_hdmi = priv;
2513 if (vc4_hdmi->cec_irq_was_rx)
2514 ret = vc4_cec_irq_handler_rx_thread(irq, priv);
2516 ret = vc4_cec_irq_handler_tx_thread(irq, priv);
2521 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1)
2523 struct drm_device *dev = vc4_hdmi->connector.dev;
2524 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg;
2527 lockdep_assert_held(&vc4_hdmi->hw_lock);
2529 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >>
2530 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT);
2532 if (msg->len > 16) {
2533 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len);
2537 for (i = 0; i < msg->len; i += 4) {
2538 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2));
2540 msg->msg[i] = val & 0xff;
2541 msg->msg[i + 1] = (val >> 8) & 0xff;
2542 msg->msg[i + 2] = (val >> 16) & 0xff;
2543 msg->msg[i + 3] = (val >> 24) & 0xff;
2547 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2552 * We don't need to protect the register access using
2553 * drm_dev_enter() there because the interrupt handler lifetime
2554 * is tied to the device itself, and not to the DRM device.
2556 * So when the device will be gone, one of the first thing we
2557 * will be doing will be to unregister the interrupt handler,
2558 * and then unregister the DRM device. drm_dev_enter() would
2559 * thus always succeed if we are here.
2562 lockdep_assert_held(&vc4_hdmi->hw_lock);
2564 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2565 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD;
2566 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2567 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2569 return IRQ_WAKE_THREAD;
2572 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv)
2574 struct vc4_hdmi *vc4_hdmi = priv;
2577 spin_lock(&vc4_hdmi->hw_lock);
2578 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2579 spin_unlock(&vc4_hdmi->hw_lock);
2584 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi)
2588 lockdep_assert_held(&vc4_hdmi->hw_lock);
2591 * We don't need to protect the register access using
2592 * drm_dev_enter() there because the interrupt handler lifetime
2593 * is tied to the device itself, and not to the DRM device.
2595 * So when the device will be gone, one of the first thing we
2596 * will be doing will be to unregister the interrupt handler,
2597 * and then unregister the DRM device. drm_dev_enter() would
2598 * thus always succeed if we are here.
2601 vc4_hdmi->cec_rx_msg.len = 0;
2602 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1);
2603 vc4_cec_read_msg(vc4_hdmi, cntrl1);
2604 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2605 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2606 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF;
2608 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1);
2610 return IRQ_WAKE_THREAD;
2613 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv)
2615 struct vc4_hdmi *vc4_hdmi = priv;
2618 spin_lock(&vc4_hdmi->hw_lock);
2619 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2620 spin_unlock(&vc4_hdmi->hw_lock);
2625 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv)
2627 struct vc4_hdmi *vc4_hdmi = priv;
2628 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS);
2633 * We don't need to protect the register access using
2634 * drm_dev_enter() there because the interrupt handler lifetime
2635 * is tied to the device itself, and not to the DRM device.
2637 * So when the device will be gone, one of the first thing we
2638 * will be doing will be to unregister the interrupt handler,
2639 * and then unregister the DRM device. drm_dev_enter() would
2640 * thus always succeed if we are here.
2643 if (!(stat & VC4_HDMI_CPU_CEC))
2646 spin_lock(&vc4_hdmi->hw_lock);
2647 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5);
2648 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT;
2649 if (vc4_hdmi->cec_irq_was_rx)
2650 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi);
2652 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi);
2654 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC);
2655 spin_unlock(&vc4_hdmi->hw_lock);
2660 static int vc4_hdmi_cec_enable(struct cec_adapter *adap)
2662 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2663 struct drm_device *drm = vc4_hdmi->connector.dev;
2664 /* clock period in microseconds */
2665 const u32 usecs = 1000000 / CEC_CLOCK_FREQ;
2666 unsigned long flags;
2672 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2673 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2674 * .detect or .get_modes might call .adap_enable, which leads to this
2675 * function being called with that mutex held.
2677 * Concurrency is not an issue for the moment since we don't share any
2678 * state with KMS, so we can ignore the lock for now, but we need to
2679 * keep it in mind if we were to change that assumption.
2682 if (!drm_dev_enter(drm, &idx))
2684 * We can't return an error code, because the CEC
2685 * framework will emit WARN_ON messages at unbind
2690 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev);
2696 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2698 val = HDMI_READ(HDMI_CEC_CNTRL_5);
2699 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET |
2700 VC4_HDMI_CEC_CNT_TO_4700_US_MASK |
2701 VC4_HDMI_CEC_CNT_TO_4500_US_MASK);
2702 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) |
2703 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT);
2705 HDMI_WRITE(HDMI_CEC_CNTRL_5, val |
2706 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2707 HDMI_WRITE(HDMI_CEC_CNTRL_5, val);
2708 HDMI_WRITE(HDMI_CEC_CNTRL_2,
2709 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) |
2710 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) |
2711 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) |
2712 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) |
2713 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT));
2714 HDMI_WRITE(HDMI_CEC_CNTRL_3,
2715 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) |
2716 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) |
2717 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) |
2718 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT));
2719 HDMI_WRITE(HDMI_CEC_CNTRL_4,
2720 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) |
2721 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) |
2722 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) |
2723 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT));
2725 if (!vc4_hdmi->variant->external_irq_controller)
2726 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC);
2728 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2735 static int vc4_hdmi_cec_disable(struct cec_adapter *adap)
2737 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2738 struct drm_device *drm = vc4_hdmi->connector.dev;
2739 unsigned long flags;
2742 if (!drm_dev_enter(drm, &idx))
2744 * We can't return an error code, because the CEC
2745 * framework will emit WARN_ON messages at unbind
2751 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2752 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2753 * .detect or .get_modes might call .adap_enable, which leads to this
2754 * function being called with that mutex held.
2756 * Concurrency is not an issue for the moment since we don't share any
2757 * state with KMS, so we can ignore the lock for now, but we need to
2758 * keep it in mind if we were to change that assumption.
2761 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2763 if (!vc4_hdmi->variant->external_irq_controller)
2764 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC);
2766 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) |
2767 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET);
2769 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2771 pm_runtime_put(&vc4_hdmi->pdev->dev);
2778 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable)
2781 return vc4_hdmi_cec_enable(adap);
2783 return vc4_hdmi_cec_disable(adap);
2786 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
2788 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2789 struct drm_device *drm = vc4_hdmi->connector.dev;
2790 unsigned long flags;
2794 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2795 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2796 * .detect or .get_modes might call .adap_enable, which leads to this
2797 * function being called with that mutex held.
2799 * Concurrency is not an issue for the moment since we don't share any
2800 * state with KMS, so we can ignore the lock for now, but we need to
2801 * keep it in mind if we were to change that assumption.
2804 if (!drm_dev_enter(drm, &idx))
2806 * We can't return an error code, because the CEC
2807 * framework will emit WARN_ON messages at unbind
2812 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2813 HDMI_WRITE(HDMI_CEC_CNTRL_1,
2814 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) |
2815 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT);
2816 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2823 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
2824 u32 signal_free_time, struct cec_msg *msg)
2826 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap);
2827 struct drm_device *dev = vc4_hdmi->connector.dev;
2828 unsigned long flags;
2834 * NOTE: This function should really take vc4_hdmi->mutex, but doing so
2835 * results in a reentrancy since cec_s_phys_addr_from_edid() called in
2836 * .detect or .get_modes might call .adap_enable, which leads to this
2837 * function being called with that mutex held.
2839 * Concurrency is not an issue for the moment since we don't share any
2840 * state with KMS, so we can ignore the lock for now, but we need to
2841 * keep it in mind if we were to change that assumption.
2844 if (!drm_dev_enter(dev, &idx))
2847 if (msg->len > 16) {
2848 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len);
2853 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
2855 for (i = 0; i < msg->len; i += 4)
2856 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2),
2858 (msg->msg[i + 1] << 8) |
2859 (msg->msg[i + 2] << 16) |
2860 (msg->msg[i + 3] << 24));
2862 val = HDMI_READ(HDMI_CEC_CNTRL_1);
2863 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN;
2864 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2865 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK;
2866 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT;
2867 val |= VC4_HDMI_CEC_START_XMIT_BEGIN;
2869 HDMI_WRITE(HDMI_CEC_CNTRL_1, val);
2871 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
2878 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = {
2879 .adap_enable = vc4_hdmi_cec_adap_enable,
2880 .adap_log_addr = vc4_hdmi_cec_adap_log_addr,
2881 .adap_transmit = vc4_hdmi_cec_adap_transmit,
2884 static void vc4_hdmi_cec_release(void *ptr)
2886 struct vc4_hdmi *vc4_hdmi = ptr;
2888 cec_unregister_adapter(vc4_hdmi->cec_adap);
2889 vc4_hdmi->cec_adap = NULL;
2892 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2894 struct cec_connector_info conn_info;
2895 struct platform_device *pdev = vc4_hdmi->pdev;
2896 struct device *dev = &pdev->dev;
2899 if (!of_find_property(dev->of_node, "interrupts", NULL)) {
2900 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n");
2904 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops,
2907 CEC_CAP_CONNECTOR_INFO, 1);
2908 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap);
2912 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector);
2913 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info);
2915 if (vc4_hdmi->variant->external_irq_controller) {
2916 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"),
2917 vc4_cec_irq_handler_rx_bare,
2918 vc4_cec_irq_handler_rx_thread, 0,
2919 "vc4 hdmi cec rx", vc4_hdmi);
2921 goto err_delete_cec_adap;
2923 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"),
2924 vc4_cec_irq_handler_tx_bare,
2925 vc4_cec_irq_handler_tx_thread, 0,
2926 "vc4 hdmi cec tx", vc4_hdmi);
2928 goto err_delete_cec_adap;
2930 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0),
2931 vc4_cec_irq_handler,
2932 vc4_cec_irq_handler_thread, 0,
2933 "vc4 hdmi cec", vc4_hdmi);
2935 goto err_delete_cec_adap;
2938 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev);
2940 goto err_delete_cec_adap;
2943 * NOTE: Strictly speaking, we should probably use a DRM-managed
2944 * registration there to avoid removing the CEC adapter by the
2945 * time the DRM driver doesn't have any user anymore.
2947 * However, the CEC framework already cleans up the CEC adapter
2948 * only when the last user has closed its file descriptor, so we
2949 * don't need to handle it in DRM.
2951 * By the time the device-managed hook is executed, we will give
2952 * up our reference to the CEC adapter and therefore don't
2953 * really care when it's actually freed.
2955 * There's still a problematic sequence: if we unregister our
2956 * CEC adapter, but the userspace keeps a handle on the CEC
2957 * adapter but not the DRM device for some reason. In such a
2958 * case, our vc4_hdmi structure will be freed, but the
2959 * cec_adapter structure will have a dangling pointer to what
2960 * used to be our HDMI controller. If we get a CEC call at that
2961 * moment, we could end up with a use-after-free. Fortunately,
2962 * the CEC framework already handles this too, by calling
2963 * cec_is_registered() in cec_ioctl() and cec_poll().
2965 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi);
2971 err_delete_cec_adap:
2972 cec_delete_adapter(vc4_hdmi->cec_adap);
2977 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi)
2983 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr)
2985 struct debugfs_reg32 *regs = ptr;
2990 static int vc4_hdmi_build_regset(struct drm_device *drm,
2991 struct vc4_hdmi *vc4_hdmi,
2992 struct debugfs_regset32 *regset,
2993 enum vc4_hdmi_regs reg)
2995 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
2996 struct debugfs_reg32 *regs, *new_regs;
2997 unsigned int count = 0;
3001 regs = kcalloc(variant->num_registers, sizeof(*regs),
3006 for (i = 0; i < variant->num_registers; i++) {
3007 const struct vc4_hdmi_register *field = &variant->registers[i];
3009 if (field->reg != reg)
3012 regs[count].name = field->name;
3013 regs[count].offset = field->offset;
3017 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL);
3021 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg);
3022 regset->regs = new_regs;
3023 regset->nregs = count;
3025 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs);
3032 static int vc4_hdmi_init_resources(struct drm_device *drm,
3033 struct vc4_hdmi *vc4_hdmi)
3035 struct platform_device *pdev = vc4_hdmi->pdev;
3036 struct device *dev = &pdev->dev;
3039 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
3040 if (IS_ERR(vc4_hdmi->hdmicore_regs))
3041 return PTR_ERR(vc4_hdmi->hdmicore_regs);
3043 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
3044 if (IS_ERR(vc4_hdmi->hd_regs))
3045 return PTR_ERR(vc4_hdmi->hd_regs);
3047 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3051 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3055 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel");
3056 if (IS_ERR(vc4_hdmi->pixel_clock)) {
3057 ret = PTR_ERR(vc4_hdmi->pixel_clock);
3058 if (ret != -EPROBE_DEFER)
3059 DRM_ERROR("Failed to get pixel clock\n");
3063 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3064 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3065 DRM_ERROR("Failed to get HDMI state machine clock\n");
3066 return PTR_ERR(vc4_hdmi->hsm_clock);
3068 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock;
3069 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock;
3074 static int vc5_hdmi_init_resources(struct drm_device *drm,
3075 struct vc4_hdmi *vc4_hdmi)
3077 struct platform_device *pdev = vc4_hdmi->pdev;
3078 struct device *dev = &pdev->dev;
3079 struct resource *res;
3082 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi");
3086 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start,
3087 resource_size(res));
3088 if (!vc4_hdmi->hdmicore_regs)
3091 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd");
3095 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res));
3096 if (!vc4_hdmi->hd_regs)
3099 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec");
3103 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res));
3104 if (!vc4_hdmi->cec_regs)
3107 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc");
3111 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res));
3112 if (!vc4_hdmi->csc_regs)
3115 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp");
3119 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res));
3120 if (!vc4_hdmi->dvp_regs)
3123 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
3127 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res));
3128 if (!vc4_hdmi->phy_regs)
3131 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet");
3135 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res));
3136 if (!vc4_hdmi->ram_regs)
3139 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm");
3143 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res));
3144 if (!vc4_hdmi->rm_regs)
3147 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
3148 if (IS_ERR(vc4_hdmi->hsm_clock)) {
3149 DRM_ERROR("Failed to get HDMI state machine clock\n");
3150 return PTR_ERR(vc4_hdmi->hsm_clock);
3153 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb");
3154 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) {
3155 DRM_ERROR("Failed to get pixel bvb clock\n");
3156 return PTR_ERR(vc4_hdmi->pixel_bvb_clock);
3159 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio");
3160 if (IS_ERR(vc4_hdmi->audio_clock)) {
3161 DRM_ERROR("Failed to get audio clock\n");
3162 return PTR_ERR(vc4_hdmi->audio_clock);
3165 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec");
3166 if (IS_ERR(vc4_hdmi->cec_clock)) {
3167 DRM_ERROR("Failed to get CEC clock\n");
3168 return PTR_ERR(vc4_hdmi->cec_clock);
3171 vc4_hdmi->reset = devm_reset_control_get(dev, NULL);
3172 if (IS_ERR(vc4_hdmi->reset)) {
3173 DRM_ERROR("Failed to get HDMI reset line\n");
3174 return PTR_ERR(vc4_hdmi->reset);
3177 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI);
3181 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD);
3185 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC);
3189 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC);
3193 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP);
3197 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY);
3201 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM);
3205 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM);
3212 static int vc4_hdmi_runtime_suspend(struct device *dev)
3214 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3216 clk_disable_unprepare(vc4_hdmi->hsm_clock);
3221 static int vc4_hdmi_runtime_resume(struct device *dev)
3223 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev);
3224 unsigned long __maybe_unused flags;
3225 u32 __maybe_unused value;
3228 ret = clk_prepare_enable(vc4_hdmi->hsm_clock);
3232 if (vc4_hdmi->variant->reset)
3233 vc4_hdmi->variant->reset(vc4_hdmi);
3235 #ifdef CONFIG_DRM_VC4_HDMI_CEC
3236 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3237 value = HDMI_READ(HDMI_CEC_CNTRL_1);
3238 /* Set the logical address to Unregistered */
3239 value |= VC4_HDMI_CEC_ADDR_MASK;
3240 HDMI_WRITE(HDMI_CEC_CNTRL_1, value);
3241 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3243 vc4_hdmi_cec_update_clk_div(vc4_hdmi);
3245 if (!vc4_hdmi->variant->external_irq_controller) {
3246 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags);
3247 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff);
3248 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags);
3255 static void vc4_hdmi_put_ddc_device(void *ptr)
3257 struct vc4_hdmi *vc4_hdmi = ptr;
3259 put_device(&vc4_hdmi->ddc->dev);
3262 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
3264 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev);
3265 struct platform_device *pdev = to_platform_device(dev);
3266 struct drm_device *drm = dev_get_drvdata(master);
3267 struct vc4_hdmi *vc4_hdmi;
3268 struct drm_encoder *encoder;
3269 struct device_node *ddc_node;
3272 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL);
3276 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex);
3280 spin_lock_init(&vc4_hdmi->hw_lock);
3281 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq);
3283 dev_set_drvdata(dev, vc4_hdmi);
3284 encoder = &vc4_hdmi->encoder.base;
3285 vc4_hdmi->encoder.type = variant->encoder_type;
3286 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure;
3287 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable;
3288 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable;
3289 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable;
3290 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown;
3291 vc4_hdmi->pdev = pdev;
3292 vc4_hdmi->variant = variant;
3295 * Since we don't know the state of the controller and its
3296 * display (if any), let's assume it's always enabled.
3297 * vc4_hdmi_disable_scrambling() will thus run at boot, make
3298 * sure it's disabled, and avoid any inconsistency.
3300 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK)
3301 vc4_hdmi->scdc_enabled = true;
3303 ret = variant->init_resources(drm, vc4_hdmi);
3307 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
3309 DRM_ERROR("Failed to find ddc node in device tree\n");
3313 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
3314 of_node_put(ddc_node);
3315 if (!vc4_hdmi->ddc) {
3316 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
3317 return -EPROBE_DEFER;
3320 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi);
3324 /* Only use the GPIO HPD pin if present in the DT, otherwise
3325 * we'll use the HDMI core's register.
3327 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN);
3328 if (IS_ERR(vc4_hdmi->hpd_gpio)) {
3329 return PTR_ERR(vc4_hdmi->hpd_gpio);
3332 vc4_hdmi->disable_wifi_frequencies =
3333 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence");
3335 if (variant->max_pixel_clock == 600000000) {
3336 struct vc4_dev *vc4 = to_vc4_dev(drm);
3337 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000);
3339 if (max_rate < 550000000)
3340 vc4_hdmi->disable_4kp60 = true;
3343 ret = devm_pm_runtime_enable(dev);
3348 * We need to have the device powered up at this point to call
3349 * our reset hook and for the CEC init.
3351 ret = pm_runtime_resume_and_get(dev);
3355 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") ||
3356 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) &&
3357 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) {
3358 clk_prepare_enable(vc4_hdmi->pixel_clock);
3359 clk_prepare_enable(vc4_hdmi->hsm_clock);
3360 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock);
3363 ret = drmm_encoder_init(drm, encoder,
3364 &vc4_hdmi_encoder_funcs,
3365 DRM_MODE_ENCODER_TMDS,
3368 goto err_put_runtime_pm;
3370 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs);
3372 ret = vc4_hdmi_connector_init(drm, vc4_hdmi);
3374 goto err_put_runtime_pm;
3376 ret = vc4_hdmi_hotplug_init(vc4_hdmi);
3378 goto err_put_runtime_pm;
3380 ret = vc4_hdmi_cec_init(vc4_hdmi);
3382 goto err_put_runtime_pm;
3384 ret = vc4_hdmi_audio_init(vc4_hdmi);
3386 goto err_put_runtime_pm;
3388 pm_runtime_put_sync(dev);
3393 pm_runtime_put_sync(dev);
3398 static const struct component_ops vc4_hdmi_ops = {
3399 .bind = vc4_hdmi_bind,
3402 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
3404 return component_add(&pdev->dev, &vc4_hdmi_ops);
3407 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
3409 component_del(&pdev->dev, &vc4_hdmi_ops);
3413 static const struct vc4_hdmi_variant bcm2835_variant = {
3414 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3415 .debugfs_name = "hdmi_regs",
3416 .card_name = "vc4-hdmi",
3417 .max_pixel_clock = 162000000,
3418 .registers = vc4_hdmi_fields,
3419 .num_registers = ARRAY_SIZE(vc4_hdmi_fields),
3421 .init_resources = vc4_hdmi_init_resources,
3422 .csc_setup = vc4_hdmi_csc_setup,
3423 .reset = vc4_hdmi_reset,
3424 .set_timings = vc4_hdmi_set_timings,
3425 .phy_init = vc4_hdmi_phy_init,
3426 .phy_disable = vc4_hdmi_phy_disable,
3427 .phy_rng_enable = vc4_hdmi_phy_rng_enable,
3428 .phy_rng_disable = vc4_hdmi_phy_rng_disable,
3429 .channel_map = vc4_hdmi_channel_map,
3430 .supports_hdr = false,
3433 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = {
3434 .encoder_type = VC4_ENCODER_TYPE_HDMI0,
3435 .debugfs_name = "hdmi0_regs",
3436 .card_name = "vc4-hdmi-0",
3437 .max_pixel_clock = 600000000,
3438 .registers = vc5_hdmi_hdmi0_fields,
3439 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields),
3440 .phy_lane_mapping = {
3446 .unsupported_odd_h_timings = true,
3447 .external_irq_controller = true,
3449 .init_resources = vc5_hdmi_init_resources,
3450 .csc_setup = vc5_hdmi_csc_setup,
3451 .reset = vc5_hdmi_reset,
3452 .set_timings = vc5_hdmi_set_timings,
3453 .phy_init = vc5_hdmi_phy_init,
3454 .phy_disable = vc5_hdmi_phy_disable,
3455 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3456 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3457 .channel_map = vc5_hdmi_channel_map,
3458 .supports_hdr = true,
3459 .hp_detect = vc5_hdmi_hp_detect,
3462 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = {
3463 .encoder_type = VC4_ENCODER_TYPE_HDMI1,
3464 .debugfs_name = "hdmi1_regs",
3465 .card_name = "vc4-hdmi-1",
3466 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK,
3467 .registers = vc5_hdmi_hdmi1_fields,
3468 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields),
3469 .phy_lane_mapping = {
3475 .unsupported_odd_h_timings = true,
3476 .external_irq_controller = true,
3478 .init_resources = vc5_hdmi_init_resources,
3479 .csc_setup = vc5_hdmi_csc_setup,
3480 .reset = vc5_hdmi_reset,
3481 .set_timings = vc5_hdmi_set_timings,
3482 .phy_init = vc5_hdmi_phy_init,
3483 .phy_disable = vc5_hdmi_phy_disable,
3484 .phy_rng_enable = vc5_hdmi_phy_rng_enable,
3485 .phy_rng_disable = vc5_hdmi_phy_rng_disable,
3486 .channel_map = vc5_hdmi_channel_map,
3487 .supports_hdr = true,
3488 .hp_detect = vc5_hdmi_hp_detect,
3491 static const struct of_device_id vc4_hdmi_dt_match[] = {
3492 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant },
3493 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant },
3494 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant },
3498 static const struct dev_pm_ops vc4_hdmi_pm_ops = {
3499 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend,
3500 vc4_hdmi_runtime_resume,
3504 struct platform_driver vc4_hdmi_driver = {
3505 .probe = vc4_hdmi_dev_probe,
3506 .remove = vc4_hdmi_dev_remove,
3509 .of_match_table = vc4_hdmi_dt_match,
3510 .pm = &vc4_hdmi_pm_ops,