1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * MIPI Display Bus Interface (DBI) LCD controller support
5 * Copyright 2016 Noralf Trønnes
8 #include <linux/debugfs.h>
9 #include <linux/delay.h>
10 #include <linux/dma-buf.h>
11 #include <linux/gpio/consumer.h>
12 #include <linux/module.h>
13 #include <linux/regulator/consumer.h>
14 #include <linux/spi/spi.h>
16 #include <drm/drm_damage_helper.h>
17 #include <drm/drm_drv.h>
18 #include <drm/drm_fb_cma_helper.h>
19 #include <drm/drm_gem_cma_helper.h>
20 #include <drm/drm_format_helper.h>
21 #include <drm/drm_fourcc.h>
22 #include <drm/drm_gem_framebuffer_helper.h>
23 #include <drm/drm_vblank.h>
24 #include <drm/drm_rect.h>
25 #include <drm/tinydrm/mipi-dbi.h>
26 #include <drm/tinydrm/tinydrm-helpers.h>
27 #include <video/mipi_display.h>
29 #define MIPI_DBI_MAX_SPI_READ_SPEED 2000000 /* 2MHz */
31 #define DCS_POWER_MODE_DISPLAY BIT(2)
32 #define DCS_POWER_MODE_DISPLAY_NORMAL_MODE BIT(3)
33 #define DCS_POWER_MODE_SLEEP_MODE BIT(4)
34 #define DCS_POWER_MODE_PARTIAL_MODE BIT(5)
35 #define DCS_POWER_MODE_IDLE_MODE BIT(6)
36 #define DCS_POWER_MODE_RESERVED_MASK (BIT(0) | BIT(1) | BIT(7))
41 * This library provides helpers for MIPI Display Bus Interface (DBI)
42 * compatible display controllers.
44 * Many controllers for tiny lcd displays are MIPI compliant and can use this
45 * library. If a controller uses registers 0x2A and 0x2B to set the area to
46 * update and uses register 0x2C to write to frame memory, it is most likely
49 * Only MIPI Type 1 displays are supported since a full frame memory is needed.
51 * There are 3 MIPI DBI implementation types:
53 * A. Motorola 6800 type parallel bus
55 * B. Intel 8080 type parallel bus
57 * C. SPI type with 3 options:
59 * 1. 9-bit with the Data/Command signal as the ninth bit
60 * 2. Same as above except it's sent as 16 bits
61 * 3. 8-bit with the Data/Command signal as a separate D/CX pin
63 * Currently mipi_dbi only supports Type C options 1 and 3 with
64 * mipi_dbi_spi_init().
67 #define MIPI_DBI_DEBUG_COMMAND(cmd, data, len) \
70 DRM_DEBUG_DRIVER("cmd=%02x\n", cmd); \
72 DRM_DEBUG_DRIVER("cmd=%02x, par=%*ph\n", cmd, (int)len, data);\
74 DRM_DEBUG_DRIVER("cmd=%02x, len=%zu\n", cmd, len); \
77 static const u8 mipi_dbi_dcs_read_commands[] = {
78 MIPI_DCS_GET_DISPLAY_ID,
79 MIPI_DCS_GET_RED_CHANNEL,
80 MIPI_DCS_GET_GREEN_CHANNEL,
81 MIPI_DCS_GET_BLUE_CHANNEL,
82 MIPI_DCS_GET_DISPLAY_STATUS,
83 MIPI_DCS_GET_POWER_MODE,
84 MIPI_DCS_GET_ADDRESS_MODE,
85 MIPI_DCS_GET_PIXEL_FORMAT,
86 MIPI_DCS_GET_DISPLAY_MODE,
87 MIPI_DCS_GET_SIGNAL_MODE,
88 MIPI_DCS_GET_DIAGNOSTIC_RESULT,
89 MIPI_DCS_READ_MEMORY_START,
90 MIPI_DCS_READ_MEMORY_CONTINUE,
91 MIPI_DCS_GET_SCANLINE,
92 MIPI_DCS_GET_DISPLAY_BRIGHTNESS,
93 MIPI_DCS_GET_CONTROL_DISPLAY,
94 MIPI_DCS_GET_POWER_SAVE,
95 MIPI_DCS_GET_CABC_MIN_BRIGHTNESS,
96 MIPI_DCS_READ_DDB_START,
97 MIPI_DCS_READ_DDB_CONTINUE,
101 static bool mipi_dbi_command_is_read(struct mipi_dbi *mipi, u8 cmd)
105 if (!mipi->read_commands)
108 for (i = 0; i < 0xff; i++) {
109 if (!mipi->read_commands[i])
111 if (cmd == mipi->read_commands[i])
119 * mipi_dbi_command_read - MIPI DCS read command
120 * @mipi: MIPI structure
124 * Send MIPI DCS read command to the controller.
127 * Zero on success, negative error code on failure.
129 int mipi_dbi_command_read(struct mipi_dbi *mipi, u8 cmd, u8 *val)
131 if (!mipi->read_commands)
134 if (!mipi_dbi_command_is_read(mipi, cmd))
137 return mipi_dbi_command_buf(mipi, cmd, val, 1);
139 EXPORT_SYMBOL(mipi_dbi_command_read);
142 * mipi_dbi_command_buf - MIPI DCS command with parameter(s) in an array
143 * @mipi: MIPI structure
145 * @data: Parameter buffer
146 * @len: Buffer length
149 * Zero on success, negative error code on failure.
151 int mipi_dbi_command_buf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len)
156 /* SPI requires dma-safe buffers */
157 cmdbuf = kmemdup(&cmd, 1, GFP_KERNEL);
161 mutex_lock(&mipi->cmdlock);
162 ret = mipi->command(mipi, cmdbuf, data, len);
163 mutex_unlock(&mipi->cmdlock);
169 EXPORT_SYMBOL(mipi_dbi_command_buf);
171 /* This should only be used by mipi_dbi_command() */
172 int mipi_dbi_command_stackbuf(struct mipi_dbi *mipi, u8 cmd, u8 *data, size_t len)
177 buf = kmemdup(data, len, GFP_KERNEL);
181 ret = mipi_dbi_command_buf(mipi, cmd, buf, len);
187 EXPORT_SYMBOL(mipi_dbi_command_stackbuf);
190 * mipi_dbi_buf_copy - Copy a framebuffer, transforming it if necessary
191 * @dst: The destination buffer
192 * @fb: The source framebuffer
193 * @clip: Clipping rectangle of the area to be copied
194 * @swap: When true, swap MSB/LSB of 16-bit values
197 * Zero on success, negative error code on failure.
199 int mipi_dbi_buf_copy(void *dst, struct drm_framebuffer *fb,
200 struct drm_rect *clip, bool swap)
202 struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
203 struct dma_buf_attachment *import_attach = cma_obj->base.import_attach;
204 struct drm_format_name_buf format_name;
205 void *src = cma_obj->vaddr;
209 ret = dma_buf_begin_cpu_access(import_attach->dmabuf,
215 switch (fb->format->format) {
216 case DRM_FORMAT_RGB565:
218 drm_fb_swab16(dst, src, fb, clip);
220 drm_fb_memcpy(dst, src, fb, clip);
222 case DRM_FORMAT_XRGB8888:
223 drm_fb_xrgb8888_to_rgb565(dst, src, fb, clip, swap);
226 dev_err_once(fb->dev->dev, "Format is not supported: %s\n",
227 drm_get_format_name(fb->format->format,
233 ret = dma_buf_end_cpu_access(import_attach->dmabuf,
237 EXPORT_SYMBOL(mipi_dbi_buf_copy);
239 static void mipi_dbi_fb_dirty(struct drm_framebuffer *fb, struct drm_rect *rect)
241 struct drm_gem_cma_object *cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
242 struct mipi_dbi *mipi = drm_to_mipi_dbi(fb->dev);
243 unsigned int height = rect->y2 - rect->y1;
244 unsigned int width = rect->x2 - rect->x1;
245 bool swap = mipi->swap_bytes;
253 if (!drm_dev_enter(fb->dev, &idx))
256 full = width == fb->width && height == fb->height;
258 DRM_DEBUG_KMS("Flushing [FB:%d] " DRM_RECT_FMT "\n", fb->base.id, DRM_RECT_ARG(rect));
260 if (!mipi->dc || !full || swap ||
261 fb->format->format == DRM_FORMAT_XRGB8888) {
263 ret = mipi_dbi_buf_copy(mipi->tx_buf, fb, rect, swap);
270 mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS,
271 (rect->x1 >> 8) & 0xff, rect->x1 & 0xff,
272 ((rect->x2 - 1) >> 8) & 0xff, (rect->x2 - 1) & 0xff);
273 mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS,
274 (rect->y1 >> 8) & 0xff, rect->y1 & 0xff,
275 ((rect->y2 - 1) >> 8) & 0xff, (rect->y2 - 1) & 0xff);
277 ret = mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START, tr,
281 dev_err_once(fb->dev->dev, "Failed to update display %d\n", ret);
287 * mipi_dbi_pipe_update - Display pipe update helper
288 * @pipe: Simple display pipe
289 * @old_state: Old plane state
291 * This function handles framebuffer flushing and vblank events. Drivers can use
292 * this as their &drm_simple_display_pipe_funcs->update callback.
294 void mipi_dbi_pipe_update(struct drm_simple_display_pipe *pipe,
295 struct drm_plane_state *old_state)
297 struct drm_plane_state *state = pipe->plane.state;
298 struct drm_crtc *crtc = &pipe->crtc;
299 struct drm_rect rect;
301 if (drm_atomic_helper_damage_merged(old_state, state, &rect))
302 mipi_dbi_fb_dirty(state->fb, &rect);
304 if (crtc->state->event) {
305 spin_lock_irq(&crtc->dev->event_lock);
306 drm_crtc_send_vblank_event(crtc, crtc->state->event);
307 spin_unlock_irq(&crtc->dev->event_lock);
308 crtc->state->event = NULL;
311 EXPORT_SYMBOL(mipi_dbi_pipe_update);
314 * mipi_dbi_enable_flush - MIPI DBI enable helper
315 * @mipi: MIPI DBI structure
316 * @crtc_state: CRTC state
317 * @plane_state: Plane state
319 * This function sets &mipi_dbi->enabled, flushes the whole framebuffer and
320 * enables the backlight. Drivers can use this in their
321 * &drm_simple_display_pipe_funcs->enable callback.
323 * Note: Drivers which don't use mipi_dbi_pipe_update() because they have custom
324 * framebuffer flushing, can't use this function since they both use the same
327 void mipi_dbi_enable_flush(struct mipi_dbi *mipi,
328 struct drm_crtc_state *crtc_state,
329 struct drm_plane_state *plane_state)
331 struct drm_framebuffer *fb = plane_state->fb;
332 struct drm_rect rect = {
340 if (!drm_dev_enter(&mipi->drm, &idx))
343 mipi->enabled = true;
344 mipi_dbi_fb_dirty(fb, &rect);
345 backlight_enable(mipi->backlight);
349 EXPORT_SYMBOL(mipi_dbi_enable_flush);
351 static void mipi_dbi_blank(struct mipi_dbi *mipi)
353 struct drm_device *drm = &mipi->drm;
354 u16 height = drm->mode_config.min_height;
355 u16 width = drm->mode_config.min_width;
356 size_t len = width * height * 2;
359 if (!drm_dev_enter(drm, &idx))
362 memset(mipi->tx_buf, 0, len);
364 mipi_dbi_command(mipi, MIPI_DCS_SET_COLUMN_ADDRESS, 0, 0,
365 (width >> 8) & 0xFF, (width - 1) & 0xFF);
366 mipi_dbi_command(mipi, MIPI_DCS_SET_PAGE_ADDRESS, 0, 0,
367 (height >> 8) & 0xFF, (height - 1) & 0xFF);
368 mipi_dbi_command_buf(mipi, MIPI_DCS_WRITE_MEMORY_START,
369 (u8 *)mipi->tx_buf, len);
375 * mipi_dbi_pipe_disable - MIPI DBI pipe disable helper
376 * @pipe: Display pipe
378 * This function disables backlight if present, if not the display memory is
379 * blanked. The regulator is disabled if in use. Drivers can use this as their
380 * &drm_simple_display_pipe_funcs->disable callback.
382 void mipi_dbi_pipe_disable(struct drm_simple_display_pipe *pipe)
384 struct mipi_dbi *mipi = drm_to_mipi_dbi(pipe->crtc.dev);
391 mipi->enabled = false;
394 backlight_disable(mipi->backlight);
396 mipi_dbi_blank(mipi);
399 regulator_disable(mipi->regulator);
401 EXPORT_SYMBOL(mipi_dbi_pipe_disable);
403 static const struct drm_mode_config_funcs mipi_dbi_mode_config_funcs = {
404 .fb_create = drm_gem_fb_create_with_dirty,
405 .atomic_check = drm_atomic_helper_check,
406 .atomic_commit = drm_atomic_helper_commit,
409 static const uint32_t mipi_dbi_formats[] = {
415 * mipi_dbi_init - MIPI DBI initialization
416 * @mipi: &mipi_dbi structure to initialize
417 * @funcs: Display pipe functions
418 * @mode: Display mode
419 * @rotation: Initial rotation in degrees Counter Clock Wise
421 * This function sets up a &drm_simple_display_pipe with a &drm_connector that
422 * has one fixed &drm_display_mode which is rotated according to @rotation.
423 * This mode is used to set the mode config min/max width/height properties.
424 * Additionally &mipi_dbi.tx_buf is allocated.
426 * Supported formats: Native RGB565 and emulated XRGB8888.
429 * Zero on success, negative error code on failure.
431 int mipi_dbi_init(struct mipi_dbi *mipi,
432 const struct drm_simple_display_pipe_funcs *funcs,
433 const struct drm_display_mode *mode, unsigned int rotation)
435 size_t bufsize = mode->vdisplay * mode->hdisplay * sizeof(u16);
436 struct drm_device *drm = &mipi->drm;
442 mutex_init(&mipi->cmdlock);
444 mipi->tx_buf = devm_kmalloc(drm->dev, bufsize, GFP_KERNEL);
448 /* TODO: Maybe add DRM_MODE_CONNECTOR_SPI */
449 ret = tinydrm_display_pipe_init(drm, &mipi->pipe, funcs,
450 DRM_MODE_CONNECTOR_VIRTUAL,
452 ARRAY_SIZE(mipi_dbi_formats), mode,
457 drm_plane_enable_fb_damage_clips(&mipi->pipe.plane);
459 drm->mode_config.funcs = &mipi_dbi_mode_config_funcs;
460 drm->mode_config.preferred_depth = 16;
461 mipi->rotation = rotation;
463 DRM_DEBUG_KMS("preferred_depth=%u, rotation = %u\n",
464 drm->mode_config.preferred_depth, rotation);
468 EXPORT_SYMBOL(mipi_dbi_init);
471 * mipi_dbi_release - DRM driver release helper
474 * This function finalizes and frees &mipi_dbi.
476 * Drivers can use this as their &drm_driver->release callback.
478 void mipi_dbi_release(struct drm_device *drm)
480 struct mipi_dbi *dbi = drm_to_mipi_dbi(drm);
482 DRM_DEBUG_DRIVER("\n");
484 drm_mode_config_cleanup(drm);
488 EXPORT_SYMBOL(mipi_dbi_release);
491 * mipi_dbi_hw_reset - Hardware reset of controller
492 * @mipi: MIPI DBI structure
494 * Reset controller if the &mipi_dbi->reset gpio is set.
496 void mipi_dbi_hw_reset(struct mipi_dbi *mipi)
501 gpiod_set_value_cansleep(mipi->reset, 0);
502 usleep_range(20, 1000);
503 gpiod_set_value_cansleep(mipi->reset, 1);
506 EXPORT_SYMBOL(mipi_dbi_hw_reset);
509 * mipi_dbi_display_is_on - Check if display is on
510 * @mipi: MIPI DBI structure
512 * This function checks the Power Mode register (if readable) to see if
513 * display output is turned on. This can be used to see if the bootloader
514 * has already turned on the display avoiding flicker when the pipeline is
518 * true if the display can be verified to be on, false otherwise.
520 bool mipi_dbi_display_is_on(struct mipi_dbi *mipi)
524 if (mipi_dbi_command_read(mipi, MIPI_DCS_GET_POWER_MODE, &val))
527 val &= ~DCS_POWER_MODE_RESERVED_MASK;
529 /* The poweron/reset value is 08h DCS_POWER_MODE_DISPLAY_NORMAL_MODE */
530 if (val != (DCS_POWER_MODE_DISPLAY |
531 DCS_POWER_MODE_DISPLAY_NORMAL_MODE | DCS_POWER_MODE_SLEEP_MODE))
534 DRM_DEBUG_DRIVER("Display is ON\n");
538 EXPORT_SYMBOL(mipi_dbi_display_is_on);
540 static int mipi_dbi_poweron_reset_conditional(struct mipi_dbi *mipi, bool cond)
542 struct device *dev = mipi->drm.dev;
545 if (mipi->regulator) {
546 ret = regulator_enable(mipi->regulator);
548 DRM_DEV_ERROR(dev, "Failed to enable regulator (%d)\n", ret);
553 if (cond && mipi_dbi_display_is_on(mipi))
556 mipi_dbi_hw_reset(mipi);
557 ret = mipi_dbi_command(mipi, MIPI_DCS_SOFT_RESET);
559 DRM_DEV_ERROR(dev, "Failed to send reset command (%d)\n", ret);
561 regulator_disable(mipi->regulator);
566 * If we did a hw reset, we know the controller is in Sleep mode and
567 * per MIPI DSC spec should wait 5ms after soft reset. If we didn't,
568 * we assume worst case and wait 120ms.
571 usleep_range(5000, 20000);
579 * mipi_dbi_poweron_reset - MIPI DBI poweron and reset
580 * @mipi: MIPI DBI structure
582 * This function enables the regulator if used and does a hardware and software
586 * Zero on success, or a negative error code.
588 int mipi_dbi_poweron_reset(struct mipi_dbi *mipi)
590 return mipi_dbi_poweron_reset_conditional(mipi, false);
592 EXPORT_SYMBOL(mipi_dbi_poweron_reset);
595 * mipi_dbi_poweron_conditional_reset - MIPI DBI poweron and conditional reset
596 * @mipi: MIPI DBI structure
598 * This function enables the regulator if used and if the display is off, it
599 * does a hardware and software reset. If mipi_dbi_display_is_on() determines
600 * that the display is on, no reset is performed.
603 * Zero if the controller was reset, 1 if the display was already on, or a
604 * negative error code.
606 int mipi_dbi_poweron_conditional_reset(struct mipi_dbi *mipi)
608 return mipi_dbi_poweron_reset_conditional(mipi, true);
610 EXPORT_SYMBOL(mipi_dbi_poweron_conditional_reset);
612 #if IS_ENABLED(CONFIG_SPI)
615 * mipi_dbi_spi_cmd_max_speed - get the maximum SPI bus speed
617 * @len: The transfer buffer length.
619 * Many controllers have a max speed of 10MHz, but can be pushed way beyond
620 * that. Increase reliability by running pixel data at max speed and the rest
621 * at 10MHz, preventing transfer glitches from messing up the init settings.
623 u32 mipi_dbi_spi_cmd_max_speed(struct spi_device *spi, size_t len)
626 return 0; /* use default */
628 return min_t(u32, 10000000, spi->max_speed_hz);
630 EXPORT_SYMBOL(mipi_dbi_spi_cmd_max_speed);
633 * MIPI DBI Type C Option 1
635 * If the SPI controller doesn't have 9 bits per word support,
636 * use blocks of 9 bytes to send 8x 9-bit words using a 8-bit SPI transfer.
637 * Pad partial blocks with MIPI_DCS_NOP (zero).
638 * This is how the D/C bit (x) is added:
650 static int mipi_dbi_spi1e_transfer(struct mipi_dbi *mipi, int dc,
651 const void *buf, size_t len,
654 bool swap_bytes = (bpw == 16 && tinydrm_machine_little_endian());
655 size_t chunk, max_chunk = mipi->tx_buf9_len;
656 struct spi_device *spi = mipi->spi;
657 struct spi_transfer tr = {
658 .tx_buf = mipi->tx_buf9,
661 struct spi_message m;
666 if (drm_debug & DRM_UT_DRIVER)
667 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
668 __func__, dc, max_chunk);
670 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
671 spi_message_init_with_transfers(&m, &tr, 1);
674 if (WARN_ON_ONCE(len != 1))
677 /* Command: pad no-op's (zeroes) at beginning of block */
683 tinydrm_dbg_spi_message(spi, &m);
685 return spi_sync(spi, &m);
688 /* max with room for adding one bit per byte */
689 max_chunk = max_chunk / 9 * 8;
690 /* but no bigger than len */
691 max_chunk = min(max_chunk, len);
693 max_chunk = max_t(size_t, 8, max_chunk & ~0x7);
698 chunk = min(len, max_chunk);
705 /* Data: pad no-op's (zeroes) at end of block */
709 for (i = 1; i < (chunk + 1); i++) {
711 *dst++ = carry | BIT(8 - i) | (val >> i);
712 carry = val << (8 - i);
715 *dst++ = carry | BIT(8 - i) | (val >> i);
716 carry = val << (8 - i);
721 for (i = 1; i < (chunk + 1); i++) {
723 *dst++ = carry | BIT(8 - i) | (val >> i);
724 carry = val << (8 - i);
732 for (i = 0; i < chunk; i += 8) {
734 *dst++ = BIT(7) | (src[1] >> 1);
735 *dst++ = (src[1] << 7) | BIT(6) | (src[0] >> 2);
736 *dst++ = (src[0] << 6) | BIT(5) | (src[3] >> 3);
737 *dst++ = (src[3] << 5) | BIT(4) | (src[2] >> 4);
738 *dst++ = (src[2] << 4) | BIT(3) | (src[5] >> 5);
739 *dst++ = (src[5] << 3) | BIT(2) | (src[4] >> 6);
740 *dst++ = (src[4] << 2) | BIT(1) | (src[7] >> 7);
741 *dst++ = (src[7] << 1) | BIT(0);
744 *dst++ = BIT(7) | (src[0] >> 1);
745 *dst++ = (src[0] << 7) | BIT(6) | (src[1] >> 2);
746 *dst++ = (src[1] << 6) | BIT(5) | (src[2] >> 3);
747 *dst++ = (src[2] << 5) | BIT(4) | (src[3] >> 4);
748 *dst++ = (src[3] << 4) | BIT(3) | (src[4] >> 5);
749 *dst++ = (src[4] << 3) | BIT(2) | (src[5] >> 6);
750 *dst++ = (src[5] << 2) | BIT(1) | (src[6] >> 7);
751 *dst++ = (src[6] << 1) | BIT(0);
760 tr.len = chunk + added;
762 tinydrm_dbg_spi_message(spi, &m);
763 ret = spi_sync(spi, &m);
771 static int mipi_dbi_spi1_transfer(struct mipi_dbi *mipi, int dc,
772 const void *buf, size_t len,
775 struct spi_device *spi = mipi->spi;
776 struct spi_transfer tr = {
779 const u16 *src16 = buf;
780 const u8 *src8 = buf;
781 struct spi_message m;
786 if (!tinydrm_spi_bpw_supported(spi, 9))
787 return mipi_dbi_spi1e_transfer(mipi, dc, buf, len, bpw);
789 tr.speed_hz = mipi_dbi_spi_cmd_max_speed(spi, len);
790 max_chunk = mipi->tx_buf9_len;
791 dst16 = mipi->tx_buf9;
793 if (drm_debug & DRM_UT_DRIVER)
794 pr_debug("[drm:%s] dc=%d, max_chunk=%zu, transfers:\n",
795 __func__, dc, max_chunk);
797 max_chunk = min(max_chunk / 2, len);
799 spi_message_init_with_transfers(&m, &tr, 1);
803 size_t chunk = min(len, max_chunk);
806 if (bpw == 16 && tinydrm_machine_little_endian()) {
807 for (i = 0; i < (chunk * 2); i += 2) {
808 dst16[i] = *src16 >> 8;
809 dst16[i + 1] = *src16++ & 0xFF;
812 dst16[i + 1] |= 0x0100;
816 for (i = 0; i < chunk; i++) {
826 tinydrm_dbg_spi_message(spi, &m);
827 ret = spi_sync(spi, &m);
835 static int mipi_dbi_typec1_command(struct mipi_dbi *mipi, u8 *cmd,
836 u8 *parameters, size_t num)
838 unsigned int bpw = (*cmd == MIPI_DCS_WRITE_MEMORY_START) ? 16 : 8;
841 if (mipi_dbi_command_is_read(mipi, *cmd))
844 MIPI_DBI_DEBUG_COMMAND(*cmd, parameters, num);
846 ret = mipi_dbi_spi1_transfer(mipi, 0, cmd, 1, 8);
850 return mipi_dbi_spi1_transfer(mipi, 1, parameters, num, bpw);
853 /* MIPI DBI Type C Option 3 */
855 static int mipi_dbi_typec3_command_read(struct mipi_dbi *mipi, u8 *cmd,
856 u8 *data, size_t len)
858 struct spi_device *spi = mipi->spi;
859 u32 speed_hz = min_t(u32, MIPI_DBI_MAX_SPI_READ_SPEED,
860 spi->max_speed_hz / 2);
861 struct spi_transfer tr[2] = {
863 .speed_hz = speed_hz,
867 .speed_hz = speed_hz,
871 struct spi_message m;
879 * Support non-standard 24-bit and 32-bit Nokia read commands which
880 * start with a dummy clock, so we need to read an extra byte.
882 if (*cmd == MIPI_DCS_GET_DISPLAY_ID ||
883 *cmd == MIPI_DCS_GET_DISPLAY_STATUS) {
884 if (!(len == 3 || len == 4))
890 buf = kmalloc(tr[1].len, GFP_KERNEL);
895 gpiod_set_value_cansleep(mipi->dc, 0);
897 spi_message_init_with_transfers(&m, tr, ARRAY_SIZE(tr));
898 ret = spi_sync(spi, &m);
902 tinydrm_dbg_spi_message(spi, &m);
904 if (tr[1].len == len) {
905 memcpy(data, buf, len);
909 for (i = 0; i < len; i++)
910 data[i] = (buf[i] << 1) | !!(buf[i + 1] & BIT(7));
913 MIPI_DBI_DEBUG_COMMAND(*cmd, data, len);
921 static int mipi_dbi_typec3_command(struct mipi_dbi *mipi, u8 *cmd,
924 struct spi_device *spi = mipi->spi;
925 unsigned int bpw = 8;
929 if (mipi_dbi_command_is_read(mipi, *cmd))
930 return mipi_dbi_typec3_command_read(mipi, cmd, par, num);
932 MIPI_DBI_DEBUG_COMMAND(*cmd, par, num);
934 gpiod_set_value_cansleep(mipi->dc, 0);
935 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, 1);
936 ret = tinydrm_spi_transfer(spi, speed_hz, NULL, 8, cmd, 1);
940 if (*cmd == MIPI_DCS_WRITE_MEMORY_START && !mipi->swap_bytes)
943 gpiod_set_value_cansleep(mipi->dc, 1);
944 speed_hz = mipi_dbi_spi_cmd_max_speed(spi, num);
946 return tinydrm_spi_transfer(spi, speed_hz, NULL, bpw, par, num);
950 * mipi_dbi_spi_init - Initialize MIPI DBI SPI interfaced controller
952 * @mipi: &mipi_dbi structure to initialize
953 * @dc: D/C gpio (optional)
955 * This function sets &mipi_dbi->command, enables &mipi->read_commands for the
956 * usual read commands. It should be followed by a call to mipi_dbi_init() or
957 * a driver-specific init.
959 * If @dc is set, a Type C Option 3 interface is assumed, if not
962 * If the SPI master driver doesn't support the necessary bits per word,
963 * the following transformation is used:
965 * - 9-bit: reorder buffer as 9x 8-bit words, padded with no-op command.
966 * - 16-bit: if big endian send as 8-bit, if little endian swap bytes
969 * Zero on success, negative error code on failure.
971 int mipi_dbi_spi_init(struct spi_device *spi, struct mipi_dbi *mipi,
972 struct gpio_desc *dc)
974 size_t tx_size = tinydrm_spi_max_transfer_size(spi, 0);
975 struct device *dev = &spi->dev;
979 DRM_ERROR("SPI transmit buffer too small: %zu\n", tx_size);
984 * Even though it's not the SPI device that does DMA (the master does),
985 * the dma mask is necessary for the dma_alloc_wc() in
986 * drm_gem_cma_create(). The dma_addr returned will be a physical
987 * address which might be different from the bus address, but this is
988 * not a problem since the address will not be used.
989 * The virtual address is used in the transfer and the SPI core
990 * re-maps it on the SPI master device using the DMA streaming API
993 if (!dev->coherent_dma_mask) {
994 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(32));
996 dev_warn(dev, "Failed to set dma mask %d\n", ret);
1002 mipi->read_commands = mipi_dbi_dcs_read_commands;
1005 mipi->command = mipi_dbi_typec3_command;
1007 if (tinydrm_machine_little_endian() &&
1008 !tinydrm_spi_bpw_supported(spi, 16))
1009 mipi->swap_bytes = true;
1011 mipi->command = mipi_dbi_typec1_command;
1012 mipi->tx_buf9_len = tx_size;
1013 mipi->tx_buf9 = devm_kmalloc(dev, tx_size, GFP_KERNEL);
1018 DRM_DEBUG_DRIVER("SPI speed: %uMHz\n", spi->max_speed_hz / 1000000);
1022 EXPORT_SYMBOL(mipi_dbi_spi_init);
1024 #endif /* CONFIG_SPI */
1026 #ifdef CONFIG_DEBUG_FS
1028 static ssize_t mipi_dbi_debugfs_command_write(struct file *file,
1029 const char __user *ubuf,
1030 size_t count, loff_t *ppos)
1032 struct seq_file *m = file->private_data;
1033 struct mipi_dbi *mipi = m->private;
1034 u8 val, cmd = 0, parameters[64];
1035 char *buf, *pos, *token;
1039 if (!drm_dev_enter(&mipi->drm, &idx))
1042 buf = memdup_user_nul(ubuf, count);
1048 /* strip trailing whitespace */
1049 for (i = count - 1; i > 0; i--)
1050 if (isspace(buf[i]))
1057 token = strsep(&pos, " ");
1063 ret = kstrtou8(token, 16, &val);
1070 parameters[i++] = val;
1078 ret = mipi_dbi_command_buf(mipi, cmd, parameters, i);
1085 return ret < 0 ? ret : count;
1088 static int mipi_dbi_debugfs_command_show(struct seq_file *m, void *unused)
1090 struct mipi_dbi *mipi = m->private;
1095 if (!drm_dev_enter(&mipi->drm, &idx))
1098 for (cmd = 0; cmd < 255; cmd++) {
1099 if (!mipi_dbi_command_is_read(mipi, cmd))
1103 case MIPI_DCS_READ_MEMORY_START:
1104 case MIPI_DCS_READ_MEMORY_CONTINUE:
1107 case MIPI_DCS_GET_DISPLAY_ID:
1110 case MIPI_DCS_GET_DISPLAY_STATUS:
1118 seq_printf(m, "%02x: ", cmd);
1119 ret = mipi_dbi_command_buf(mipi, cmd, val, len);
1121 seq_puts(m, "XX\n");
1124 seq_printf(m, "%*phN\n", (int)len, val);
1132 static int mipi_dbi_debugfs_command_open(struct inode *inode,
1135 return single_open(file, mipi_dbi_debugfs_command_show,
1139 static const struct file_operations mipi_dbi_debugfs_command_fops = {
1140 .owner = THIS_MODULE,
1141 .open = mipi_dbi_debugfs_command_open,
1143 .llseek = seq_lseek,
1144 .release = single_release,
1145 .write = mipi_dbi_debugfs_command_write,
1149 * mipi_dbi_debugfs_init - Create debugfs entries
1152 * This function creates a 'command' debugfs file for sending commands to the
1153 * controller or getting the read command values.
1154 * Drivers can use this as their &drm_driver->debugfs_init callback.
1157 * Zero on success, negative error code on failure.
1159 int mipi_dbi_debugfs_init(struct drm_minor *minor)
1161 struct mipi_dbi *mipi = drm_to_mipi_dbi(minor->dev);
1162 umode_t mode = S_IFREG | S_IWUSR;
1164 if (mipi->read_commands)
1166 debugfs_create_file("command", mode, minor->debugfs_root, mipi,
1167 &mipi_dbi_debugfs_command_fops);
1171 EXPORT_SYMBOL(mipi_dbi_debugfs_init);
1175 MODULE_LICENSE("GPL");