drivers/gpu/drm/stm/ltdc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics SA 2017
   4  *
   5  * Authors: Philippe Cornu <philippe.cornu@st.com>
   6  *          Yannick Fertre <yannick.fertre@st.com>
   7  *          Fabien Dessenne <fabien.dessenne@st.com>
   8  *          Mickael Reulier <mickael.reulier@st.com>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/component.h>
  13 #include <linux/delay.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/module.h>
  16 #include <linux/of_address.h>
  17 #include <linux/of_graph.h>
  18 #include <linux/pinctrl/consumer.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/regmap.h>
  22 #include <linux/reset.h>
  23
  24 #include <drm/drm_atomic.h>
  25 #include <drm/drm_atomic_helper.h>
  26 #include <drm/drm_blend.h>
  27 #include <drm/drm_bridge.h>
  28 #include <drm/drm_device.h>
  29 #include <drm/drm_edid.h>
  30 #include <drm/drm_fb_cma_helper.h>
  31 #include <drm/drm_fourcc.h>
  32 #include <drm/drm_framebuffer.h>
  33 #include <drm/drm_gem_atomic_helper.h>
  34 #include <drm/drm_gem_cma_helper.h>
  35 #include <drm/drm_of.h>
  36 #include <drm/drm_plane_helper.h>
  37 #include <drm/drm_probe_helper.h>
  38 #include <drm/drm_simple_kms_helper.h>
  39 #include <drm/drm_vblank.h>
  40
  41 #include <video/videomode.h>
  42
  43 #include "ltdc.h"
  44
  45 #define NB_CRTC 1
  46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
  47
  48 #define MAX_IRQ 4
  49
  50 #define HWVER_10200 0x010200
  51 #define HWVER_10300 0x010300
  52 #define HWVER_20101 0x020101
  53 #define HWVER_40100 0x040100
  54
  55 /*
  56  * The address of some registers depends on the HW version: such registers have
  57  * an extra offset specified with layer_ofs.
  58  */
  59 #define LAY_OFS_0       0x80
  60 #define LAY_OFS_1       0x100
  61 #define LAY_OFS (ldev->caps.layer_ofs)
  62
  63 /* Global register offsets */
  64 #define LTDC_IDR        0x0000          /* IDentification */
  65 #define LTDC_LCR        0x0004          /* Layer Count */
  66 #define LTDC_SSCR       0x0008          /* Synchronization Size Configuration */
  67 #define LTDC_BPCR       0x000C          /* Back Porch Configuration */
  68 #define LTDC_AWCR       0x0010          /* Active Width Configuration */
  69 #define LTDC_TWCR       0x0014          /* Total Width Configuration */
  70 #define LTDC_GCR        0x0018          /* Global Control */
  71 #define LTDC_GC1R       0x001C          /* Global Configuration 1 */
  72 #define LTDC_GC2R       0x0020          /* Global Configuration 2 */
  73 #define LTDC_SRCR       0x0024          /* Shadow Reload Configuration */
  74 #define LTDC_GACR       0x0028          /* GAmma Correction */
  75 #define LTDC_BCCR       0x002C          /* Background Color Configuration */
  76 #define LTDC_IER        0x0034          /* Interrupt Enable */
  77 #define LTDC_ISR        0x0038          /* Interrupt Status */
  78 #define LTDC_ICR        0x003C          /* Interrupt Clear */
  79 #define LTDC_LIPCR      0x0040          /* Line Interrupt Position Conf. */
  80 #define LTDC_CPSR       0x0044          /* Current Position Status */
  81 #define LTDC_CDSR       0x0048          /* Current Display Status */
  82 #define LTDC_EDCR       0x0060          /* External Display Control */
  83 #define LTDC_CCRCR      0x007C          /* Computed CRC value */
  84 #define LTDC_FUT        0x0090          /* Fifo underrun Threshold */
  85
  86 /* Layer register offsets */
  87 #define LTDC_L1C0R      (ldev->caps.layer_regs[0])      /* L1 configuration 0 */
  88 #define LTDC_L1C1R      (ldev->caps.layer_regs[1])      /* L1 configuration 1 */
  89 #define LTDC_L1RCR      (ldev->caps.layer_regs[2])      /* L1 reload control */
  90 #define LTDC_L1CR       (ldev->caps.layer_regs[3])      /* L1 control register */
  91 #define LTDC_L1WHPCR    (ldev->caps.layer_regs[4])      /* L1 window horizontal position configuration */
  92 #define LTDC_L1WVPCR    (ldev->caps.layer_regs[5])      /* L1 window vertical position configuration */
  93 #define LTDC_L1CKCR     (ldev->caps.layer_regs[6])      /* L1 color keying configuration */
  94 #define LTDC_L1PFCR     (ldev->caps.layer_regs[7])      /* L1 pixel format configuration */
  95 #define LTDC_L1CACR     (ldev->caps.layer_regs[8])      /* L1 constant alpha configuration */
  96 #define LTDC_L1DCCR     (ldev->caps.layer_regs[9])      /* L1 default color configuration */
  97 #define LTDC_L1BFCR     (ldev->caps.layer_regs[10])     /* L1 blending factors configuration */
  98 #define LTDC_L1BLCR     (ldev->caps.layer_regs[11])     /* L1 burst length configuration */
  99 #define LTDC_L1PCR      (ldev->caps.layer_regs[12])     /* L1 planar configuration */
 100 #define LTDC_L1CFBAR    (ldev->caps.layer_regs[13])     /* L1 color frame buffer address */
 101 #define LTDC_L1CFBLR    (ldev->caps.layer_regs[14])     /* L1 color frame buffer length */
 102 #define LTDC_L1CFBLNR   (ldev->caps.layer_regs[15])     /* L1 color frame buffer line number */
 103 #define LTDC_L1AFBA0R   (ldev->caps.layer_regs[16])     /* L1 auxiliary frame buffer address 0 */
 104 #define LTDC_L1AFBA1R   (ldev->caps.layer_regs[17])     /* L1 auxiliary frame buffer address 1 */
 105 #define LTDC_L1AFBLR    (ldev->caps.layer_regs[18])     /* L1 auxiliary frame buffer length */
 106 #define LTDC_L1AFBLNR   (ldev->caps.layer_regs[19])     /* L1 auxiliary frame buffer line number */
 107 #define LTDC_L1CLUTWR   (ldev->caps.layer_regs[20])     /* L1 CLUT write */
 108 #define LTDC_L1CYR0R    (ldev->caps.layer_regs[21])     /* L1 Conversion YCbCr RGB 0 */
 109 #define LTDC_L1CYR1R    (ldev->caps.layer_regs[22])     /* L1 Conversion YCbCr RGB 1 */
 110 #define LTDC_L1FPF0R    (ldev->caps.layer_regs[23])     /* L1 Flexible Pixel Format 0 */
 111 #define LTDC_L1FPF1R    (ldev->caps.layer_regs[24])     /* L1 Flexible Pixel Format 1 */
 112
 113 /* Bit definitions */
 114 #define SSCR_VSH        GENMASK(10, 0)  /* Vertical Synchronization Height */
 115 #define SSCR_HSW        GENMASK(27, 16) /* Horizontal Synchronization Width */
 116
 117 #define BPCR_AVBP       GENMASK(10, 0)  /* Accumulated Vertical Back Porch */
 118 #define BPCR_AHBP       GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
 119
 120 #define AWCR_AAH        GENMASK(10, 0)  /* Accumulated Active Height */
 121 #define AWCR_AAW        GENMASK(27, 16) /* Accumulated Active Width */
 122
 123 #define TWCR_TOTALH     GENMASK(10, 0)  /* TOTAL Height */
 124 #define TWCR_TOTALW     GENMASK(27, 16) /* TOTAL Width */
 125
 126 #define GCR_LTDCEN      BIT(0)          /* LTDC ENable */
 127 #define GCR_DEN         BIT(16)         /* Dither ENable */
 128 #define GCR_CRCEN       BIT(19)         /* CRC ENable */
 129 #define GCR_PCPOL       BIT(28)         /* Pixel Clock POLarity-Inverted */
 130 #define GCR_DEPOL       BIT(29)         /* Data Enable POLarity-High */
 131 #define GCR_VSPOL       BIT(30)         /* Vertical Synchro POLarity-High */
 132 #define GCR_HSPOL       BIT(31)         /* Horizontal Synchro POLarity-High */
 133
 134 #define GC1R_WBCH       GENMASK(3, 0)   /* Width of Blue CHannel output */
 135 #define GC1R_WGCH       GENMASK(7, 4)   /* Width of Green Channel output */
 136 #define GC1R_WRCH       GENMASK(11, 8)  /* Width of Red Channel output */
 137 #define GC1R_PBEN       BIT(12)         /* Precise Blending ENable */
 138 #define GC1R_DT         GENMASK(15, 14) /* Dithering Technique */
 139 #define GC1R_GCT        GENMASK(19, 17) /* Gamma Correction Technique */
 140 #define GC1R_SHREN      BIT(21)         /* SHadow Registers ENabled */
 141 #define GC1R_BCP        BIT(22)         /* Background Colour Programmable */
 142 #define GC1R_BBEN       BIT(23)         /* Background Blending ENabled */
 143 #define GC1R_LNIP       BIT(24)         /* Line Number IRQ Position */
 144 #define GC1R_TP         BIT(25)         /* Timing Programmable */
 145 #define GC1R_IPP        BIT(26)         /* IRQ Polarity Programmable */
 146 #define GC1R_SPP        BIT(27)         /* Sync Polarity Programmable */
 147 #define GC1R_DWP        BIT(28)         /* Dither Width Programmable */
 148 #define GC1R_STREN      BIT(29)         /* STatus Registers ENabled */
 149 #define GC1R_BMEN       BIT(31)         /* Blind Mode ENabled */
 150
 151 #define GC2R_EDCA       BIT(0)          /* External Display Control Ability  */
 152 #define GC2R_STSAEN     BIT(1)          /* Slave Timing Sync Ability ENabled */
 153 #define GC2R_DVAEN      BIT(2)          /* Dual-View Ability ENabled */
 154 #define GC2R_DPAEN      BIT(3)          /* Dual-Port Ability ENabled */
 155 #define GC2R_BW         GENMASK(6, 4)   /* Bus Width (log2 of nb of bytes) */
 156 #define GC2R_EDCEN      BIT(7)          /* External Display Control ENabled */
 157
 158 #define SRCR_IMR        BIT(0)          /* IMmediate Reload */
 159 #define SRCR_VBR        BIT(1)          /* Vertical Blanking Reload */
 160
 161 #define BCCR_BCBLACK    0x00            /* Background Color BLACK */
 162 #define BCCR_BCBLUE     GENMASK(7, 0)   /* Background Color BLUE */
 163 #define BCCR_BCGREEN    GENMASK(15, 8)  /* Background Color GREEN */
 164 #define BCCR_BCRED      GENMASK(23, 16) /* Background Color RED */
 165 #define BCCR_BCWHITE    GENMASK(23, 0)  /* Background Color WHITE */
 166
 167 #define IER_LIE         BIT(0)          /* Line Interrupt Enable */
 168 #define IER_FUIE        BIT(1)          /* Fifo Underrun Interrupt Enable */
 169 #define IER_TERRIE      BIT(2)          /* Transfer ERRor Interrupt Enable */
 170 #define IER_RRIE        BIT(3)          /* Register Reload Interrupt enable */
 171
 172 #define CPSR_CYPOS      GENMASK(15, 0)  /* Current Y position */
 173
 174 #define ISR_LIF         BIT(0)          /* Line Interrupt Flag */
 175 #define ISR_FUIF        BIT(1)          /* Fifo Underrun Interrupt Flag */
 176 #define ISR_TERRIF      BIT(2)          /* Transfer ERRor Interrupt Flag */
 177 #define ISR_RRIF        BIT(3)          /* Register Reload Interrupt Flag */
 178
 179 #define EDCR_OCYEN      BIT(25)         /* Output Conversion to YCbCr 422: ENable */
 180 #define EDCR_OCYSEL     BIT(26)         /* Output Conversion to YCbCr 422: SELection of the CCIR */
 181 #define EDCR_OCYCO      BIT(27)         /* Output Conversion to YCbCr 422: Chrominance Order */
 182
 183 #define LXCR_LEN        BIT(0)          /* Layer ENable */
 184 #define LXCR_COLKEN     BIT(1)          /* Color Keying Enable */
 185 #define LXCR_CLUTEN     BIT(4)          /* Color Look-Up Table ENable */
 186
 187 #define LXWHPCR_WHSTPOS GENMASK(11, 0)  /* Window Horizontal StarT POSition */
 188 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
 189
 190 #define LXWVPCR_WVSTPOS GENMASK(10, 0)  /* Window Vertical StarT POSition */
 191 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
 192
 193 #define LXPFCR_PF       GENMASK(2, 0)   /* Pixel Format */
 194 #define PF_FLEXIBLE     0x7             /* Flexible Pixel Format selected */
 195
 196 #define LXCACR_CONSTA   GENMASK(7, 0)   /* CONSTant Alpha */
 197
 198 #define LXBFCR_BF2      GENMASK(2, 0)   /* Blending Factor 2 */
 199 #define LXBFCR_BF1      GENMASK(10, 8)  /* Blending Factor 1 */
 200
 201 #define LXCFBLR_CFBLL   GENMASK(12, 0)  /* Color Frame Buffer Line Length */
 202 #define LXCFBLR_CFBP    GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
 203
 204 #define LXCFBLNR_CFBLN  GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 205
 206 #define LXCR_C1R_YIA    BIT(0)          /* Ycbcr 422 Interleaved Ability */
 207 #define LXCR_C1R_YSPA   BIT(1)          /* Ycbcr 420 Semi-Planar Ability */
 208 #define LXCR_C1R_YFPA   BIT(2)          /* Ycbcr 420 Full-Planar Ability */
 209 #define LXCR_C1R_SCA    BIT(31)         /* SCaling Ability*/
 210
 211 #define LxPCR_YREN      BIT(9)          /* Y Rescale Enable for the color dynamic range */
 212 #define LxPCR_OF        BIT(8)          /* Odd pixel First */
 213 #define LxPCR_CBF       BIT(7)          /* CB component First */
 214 #define LxPCR_YF        BIT(6)          /* Y component First */
 215 #define LxPCR_YCM       GENMASK(5, 4)   /* Ycbcr Conversion Mode */
 216 #define YCM_I           0x0             /* Interleaved 422 */
 217 #define YCM_SP          0x1             /* Semi-Planar 420 */
 218 #define YCM_FP          0x2             /* Full-Planar 420 */
 219 #define LxPCR_YCEN      BIT(3)          /* YCbCr-to-RGB Conversion Enable */
 220
 221 #define LXRCR_IMR       BIT(0)          /* IMmediate Reload */
 222 #define LXRCR_VBR       BIT(1)          /* Vertical Blanking Reload */
 223 #define LXRCR_GRMSK     BIT(2)          /* Global (centralized) Reload MaSKed */
 224
 225 #define CLUT_SIZE       256
 226
 227 #define CONSTA_MAX      0xFF            /* CONSTant Alpha MAX= 1.0 */
 228 #define BF1_PAXCA       0x600           /* Pixel Alpha x Constant Alpha */
 229 #define BF1_CA          0x400           /* Constant Alpha */
 230 #define BF2_1PAXCA      0x007           /* 1 - (Pixel Alpha x Constant Alpha) */
 231 #define BF2_1CA         0x005           /* 1 - Constant Alpha */
 232
 233 #define NB_PF           8               /* Max nb of HW pixel format */
 234
 235 /*
 236  * Skip the first value and the second in case CRC was enabled during
 237  * the thread irq. This is to be sure CRC value is relevant for the
 238  * frame.
 239  */
 240 #define CRC_SKIP_FRAMES 2
 241
 242 enum ltdc_pix_fmt {
 243         PF_NONE,
 244         /* RGB formats */
 245         PF_ARGB8888,            /* ARGB [32 bits] */
 246         PF_RGBA8888,            /* RGBA [32 bits] */
 247         PF_ABGR8888,            /* ABGR [32 bits] */
 248         PF_BGRA8888,            /* BGRA [32 bits] */
 249         PF_RGB888,              /* RGB [24 bits] */
 250         PF_BGR888,              /* BGR [24 bits] */
 251         PF_RGB565,              /* RGB [16 bits] */
 252         PF_BGR565,              /* BGR [16 bits] */
 253         PF_ARGB1555,            /* ARGB A:1 bit RGB:15 bits [16 bits] */
 254         PF_ARGB4444,            /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
 255         /* Indexed formats */
 256         PF_L8,                  /* Indexed 8 bits [8 bits] */
 257         PF_AL44,                /* Alpha:4 bits + indexed 4 bits [8 bits] */
 258         PF_AL88                 /* Alpha:8 bits + indexed 8 bits [16 bits] */
 259 };
 260
 261 /* The index gives the encoding of the pixel format for an HW version */
 262 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
 263         PF_ARGB8888,            /* 0x00 */
 264         PF_RGB888,              /* 0x01 */
 265         PF_RGB565,              /* 0x02 */
 266         PF_ARGB1555,            /* 0x03 */
 267         PF_ARGB4444,            /* 0x04 */
 268         PF_L8,                  /* 0x05 */
 269         PF_AL44,                /* 0x06 */
 270         PF_AL88                 /* 0x07 */
 271 };
 272
 273 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
 274         PF_ARGB8888,            /* 0x00 */
 275         PF_RGB888,              /* 0x01 */
 276         PF_RGB565,              /* 0x02 */
 277         PF_RGBA8888,            /* 0x03 */
 278         PF_AL44,                /* 0x04 */
 279         PF_L8,                  /* 0x05 */
 280         PF_ARGB1555,            /* 0x06 */
 281         PF_ARGB4444             /* 0x07 */
 282 };
 283
 284 static const enum ltdc_pix_fmt ltdc_pix_fmt_a2[NB_PF] = {
 285         PF_ARGB8888,            /* 0x00 */
 286         PF_ABGR8888,            /* 0x01 */
 287         PF_RGBA8888,            /* 0x02 */
 288         PF_BGRA8888,            /* 0x03 */
 289         PF_RGB565,              /* 0x04 */
 290         PF_BGR565,              /* 0x05 */
 291         PF_RGB888,              /* 0x06 */
 292         PF_NONE                 /* 0x07 */
 293 };
 294
 295 static const u32 ltdc_drm_fmt_a0[] = {
 296         DRM_FORMAT_ARGB8888,
 297         DRM_FORMAT_XRGB8888,
 298         DRM_FORMAT_RGB888,
 299         DRM_FORMAT_RGB565,
 300         DRM_FORMAT_ARGB1555,
 301         DRM_FORMAT_XRGB1555,
 302         DRM_FORMAT_ARGB4444,
 303         DRM_FORMAT_XRGB4444,
 304         DRM_FORMAT_C8
 305 };
 306
 307 static const u32 ltdc_drm_fmt_a1[] = {
 308         DRM_FORMAT_ARGB8888,
 309         DRM_FORMAT_XRGB8888,
 310         DRM_FORMAT_RGB888,
 311         DRM_FORMAT_RGB565,
 312         DRM_FORMAT_RGBA8888,
 313         DRM_FORMAT_RGBX8888,
 314         DRM_FORMAT_ARGB1555,
 315         DRM_FORMAT_XRGB1555,
 316         DRM_FORMAT_ARGB4444,
 317         DRM_FORMAT_XRGB4444,
 318         DRM_FORMAT_C8
 319 };
 320
 321 static const u32 ltdc_drm_fmt_a2[] = {
 322         DRM_FORMAT_ARGB8888,
 323         DRM_FORMAT_XRGB8888,
 324         DRM_FORMAT_ABGR8888,
 325         DRM_FORMAT_XBGR8888,
 326         DRM_FORMAT_RGBA8888,
 327         DRM_FORMAT_RGBX8888,
 328         DRM_FORMAT_BGRA8888,
 329         DRM_FORMAT_BGRX8888,
 330         DRM_FORMAT_RGB565,
 331         DRM_FORMAT_BGR565,
 332         DRM_FORMAT_RGB888,
 333         DRM_FORMAT_BGR888,
 334         DRM_FORMAT_ARGB1555,
 335         DRM_FORMAT_XRGB1555,
 336         DRM_FORMAT_ARGB4444,
 337         DRM_FORMAT_XRGB4444,
 338         DRM_FORMAT_C8
 339 };
 340
 341 static const u32 ltdc_drm_fmt_ycbcr_cp[] = {
 342         DRM_FORMAT_YUYV,
 343         DRM_FORMAT_YVYU,
 344         DRM_FORMAT_UYVY,
 345         DRM_FORMAT_VYUY
 346 };
 347
 348 static const u32 ltdc_drm_fmt_ycbcr_sp[] = {
 349         DRM_FORMAT_NV12,
 350         DRM_FORMAT_NV21
 351 };
 352
 353 static const u32 ltdc_drm_fmt_ycbcr_fp[] = {
 354         DRM_FORMAT_YUV420,
 355         DRM_FORMAT_YVU420
 356 };
 357
 358 /* Layer register offsets */
 359 static const u32 ltdc_layer_regs_a0[] = {
 360         0x80,   /* L1 configuration 0 */
 361         0x00,   /* not available */
 362         0x00,   /* not available */
 363         0x84,   /* L1 control register */
 364         0x88,   /* L1 window horizontal position configuration */
 365         0x8c,   /* L1 window vertical position configuration */
 366         0x90,   /* L1 color keying configuration */
 367         0x94,   /* L1 pixel format configuration */
 368         0x98,   /* L1 constant alpha configuration */
 369         0x9c,   /* L1 default color configuration */
 370         0xa0,   /* L1 blending factors configuration */
 371         0x00,   /* not available */
 372         0x00,   /* not available */
 373         0xac,   /* L1 color frame buffer address */
 374         0xb0,   /* L1 color frame buffer length */
 375         0xb4,   /* L1 color frame buffer line number */
 376         0x00,   /* not available */
 377         0x00,   /* not available */
 378         0x00,   /* not available */
 379         0x00,   /* not available */
 380         0xc4,   /* L1 CLUT write */
 381         0x00,   /* not available */
 382         0x00,   /* not available */
 383         0x00,   /* not available */
 384         0x00    /* not available */
 385 };
 386
 387 static const u32 ltdc_layer_regs_a1[] = {
 388         0x80,   /* L1 configuration 0 */
 389         0x84,   /* L1 configuration 1 */
 390         0x00,   /* L1 reload control */
 391         0x88,   /* L1 control register */
 392         0x8c,   /* L1 window horizontal position configuration */
 393         0x90,   /* L1 window vertical position configuration */
 394         0x94,   /* L1 color keying configuration */
 395         0x98,   /* L1 pixel format configuration */
 396         0x9c,   /* L1 constant alpha configuration */
 397         0xa0,   /* L1 default color configuration */
 398         0xa4,   /* L1 blending factors configuration */
 399         0xa8,   /* L1 burst length configuration */
 400         0x00,   /* not available */
 401         0xac,   /* L1 color frame buffer address */
 402         0xb0,   /* L1 color frame buffer length */
 403         0xb4,   /* L1 color frame buffer line number */
 404         0xb8,   /* L1 auxiliary frame buffer address 0 */
 405         0xbc,   /* L1 auxiliary frame buffer address 1 */
 406         0xc0,   /* L1 auxiliary frame buffer length */
 407         0xc4,   /* L1 auxiliary frame buffer line number */
 408         0xc8,   /* L1 CLUT write */
 409         0x00,   /* not available */
 410         0x00,   /* not available */
 411         0x00,   /* not available */
 412         0x00    /* not available */
 413 };
 414
 415 static const u32 ltdc_layer_regs_a2[] = {
 416         0x100,  /* L1 configuration 0 */
 417         0x104,  /* L1 configuration 1 */
 418         0x108,  /* L1 reload control */
 419         0x10c,  /* L1 control register */
 420         0x110,  /* L1 window horizontal position configuration */
 421         0x114,  /* L1 window vertical position configuration */
 422         0x118,  /* L1 color keying configuration */
 423         0x11c,  /* L1 pixel format configuration */
 424         0x120,  /* L1 constant alpha configuration */
 425         0x124,  /* L1 default color configuration */
 426         0x128,  /* L1 blending factors configuration */
 427         0x12c,  /* L1 burst length configuration */
 428         0x130,  /* L1 planar configuration */
 429         0x134,  /* L1 color frame buffer address */
 430         0x138,  /* L1 color frame buffer length */
 431         0x13c,  /* L1 color frame buffer line number */
 432         0x140,  /* L1 auxiliary frame buffer address 0 */
 433         0x144,  /* L1 auxiliary frame buffer address 1 */
 434         0x148,  /* L1 auxiliary frame buffer length */
 435         0x14c,  /* L1 auxiliary frame buffer line number */
 436         0x150,  /* L1 CLUT write */
 437         0x16c,  /* L1 Conversion YCbCr RGB 0 */
 438         0x170,  /* L1 Conversion YCbCr RGB 1 */
 439         0x174,  /* L1 Flexible Pixel Format 0 */
 440         0x178   /* L1 Flexible Pixel Format 1 */
 441 };
 442
 443 static const u64 ltdc_format_modifiers[] = {
 444         DRM_FORMAT_MOD_LINEAR,
 445         DRM_FORMAT_MOD_INVALID
 446 };
 447
 448 static const struct regmap_config stm32_ltdc_regmap_cfg = {
 449         .reg_bits = 32,
 450         .val_bits = 32,
 451         .reg_stride = sizeof(u32),
 452         .max_register = 0x400,
 453         .use_relaxed_mmio = true,
 454         .cache_type = REGCACHE_NONE,
 455 };
 456
 457 static const u32 ltdc_ycbcr2rgb_coeffs[DRM_COLOR_ENCODING_MAX][DRM_COLOR_RANGE_MAX][2] = {
 458         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 459                 0x02040199,     /* (b_cb = 516 / r_cr = 409) */
 460                 0x006400D0      /* (g_cb = 100 / g_cr = 208) */
 461         },
 462         [DRM_COLOR_YCBCR_BT601][DRM_COLOR_YCBCR_FULL_RANGE] = {
 463                 0x01C60167,     /* (b_cb = 454 / r_cr = 359) */
 464                 0x005800B7      /* (g_cb = 88 / g_cr = 183) */
 465         },
 466         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_LIMITED_RANGE] = {
 467                 0x021D01CB,     /* (b_cb = 541 / r_cr = 459) */
 468                 0x00370089      /* (g_cb = 55 / g_cr = 137) */
 469         },
 470         [DRM_COLOR_YCBCR_BT709][DRM_COLOR_YCBCR_FULL_RANGE] = {
 471                 0x01DB0193,     /* (b_cb = 475 / r_cr = 403) */
 472                 0x00300078      /* (g_cb = 48 / g_cr = 120) */
 473         }
 474         /* BT2020 not supported */
 475 };
 476
 477 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
 478 {
 479         return (struct ltdc_device *)crtc->dev->dev_private;
 480 }
 481
 482 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
 483 {
 484         return (struct ltdc_device *)plane->dev->dev_private;
 485 }
 486
 487 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
 488 {
 489         return (struct ltdc_device *)enc->dev->dev_private;
 490 }
 491
 492 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
 493 {
 494         enum ltdc_pix_fmt pf;
 495
 496         switch (drm_fmt) {
 497         case DRM_FORMAT_ARGB8888:
 498         case DRM_FORMAT_XRGB8888:
 499                 pf = PF_ARGB8888;
 500                 break;
 501         case DRM_FORMAT_ABGR8888:
 502         case DRM_FORMAT_XBGR8888:
 503                 pf = PF_ABGR8888;
 504                 break;
 505         case DRM_FORMAT_RGBA8888:
 506         case DRM_FORMAT_RGBX8888:
 507                 pf = PF_RGBA8888;
 508                 break;
 509         case DRM_FORMAT_BGRA8888:
 510         case DRM_FORMAT_BGRX8888:
 511                 pf = PF_BGRA8888;
 512                 break;
 513         case DRM_FORMAT_RGB888:
 514                 pf = PF_RGB888;
 515                 break;
 516         case DRM_FORMAT_BGR888:
 517                 pf = PF_BGR888;
 518                 break;
 519         case DRM_FORMAT_RGB565:
 520                 pf = PF_RGB565;
 521                 break;
 522         case DRM_FORMAT_BGR565:
 523                 pf = PF_BGR565;
 524                 break;
 525         case DRM_FORMAT_ARGB1555:
 526         case DRM_FORMAT_XRGB1555:
 527                 pf = PF_ARGB1555;
 528                 break;
 529         case DRM_FORMAT_ARGB4444:
 530         case DRM_FORMAT_XRGB4444:
 531                 pf = PF_ARGB4444;
 532                 break;
 533         case DRM_FORMAT_C8:
 534                 pf = PF_L8;
 535                 break;
 536         default:
 537                 pf = PF_NONE;
 538                 break;
 539                 /* Note: There are no DRM_FORMAT for AL44 and AL88 */
 540         }
 541
 542         return pf;
 543 }
 544
 545 static inline u32 ltdc_set_flexible_pixel_format(struct drm_plane *plane, enum ltdc_pix_fmt pix_fmt)
 546 {
 547         struct ltdc_device *ldev = plane_to_ltdc(plane);
 548         u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE;
 549         int psize, alen, apos, rlen, rpos, glen, gpos, blen, bpos;
 550
 551         switch (pix_fmt) {
 552         case PF_BGR888:
 553                 psize = 3;
 554                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 555                 glen = 8; gpos = 8; blen = 8; bpos = 16;
 556         break;
 557         case PF_ARGB1555:
 558                 psize = 2;
 559                 alen = 1; apos = 15; rlen = 5; rpos = 10;
 560                 glen = 5; gpos = 5;  blen = 5; bpos = 0;
 561         break;
 562         case PF_ARGB4444:
 563                 psize = 2;
 564                 alen = 4; apos = 12; rlen = 4; rpos = 8;
 565                 glen = 4; gpos = 4; blen = 4; bpos = 0;
 566         break;
 567         case PF_L8:
 568                 psize = 1;
 569                 alen = 0; apos = 0; rlen = 8; rpos = 0;
 570                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 571         break;
 572         case PF_AL44:
 573                 psize = 1;
 574                 alen = 4; apos = 4; rlen = 4; rpos = 0;
 575                 glen = 4; gpos = 0; blen = 4; bpos = 0;
 576         break;
 577         case PF_AL88:
 578                 psize = 2;
 579                 alen = 8; apos = 8; rlen = 8; rpos = 0;
 580                 glen = 8; gpos = 0; blen = 8; bpos = 0;
 581         break;
 582         default:
 583                 ret = NB_PF; /* error case, trace msg is handled by the caller */
 584         break;
 585         }
 586
 587         if (ret == PF_FLEXIBLE) {
 588                 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs,
 589                              (rlen << 14)  + (rpos << 9) + (alen << 5) + apos);
 590
 591                 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs,
 592                              (psize << 18) + (blen << 14)  + (bpos << 9) + (glen << 5) + gpos);
 593         }
 594
 595         return ret;
 596 }
 597
 598 /*
 599  * All non-alpha color formats derived from native alpha color formats are
 600  * either characterized by a FourCC format code
 601  */
 602 static inline u32 is_xrgb(u32 drm)
 603 {
 604         return ((drm & 0xFF) == 'X' || ((drm >> 8) & 0xFF) == 'X');
 605 }
 606
 607 static inline void ltdc_set_ycbcr_config(struct drm_plane *plane, u32 drm_pix_fmt)
 608 {
 609         struct ltdc_device *ldev = plane_to_ltdc(plane);
 610         struct drm_plane_state *state = plane->state;
 611         u32 lofs = plane->index * LAY_OFS;
 612         u32 val;
 613
 614         switch (drm_pix_fmt) {
 615         case DRM_FORMAT_YUYV:
 616                 val = (YCM_I << 4) | LxPCR_YF | LxPCR_CBF;
 617                 break;
 618         case DRM_FORMAT_YVYU:
 619                 val = (YCM_I << 4) | LxPCR_YF;
 620                 break;
 621         case DRM_FORMAT_UYVY:
 622                 val = (YCM_I << 4) | LxPCR_CBF;
 623                 break;
 624         case DRM_FORMAT_VYUY:
 625                 val = (YCM_I << 4);
 626                 break;
 627         case DRM_FORMAT_NV12:
 628                 val = (YCM_SP << 4) | LxPCR_CBF;
 629                 break;
 630         case DRM_FORMAT_NV21:
 631                 val = (YCM_SP << 4);
 632                 break;
 633         case DRM_FORMAT_YUV420:
 634         case DRM_FORMAT_YVU420:
 635                 val = (YCM_FP << 4);
 636                 break;
 637         default:
 638                 /* RGB or not a YCbCr supported format */
 639                 DRM_ERROR("Unsupported pixel format: %u\n", drm_pix_fmt);
 640                 return;
 641         }
 642
 643         /* Enable limited range */
 644         if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE)
 645                 val |= LxPCR_YREN;
 646
 647         /* enable ycbcr conversion */
 648         val |= LxPCR_YCEN;
 649
 650         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val);
 651 }
 652
 653 static inline void ltdc_set_ycbcr_coeffs(struct drm_plane *plane)
 654 {
 655         struct ltdc_device *ldev = plane_to_ltdc(plane);
 656         struct drm_plane_state *state = plane->state;
 657         enum drm_color_encoding enc = state->color_encoding;
 658         enum drm_color_range ran = state->color_range;
 659         u32 lofs = plane->index * LAY_OFS;
 660
 661         if (enc != DRM_COLOR_YCBCR_BT601 && enc != DRM_COLOR_YCBCR_BT709) {
 662                 DRM_ERROR("color encoding %d not supported, use bt601 by default\n", enc);
 663                 /* set by default color encoding to DRM_COLOR_YCBCR_BT601 */
 664                 enc = DRM_COLOR_YCBCR_BT601;
 665         }
 666
 667         if (ran != DRM_COLOR_YCBCR_LIMITED_RANGE && ran != DRM_COLOR_YCBCR_FULL_RANGE) {
 668                 DRM_ERROR("color range %d not supported, use limited range by default\n", ran);
 669                 /* set by default color range to DRM_COLOR_YCBCR_LIMITED_RANGE */
 670                 ran = DRM_COLOR_YCBCR_LIMITED_RANGE;
 671         }
 672
 673         DRM_DEBUG_DRIVER("Color encoding=%d, range=%d\n", enc, ran);
 674         regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs,
 675                      ltdc_ycbcr2rgb_coeffs[enc][ran][0]);
 676         regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs,
 677                      ltdc_ycbcr2rgb_coeffs[enc][ran][1]);
 678 }
 679
 680 static inline void ltdc_irq_crc_handle(struct ltdc_device *ldev,
 681                                        struct drm_crtc *crtc)
 682 {
 683         u32 crc;
 684         int ret;
 685
 686         if (ldev->crc_skip_count < CRC_SKIP_FRAMES) {
 687                 ldev->crc_skip_count++;
 688                 return;
 689         }
 690
 691         /* Get the CRC of the frame */
 692         ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc);
 693         if (ret)
 694                 return;
 695
 696         /* Report to DRM the CRC (hw dependent feature) */
 697         drm_crtc_add_crc_entry(crtc, true, drm_crtc_accurate_vblank_count(crtc), &crc);
 698 }
 699
 700 static irqreturn_t ltdc_irq_thread(int irq, void *arg)
 701 {
 702         struct drm_device *ddev = arg;
 703         struct ltdc_device *ldev = ddev->dev_private;
 704         struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
 705
 706         /* Line IRQ : trigger the vblank event */
 707         if (ldev->irq_status & ISR_LIF) {
 708                 drm_crtc_handle_vblank(crtc);
 709
 710                 /* Early return if CRC is not active */
 711                 if (ldev->crc_active)
 712                         ltdc_irq_crc_handle(ldev, crtc);
 713         }
 714
 715         /* Save FIFO Underrun & Transfer Error status */
 716         mutex_lock(&ldev->err_lock);
 717         if (ldev->irq_status & ISR_FUIF)
 718                 ldev->error_status |= ISR_FUIF;
 719         if (ldev->irq_status & ISR_TERRIF)
 720                 ldev->error_status |= ISR_TERRIF;
 721         mutex_unlock(&ldev->err_lock);
 722
 723         return IRQ_HANDLED;
 724 }
 725
 726 static irqreturn_t ltdc_irq(int irq, void *arg)
 727 {
 728         struct drm_device *ddev = arg;
 729         struct ltdc_device *ldev = ddev->dev_private;
 730
 731         /*
 732          *  Read & Clear the interrupt status
 733          *  In order to write / read registers in this critical section
 734          *  very quickly, the regmap functions are not used.
 735          */
 736         ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR);
 737         writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR);
 738
 739         return IRQ_WAKE_THREAD;
 740 }
 741
 742 /*
 743  * DRM_CRTC
 744  */
 745
 746 static void ltdc_crtc_update_clut(struct drm_crtc *crtc)
 747 {
 748         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 749         struct drm_color_lut *lut;
 750         u32 val;
 751         int i;
 752
 753         if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut)
 754                 return;
 755
 756         lut = (struct drm_color_lut *)crtc->state->gamma_lut->data;
 757
 758         for (i = 0; i < CLUT_SIZE; i++, lut++) {
 759                 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) |
 760                         (lut->blue >> 8) | (i << 24);
 761                 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val);
 762         }
 763 }
 764
 765 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc,
 766                                     struct drm_atomic_state *state)
 767 {
 768         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 769         struct drm_device *ddev = crtc->dev;
 770
 771         DRM_DEBUG_DRIVER("\n");
 772
 773         pm_runtime_get_sync(ddev->dev);
 774
 775         /* Sets the background color value */
 776         regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK);
 777
 778         /* Enable IRQ */
 779         regmap_set_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 780
 781         /* Commit shadow registers = update planes at next vblank */
 782         if (!ldev->caps.plane_reg_shadow)
 783                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
 784
 785         drm_crtc_vblank_on(crtc);
 786 }
 787
 788 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc,
 789                                      struct drm_atomic_state *state)
 790 {
 791         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 792         struct drm_device *ddev = crtc->dev;
 793         int layer_index = 0;
 794
 795         DRM_DEBUG_DRIVER("\n");
 796
 797         drm_crtc_vblank_off(crtc);
 798
 799         /* Disable all layers */
 800         for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++)
 801                 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS,
 802                                   LXCR_CLUTEN | LXCR_LEN, 0);
 803
 804         /* disable IRQ */
 805         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
 806
 807         /* immediately commit disable of layers before switching off LTDC */
 808         if (!ldev->caps.plane_reg_shadow)
 809                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR);
 810
 811         pm_runtime_put_sync(ddev->dev);
 812 }
 813
 814 #define CLK_TOLERANCE_HZ 50
 815
 816 static enum drm_mode_status
 817 ltdc_crtc_mode_valid(struct drm_crtc *crtc,
 818                      const struct drm_display_mode *mode)
 819 {
 820         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 821         int target = mode->clock * 1000;
 822         int target_min = target - CLK_TOLERANCE_HZ;
 823         int target_max = target + CLK_TOLERANCE_HZ;
 824         int result;
 825
 826         result = clk_round_rate(ldev->pixel_clk, target);
 827
 828         DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result);
 829
 830         /* Filter modes according to the max frequency supported by the pads */
 831         if (result > ldev->caps.pad_max_freq_hz)
 832                 return MODE_CLOCK_HIGH;
 833
 834         /*
 835          * Accept all "preferred" modes:
 836          * - this is important for panels because panel clock tolerances are
 837          *   bigger than hdmi ones and there is no reason to not accept them
 838          *   (the fps may vary a little but it is not a problem).
 839          * - the hdmi preferred mode will be accepted too, but userland will
 840          *   be able to use others hdmi "valid" modes if necessary.
 841          */
 842         if (mode->type & DRM_MODE_TYPE_PREFERRED)
 843                 return MODE_OK;
 844
 845         /*
 846          * Filter modes according to the clock value, particularly useful for
 847          * hdmi modes that require precise pixel clocks.
 848          */
 849         if (result < target_min || result > target_max)
 850                 return MODE_CLOCK_RANGE;
 851
 852         return MODE_OK;
 853 }
 854
 855 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc,
 856                                  const struct drm_display_mode *mode,
 857                                  struct drm_display_mode *adjusted_mode)
 858 {
 859         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 860         int rate = mode->clock * 1000;
 861
 862         if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
 863                 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
 864                 return false;
 865         }
 866
 867         adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000;
 868
 869         DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n",
 870                          mode->clock, adjusted_mode->clock);
 871
 872         return true;
 873 }
 874
 875 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
 876 {
 877         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
 878         struct drm_device *ddev = crtc->dev;
 879         struct drm_connector_list_iter iter;
 880         struct drm_connector *connector = NULL;
 881         struct drm_encoder *encoder = NULL, *en_iter;
 882         struct drm_bridge *bridge = NULL, *br_iter;
 883         struct drm_display_mode *mode = &crtc->state->adjusted_mode;
 884         u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
 885         u32 total_width, total_height;
 886         u32 bus_formats = MEDIA_BUS_FMT_RGB888_1X24;
 887         u32 bus_flags = 0;
 888         u32 val;
 889         int ret;
 890
 891         /* get encoder from crtc */
 892         drm_for_each_encoder(en_iter, ddev)
 893                 if (en_iter->crtc == crtc) {
 894                         encoder = en_iter;
 895                         break;
 896                 }
 897
 898         if (encoder) {
 899                 /* get bridge from encoder */
 900                 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node)
 901                         if (br_iter->encoder == encoder) {
 902                                 bridge = br_iter;
 903                                 break;
 904                         }
 905
 906                 /* Get the connector from encoder */
 907                 drm_connector_list_iter_begin(ddev, &iter);
 908                 drm_for_each_connector_iter(connector, &iter)
 909                         if (connector->encoder == encoder)
 910                                 break;
 911                 drm_connector_list_iter_end(&iter);
 912         }
 913
 914         if (bridge && bridge->timings)
 915                 bus_flags = bridge->timings->input_bus_flags;
 916         else if (connector) {
 917                 bus_flags = connector->display_info.bus_flags;
 918                 if (connector->display_info.num_bus_formats)
 919                         bus_formats = connector->display_info.bus_formats[0];
 920         }
 921
 922         if (!pm_runtime_active(ddev->dev)) {
 923                 ret = pm_runtime_get_sync(ddev->dev);
 924                 if (ret) {
 925                         DRM_ERROR("Failed to set mode, cannot get sync\n");
 926                         return;
 927                 }
 928         }
 929
 930         DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
 931         DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay);
 932         DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
 933                          mode->hsync_start - mode->hdisplay,
 934                          mode->htotal - mode->hsync_end,
 935                          mode->hsync_end - mode->hsync_start,
 936                          mode->vsync_start - mode->vdisplay,
 937                          mode->vtotal - mode->vsync_end,
 938                          mode->vsync_end - mode->vsync_start);
 939
 940         /* Convert video timings to ltdc timings */
 941         hsync = mode->hsync_end - mode->hsync_start - 1;
 942         vsync = mode->vsync_end - mode->vsync_start - 1;
 943         accum_hbp = mode->htotal - mode->hsync_start - 1;
 944         accum_vbp = mode->vtotal - mode->vsync_start - 1;
 945         accum_act_w = accum_hbp + mode->hdisplay;
 946         accum_act_h = accum_vbp + mode->vdisplay;
 947         total_width = mode->htotal - 1;
 948         total_height = mode->vtotal - 1;
 949
 950         /* Configures the HS, VS, DE and PC polarities. Default Active Low */
 951         val = 0;
 952
 953         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
 954                 val |= GCR_HSPOL;
 955
 956         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
 957                 val |= GCR_VSPOL;
 958
 959         if (bus_flags & DRM_BUS_FLAG_DE_LOW)
 960                 val |= GCR_DEPOL;
 961
 962         if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
 963                 val |= GCR_PCPOL;
 964
 965         regmap_update_bits(ldev->regmap, LTDC_GCR,
 966                            GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
 967
 968         /* Set Synchronization size */
 969         val = (hsync << 16) | vsync;
 970         regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
 971
 972         /* Set Accumulated Back porch */
 973         val = (accum_hbp << 16) | accum_vbp;
 974         regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
 975
 976         /* Set Accumulated Active Width */
 977         val = (accum_act_w << 16) | accum_act_h;
 978         regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
 979
 980         /* Set total width & height */
 981         val = (total_width << 16) | total_height;
 982         regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 983
 984         regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1));
 985
 986         /* Configure the output format (hw version dependent) */
 987         if (ldev->caps.ycbcr_output) {
 988                 /* Input video dynamic_range & colorimetry */
 989                 int vic = drm_match_cea_mode(mode);
 990                 u32 val;
 991
 992                 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 ||
 993                     vic == 2 || vic == 3 || vic == 17 || vic == 18)
 994                         /* ITU-R BT.601 */
 995                         val = 0;
 996                 else
 997                         /* ITU-R BT.709 */
 998                         val = EDCR_OCYSEL;
 999
1000                 switch (bus_formats) {
1001                 case MEDIA_BUS_FMT_YUYV8_1X16:
1002                         /* enable ycbcr output converter */
1003                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val);
1004                         break;
1005                 case MEDIA_BUS_FMT_YVYU8_1X16:
1006                         /* enable ycbcr output converter & invert chrominance order */
1007                         regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val);
1008                         break;
1009                 default:
1010                         /* disable ycbcr output converter */
1011                         regmap_write(ldev->regmap, LTDC_EDCR, 0);
1012                         break;
1013                 }
1014         }
1015 }
1016
1017 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
1018                                    struct drm_atomic_state *state)
1019 {
1020         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1021         struct drm_device *ddev = crtc->dev;
1022         struct drm_pending_vblank_event *event = crtc->state->event;
1023
1024         DRM_DEBUG_ATOMIC("\n");
1025
1026         ltdc_crtc_update_clut(crtc);
1027
1028         /* Commit shadow registers = update planes at next vblank */
1029         if (!ldev->caps.plane_reg_shadow)
1030                 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR);
1031
1032         if (event) {
1033                 crtc->state->event = NULL;
1034
1035                 spin_lock_irq(&ddev->event_lock);
1036                 if (drm_crtc_vblank_get(crtc) == 0)
1037                         drm_crtc_arm_vblank_event(crtc, event);
1038                 else
1039                         drm_crtc_send_vblank_event(crtc, event);
1040                 spin_unlock_irq(&ddev->event_lock);
1041         }
1042 }
1043
1044 static bool ltdc_crtc_get_scanout_position(struct drm_crtc *crtc,
1045                                            bool in_vblank_irq,
1046                                            int *vpos, int *hpos,
1047                                            ktime_t *stime, ktime_t *etime,
1048                                            const struct drm_display_mode *mode)
1049 {
1050         struct drm_device *ddev = crtc->dev;
1051         struct ltdc_device *ldev = ddev->dev_private;
1052         int line, vactive_start, vactive_end, vtotal;
1053
1054         if (stime)
1055                 *stime = ktime_get();
1056
1057         /* The active area starts after vsync + front porch and ends
1058          * at vsync + front porc + display size.
1059          * The total height also include back porch.
1060          * We have 3 possible cases to handle:
1061          * - line < vactive_start: vpos = line - vactive_start and will be
1062          * negative
1063          * - vactive_start < line < vactive_end: vpos = line - vactive_start
1064          * and will be positive
1065          * - line > vactive_end: vpos = line - vtotal - vactive_start
1066          * and will negative
1067          *
1068          * Computation for the two first cases are identical so we can
1069          * simplify the code and only test if line > vactive_end
1070          */
1071         if (pm_runtime_active(ddev->dev)) {
1072                 regmap_read(ldev->regmap, LTDC_CPSR, &line);
1073                 line &= CPSR_CYPOS;
1074                 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start);
1075                 vactive_start &= BPCR_AVBP;
1076                 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end);
1077                 vactive_end &= AWCR_AAH;
1078                 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal);
1079                 vtotal &= TWCR_TOTALH;
1080
1081                 if (line > vactive_end)
1082                         *vpos = line - vtotal - vactive_start;
1083                 else
1084                         *vpos = line - vactive_start;
1085         } else {
1086                 *vpos = 0;
1087         }
1088
1089         *hpos = 0;
1090
1091         if (etime)
1092                 *etime = ktime_get();
1093
1094         return true;
1095 }
1096
1097 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
1098         .mode_valid = ltdc_crtc_mode_valid,
1099         .mode_fixup = ltdc_crtc_mode_fixup,
1100         .mode_set_nofb = ltdc_crtc_mode_set_nofb,
1101         .atomic_flush = ltdc_crtc_atomic_flush,
1102         .atomic_enable = ltdc_crtc_atomic_enable,
1103         .atomic_disable = ltdc_crtc_atomic_disable,
1104         .get_scanout_position = ltdc_crtc_get_scanout_position,
1105 };
1106
1107 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc)
1108 {
1109         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1110         struct drm_crtc_state *state = crtc->state;
1111
1112         DRM_DEBUG_DRIVER("\n");
1113
1114         if (state->enable)
1115                 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE);
1116         else
1117                 return -EPERM;
1118
1119         return 0;
1120 }
1121
1122 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc)
1123 {
1124         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1125
1126         DRM_DEBUG_DRIVER("\n");
1127         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE);
1128 }
1129
1130 static int ltdc_crtc_set_crc_source(struct drm_crtc *crtc, const char *source)
1131 {
1132         struct ltdc_device *ldev = crtc_to_ltdc(crtc);
1133         int ret;
1134
1135         DRM_DEBUG_DRIVER("\n");
1136
1137         if (!crtc)
1138                 return -ENODEV;
1139
1140         if (source && strcmp(source, "auto") == 0) {
1141                 ldev->crc_active = true;
1142                 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1143         } else if (!source) {
1144                 ldev->crc_active = false;
1145                 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN);
1146         } else {
1147                 ret = -EINVAL;
1148         }
1149
1150         ldev->crc_skip_count = 0;
1151         return ret;
1152 }
1153
1154 static int ltdc_crtc_verify_crc_source(struct drm_crtc *crtc,
1155                                        const char *source, size_t *values_cnt)
1156 {
1157         DRM_DEBUG_DRIVER("\n");
1158
1159         if (!crtc)
1160                 return -ENODEV;
1161
1162         if (source && strcmp(source, "auto") != 0) {
1163                 DRM_DEBUG_DRIVER("Unknown CRC source %s for %s\n",
1164                                  source, crtc->name);
1165                 return -EINVAL;
1166         }
1167
1168         *values_cnt = 1;
1169         return 0;
1170 }
1171
1172 static const struct drm_crtc_funcs ltdc_crtc_funcs = {
1173         .destroy = drm_crtc_cleanup,
1174         .set_config = drm_atomic_helper_set_config,
1175         .page_flip = drm_atomic_helper_page_flip,
1176         .reset = drm_atomic_helper_crtc_reset,
1177         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1178         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1179         .enable_vblank = ltdc_crtc_enable_vblank,
1180         .disable_vblank = ltdc_crtc_disable_vblank,
1181         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1182 };
1183
1184 static const struct drm_crtc_funcs ltdc_crtc_with_crc_support_funcs = {
1185         .destroy = drm_crtc_cleanup,
1186         .set_config = drm_atomic_helper_set_config,
1187         .page_flip = drm_atomic_helper_page_flip,
1188         .reset = drm_atomic_helper_crtc_reset,
1189         .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
1190         .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
1191         .enable_vblank = ltdc_crtc_enable_vblank,
1192         .disable_vblank = ltdc_crtc_disable_vblank,
1193         .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
1194         .set_crc_source = ltdc_crtc_set_crc_source,
1195         .verify_crc_source = ltdc_crtc_verify_crc_source,
1196 };
1197
1198 /*
1199  * DRM_PLANE
1200  */
1201
1202 static int ltdc_plane_atomic_check(struct drm_plane *plane,
1203                                    struct drm_atomic_state *state)
1204 {
1205         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1206                                                                                  plane);
1207         struct drm_framebuffer *fb = new_plane_state->fb;
1208         u32 src_w, src_h;
1209
1210         DRM_DEBUG_DRIVER("\n");
1211
1212         if (!fb)
1213                 return 0;
1214
1215         /* convert src_ from 16:16 format */
1216         src_w = new_plane_state->src_w >> 16;
1217         src_h = new_plane_state->src_h >> 16;
1218
1219         /* Reject scaling */
1220         if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) {
1221                 DRM_ERROR("Scaling is not supported");
1222                 return -EINVAL;
1223         }
1224
1225         return 0;
1226 }
1227
1228 static void ltdc_plane_atomic_update(struct drm_plane *plane,
1229                                      struct drm_atomic_state *state)
1230 {
1231         struct ltdc_device *ldev = plane_to_ltdc(plane);
1232         struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
1233                                                                           plane);
1234         struct drm_framebuffer *fb = newstate->fb;
1235         u32 lofs = plane->index * LAY_OFS;
1236         u32 x0 = newstate->crtc_x;
1237         u32 x1 = newstate->crtc_x + newstate->crtc_w - 1;
1238         u32 y0 = newstate->crtc_y;
1239         u32 y1 = newstate->crtc_y + newstate->crtc_h - 1;
1240         u32 src_x, src_y, src_w, src_h;
1241         u32 val, pitch_in_bytes, line_length, line_number, paddr, ahbp, avbp, bpcr;
1242         enum ltdc_pix_fmt pf;
1243
1244         if (!newstate->crtc || !fb) {
1245                 DRM_DEBUG_DRIVER("fb or crtc NULL");
1246                 return;
1247         }
1248
1249         /* convert src_ from 16:16 format */
1250         src_x = newstate->src_x >> 16;
1251         src_y = newstate->src_y >> 16;
1252         src_w = newstate->src_w >> 16;
1253         src_h = newstate->src_h >> 16;
1254
1255         DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
1256                          plane->base.id, fb->base.id,
1257                          src_w, src_h, src_x, src_y,
1258                          newstate->crtc_w, newstate->crtc_h,
1259                          newstate->crtc_x, newstate->crtc_y);
1260
1261         regmap_read(ldev->regmap, LTDC_BPCR, &bpcr);
1262
1263         ahbp = (bpcr & BPCR_AHBP) >> 16;
1264         avbp = bpcr & BPCR_AVBP;
1265
1266         /* Configures the horizontal start and stop position */
1267         val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
1268         regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs,
1269                           LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
1270
1271         /* Configures the vertical start and stop position */
1272         val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
1273         regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs,
1274                           LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
1275
1276         /* Specifies the pixel format */
1277         pf = to_ltdc_pixelformat(fb->format->format);
1278         for (val = 0; val < NB_PF; val++)
1279                 if (ldev->caps.pix_fmt_hw[val] == pf)
1280                         break;
1281
1282         /* Use the flexible color format feature if necessary and available */
1283         if (ldev->caps.pix_fmt_flex && val == NB_PF)
1284                 val = ltdc_set_flexible_pixel_format(plane, pf);
1285
1286         if (val == NB_PF) {
1287                 DRM_ERROR("Pixel format %.4s not supported\n",
1288                           (char *)&fb->format->format);
1289                 val = 0;        /* set by default ARGB 32 bits */
1290         }
1291         regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
1292
1293         /* Configures the color frame buffer pitch in bytes & line length */
1294         pitch_in_bytes = fb->pitches[0];
1295         line_length = fb->format->cpp[0] *
1296                       (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
1297         val = ((pitch_in_bytes << 16) | line_length);
1298         regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
1299
1300         /* Specifies the constant alpha value */
1301         val = newstate->alpha >> 8;
1302         regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val);
1303
1304         /* Specifies the blending factors */
1305         val = BF1_PAXCA | BF2_1PAXCA;
1306         if (!fb->format->has_alpha)
1307                 val = BF1_CA | BF2_1CA;
1308
1309         /* Manage hw-specific capabilities */
1310         if (ldev->caps.non_alpha_only_l1 &&
1311             plane->type != DRM_PLANE_TYPE_PRIMARY)
1312                 val = BF1_PAXCA | BF2_1PAXCA;
1313
1314         regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, LXBFCR_BF2 | LXBFCR_BF1, val);
1315
1316         /* Configures the frame buffer line number */
1317         line_number = y1 - y0 + 1;
1318         regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number);
1319
1320         /* Sets the FB address */
1321         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 0);
1322
1323         DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
1324         regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr);
1325
1326         if (ldev->caps.ycbcr_input) {
1327                 if (fb->format->is_yuv) {
1328                         switch (fb->format->format) {
1329                         case DRM_FORMAT_NV12:
1330                         case DRM_FORMAT_NV21:
1331                         /* Configure the auxiliary frame buffer address 0 & 1 */
1332                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
1333                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr);
1334                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr + 1);
1335
1336                         /* Configure the buffer length */
1337                         val = ((pitch_in_bytes << 16) | line_length);
1338                         regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1339
1340                         /* Configure the frame buffer line number */
1341                         val = (line_number >> 1);
1342                         regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1343                         break;
1344                         case DRM_FORMAT_YUV420:
1345                         /* Configure the auxiliary frame buffer address 0 */
1346                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
1347                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr);
1348
1349                         /* Configure the auxiliary frame buffer address 1 */
1350                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2);
1351                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr);
1352
1353                         line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) +
1354                                       (ldev->caps.bus_width >> 3) - 1;
1355
1356                         /* Configure the buffer length */
1357                         val = (((pitch_in_bytes >> 1) << 16) | line_length);
1358                         regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1359
1360                         /* Configure the frame buffer line number */
1361                         val = (line_number >> 1);
1362                         regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1363                         break;
1364                         case DRM_FORMAT_YVU420:
1365                         /* Configure the auxiliary frame buffer address 0 */
1366                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 2);
1367                         regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr);
1368
1369                         /* Configure the auxiliary frame buffer address 1 */
1370                         paddr = (u32)drm_fb_cma_get_gem_addr(fb, newstate, 1);
1371                         regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr);
1372
1373                         line_length = ((fb->format->cpp[0] * (x1 - x0 + 1)) >> 1) +
1374                                       (ldev->caps.bus_width >> 3) - 1;
1375
1376                         /* Configure the buffer length */
1377                         val = (((pitch_in_bytes >> 1) << 16) | line_length);
1378                         regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val);
1379
1380                         /* Configure the frame buffer line number */
1381                         val = (line_number >> 1);
1382                         regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val);
1383                         break;
1384                         }
1385
1386                         /* Configure YCbC conversion coefficient */
1387                         ltdc_set_ycbcr_coeffs(plane);
1388
1389                         /* Configure YCbCr format and enable/disable conversion */
1390                         ltdc_set_ycbcr_config(plane, fb->format->format);
1391                 } else {
1392                         /* disable ycbcr conversion */
1393                         regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0);
1394                 }
1395         }
1396
1397         /* Enable layer and CLUT if needed */
1398         val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
1399         val |= LXCR_LEN;
1400         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN, val);
1401
1402         /* Commit shadow registers = update plane at next vblank */
1403         if (ldev->caps.plane_reg_shadow)
1404                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1405                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1406
1407         ldev->plane_fpsi[plane->index].counter++;
1408
1409         mutex_lock(&ldev->err_lock);
1410         if (ldev->error_status & ISR_FUIF) {
1411                 DRM_WARN("ltdc fifo underrun: please verify display mode\n");
1412                 ldev->error_status &= ~ISR_FUIF;
1413         }
1414         if (ldev->error_status & ISR_TERRIF) {
1415                 DRM_WARN("ltdc transfer error\n");
1416                 ldev->error_status &= ~ISR_TERRIF;
1417         }
1418         mutex_unlock(&ldev->err_lock);
1419 }
1420
1421 static void ltdc_plane_atomic_disable(struct drm_plane *plane,
1422                                       struct drm_atomic_state *state)
1423 {
1424         struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
1425                                                                           plane);
1426         struct ltdc_device *ldev = plane_to_ltdc(plane);
1427         u32 lofs = plane->index * LAY_OFS;
1428
1429         /* disable layer */
1430         regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN, 0);
1431
1432         /* Commit shadow registers = update plane at next vblank */
1433         if (ldev->caps.plane_reg_shadow)
1434                 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs,
1435                                   LXRCR_IMR | LXRCR_VBR | LXRCR_GRMSK, LXRCR_VBR);
1436
1437         DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
1438                          oldstate->crtc->base.id, plane->base.id);
1439 }
1440
1441 static void ltdc_plane_atomic_print_state(struct drm_printer *p,
1442                                           const struct drm_plane_state *state)
1443 {
1444         struct drm_plane *plane = state->plane;
1445         struct ltdc_device *ldev = plane_to_ltdc(plane);
1446         struct fps_info *fpsi = &ldev->plane_fpsi[plane->index];
1447         int ms_since_last;
1448         ktime_t now;
1449
1450         now = ktime_get();
1451         ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp));
1452
1453         drm_printf(p, "\tuser_updates=%dfps\n",
1454                    DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last));
1455
1456         fpsi->last_timestamp = now;
1457         fpsi->counter = 0;
1458 }
1459
1460 static const struct drm_plane_funcs ltdc_plane_funcs = {
1461         .update_plane = drm_atomic_helper_update_plane,
1462         .disable_plane = drm_atomic_helper_disable_plane,
1463         .destroy = drm_plane_cleanup,
1464         .reset = drm_atomic_helper_plane_reset,
1465         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1466         .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1467         .atomic_print_state = ltdc_plane_atomic_print_state,
1468 };
1469
1470 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
1471         .atomic_check = ltdc_plane_atomic_check,
1472         .atomic_update = ltdc_plane_atomic_update,
1473         .atomic_disable = ltdc_plane_atomic_disable,
1474 };
1475
1476 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
1477                                            enum drm_plane_type type,
1478                                            int index)
1479 {
1480         unsigned long possible_crtcs = CRTC_MASK;
1481         struct ltdc_device *ldev = ddev->dev_private;
1482         struct device *dev = ddev->dev;
1483         struct drm_plane *plane;
1484         unsigned int i, nb_fmt = 0;
1485         u32 *formats;
1486         u32 drm_fmt;
1487         const u64 *modifiers = ltdc_format_modifiers;
1488         u32 lofs = index * LAY_OFS;
1489         u32 val;
1490         int ret;
1491
1492         /* Allocate the biggest size according to supported color formats */
1493         formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb +
1494                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) +
1495                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) +
1496                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp)) *
1497                                sizeof(*formats), GFP_KERNEL);
1498
1499         for (i = 0; i < ldev->caps.pix_fmt_nb; i++) {
1500                 drm_fmt = ldev->caps.pix_fmt_drm[i];
1501
1502                 /* Manage hw-specific capabilities */
1503                 if (ldev->caps.non_alpha_only_l1)
1504                         /* XR24 & RX24 like formats supported only on primary layer */
1505                         if (type != DRM_PLANE_TYPE_PRIMARY && is_xrgb(drm_fmt))
1506                                 continue;
1507
1508                 formats[nb_fmt++] = drm_fmt;
1509         }
1510
1511         /* Add YCbCr supported pixel formats */
1512         if (ldev->caps.ycbcr_input) {
1513                 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val);
1514                 if (val & LXCR_C1R_YIA) {
1515                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_cp,
1516                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp) * sizeof(*formats));
1517                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_cp);
1518                 }
1519                 if (val & LXCR_C1R_YSPA) {
1520                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_sp,
1521                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp) * sizeof(*formats));
1522                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_sp);
1523                 }
1524                 if (val & LXCR_C1R_YFPA) {
1525                         memcpy(&formats[nb_fmt], ltdc_drm_fmt_ycbcr_fp,
1526                                ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp) * sizeof(*formats));
1527                         nb_fmt += ARRAY_SIZE(ltdc_drm_fmt_ycbcr_fp);
1528                 }
1529         }
1530
1531         plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
1532         if (!plane)
1533                 return NULL;
1534
1535         ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
1536                                        &ltdc_plane_funcs, formats, nb_fmt,
1537                                        modifiers, type, NULL);
1538         if (ret < 0)
1539                 return NULL;
1540
1541         if (ldev->caps.ycbcr_input) {
1542                 if (val & (LXCR_C1R_YIA | LXCR_C1R_YSPA | LXCR_C1R_YFPA))
1543                         drm_plane_create_color_properties(plane,
1544                                                           BIT(DRM_COLOR_YCBCR_BT601) |
1545                                                           BIT(DRM_COLOR_YCBCR_BT709),
1546                                                           BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
1547                                                           BIT(DRM_COLOR_YCBCR_FULL_RANGE),
1548                                                           DRM_COLOR_YCBCR_BT601,
1549                                                           DRM_COLOR_YCBCR_LIMITED_RANGE);
1550         }
1551
1552         drm_plane_helper_add(plane, &ltdc_plane_helper_funcs);
1553
1554         drm_plane_create_alpha_property(plane);
1555
1556         DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
1557
1558         return plane;
1559 }
1560
1561 static void ltdc_plane_destroy_all(struct drm_device *ddev)
1562 {
1563         struct drm_plane *plane, *plane_temp;
1564
1565         list_for_each_entry_safe(plane, plane_temp,
1566                                  &ddev->mode_config.plane_list, head)
1567                 drm_plane_cleanup(plane);
1568 }
1569
1570 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
1571 {
1572         struct ltdc_device *ldev = ddev->dev_private;
1573         struct drm_plane *primary, *overlay;
1574         unsigned int i;
1575         int ret;
1576
1577         primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0);
1578         if (!primary) {
1579                 DRM_ERROR("Can not create primary plane\n");
1580                 return -EINVAL;
1581         }
1582
1583         drm_plane_create_zpos_immutable_property(primary, 0);
1584
1585         /* Init CRTC according to its hardware features */
1586         if (ldev->caps.crc)
1587                 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1588                                                 &ltdc_crtc_with_crc_support_funcs, NULL);
1589         else
1590                 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
1591                                                 &ltdc_crtc_funcs, NULL);
1592         if (ret) {
1593                 DRM_ERROR("Can not initialize CRTC\n");
1594                 goto cleanup;
1595         }
1596
1597         drm_crtc_helper_add(crtc, &ltdc_crtc_helper_funcs);
1598
1599         drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE);
1600         drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE);
1601
1602         DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
1603
1604         /* Add planes. Note : the first layer is used by primary plane */
1605         for (i = 1; i < ldev->caps.nb_layers; i++) {
1606                 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY, i);
1607                 if (!overlay) {
1608                         ret = -ENOMEM;
1609                         DRM_ERROR("Can not create overlay plane %d\n", i);
1610                         goto cleanup;
1611                 }
1612                 drm_plane_create_zpos_immutable_property(overlay, i);
1613         }
1614
1615         return 0;
1616
1617 cleanup:
1618         ltdc_plane_destroy_all(ddev);
1619         return ret;
1620 }
1621
1622 static void ltdc_encoder_disable(struct drm_encoder *encoder)
1623 {
1624         struct drm_device *ddev = encoder->dev;
1625         struct ltdc_device *ldev = ddev->dev_private;
1626
1627         DRM_DEBUG_DRIVER("\n");
1628
1629         /* Disable LTDC */
1630         regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1631
1632         /* Set to sleep state the pinctrl whatever type of encoder */
1633         pinctrl_pm_select_sleep_state(ddev->dev);
1634 }
1635
1636 static void ltdc_encoder_enable(struct drm_encoder *encoder)
1637 {
1638         struct drm_device *ddev = encoder->dev;
1639         struct ltdc_device *ldev = ddev->dev_private;
1640
1641         DRM_DEBUG_DRIVER("\n");
1642
1643         /* Enable LTDC */
1644         regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN);
1645 }
1646
1647 static void ltdc_encoder_mode_set(struct drm_encoder *encoder,
1648                                   struct drm_display_mode *mode,
1649                                   struct drm_display_mode *adjusted_mode)
1650 {
1651         struct drm_device *ddev = encoder->dev;
1652
1653         DRM_DEBUG_DRIVER("\n");
1654
1655         /*
1656          * Set to default state the pinctrl only with DPI type.
1657          * Others types like DSI, don't need pinctrl due to
1658          * internal bridge (the signals do not come out of the chipset).
1659          */
1660         if (encoder->encoder_type == DRM_MODE_ENCODER_DPI)
1661                 pinctrl_pm_select_default_state(ddev->dev);
1662 }
1663
1664 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = {
1665         .disable = ltdc_encoder_disable,
1666         .enable = ltdc_encoder_enable,
1667         .mode_set = ltdc_encoder_mode_set,
1668 };
1669
1670 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge)
1671 {
1672         struct drm_encoder *encoder;
1673         int ret;
1674
1675         encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
1676         if (!encoder)
1677                 return -ENOMEM;
1678
1679         encoder->possible_crtcs = CRTC_MASK;
1680         encoder->possible_clones = 0;   /* No cloning support */
1681
1682         drm_simple_encoder_init(ddev, encoder, DRM_MODE_ENCODER_DPI);
1683
1684         drm_encoder_helper_add(encoder, &ltdc_encoder_helper_funcs);
1685
1686         ret = drm_bridge_attach(encoder, bridge, NULL, 0);
1687         if (ret) {
1688                 if (ret != -EPROBE_DEFER)
1689                         drm_encoder_cleanup(encoder);
1690                 return ret;
1691         }
1692
1693         DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id);
1694
1695         return 0;
1696 }
1697
1698 static int ltdc_get_caps(struct drm_device *ddev)
1699 {
1700         struct ltdc_device *ldev = ddev->dev_private;
1701         u32 bus_width_log2, lcr, gc2r;
1702
1703         /*
1704          * at least 1 layer must be managed & the number of layers
1705          * must not exceed LTDC_MAX_LAYER
1706          */
1707         regmap_read(ldev->regmap, LTDC_LCR, &lcr);
1708
1709         ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER);
1710
1711         /* set data bus width */
1712         regmap_read(ldev->regmap, LTDC_GC2R, &gc2r);
1713         bus_width_log2 = (gc2r & GC2R_BW) >> 4;
1714         ldev->caps.bus_width = 8 << bus_width_log2;
1715         regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version);
1716
1717         switch (ldev->caps.hw_version) {
1718         case HWVER_10200:
1719         case HWVER_10300:
1720                 ldev->caps.layer_ofs = LAY_OFS_0;
1721                 ldev->caps.layer_regs = ltdc_layer_regs_a0;
1722                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
1723                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0;
1724                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0);
1725                 ldev->caps.pix_fmt_flex = false;
1726                 /*
1727                  * Hw older versions support non-alpha color formats derived
1728                  * from native alpha color formats only on the primary layer.
1729                  * For instance, RG16 native format without alpha works fine
1730                  * on 2nd layer but XR24 (derived color format from AR24)
1731                  * does not work on 2nd layer.
1732                  */
1733                 ldev->caps.non_alpha_only_l1 = true;
1734                 ldev->caps.pad_max_freq_hz = 90000000;
1735                 if (ldev->caps.hw_version == HWVER_10200)
1736                         ldev->caps.pad_max_freq_hz = 65000000;
1737                 ldev->caps.nb_irq = 2;
1738                 ldev->caps.ycbcr_input = false;
1739                 ldev->caps.ycbcr_output = false;
1740                 ldev->caps.plane_reg_shadow = false;
1741                 ldev->caps.crc = false;
1742                 break;
1743         case HWVER_20101:
1744                 ldev->caps.layer_ofs = LAY_OFS_0;
1745                 ldev->caps.layer_regs = ltdc_layer_regs_a1;
1746                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
1747                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1;
1748                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1);
1749                 ldev->caps.pix_fmt_flex = false;
1750                 ldev->caps.non_alpha_only_l1 = false;
1751                 ldev->caps.pad_max_freq_hz = 150000000;
1752                 ldev->caps.nb_irq = 4;
1753                 ldev->caps.ycbcr_input = false;
1754                 ldev->caps.ycbcr_output = false;
1755                 ldev->caps.plane_reg_shadow = false;
1756                 ldev->caps.crc = false;
1757                 break;
1758         case HWVER_40100:
1759                 ldev->caps.layer_ofs = LAY_OFS_1;
1760                 ldev->caps.layer_regs = ltdc_layer_regs_a2;
1761                 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2;
1762                 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2;
1763                 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2);
1764                 ldev->caps.pix_fmt_flex = true;
1765                 ldev->caps.non_alpha_only_l1 = false;
1766                 ldev->caps.pad_max_freq_hz = 90000000;
1767                 ldev->caps.nb_irq = 2;
1768                 ldev->caps.ycbcr_input = true;
1769                 ldev->caps.ycbcr_output = true;
1770                 ldev->caps.plane_reg_shadow = true;
1771                 ldev->caps.crc = true;
1772                 break;
1773         default:
1774                 return -ENODEV;
1775         }
1776
1777         return 0;
1778 }
1779
1780 void ltdc_suspend(struct drm_device *ddev)
1781 {
1782         struct ltdc_device *ldev = ddev->dev_private;
1783
1784         DRM_DEBUG_DRIVER("\n");
1785         clk_disable_unprepare(ldev->pixel_clk);
1786 }
1787
1788 int ltdc_resume(struct drm_device *ddev)
1789 {
1790         struct ltdc_device *ldev = ddev->dev_private;
1791         int ret;
1792
1793         DRM_DEBUG_DRIVER("\n");
1794
1795         ret = clk_prepare_enable(ldev->pixel_clk);
1796         if (ret) {
1797                 DRM_ERROR("failed to enable pixel clock (%d)\n", ret);
1798                 return ret;
1799         }
1800
1801         return 0;
1802 }
1803
1804 int ltdc_load(struct drm_device *ddev)
1805 {
1806         struct platform_device *pdev = to_platform_device(ddev->dev);
1807         struct ltdc_device *ldev = ddev->dev_private;
1808         struct device *dev = ddev->dev;
1809         struct device_node *np = dev->of_node;
1810         struct drm_bridge *bridge;
1811         struct drm_panel *panel;
1812         struct drm_crtc *crtc;
1813         struct reset_control *rstc;
1814         struct resource *res;
1815         int irq, i, nb_endpoints;
1816         int ret = -ENODEV;
1817
1818         DRM_DEBUG_DRIVER("\n");
1819
1820         /* Get number of endpoints */
1821         nb_endpoints = of_graph_get_endpoint_count(np);
1822         if (!nb_endpoints)
1823                 return -ENODEV;
1824
1825         ldev->pixel_clk = devm_clk_get(dev, "lcd");
1826         if (IS_ERR(ldev->pixel_clk)) {
1827                 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER)
1828                         DRM_ERROR("Unable to get lcd clock\n");
1829                 return PTR_ERR(ldev->pixel_clk);
1830         }
1831
1832         if (clk_prepare_enable(ldev->pixel_clk)) {
1833                 DRM_ERROR("Unable to prepare pixel clock\n");
1834                 return -ENODEV;
1835         }
1836
1837         /* Get endpoints if any */
1838         for (i = 0; i < nb_endpoints; i++) {
1839                 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge);
1840
1841                 /*
1842                  * If at least one endpoint is -ENODEV, continue probing,
1843                  * else if at least one endpoint returned an error
1844                  * (ie -EPROBE_DEFER) then stop probing.
1845                  */
1846                 if (ret == -ENODEV)
1847                         continue;
1848                 else if (ret)
1849                         goto err;
1850
1851                 if (panel) {
1852                         bridge = drm_panel_bridge_add_typed(panel,
1853                                                             DRM_MODE_CONNECTOR_DPI);
1854                         if (IS_ERR(bridge)) {
1855                                 DRM_ERROR("panel-bridge endpoint %d\n", i);
1856                                 ret = PTR_ERR(bridge);
1857                                 goto err;
1858                         }
1859                 }
1860
1861                 if (bridge) {
1862                         ret = ltdc_encoder_init(ddev, bridge);
1863                         if (ret) {
1864                                 if (ret != -EPROBE_DEFER)
1865                                         DRM_ERROR("init encoder endpoint %d\n", i);
1866                                 goto err;
1867                         }
1868                 }
1869         }
1870
1871         rstc = devm_reset_control_get_exclusive(dev, NULL);
1872
1873         mutex_init(&ldev->err_lock);
1874
1875         if (!IS_ERR(rstc)) {
1876                 reset_control_assert(rstc);
1877                 usleep_range(10, 20);
1878                 reset_control_deassert(rstc);
1879         }
1880
1881         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1882         ldev->regs = devm_ioremap_resource(dev, res);
1883         if (IS_ERR(ldev->regs)) {
1884                 DRM_ERROR("Unable to get ltdc registers\n");
1885                 ret = PTR_ERR(ldev->regs);
1886                 goto err;
1887         }
1888
1889         ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg);
1890         if (IS_ERR(ldev->regmap)) {
1891                 DRM_ERROR("Unable to regmap ltdc registers\n");
1892                 ret = PTR_ERR(ldev->regmap);
1893                 goto err;
1894         }
1895
1896         /* Disable interrupts */
1897         regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
1898
1899         ret = ltdc_get_caps(ddev);
1900         if (ret) {
1901                 DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
1902                           ldev->caps.hw_version);
1903                 goto err;
1904         }
1905
1906         DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version);
1907
1908         for (i = 0; i < ldev->caps.nb_irq; i++) {
1909                 irq = platform_get_irq(pdev, i);
1910                 if (irq < 0) {
1911                         ret = irq;
1912                         goto err;
1913                 }
1914
1915                 ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
1916                                                 ltdc_irq_thread, IRQF_ONESHOT,
1917                                                 dev_name(dev), ddev);
1918                 if (ret) {
1919                         DRM_ERROR("Failed to register LTDC interrupt\n");
1920                         goto err;
1921                 }
1922
1923         }
1924
1925         crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
1926         if (!crtc) {
1927                 DRM_ERROR("Failed to allocate crtc\n");
1928                 ret = -ENOMEM;
1929                 goto err;
1930         }
1931
1932         ret = ltdc_crtc_init(ddev, crtc);
1933         if (ret) {
1934                 DRM_ERROR("Failed to init crtc\n");
1935                 goto err;
1936         }
1937
1938         ret = drm_vblank_init(ddev, NB_CRTC);
1939         if (ret) {
1940                 DRM_ERROR("Failed calling drm_vblank_init()\n");
1941                 goto err;
1942         }
1943
1944         clk_disable_unprepare(ldev->pixel_clk);
1945
1946         pinctrl_pm_select_sleep_state(ddev->dev);
1947
1948         pm_runtime_enable(ddev->dev);
1949
1950         return 0;
1951 err:
1952         for (i = 0; i < nb_endpoints; i++)
1953                 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1954
1955         clk_disable_unprepare(ldev->pixel_clk);
1956
1957         return ret;
1958 }
1959
1960 void ltdc_unload(struct drm_device *ddev)
1961 {
1962         struct device *dev = ddev->dev;
1963         int nb_endpoints, i;
1964
1965         DRM_DEBUG_DRIVER("\n");
1966
1967         nb_endpoints = of_graph_get_endpoint_count(dev->of_node);
1968
1969         for (i = 0; i < nb_endpoints; i++)
1970                 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i);
1971
1972         pm_runtime_disable(ddev->dev);
1973 }
1974
1975 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
1976 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
1977 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
1978 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
1979 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
1980 MODULE_LICENSE("GPL v2");