drivers/gpu/drm/radeon/radeon_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <glisse@freedesktop.org>
  29  *    Dave Airlie
  30  */
  31
  32 #include <linux/atomic.h>
  33 #include <linux/firmware.h>
  34 #include <linux/kref.h>
  35 #include <linux/sched/signal.h>
  36 #include <linux/seq_file.h>
  37 #include <linux/slab.h>
  38 #include <linux/wait.h>
  39
  40 #include <drm/drm_device.h>
  41 #include <drm/drm_file.h>
  42
  43 #include "radeon.h"
  44 #include "radeon_reg.h"
  45 #include "radeon_trace.h"
  46
  47 /*
  48  * Fences
  49  * Fences mark an event in the GPUs pipeline and are used
  50  * for GPU/CPU synchronization.  When the fence is written,
  51  * it is expected that all buffers associated with that fence
  52  * are no longer in use by the associated ring on the GPU and
  53  * that the relevant GPU caches have been flushed.  Whether
  54  * we use a scratch register or memory location depends on the asic
  55  * and whether writeback is enabled.
  56  */
  57
  58 /**
  59  * radeon_fence_write - write a fence value
  60  *
  61  * @rdev: radeon_device pointer
  62  * @seq: sequence number to write
  63  * @ring: ring index the fence is associated with
  64  *
  65  * Writes a fence value to memory or a scratch register (all asics).
  66  */
  67 static void radeon_fence_write(struct radeon_device *rdev, u32 seq, int ring)
  68 {
  69         struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  70         if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  71                 if (drv->cpu_addr) {
  72                         *drv->cpu_addr = cpu_to_le32(seq);
  73                 }
  74         } else {
  75                 WREG32(drv->scratch_reg, seq);
  76         }
  77 }
  78
  79 /**
  80  * radeon_fence_read - read a fence value
  81  *
  82  * @rdev: radeon_device pointer
  83  * @ring: ring index the fence is associated with
  84  *
  85  * Reads a fence value from memory or a scratch register (all asics).
  86  * Returns the value of the fence read from memory or register.
  87  */
  88 static u32 radeon_fence_read(struct radeon_device *rdev, int ring)
  89 {
  90         struct radeon_fence_driver *drv = &rdev->fence_drv[ring];
  91         u32 seq = 0;
  92
  93         if (likely(rdev->wb.enabled || !drv->scratch_reg)) {
  94                 if (drv->cpu_addr) {
  95                         seq = le32_to_cpu(*drv->cpu_addr);
  96                 } else {
  97                         seq = lower_32_bits(atomic64_read(&drv->last_seq));
  98                 }
  99         } else {
 100                 seq = RREG32(drv->scratch_reg);
 101         }
 102         return seq;
 103 }
 104
 105 /**
 106  * radeon_fence_schedule_check - schedule lockup check
 107  *
 108  * @rdev: radeon_device pointer
 109  * @ring: ring index we should work with
 110  *
 111  * Queues a delayed work item to check for lockups.
 112  */
 113 static void radeon_fence_schedule_check(struct radeon_device *rdev, int ring)
 114 {
 115         /*
 116          * Do not reset the timer here with mod_delayed_work,
 117          * this can livelock in an interaction with TTM delayed destroy.
 118          */
 119         queue_delayed_work(system_power_efficient_wq,
 120                            &rdev->fence_drv[ring].lockup_work,
 121                            RADEON_FENCE_JIFFIES_TIMEOUT);
 122 }
 123
 124 /**
 125  * radeon_fence_emit - emit a fence on the requested ring
 126  *
 127  * @rdev: radeon_device pointer
 128  * @fence: radeon fence object
 129  * @ring: ring index the fence is associated with
 130  *
 131  * Emits a fence command on the requested ring (all asics).
 132  * Returns 0 on success, -ENOMEM on failure.
 133  */
 134 int radeon_fence_emit(struct radeon_device *rdev,
 135                       struct radeon_fence **fence,
 136                       int ring)
 137 {
 138         u64 seq;
 139
 140         /* we are protected by the ring emission mutex */
 141         *fence = kmalloc(sizeof(struct radeon_fence), GFP_KERNEL);
 142         if ((*fence) == NULL) {
 143                 return -ENOMEM;
 144         }
 145         (*fence)->rdev = rdev;
 146         (*fence)->seq = seq = ++rdev->fence_drv[ring].sync_seq[ring];
 147         (*fence)->ring = ring;
 148         (*fence)->is_vm_update = false;
 149         dma_fence_init(&(*fence)->base, &radeon_fence_ops,
 150                        &rdev->fence_queue.lock,
 151                        rdev->fence_context + ring,
 152                        seq);
 153         radeon_fence_ring_emit(rdev, ring, *fence);
 154         trace_radeon_fence_emit(rdev->ddev, ring, (*fence)->seq);
 155         radeon_fence_schedule_check(rdev, ring);
 156         return 0;
 157 }
 158
 159 /*
 160  * radeon_fence_check_signaled - callback from fence_queue
 161  *
 162  * this function is called with fence_queue lock held, which is also used
 163  * for the fence locking itself, so unlocked variants are used for
 164  * fence_signal, and remove_wait_queue.
 165  */
 166 static int radeon_fence_check_signaled(wait_queue_entry_t *wait, unsigned mode, int flags, void *key)
 167 {
 168         struct radeon_fence *fence;
 169         u64 seq;
 170
 171         fence = container_of(wait, struct radeon_fence, fence_wake);
 172
 173         /*
 174          * We cannot use radeon_fence_process here because we're already
 175          * in the waitqueue, in a call from wake_up_all.
 176          */
 177         seq = atomic64_read(&fence->rdev->fence_drv[fence->ring].last_seq);
 178         if (seq >= fence->seq) {
 179                 dma_fence_signal_locked(&fence->base);
 180                 radeon_irq_kms_sw_irq_put(fence->rdev, fence->ring);
 181                 __remove_wait_queue(&fence->rdev->fence_queue, &fence->fence_wake);
 182                 dma_fence_put(&fence->base);
 183         }
 184         return 0;
 185 }
 186
 187 /**
 188  * radeon_fence_activity - check for fence activity
 189  *
 190  * @rdev: radeon_device pointer
 191  * @ring: ring index the fence is associated with
 192  *
 193  * Checks the current fence value and calculates the last
 194  * signalled fence value. Returns true if activity occured
 195  * on the ring, and the fence_queue should be waken up.
 196  */
 197 static bool radeon_fence_activity(struct radeon_device *rdev, int ring)
 198 {
 199         uint64_t seq, last_seq, last_emitted;
 200         unsigned count_loop = 0;
 201         bool wake = false;
 202
 203         /* Note there is a scenario here for an infinite loop but it's
 204          * very unlikely to happen. For it to happen, the current polling
 205          * process need to be interrupted by another process and another
 206          * process needs to update the last_seq btw the atomic read and
 207          * xchg of the current process.
 208          *
 209          * More over for this to go in infinite loop there need to be
 210          * continuously new fence signaled ie radeon_fence_read needs
 211          * to return a different value each time for both the currently
 212          * polling process and the other process that xchg the last_seq
 213          * btw atomic read and xchg of the current process. And the
 214          * value the other process set as last seq must be higher than
 215          * the seq value we just read. Which means that current process
 216          * need to be interrupted after radeon_fence_read and before
 217          * atomic xchg.
 218          *
 219          * To be even more safe we count the number of time we loop and
 220          * we bail after 10 loop just accepting the fact that we might
 221          * have temporarly set the last_seq not to the true real last
 222          * seq but to an older one.
 223          */
 224         last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
 225         do {
 226                 last_emitted = rdev->fence_drv[ring].sync_seq[ring];
 227                 seq = radeon_fence_read(rdev, ring);
 228                 seq |= last_seq & 0xffffffff00000000LL;
 229                 if (seq < last_seq) {
 230                         seq &= 0xffffffff;
 231                         seq |= last_emitted & 0xffffffff00000000LL;
 232                 }
 233
 234                 if (seq <= last_seq || seq > last_emitted) {
 235                         break;
 236                 }
 237                 /* If we loop over we don't want to return without
 238                  * checking if a fence is signaled as it means that the
 239                  * seq we just read is different from the previous on.
 240                  */
 241                 wake = true;
 242                 last_seq = seq;
 243                 if ((count_loop++) > 10) {
 244                         /* We looped over too many time leave with the
 245                          * fact that we might have set an older fence
 246                          * seq then the current real last seq as signaled
 247                          * by the hw.
 248                          */
 249                         break;
 250                 }
 251         } while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
 252
 253         if (seq < last_emitted)
 254                 radeon_fence_schedule_check(rdev, ring);
 255
 256         return wake;
 257 }
 258
 259 /**
 260  * radeon_fence_check_lockup - check for hardware lockup
 261  *
 262  * @work: delayed work item
 263  *
 264  * Checks for fence activity and if there is none probe
 265  * the hardware if a lockup occured.
 266  */
 267 static void radeon_fence_check_lockup(struct work_struct *work)
 268 {
 269         struct radeon_fence_driver *fence_drv;
 270         struct radeon_device *rdev;
 271         int ring;
 272
 273         fence_drv = container_of(work, struct radeon_fence_driver,
 274                                  lockup_work.work);
 275         rdev = fence_drv->rdev;
 276         ring = fence_drv - &rdev->fence_drv[0];
 277
 278         if (!down_read_trylock(&rdev->exclusive_lock)) {
 279                 /* just reschedule the check if a reset is going on */
 280                 radeon_fence_schedule_check(rdev, ring);
 281                 return;
 282         }
 283
 284         if (fence_drv->delayed_irq && rdev->irq.installed) {
 285                 unsigned long irqflags;
 286
 287                 fence_drv->delayed_irq = false;
 288                 spin_lock_irqsave(&rdev->irq.lock, irqflags);
 289                 radeon_irq_set(rdev);
 290                 spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 291         }
 292
 293         if (radeon_fence_activity(rdev, ring))
 294                 wake_up_all(&rdev->fence_queue);
 295
 296         else if (radeon_ring_is_lockup(rdev, ring, &rdev->ring[ring])) {
 297
 298                 /* good news we believe it's a lockup */
 299                 dev_warn(rdev->dev, "GPU lockup (current fence id "
 300                          "0x%016llx last fence id 0x%016llx on ring %d)\n",
 301                          (uint64_t)atomic64_read(&fence_drv->last_seq),
 302                          fence_drv->sync_seq[ring], ring);
 303
 304                 /* remember that we need an reset */
 305                 rdev->needs_reset = true;
 306                 wake_up_all(&rdev->fence_queue);
 307         }
 308         up_read(&rdev->exclusive_lock);
 309 }
 310
 311 /**
 312  * radeon_fence_process - process a fence
 313  *
 314  * @rdev: radeon_device pointer
 315  * @ring: ring index the fence is associated with
 316  *
 317  * Checks the current fence value and wakes the fence queue
 318  * if the sequence number has increased (all asics).
 319  */
 320 void radeon_fence_process(struct radeon_device *rdev, int ring)
 321 {
 322         if (radeon_fence_activity(rdev, ring))
 323                 wake_up_all(&rdev->fence_queue);
 324 }
 325
 326 /**
 327  * radeon_fence_seq_signaled - check if a fence sequence number has signaled
 328  *
 329  * @rdev: radeon device pointer
 330  * @seq: sequence number
 331  * @ring: ring index the fence is associated with
 332  *
 333  * Check if the last signaled fence sequnce number is >= the requested
 334  * sequence number (all asics).
 335  * Returns true if the fence has signaled (current fence value
 336  * is >= requested value) or false if it has not (current fence
 337  * value is < the requested value.  Helper function for
 338  * radeon_fence_signaled().
 339  */
 340 static bool radeon_fence_seq_signaled(struct radeon_device *rdev,
 341                                       u64 seq, unsigned ring)
 342 {
 343         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 344                 return true;
 345         }
 346         /* poll new last sequence at least once */
 347         radeon_fence_process(rdev, ring);
 348         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 349                 return true;
 350         }
 351         return false;
 352 }
 353
 354 static bool radeon_fence_is_signaled(struct dma_fence *f)
 355 {
 356         struct radeon_fence *fence = to_radeon_fence(f);
 357         struct radeon_device *rdev = fence->rdev;
 358         unsigned ring = fence->ring;
 359         u64 seq = fence->seq;
 360
 361         if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 362                 return true;
 363         }
 364
 365         if (down_read_trylock(&rdev->exclusive_lock)) {
 366                 radeon_fence_process(rdev, ring);
 367                 up_read(&rdev->exclusive_lock);
 368
 369                 if (atomic64_read(&rdev->fence_drv[ring].last_seq) >= seq) {
 370                         return true;
 371                 }
 372         }
 373         return false;
 374 }
 375
 376 /**
 377  * radeon_fence_enable_signaling - enable signalling on fence
 378  * @f: fence
 379  *
 380  * This function is called with fence_queue lock held, and adds a callback
 381  * to fence_queue that checks if this fence is signaled, and if so it
 382  * signals the fence and removes itself.
 383  */
 384 static bool radeon_fence_enable_signaling(struct dma_fence *f)
 385 {
 386         struct radeon_fence *fence = to_radeon_fence(f);
 387         struct radeon_device *rdev = fence->rdev;
 388
 389         if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq)
 390                 return false;
 391
 392         if (down_read_trylock(&rdev->exclusive_lock)) {
 393                 radeon_irq_kms_sw_irq_get(rdev, fence->ring);
 394
 395                 if (radeon_fence_activity(rdev, fence->ring))
 396                         wake_up_all_locked(&rdev->fence_queue);
 397
 398                 /* did fence get signaled after we enabled the sw irq? */
 399                 if (atomic64_read(&rdev->fence_drv[fence->ring].last_seq) >= fence->seq) {
 400                         radeon_irq_kms_sw_irq_put(rdev, fence->ring);
 401                         up_read(&rdev->exclusive_lock);
 402                         return false;
 403                 }
 404
 405                 up_read(&rdev->exclusive_lock);
 406         } else {
 407                 /* we're probably in a lockup, lets not fiddle too much */
 408                 if (radeon_irq_kms_sw_irq_get_delayed(rdev, fence->ring))
 409                         rdev->fence_drv[fence->ring].delayed_irq = true;
 410                 radeon_fence_schedule_check(rdev, fence->ring);
 411         }
 412
 413         fence->fence_wake.flags = 0;
 414         fence->fence_wake.private = NULL;
 415         fence->fence_wake.func = radeon_fence_check_signaled;
 416         __add_wait_queue(&rdev->fence_queue, &fence->fence_wake);
 417         dma_fence_get(f);
 418         return true;
 419 }
 420
 421 /**
 422  * radeon_fence_signaled - check if a fence has signaled
 423  *
 424  * @fence: radeon fence object
 425  *
 426  * Check if the requested fence has signaled (all asics).
 427  * Returns true if the fence has signaled or false if it has not.
 428  */
 429 bool radeon_fence_signaled(struct radeon_fence *fence)
 430 {
 431         if (!fence)
 432                 return true;
 433
 434         if (radeon_fence_seq_signaled(fence->rdev, fence->seq, fence->ring)) {
 435                 dma_fence_signal(&fence->base);
 436                 return true;
 437         }
 438         return false;
 439 }
 440
 441 /**
 442  * radeon_fence_any_seq_signaled - check if any sequence number is signaled
 443  *
 444  * @rdev: radeon device pointer
 445  * @seq: sequence numbers
 446  *
 447  * Check if the last signaled fence sequnce number is >= the requested
 448  * sequence number (all asics).
 449  * Returns true if any has signaled (current value is >= requested value)
 450  * or false if it has not. Helper function for radeon_fence_wait_seq.
 451  */
 452 static bool radeon_fence_any_seq_signaled(struct radeon_device *rdev, u64 *seq)
 453 {
 454         unsigned i;
 455
 456         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 457                 if (seq[i] && radeon_fence_seq_signaled(rdev, seq[i], i))
 458                         return true;
 459         }
 460         return false;
 461 }
 462
 463 /**
 464  * radeon_fence_wait_seq_timeout - wait for a specific sequence numbers
 465  *
 466  * @rdev: radeon device pointer
 467  * @target_seq: sequence number(s) we want to wait for
 468  * @intr: use interruptable sleep
 469  * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
 470  *
 471  * Wait for the requested sequence number(s) to be written by any ring
 472  * (all asics).  Sequnce number array is indexed by ring id.
 473  * @intr selects whether to use interruptable (true) or non-interruptable
 474  * (false) sleep when waiting for the sequence number.  Helper function
 475  * for radeon_fence_wait_*().
 476  * Returns remaining time if the sequence number has passed, 0 when
 477  * the wait timeout, or an error for all other cases.
 478  * -EDEADLK is returned when a GPU lockup has been detected.
 479  */
 480 static long radeon_fence_wait_seq_timeout(struct radeon_device *rdev,
 481                                           u64 *target_seq, bool intr,
 482                                           long timeout)
 483 {
 484         long r;
 485         int i;
 486
 487         if (radeon_fence_any_seq_signaled(rdev, target_seq))
 488                 return timeout;
 489
 490         /* enable IRQs and tracing */
 491         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 492                 if (!target_seq[i])
 493                         continue;
 494
 495                 trace_radeon_fence_wait_begin(rdev->ddev, i, target_seq[i]);
 496                 radeon_irq_kms_sw_irq_get(rdev, i);
 497         }
 498
 499         if (intr) {
 500                 r = wait_event_interruptible_timeout(rdev->fence_queue, (
 501                         radeon_fence_any_seq_signaled(rdev, target_seq)
 502                          || rdev->needs_reset), timeout);
 503         } else {
 504                 r = wait_event_timeout(rdev->fence_queue, (
 505                         radeon_fence_any_seq_signaled(rdev, target_seq)
 506                          || rdev->needs_reset), timeout);
 507         }
 508
 509         if (rdev->needs_reset)
 510                 r = -EDEADLK;
 511
 512         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 513                 if (!target_seq[i])
 514                         continue;
 515
 516                 radeon_irq_kms_sw_irq_put(rdev, i);
 517                 trace_radeon_fence_wait_end(rdev->ddev, i, target_seq[i]);
 518         }
 519
 520         return r;
 521 }
 522
 523 /**
 524  * radeon_fence_wait_timeout - wait for a fence to signal with timeout
 525  *
 526  * @fence: radeon fence object
 527  * @intr: use interruptible sleep
 528  *
 529  * Wait for the requested fence to signal (all asics).
 530  * @intr selects whether to use interruptable (true) or non-interruptable
 531  * (false) sleep when waiting for the fence.
 532  * @timeout: maximum time to wait, or MAX_SCHEDULE_TIMEOUT for infinite wait
 533  * Returns remaining time if the sequence number has passed, 0 when
 534  * the wait timeout, or an error for all other cases.
 535  */
 536 long radeon_fence_wait_timeout(struct radeon_fence *fence, bool intr, long timeout)
 537 {
 538         uint64_t seq[RADEON_NUM_RINGS] = {};
 539         long r;
 540
 541         /*
 542          * This function should not be called on !radeon fences.
 543          * If this is the case, it would mean this function can
 544          * also be called on radeon fences belonging to another card.
 545          * exclusive_lock is not held in that case.
 546          */
 547         if (WARN_ON_ONCE(!to_radeon_fence(&fence->base)))
 548                 return dma_fence_wait(&fence->base, intr);
 549
 550         seq[fence->ring] = fence->seq;
 551         r = radeon_fence_wait_seq_timeout(fence->rdev, seq, intr, timeout);
 552         if (r <= 0) {
 553                 return r;
 554         }
 555
 556         dma_fence_signal(&fence->base);
 557         return r;
 558 }
 559
 560 /**
 561  * radeon_fence_wait - wait for a fence to signal
 562  *
 563  * @fence: radeon fence object
 564  * @intr: use interruptible sleep
 565  *
 566  * Wait for the requested fence to signal (all asics).
 567  * @intr selects whether to use interruptable (true) or non-interruptable
 568  * (false) sleep when waiting for the fence.
 569  * Returns 0 if the fence has passed, error for all other cases.
 570  */
 571 int radeon_fence_wait(struct radeon_fence *fence, bool intr)
 572 {
 573         long r = radeon_fence_wait_timeout(fence, intr, MAX_SCHEDULE_TIMEOUT);
 574         if (r > 0) {
 575                 return 0;
 576         } else {
 577                 return r;
 578         }
 579 }
 580
 581 /**
 582  * radeon_fence_wait_any - wait for a fence to signal on any ring
 583  *
 584  * @rdev: radeon device pointer
 585  * @fences: radeon fence object(s)
 586  * @intr: use interruptable sleep
 587  *
 588  * Wait for any requested fence to signal (all asics).  Fence
 589  * array is indexed by ring id.  @intr selects whether to use
 590  * interruptable (true) or non-interruptable (false) sleep when
 591  * waiting for the fences. Used by the suballocator.
 592  * Returns 0 if any fence has passed, error for all other cases.
 593  */
 594 int radeon_fence_wait_any(struct radeon_device *rdev,
 595                           struct radeon_fence **fences,
 596                           bool intr)
 597 {
 598         uint64_t seq[RADEON_NUM_RINGS];
 599         unsigned i, num_rings = 0;
 600         long r;
 601
 602         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 603                 seq[i] = 0;
 604
 605                 if (!fences[i]) {
 606                         continue;
 607                 }
 608
 609                 seq[i] = fences[i]->seq;
 610                 ++num_rings;
 611         }
 612
 613         /* nothing to wait for ? */
 614         if (num_rings == 0)
 615                 return -ENOENT;
 616
 617         r = radeon_fence_wait_seq_timeout(rdev, seq, intr, MAX_SCHEDULE_TIMEOUT);
 618         if (r < 0) {
 619                 return r;
 620         }
 621         return 0;
 622 }
 623
 624 /**
 625  * radeon_fence_wait_next - wait for the next fence to signal
 626  *
 627  * @rdev: radeon device pointer
 628  * @ring: ring index the fence is associated with
 629  *
 630  * Wait for the next fence on the requested ring to signal (all asics).
 631  * Returns 0 if the next fence has passed, error for all other cases.
 632  * Caller must hold ring lock.
 633  */
 634 int radeon_fence_wait_next(struct radeon_device *rdev, int ring)
 635 {
 636         uint64_t seq[RADEON_NUM_RINGS] = {};
 637         long r;
 638
 639         seq[ring] = atomic64_read(&rdev->fence_drv[ring].last_seq) + 1ULL;
 640         if (seq[ring] >= rdev->fence_drv[ring].sync_seq[ring]) {
 641                 /* nothing to wait for, last_seq is
 642                    already the last emited fence */
 643                 return -ENOENT;
 644         }
 645         r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
 646         if (r < 0)
 647                 return r;
 648         return 0;
 649 }
 650
 651 /**
 652  * radeon_fence_wait_empty - wait for all fences to signal
 653  *
 654  * @rdev: radeon device pointer
 655  * @ring: ring index the fence is associated with
 656  *
 657  * Wait for all fences on the requested ring to signal (all asics).
 658  * Returns 0 if the fences have passed, error for all other cases.
 659  * Caller must hold ring lock.
 660  */
 661 int radeon_fence_wait_empty(struct radeon_device *rdev, int ring)
 662 {
 663         uint64_t seq[RADEON_NUM_RINGS] = {};
 664         long r;
 665
 666         seq[ring] = rdev->fence_drv[ring].sync_seq[ring];
 667         if (!seq[ring])
 668                 return 0;
 669
 670         r = radeon_fence_wait_seq_timeout(rdev, seq, false, MAX_SCHEDULE_TIMEOUT);
 671         if (r < 0) {
 672                 if (r == -EDEADLK)
 673                         return -EDEADLK;
 674
 675                 dev_err(rdev->dev, "error waiting for ring[%d] to become idle (%ld)\n",
 676                         ring, r);
 677         }
 678         return 0;
 679 }
 680
 681 /**
 682  * radeon_fence_ref - take a ref on a fence
 683  *
 684  * @fence: radeon fence object
 685  *
 686  * Take a reference on a fence (all asics).
 687  * Returns the fence.
 688  */
 689 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence)
 690 {
 691         dma_fence_get(&fence->base);
 692         return fence;
 693 }
 694
 695 /**
 696  * radeon_fence_unref - remove a ref on a fence
 697  *
 698  * @fence: radeon fence object
 699  *
 700  * Remove a reference on a fence (all asics).
 701  */
 702 void radeon_fence_unref(struct radeon_fence **fence)
 703 {
 704         struct radeon_fence *tmp = *fence;
 705
 706         *fence = NULL;
 707         if (tmp) {
 708                 dma_fence_put(&tmp->base);
 709         }
 710 }
 711
 712 /**
 713  * radeon_fence_count_emitted - get the count of emitted fences
 714  *
 715  * @rdev: radeon device pointer
 716  * @ring: ring index the fence is associated with
 717  *
 718  * Get the number of fences emitted on the requested ring (all asics).
 719  * Returns the number of emitted fences on the ring.  Used by the
 720  * dynpm code to ring track activity.
 721  */
 722 unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring)
 723 {
 724         uint64_t emitted;
 725
 726         /* We are not protected by ring lock when reading the last sequence
 727          * but it's ok to report slightly wrong fence count here.
 728          */
 729         radeon_fence_process(rdev, ring);
 730         emitted = rdev->fence_drv[ring].sync_seq[ring]
 731                 - atomic64_read(&rdev->fence_drv[ring].last_seq);
 732         /* to avoid 32bits warp around */
 733         if (emitted > 0x10000000) {
 734                 emitted = 0x10000000;
 735         }
 736         return (unsigned)emitted;
 737 }
 738
 739 /**
 740  * radeon_fence_need_sync - do we need a semaphore
 741  *
 742  * @fence: radeon fence object
 743  * @dst_ring: which ring to check against
 744  *
 745  * Check if the fence needs to be synced against another ring
 746  * (all asics).  If so, we need to emit a semaphore.
 747  * Returns true if we need to sync with another ring, false if
 748  * not.
 749  */
 750 bool radeon_fence_need_sync(struct radeon_fence *fence, int dst_ring)
 751 {
 752         struct radeon_fence_driver *fdrv;
 753
 754         if (!fence) {
 755                 return false;
 756         }
 757
 758         if (fence->ring == dst_ring) {
 759                 return false;
 760         }
 761
 762         /* we are protected by the ring mutex */
 763         fdrv = &fence->rdev->fence_drv[dst_ring];
 764         if (fence->seq <= fdrv->sync_seq[fence->ring]) {
 765                 return false;
 766         }
 767
 768         return true;
 769 }
 770
 771 /**
 772  * radeon_fence_note_sync - record the sync point
 773  *
 774  * @fence: radeon fence object
 775  * @dst_ring: which ring to check against
 776  *
 777  * Note the sequence number at which point the fence will
 778  * be synced with the requested ring (all asics).
 779  */
 780 void radeon_fence_note_sync(struct radeon_fence *fence, int dst_ring)
 781 {
 782         struct radeon_fence_driver *dst, *src;
 783         unsigned i;
 784
 785         if (!fence) {
 786                 return;
 787         }
 788
 789         if (fence->ring == dst_ring) {
 790                 return;
 791         }
 792
 793         /* we are protected by the ring mutex */
 794         src = &fence->rdev->fence_drv[fence->ring];
 795         dst = &fence->rdev->fence_drv[dst_ring];
 796         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 797                 if (i == dst_ring) {
 798                         continue;
 799                 }
 800                 dst->sync_seq[i] = max(dst->sync_seq[i], src->sync_seq[i]);
 801         }
 802 }
 803
 804 /**
 805  * radeon_fence_driver_start_ring - make the fence driver
 806  * ready for use on the requested ring.
 807  *
 808  * @rdev: radeon device pointer
 809  * @ring: ring index to start the fence driver on
 810  *
 811  * Make the fence driver ready for processing (all asics).
 812  * Not all asics have all rings, so each asic will only
 813  * start the fence driver on the rings it has.
 814  * Returns 0 for success, errors for failure.
 815  */
 816 int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
 817 {
 818         uint64_t index;
 819         int r;
 820
 821         radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 822         if (rdev->wb.use_event || !radeon_ring_supports_scratch_reg(rdev, &rdev->ring[ring])) {
 823                 rdev->fence_drv[ring].scratch_reg = 0;
 824                 if (ring != R600_RING_TYPE_UVD_INDEX) {
 825                         index = R600_WB_EVENT_OFFSET + ring * 4;
 826                         rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 827                         rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr +
 828                                                          index;
 829
 830                 } else {
 831                         /* put fence directly behind firmware */
 832                         index = ALIGN(rdev->uvd_fw->size, 8);
 833                         rdev->fence_drv[ring].cpu_addr = rdev->uvd.cpu_addr + index;
 834                         rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index;
 835                 }
 836
 837         } else {
 838                 r = radeon_scratch_get(rdev, &rdev->fence_drv[ring].scratch_reg);
 839                 if (r) {
 840                         dev_err(rdev->dev, "fence failed to get scratch register\n");
 841                         return r;
 842                 }
 843                 index = RADEON_WB_SCRATCH_OFFSET +
 844                         rdev->fence_drv[ring].scratch_reg -
 845                         rdev->scratch.reg_base;
 846                 rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
 847                 rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
 848         }
 849         radeon_fence_write(rdev, atomic64_read(&rdev->fence_drv[ring].last_seq), ring);
 850         rdev->fence_drv[ring].initialized = true;
 851         dev_info(rdev->dev, "fence driver on ring %d use gpu addr 0x%016llx\n",
 852                  ring, rdev->fence_drv[ring].gpu_addr);
 853         return 0;
 854 }
 855
 856 /**
 857  * radeon_fence_driver_init_ring - init the fence driver
 858  * for the requested ring.
 859  *
 860  * @rdev: radeon device pointer
 861  * @ring: ring index to start the fence driver on
 862  *
 863  * Init the fence driver for the requested ring (all asics).
 864  * Helper function for radeon_fence_driver_init().
 865  */
 866 static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
 867 {
 868         int i;
 869
 870         rdev->fence_drv[ring].scratch_reg = -1;
 871         rdev->fence_drv[ring].cpu_addr = NULL;
 872         rdev->fence_drv[ring].gpu_addr = 0;
 873         for (i = 0; i < RADEON_NUM_RINGS; ++i)
 874                 rdev->fence_drv[ring].sync_seq[i] = 0;
 875         atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
 876         rdev->fence_drv[ring].initialized = false;
 877         INIT_DELAYED_WORK(&rdev->fence_drv[ring].lockup_work,
 878                           radeon_fence_check_lockup);
 879         rdev->fence_drv[ring].rdev = rdev;
 880 }
 881
 882 /**
 883  * radeon_fence_driver_init - init the fence driver
 884  * for all possible rings.
 885  *
 886  * @rdev: radeon device pointer
 887  *
 888  * Init the fence driver for all possible rings (all asics).
 889  * Not all asics have all rings, so each asic will only
 890  * start the fence driver on the rings it has using
 891  * radeon_fence_driver_start_ring().
 892  */
 893 void radeon_fence_driver_init(struct radeon_device *rdev)
 894 {
 895         int ring;
 896
 897         init_waitqueue_head(&rdev->fence_queue);
 898         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 899                 radeon_fence_driver_init_ring(rdev, ring);
 900         }
 901
 902         radeon_debugfs_fence_init(rdev);
 903 }
 904
 905 /**
 906  * radeon_fence_driver_fini - tear down the fence driver
 907  * for all possible rings.
 908  *
 909  * @rdev: radeon device pointer
 910  *
 911  * Tear down the fence driver for all possible rings (all asics).
 912  */
 913 void radeon_fence_driver_fini(struct radeon_device *rdev)
 914 {
 915         int ring, r;
 916
 917         mutex_lock(&rdev->ring_lock);
 918         for (ring = 0; ring < RADEON_NUM_RINGS; ring++) {
 919                 if (!rdev->fence_drv[ring].initialized)
 920                         continue;
 921                 r = radeon_fence_wait_empty(rdev, ring);
 922                 if (r) {
 923                         /* no need to trigger GPU reset as we are unloading */
 924                         radeon_fence_driver_force_completion(rdev, ring);
 925                 }
 926                 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
 927                 wake_up_all(&rdev->fence_queue);
 928                 radeon_scratch_free(rdev, rdev->fence_drv[ring].scratch_reg);
 929                 rdev->fence_drv[ring].initialized = false;
 930         }
 931         mutex_unlock(&rdev->ring_lock);
 932 }
 933
 934 /**
 935  * radeon_fence_driver_force_completion - force all fence waiter to complete
 936  *
 937  * @rdev: radeon device pointer
 938  * @ring: the ring to complete
 939  *
 940  * In case of GPU reset failure make sure no process keep waiting on fence
 941  * that will never complete.
 942  */
 943 void radeon_fence_driver_force_completion(struct radeon_device *rdev, int ring)
 944 {
 945         if (rdev->fence_drv[ring].initialized) {
 946                 radeon_fence_write(rdev, rdev->fence_drv[ring].sync_seq[ring], ring);
 947                 cancel_delayed_work_sync(&rdev->fence_drv[ring].lockup_work);
 948         }
 949 }
 950
 951
 952 /*
 953  * Fence debugfs
 954  */
 955 #if defined(CONFIG_DEBUG_FS)
 956 static int radeon_debugfs_fence_info_show(struct seq_file *m, void *data)
 957 {
 958         struct radeon_device *rdev = m->private;
 959         int i, j;
 960
 961         for (i = 0; i < RADEON_NUM_RINGS; ++i) {
 962                 if (!rdev->fence_drv[i].initialized)
 963                         continue;
 964
 965                 radeon_fence_process(rdev, i);
 966
 967                 seq_printf(m, "--- ring %d ---\n", i);
 968                 seq_printf(m, "Last signaled fence 0x%016llx\n",
 969                            (unsigned long long)atomic64_read(&rdev->fence_drv[i].last_seq));
 970                 seq_printf(m, "Last emitted        0x%016llx\n",
 971                            rdev->fence_drv[i].sync_seq[i]);
 972
 973                 for (j = 0; j < RADEON_NUM_RINGS; ++j) {
 974                         if (i != j && rdev->fence_drv[j].initialized)
 975                                 seq_printf(m, "Last sync to ring %d 0x%016llx\n",
 976                                            j, rdev->fence_drv[i].sync_seq[j]);
 977                 }
 978         }
 979         return 0;
 980 }
 981
 982 /*
 983  * radeon_debugfs_gpu_reset - manually trigger a gpu reset
 984  *
 985  * Manually trigger a gpu reset at the next fence wait.
 986  */
 987 static int radeon_debugfs_gpu_reset(void *data, u64 *val)
 988 {
 989         struct radeon_device *rdev = (struct radeon_device *)data;
 990
 991         down_read(&rdev->exclusive_lock);
 992         *val = rdev->needs_reset;
 993         rdev->needs_reset = true;
 994         wake_up_all(&rdev->fence_queue);
 995         up_read(&rdev->exclusive_lock);
 996
 997         return 0;
 998 }
 999 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_fence_info);
1000 DEFINE_DEBUGFS_ATTRIBUTE(radeon_debugfs_gpu_reset_fops,
1001                          radeon_debugfs_gpu_reset, NULL, "%lld\n");
1002 #endif
1003
1004 void radeon_debugfs_fence_init(struct radeon_device *rdev)
1005 {
1006 #if defined(CONFIG_DEBUG_FS)
1007         struct dentry *root = rdev->ddev->primary->debugfs_root;
1008
1009         debugfs_create_file("radeon_gpu_reset", 0444, root, rdev,
1010                             &radeon_debugfs_gpu_reset_fops);
1011         debugfs_create_file("radeon_fence_info", 0444, root, rdev,
1012                             &radeon_debugfs_fence_info_fops);
1013
1014
1015 #endif
1016 }
1017
1018 static const char *radeon_fence_get_driver_name(struct dma_fence *fence)
1019 {
1020         return "radeon";
1021 }
1022
1023 static const char *radeon_fence_get_timeline_name(struct dma_fence *f)
1024 {
1025         struct radeon_fence *fence = to_radeon_fence(f);
1026         switch (fence->ring) {
1027         case RADEON_RING_TYPE_GFX_INDEX: return "radeon.gfx";
1028         case CAYMAN_RING_TYPE_CP1_INDEX: return "radeon.cp1";
1029         case CAYMAN_RING_TYPE_CP2_INDEX: return "radeon.cp2";
1030         case R600_RING_TYPE_DMA_INDEX: return "radeon.dma";
1031         case CAYMAN_RING_TYPE_DMA1_INDEX: return "radeon.dma1";
1032         case R600_RING_TYPE_UVD_INDEX: return "radeon.uvd";
1033         case TN_RING_TYPE_VCE1_INDEX: return "radeon.vce1";
1034         case TN_RING_TYPE_VCE2_INDEX: return "radeon.vce2";
1035         default: WARN_ON_ONCE(1); return "radeon.unk";
1036         }
1037 }
1038
1039 static inline bool radeon_test_signaled(struct radeon_fence *fence)
1040 {
1041         return test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->base.flags);
1042 }
1043
1044 struct radeon_wait_cb {
1045         struct dma_fence_cb base;
1046         struct task_struct *task;
1047 };
1048
1049 static void
1050 radeon_fence_wait_cb(struct dma_fence *fence, struct dma_fence_cb *cb)
1051 {
1052         struct radeon_wait_cb *wait =
1053                 container_of(cb, struct radeon_wait_cb, base);
1054
1055         wake_up_process(wait->task);
1056 }
1057
1058 static signed long radeon_fence_default_wait(struct dma_fence *f, bool intr,
1059                                              signed long t)
1060 {
1061         struct radeon_fence *fence = to_radeon_fence(f);
1062         struct radeon_device *rdev = fence->rdev;
1063         struct radeon_wait_cb cb;
1064
1065         cb.task = current;
1066
1067         if (dma_fence_add_callback(f, &cb.base, radeon_fence_wait_cb))
1068                 return t;
1069
1070         while (t > 0) {
1071                 if (intr)
1072                         set_current_state(TASK_INTERRUPTIBLE);
1073                 else
1074                         set_current_state(TASK_UNINTERRUPTIBLE);
1075
1076                 /*
1077                  * radeon_test_signaled must be called after
1078                  * set_current_state to prevent a race with wake_up_process
1079                  */
1080                 if (radeon_test_signaled(fence))
1081                         break;
1082
1083                 if (rdev->needs_reset) {
1084                         t = -EDEADLK;
1085                         break;
1086                 }
1087
1088                 t = schedule_timeout(t);
1089
1090                 if (t > 0 && intr && signal_pending(current))
1091                         t = -ERESTARTSYS;
1092         }
1093
1094         __set_current_state(TASK_RUNNING);
1095         dma_fence_remove_callback(f, &cb.base);
1096
1097         return t;
1098 }
1099
1100 const struct dma_fence_ops radeon_fence_ops = {
1101         .get_driver_name = radeon_fence_get_driver_name,
1102         .get_timeline_name = radeon_fence_get_timeline_name,
1103         .enable_signaling = radeon_fence_enable_signaling,
1104         .signaled = radeon_fence_is_signaled,
1105         .wait = radeon_fence_default_wait,
1106         .release = NULL,
1107 };