91a34dd835d7b3d849e2aab0b1342817b4825602
[sfrench/cifs-2.6.git] / drivers / gpu / drm / qxl / qxl_kms.c
1 /*
2  * Copyright 2013 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Dave Airlie
23  *          Alon Levy
24  */
25
26 #include <linux/io-mapping.h>
27 #include <linux/pci.h>
28
29 #include <drm/drm_drv.h>
30 #include <drm/drm_managed.h>
31 #include <drm/drm_probe_helper.h>
32
33 #include "qxl_drv.h"
34 #include "qxl_object.h"
35
36 int qxl_log_level;
37
38 static bool qxl_check_device(struct qxl_device *qdev)
39 {
40         struct qxl_rom *rom = qdev->rom;
41
42         if (rom->magic != 0x4f525851) {
43                 DRM_ERROR("bad rom signature %x\n", rom->magic);
44                 return false;
45         }
46
47         DRM_INFO("Device Version %d.%d\n", rom->id, rom->update_id);
48         DRM_INFO("Compression level %d log level %d\n", rom->compression_level,
49                  rom->log_level);
50         DRM_INFO("%d io pages at offset 0x%x\n",
51                  rom->num_io_pages, rom->pages_offset);
52         DRM_INFO("%d byte draw area at offset 0x%x\n",
53                  rom->surface0_area_size, rom->draw_area_offset);
54
55         qdev->vram_size = rom->surface0_area_size;
56         DRM_INFO("RAM header offset: 0x%x\n", rom->ram_header_offset);
57         return true;
58 }
59
60 static void setup_hw_slot(struct qxl_device *qdev, struct qxl_memslot *slot)
61 {
62         qdev->ram_header->mem_slot.mem_start = slot->start_phys_addr;
63         qdev->ram_header->mem_slot.mem_end = slot->start_phys_addr + slot->size;
64         qxl_io_memslot_add(qdev, qdev->rom->slots_start + slot->index);
65 }
66
67 static void setup_slot(struct qxl_device *qdev,
68                        struct qxl_memslot *slot,
69                        unsigned int slot_index,
70                        const char *slot_name,
71                        unsigned long start_phys_addr,
72                        unsigned long size)
73 {
74         uint64_t high_bits;
75
76         slot->index = slot_index;
77         slot->name = slot_name;
78         slot->start_phys_addr = start_phys_addr;
79         slot->size = size;
80
81         setup_hw_slot(qdev, slot);
82
83         slot->generation = qdev->rom->slot_generation;
84         high_bits = (qdev->rom->slots_start + slot->index)
85                 << qdev->rom->slot_gen_bits;
86         high_bits |= slot->generation;
87         high_bits <<= (64 - (qdev->rom->slot_gen_bits + qdev->rom->slot_id_bits));
88         slot->high_bits = high_bits;
89
90         DRM_INFO("slot %d (%s): base 0x%08lx, size 0x%08lx, gpu_offset 0x%lx\n",
91                  slot->index, slot->name,
92                  (unsigned long)slot->start_phys_addr,
93                  (unsigned long)slot->size,
94                  (unsigned long)slot->gpu_offset);
95 }
96
97 void qxl_reinit_memslots(struct qxl_device *qdev)
98 {
99         setup_hw_slot(qdev, &qdev->main_slot);
100         setup_hw_slot(qdev, &qdev->surfaces_slot);
101 }
102
103 static void qxl_gc_work(struct work_struct *work)
104 {
105         struct qxl_device *qdev = container_of(work, struct qxl_device, gc_work);
106
107         qxl_garbage_collect(qdev);
108 }
109
110 int qxl_device_init(struct qxl_device *qdev,
111                     struct pci_dev *pdev)
112 {
113         int r, sb;
114
115         qdev->ddev.pdev = pdev;
116         pci_set_drvdata(pdev, &qdev->ddev);
117         qdev->ddev.dev_private = qdev;
118
119         mutex_init(&qdev->gem.mutex);
120         mutex_init(&qdev->update_area_mutex);
121         mutex_init(&qdev->release_mutex);
122         mutex_init(&qdev->surf_evict_mutex);
123         qxl_gem_init(qdev);
124
125         qdev->rom_base = pci_resource_start(pdev, 2);
126         qdev->rom_size = pci_resource_len(pdev, 2);
127         qdev->vram_base = pci_resource_start(pdev, 0);
128         qdev->io_base = pci_resource_start(pdev, 3);
129
130         qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));
131         if (!qdev->vram_mapping) {
132                 pr_err("Unable to create vram_mapping");
133                 return -ENOMEM;
134         }
135
136         if (pci_resource_len(pdev, 4) > 0) {
137                 /* 64bit surface bar present */
138                 sb = 4;
139                 qdev->surfaceram_base = pci_resource_start(pdev, sb);
140                 qdev->surfaceram_size = pci_resource_len(pdev, sb);
141                 qdev->surface_mapping =
142                         io_mapping_create_wc(qdev->surfaceram_base,
143                                              qdev->surfaceram_size);
144         }
145         if (qdev->surface_mapping == NULL) {
146                 /* 64bit surface bar not present (or mapping failed) */
147                 sb = 1;
148                 qdev->surfaceram_base = pci_resource_start(pdev, sb);
149                 qdev->surfaceram_size = pci_resource_len(pdev, sb);
150                 qdev->surface_mapping =
151                         io_mapping_create_wc(qdev->surfaceram_base,
152                                              qdev->surfaceram_size);
153                 if (!qdev->surface_mapping) {
154                         pr_err("Unable to create surface_mapping");
155                         r = -ENOMEM;
156                         goto vram_mapping_free;
157                 }
158         }
159
160         DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk, %s)\n",
161                  (unsigned long long)qdev->vram_base,
162                  (unsigned long long)pci_resource_end(pdev, 0),
163                  (int)pci_resource_len(pdev, 0) / 1024 / 1024,
164                  (int)pci_resource_len(pdev, 0) / 1024,
165                  (unsigned long long)qdev->surfaceram_base,
166                  (unsigned long long)pci_resource_end(pdev, sb),
167                  (int)qdev->surfaceram_size / 1024 / 1024,
168                  (int)qdev->surfaceram_size / 1024,
169                  (sb == 4) ? "64bit" : "32bit");
170
171         qdev->rom = ioremap(qdev->rom_base, qdev->rom_size);
172         if (!qdev->rom) {
173                 pr_err("Unable to ioremap ROM\n");
174                 r = -ENOMEM;
175                 goto surface_mapping_free;
176         }
177
178         if (!qxl_check_device(qdev)) {
179                 r = -ENODEV;
180                 goto rom_unmap;
181         }
182
183         r = qxl_bo_init(qdev);
184         if (r) {
185                 DRM_ERROR("bo init failed %d\n", r);
186                 goto rom_unmap;
187         }
188
189         qdev->ram_header = ioremap(qdev->vram_base +
190                                    qdev->rom->ram_header_offset,
191                                    sizeof(*qdev->ram_header));
192         if (!qdev->ram_header) {
193                 DRM_ERROR("Unable to ioremap RAM header\n");
194                 r = -ENOMEM;
195                 goto bo_fini;
196         }
197
198         qdev->command_ring = qxl_ring_create(&(qdev->ram_header->cmd_ring_hdr),
199                                              sizeof(struct qxl_command),
200                                              QXL_COMMAND_RING_SIZE,
201                                              qdev->io_base + QXL_IO_NOTIFY_CMD,
202                                              false,
203                                              &qdev->display_event);
204         if (!qdev->command_ring) {
205                 DRM_ERROR("Unable to create command ring\n");
206                 r = -ENOMEM;
207                 goto ram_header_unmap;
208         }
209
210         qdev->cursor_ring = qxl_ring_create(
211                                 &(qdev->ram_header->cursor_ring_hdr),
212                                 sizeof(struct qxl_command),
213                                 QXL_CURSOR_RING_SIZE,
214                                 qdev->io_base + QXL_IO_NOTIFY_CURSOR,
215                                 false,
216                                 &qdev->cursor_event);
217
218         if (!qdev->cursor_ring) {
219                 DRM_ERROR("Unable to create cursor ring\n");
220                 r = -ENOMEM;
221                 goto command_ring_free;
222         }
223
224         qdev->release_ring = qxl_ring_create(
225                                 &(qdev->ram_header->release_ring_hdr),
226                                 sizeof(uint64_t),
227                                 QXL_RELEASE_RING_SIZE, 0, true,
228                                 NULL);
229
230         if (!qdev->release_ring) {
231                 DRM_ERROR("Unable to create release ring\n");
232                 r = -ENOMEM;
233                 goto cursor_ring_free;
234         }
235
236         idr_init(&qdev->release_idr);
237         spin_lock_init(&qdev->release_idr_lock);
238         spin_lock_init(&qdev->release_lock);
239
240         idr_init(&qdev->surf_id_idr);
241         spin_lock_init(&qdev->surf_id_idr_lock);
242
243         mutex_init(&qdev->async_io_mutex);
244
245         /* reset the device into a known state - no memslots, no primary
246          * created, no surfaces. */
247         qxl_io_reset(qdev);
248
249         /* must initialize irq before first async io - slot creation */
250         r = qxl_irq_init(qdev);
251         if (r) {
252                 DRM_ERROR("Unable to init qxl irq\n");
253                 goto release_ring_free;
254         }
255
256         /*
257          * Note that virtual is surface0. We rely on the single ioremap done
258          * before.
259          */
260         setup_slot(qdev, &qdev->main_slot, 0, "main",
261                    (unsigned long)qdev->vram_base,
262                    (unsigned long)qdev->rom->ram_header_offset);
263         setup_slot(qdev, &qdev->surfaces_slot, 1, "surfaces",
264                    (unsigned long)qdev->surfaceram_base,
265                    (unsigned long)qdev->surfaceram_size);
266
267         INIT_WORK(&qdev->gc_work, qxl_gc_work);
268
269         return 0;
270
271 release_ring_free:
272         qxl_ring_free(qdev->release_ring);
273 cursor_ring_free:
274         qxl_ring_free(qdev->cursor_ring);
275 command_ring_free:
276         qxl_ring_free(qdev->command_ring);
277 ram_header_unmap:
278         iounmap(qdev->ram_header);
279 bo_fini:
280         qxl_bo_fini(qdev);
281 rom_unmap:
282         iounmap(qdev->rom);
283 surface_mapping_free:
284         io_mapping_free(qdev->surface_mapping);
285 vram_mapping_free:
286         io_mapping_free(qdev->vram_mapping);
287         return r;
288 }
289
290 void qxl_device_fini(struct qxl_device *qdev)
291 {
292         qxl_bo_unref(&qdev->current_release_bo[0]);
293         qxl_bo_unref(&qdev->current_release_bo[1]);
294         qxl_gem_fini(qdev);
295         qxl_bo_fini(qdev);
296         flush_work(&qdev->gc_work);
297         qxl_ring_free(qdev->command_ring);
298         qxl_ring_free(qdev->cursor_ring);
299         qxl_ring_free(qdev->release_ring);
300         io_mapping_free(qdev->surface_mapping);
301         io_mapping_free(qdev->vram_mapping);
302         iounmap(qdev->ram_header);
303         iounmap(qdev->rom);
304         qdev->rom = NULL;
305 }