2 * Copyright (C) 2013, NVIDIA Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sub license,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the
12 * next paragraph) shall be included in all copies or substantial portions
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 #include <linux/delay.h>
25 #include <linux/gpio/consumer.h>
26 #include <linux/i2c.h>
27 #include <linux/media-bus-format.h>
28 #include <linux/module.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/regulator/consumer.h>
34 #include <video/display_timing.h>
35 #include <video/of_display_timing.h>
36 #include <video/videomode.h>
38 #include <drm/drm_crtc.h>
39 #include <drm/drm_device.h>
40 #include <drm/drm_edid.h>
41 #include <drm/drm_mipi_dsi.h>
42 #include <drm/drm_panel.h>
43 #include <drm/drm_of.h>
46 * struct panel_desc - Describes a simple panel.
50 * @modes: Pointer to array of fixed modes appropriate for this panel.
52 * If only one mode then this can just be the address of the mode.
53 * NOTE: cannot be used with "timings" and also if this is specified
54 * then you cannot override the mode in the device tree.
56 const struct drm_display_mode *modes;
58 /** @num_modes: Number of elements in modes array. */
59 unsigned int num_modes;
62 * @timings: Pointer to array of display timings
64 * NOTE: cannot be used with "modes" and also these will be used to
65 * validate a device tree override if one is present.
67 const struct display_timing *timings;
69 /** @num_timings: Number of elements in timings array. */
70 unsigned int num_timings;
72 /** @bpc: Bits per color. */
75 /** @size: Structure containing the physical size of this panel. */
78 * @size.width: Width (in mm) of the active display area.
83 * @size.height: Height (in mm) of the active display area.
88 /** @delay: Structure containing various delay values for this panel. */
91 * @delay.prepare: Time for the panel to become ready.
93 * The time (in milliseconds) that it takes for the panel to
94 * become ready and start receiving video data
99 * @delay.enable: Time for the panel to display a valid frame.
101 * The time (in milliseconds) that it takes for the panel to
102 * display the first valid frame after starting to receive
108 * @delay.disable: Time for the panel to turn the display off.
110 * The time (in milliseconds) that it takes for the panel to
111 * turn the display off (no content is visible).
113 unsigned int disable;
116 * @delay.unprepare: Time to power down completely.
118 * The time (in milliseconds) that it takes for the panel
119 * to power itself down completely.
121 * This time is used to prevent a future "prepare" from
122 * starting until at least this many milliseconds has passed.
123 * If at prepare time less time has passed since unprepare
124 * finished, the driver waits for the remaining time.
126 unsigned int unprepare;
129 /** @bus_format: See MEDIA_BUS_FMT_... defines. */
132 /** @bus_flags: See DRM_BUS_FLAG_... defines. */
135 /** @connector_type: LVDS, eDP, DSI, DPI, etc. */
139 struct panel_simple {
140 struct drm_panel base;
145 ktime_t unprepared_time;
147 const struct panel_desc *desc;
149 struct regulator *supply;
150 struct i2c_adapter *ddc;
152 struct gpio_desc *enable_gpio;
156 struct drm_display_mode override_mode;
158 enum drm_panel_orientation orientation;
161 static inline struct panel_simple *to_panel_simple(struct drm_panel *panel)
163 return container_of(panel, struct panel_simple, base);
166 static unsigned int panel_simple_get_timings_modes(struct panel_simple *panel,
167 struct drm_connector *connector)
169 struct drm_display_mode *mode;
170 unsigned int i, num = 0;
172 for (i = 0; i < panel->desc->num_timings; i++) {
173 const struct display_timing *dt = &panel->desc->timings[i];
176 videomode_from_timing(dt, &vm);
177 mode = drm_mode_create(connector->dev);
179 dev_err(panel->base.dev, "failed to add mode %ux%u\n",
180 dt->hactive.typ, dt->vactive.typ);
184 drm_display_mode_from_videomode(&vm, mode);
186 mode->type |= DRM_MODE_TYPE_DRIVER;
188 if (panel->desc->num_timings == 1)
189 mode->type |= DRM_MODE_TYPE_PREFERRED;
191 drm_mode_probed_add(connector, mode);
198 static unsigned int panel_simple_get_display_modes(struct panel_simple *panel,
199 struct drm_connector *connector)
201 struct drm_display_mode *mode;
202 unsigned int i, num = 0;
204 for (i = 0; i < panel->desc->num_modes; i++) {
205 const struct drm_display_mode *m = &panel->desc->modes[i];
207 mode = drm_mode_duplicate(connector->dev, m);
209 dev_err(panel->base.dev, "failed to add mode %ux%u@%u\n",
210 m->hdisplay, m->vdisplay,
211 drm_mode_vrefresh(m));
215 mode->type |= DRM_MODE_TYPE_DRIVER;
217 if (panel->desc->num_modes == 1)
218 mode->type |= DRM_MODE_TYPE_PREFERRED;
220 drm_mode_set_name(mode);
222 drm_mode_probed_add(connector, mode);
229 static int panel_simple_get_non_edid_modes(struct panel_simple *panel,
230 struct drm_connector *connector)
232 struct drm_display_mode *mode;
233 bool has_override = panel->override_mode.type;
234 unsigned int num = 0;
240 mode = drm_mode_duplicate(connector->dev,
241 &panel->override_mode);
243 drm_mode_probed_add(connector, mode);
246 dev_err(panel->base.dev, "failed to add override mode\n");
250 /* Only add timings if override was not there or failed to validate */
251 if (num == 0 && panel->desc->num_timings)
252 num = panel_simple_get_timings_modes(panel, connector);
255 * Only add fixed modes if timings/override added no mode.
257 * We should only ever have either the display timings specified
258 * or a fixed mode. Anything else is rather bogus.
260 WARN_ON(panel->desc->num_timings && panel->desc->num_modes);
262 num = panel_simple_get_display_modes(panel, connector);
264 connector->display_info.bpc = panel->desc->bpc;
265 connector->display_info.width_mm = panel->desc->size.width;
266 connector->display_info.height_mm = panel->desc->size.height;
267 if (panel->desc->bus_format)
268 drm_display_info_set_bus_formats(&connector->display_info,
269 &panel->desc->bus_format, 1);
270 connector->display_info.bus_flags = panel->desc->bus_flags;
275 static void panel_simple_wait(ktime_t start_ktime, unsigned int min_ms)
277 ktime_t now_ktime, min_ktime;
282 min_ktime = ktime_add(start_ktime, ms_to_ktime(min_ms));
283 now_ktime = ktime_get_boottime();
285 if (ktime_before(now_ktime, min_ktime))
286 msleep(ktime_to_ms(ktime_sub(min_ktime, now_ktime)) + 1);
289 static int panel_simple_disable(struct drm_panel *panel)
291 struct panel_simple *p = to_panel_simple(panel);
296 if (p->desc->delay.disable)
297 msleep(p->desc->delay.disable);
304 static int panel_simple_suspend(struct device *dev)
306 struct panel_simple *p = dev_get_drvdata(dev);
308 gpiod_set_value_cansleep(p->enable_gpio, 0);
309 regulator_disable(p->supply);
310 p->unprepared_time = ktime_get_boottime();
318 static int panel_simple_unprepare(struct drm_panel *panel)
320 struct panel_simple *p = to_panel_simple(panel);
323 /* Unpreparing when already unprepared is a no-op */
327 pm_runtime_mark_last_busy(panel->dev);
328 ret = pm_runtime_put_autosuspend(panel->dev);
336 static int panel_simple_resume(struct device *dev)
338 struct panel_simple *p = dev_get_drvdata(dev);
341 panel_simple_wait(p->unprepared_time, p->desc->delay.unprepare);
343 err = regulator_enable(p->supply);
345 dev_err(dev, "failed to enable supply: %d\n", err);
349 gpiod_set_value_cansleep(p->enable_gpio, 1);
351 if (p->desc->delay.prepare)
352 msleep(p->desc->delay.prepare);
357 static int panel_simple_prepare(struct drm_panel *panel)
359 struct panel_simple *p = to_panel_simple(panel);
362 /* Preparing when already prepared is a no-op */
366 ret = pm_runtime_get_sync(panel->dev);
368 pm_runtime_put_autosuspend(panel->dev);
377 static int panel_simple_enable(struct drm_panel *panel)
379 struct panel_simple *p = to_panel_simple(panel);
384 if (p->desc->delay.enable)
385 msleep(p->desc->delay.enable);
392 static int panel_simple_get_modes(struct drm_panel *panel,
393 struct drm_connector *connector)
395 struct panel_simple *p = to_panel_simple(panel);
398 /* probe EDID if a DDC bus is available */
400 pm_runtime_get_sync(panel->dev);
403 p->edid = drm_get_edid(connector, p->ddc);
406 num += drm_add_edid_modes(connector, p->edid);
408 pm_runtime_mark_last_busy(panel->dev);
409 pm_runtime_put_autosuspend(panel->dev);
412 /* add hard-coded panel modes */
413 num += panel_simple_get_non_edid_modes(p, connector);
416 * TODO: Remove once all drm drivers call
417 * drm_connector_set_orientation_from_panel()
419 drm_connector_set_panel_orientation(connector, p->orientation);
424 static int panel_simple_get_timings(struct drm_panel *panel,
425 unsigned int num_timings,
426 struct display_timing *timings)
428 struct panel_simple *p = to_panel_simple(panel);
431 if (p->desc->num_timings < num_timings)
432 num_timings = p->desc->num_timings;
435 for (i = 0; i < num_timings; i++)
436 timings[i] = p->desc->timings[i];
438 return p->desc->num_timings;
441 static enum drm_panel_orientation panel_simple_get_orientation(struct drm_panel *panel)
443 struct panel_simple *p = to_panel_simple(panel);
445 return p->orientation;
448 static const struct drm_panel_funcs panel_simple_funcs = {
449 .disable = panel_simple_disable,
450 .unprepare = panel_simple_unprepare,
451 .prepare = panel_simple_prepare,
452 .enable = panel_simple_enable,
453 .get_modes = panel_simple_get_modes,
454 .get_orientation = panel_simple_get_orientation,
455 .get_timings = panel_simple_get_timings,
458 static struct panel_desc panel_dpi;
460 static int panel_dpi_probe(struct device *dev,
461 struct panel_simple *panel)
463 struct display_timing *timing;
464 const struct device_node *np;
465 struct panel_desc *desc;
466 unsigned int bus_flags;
471 desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
475 timing = devm_kzalloc(dev, sizeof(*timing), GFP_KERNEL);
479 ret = of_get_display_timing(np, "panel-timing", timing);
481 dev_err(dev, "%pOF: no panel-timing node found for \"panel-dpi\" binding\n",
486 desc->timings = timing;
487 desc->num_timings = 1;
489 of_property_read_u32(np, "width-mm", &desc->size.width);
490 of_property_read_u32(np, "height-mm", &desc->size.height);
492 /* Extract bus_flags from display_timing */
494 vm.flags = timing->flags;
495 drm_bus_flags_from_videomode(&vm, &bus_flags);
496 desc->bus_flags = bus_flags;
498 /* We do not know the connector for the DT node, so guess it */
499 desc->connector_type = DRM_MODE_CONNECTOR_DPI;
506 #define PANEL_SIMPLE_BOUNDS_CHECK(to_check, bounds, field) \
507 (to_check->field.typ >= bounds->field.min && \
508 to_check->field.typ <= bounds->field.max)
509 static void panel_simple_parse_panel_timing_node(struct device *dev,
510 struct panel_simple *panel,
511 const struct display_timing *ot)
513 const struct panel_desc *desc = panel->desc;
517 if (WARN_ON(desc->num_modes)) {
518 dev_err(dev, "Reject override mode: panel has a fixed mode\n");
521 if (WARN_ON(!desc->num_timings)) {
522 dev_err(dev, "Reject override mode: no timings specified\n");
526 for (i = 0; i < panel->desc->num_timings; i++) {
527 const struct display_timing *dt = &panel->desc->timings[i];
529 if (!PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hactive) ||
530 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hfront_porch) ||
531 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hback_porch) ||
532 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, hsync_len) ||
533 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vactive) ||
534 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vfront_porch) ||
535 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vback_porch) ||
536 !PANEL_SIMPLE_BOUNDS_CHECK(ot, dt, vsync_len))
539 if (ot->flags != dt->flags)
542 videomode_from_timing(ot, &vm);
543 drm_display_mode_from_videomode(&vm, &panel->override_mode);
544 panel->override_mode.type |= DRM_MODE_TYPE_DRIVER |
545 DRM_MODE_TYPE_PREFERRED;
549 if (WARN_ON(!panel->override_mode.type))
550 dev_err(dev, "Reject override mode: No display_timing found\n");
553 static int panel_simple_override_nondefault_lvds_datamapping(struct device *dev,
554 struct panel_simple *panel)
558 ret = drm_of_lvds_get_data_mapping(dev->of_node);
561 dev_warn(dev, "Ignore invalid data-mapping property\n");
564 * Ignore non-existing or malformatted property, fallback to
565 * default data-mapping, and return 0.
574 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
576 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
579 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
583 if (panel->desc->bpc != bpc || panel->desc->bus_format != ret) {
584 struct panel_desc *override_desc;
586 override_desc = devm_kmemdup(dev, panel->desc, sizeof(*panel->desc), GFP_KERNEL);
590 override_desc->bus_format = ret;
591 override_desc->bpc = bpc;
592 panel->desc = override_desc;
598 static int panel_simple_probe(struct device *dev, const struct panel_desc *desc)
600 struct panel_simple *panel;
601 struct display_timing dt;
602 struct device_node *ddc;
607 panel = devm_kzalloc(dev, sizeof(*panel), GFP_KERNEL);
611 panel->enabled = false;
614 panel->supply = devm_regulator_get(dev, "power");
615 if (IS_ERR(panel->supply))
616 return PTR_ERR(panel->supply);
618 panel->enable_gpio = devm_gpiod_get_optional(dev, "enable",
620 if (IS_ERR(panel->enable_gpio))
621 return dev_err_probe(dev, PTR_ERR(panel->enable_gpio),
622 "failed to request GPIO\n");
624 err = of_drm_get_panel_orientation(dev->of_node, &panel->orientation);
626 dev_err(dev, "%pOF: failed to get orientation %d\n", dev->of_node, err);
630 ddc = of_parse_phandle(dev->of_node, "ddc-i2c-bus", 0);
632 panel->ddc = of_find_i2c_adapter_by_node(ddc);
636 return -EPROBE_DEFER;
639 if (desc == &panel_dpi) {
640 /* Handle the generic panel-dpi binding */
641 err = panel_dpi_probe(dev, panel);
646 if (!of_get_display_timing(dev->of_node, "panel-timing", &dt))
647 panel_simple_parse_panel_timing_node(dev, panel, &dt);
650 if (desc->connector_type == DRM_MODE_CONNECTOR_LVDS) {
651 /* Optional data-mapping property for overriding bus format */
652 err = panel_simple_override_nondefault_lvds_datamapping(dev, panel);
657 connector_type = desc->connector_type;
658 /* Catch common mistakes for panels. */
659 switch (connector_type) {
661 dev_warn(dev, "Specify missing connector_type\n");
662 connector_type = DRM_MODE_CONNECTOR_DPI;
664 case DRM_MODE_CONNECTOR_LVDS:
665 WARN_ON(desc->bus_flags &
666 ~(DRM_BUS_FLAG_DE_LOW |
667 DRM_BUS_FLAG_DE_HIGH |
668 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
669 DRM_BUS_FLAG_DATA_LSB_TO_MSB));
670 WARN_ON(desc->bus_format != MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
671 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_SPWG &&
672 desc->bus_format != MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA);
673 WARN_ON(desc->bus_format == MEDIA_BUS_FMT_RGB666_1X7X3_SPWG &&
675 WARN_ON((desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG ||
676 desc->bus_format == MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA) &&
679 case DRM_MODE_CONNECTOR_eDP:
680 dev_warn(dev, "eDP panels moved to panel-edp\n");
683 case DRM_MODE_CONNECTOR_DSI:
684 if (desc->bpc != 6 && desc->bpc != 8)
685 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
687 case DRM_MODE_CONNECTOR_DPI:
688 bus_flags = DRM_BUS_FLAG_DE_LOW |
689 DRM_BUS_FLAG_DE_HIGH |
690 DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE |
691 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
692 DRM_BUS_FLAG_DATA_MSB_TO_LSB |
693 DRM_BUS_FLAG_DATA_LSB_TO_MSB |
694 DRM_BUS_FLAG_SYNC_SAMPLE_POSEDGE |
695 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE;
696 if (desc->bus_flags & ~bus_flags)
697 dev_warn(dev, "Unexpected bus_flags(%d)\n", desc->bus_flags & ~bus_flags);
698 if (!(desc->bus_flags & bus_flags))
699 dev_warn(dev, "Specify missing bus_flags\n");
700 if (desc->bus_format == 0)
701 dev_warn(dev, "Specify missing bus_format\n");
702 if (desc->bpc != 6 && desc->bpc != 8)
703 dev_warn(dev, "Expected bpc in {6,8} but got: %u\n", desc->bpc);
706 dev_warn(dev, "Specify a valid connector_type: %d\n", desc->connector_type);
707 connector_type = DRM_MODE_CONNECTOR_DPI;
711 dev_set_drvdata(dev, panel);
714 * We use runtime PM for prepare / unprepare since those power the panel
715 * on and off and those can be very slow operations. This is important
716 * to optimize powering the panel on briefly to read the EDID before
717 * fully enabling the panel.
719 pm_runtime_enable(dev);
720 pm_runtime_set_autosuspend_delay(dev, 1000);
721 pm_runtime_use_autosuspend(dev);
723 drm_panel_init(&panel->base, dev, &panel_simple_funcs, connector_type);
725 err = drm_panel_of_backlight(&panel->base);
727 dev_err_probe(dev, err, "Could not find backlight\n");
728 goto disable_pm_runtime;
731 drm_panel_add(&panel->base);
736 pm_runtime_dont_use_autosuspend(dev);
737 pm_runtime_disable(dev);
740 put_device(&panel->ddc->dev);
745 static void panel_simple_remove(struct device *dev)
747 struct panel_simple *panel = dev_get_drvdata(dev);
749 drm_panel_remove(&panel->base);
750 drm_panel_disable(&panel->base);
751 drm_panel_unprepare(&panel->base);
753 pm_runtime_dont_use_autosuspend(dev);
754 pm_runtime_disable(dev);
756 put_device(&panel->ddc->dev);
759 static void panel_simple_shutdown(struct device *dev)
761 struct panel_simple *panel = dev_get_drvdata(dev);
763 drm_panel_disable(&panel->base);
764 drm_panel_unprepare(&panel->base);
767 static const struct drm_display_mode ampire_am_1280800n3tzqw_t00h_mode = {
770 .hsync_start = 1280 + 40,
771 .hsync_end = 1280 + 40 + 80,
772 .htotal = 1280 + 40 + 80 + 40,
774 .vsync_start = 800 + 3,
775 .vsync_end = 800 + 3 + 10,
776 .vtotal = 800 + 3 + 10 + 10,
777 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
780 static const struct panel_desc ampire_am_1280800n3tzqw_t00h = {
781 .modes = &ire_am_1280800n3tzqw_t00h_mode,
788 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
789 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
790 .connector_type = DRM_MODE_CONNECTOR_LVDS,
793 static const struct drm_display_mode ampire_am_480272h3tmqw_t01h_mode = {
796 .hsync_start = 480 + 2,
797 .hsync_end = 480 + 2 + 41,
798 .htotal = 480 + 2 + 41 + 2,
800 .vsync_start = 272 + 2,
801 .vsync_end = 272 + 2 + 10,
802 .vtotal = 272 + 2 + 10 + 2,
803 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
806 static const struct panel_desc ampire_am_480272h3tmqw_t01h = {
807 .modes = &ire_am_480272h3tmqw_t01h_mode,
814 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
817 static const struct drm_display_mode ampire_am800480r3tmqwa1h_mode = {
820 .hsync_start = 800 + 0,
821 .hsync_end = 800 + 0 + 255,
822 .htotal = 800 + 0 + 255 + 0,
824 .vsync_start = 480 + 2,
825 .vsync_end = 480 + 2 + 45,
826 .vtotal = 480 + 2 + 45 + 0,
827 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
830 static const struct display_timing ampire_am_800480l1tmqw_t00h_timing = {
831 .pixelclock = { 29930000, 33260000, 36590000 },
832 .hactive = { 800, 800, 800 },
833 .hfront_porch = { 1, 40, 168 },
834 .hback_porch = { 88, 88, 88 },
835 .hsync_len = { 1, 128, 128 },
836 .vactive = { 480, 480, 480 },
837 .vfront_porch = { 1, 35, 37 },
838 .vback_porch = { 8, 8, 8 },
839 .vsync_len = { 1, 2, 2 },
840 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
841 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
842 DISPLAY_FLAGS_SYNC_POSEDGE,
845 static const struct panel_desc ampire_am_800480l1tmqw_t00h = {
846 .timings = &ire_am_800480l1tmqw_t00h_timing,
853 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
854 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
855 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
856 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
857 .connector_type = DRM_MODE_CONNECTOR_DPI,
860 static const struct panel_desc ampire_am800480r3tmqwa1h = {
861 .modes = &ire_am800480r3tmqwa1h_mode,
868 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
871 static const struct display_timing ampire_am800600p5tmqw_tb8h_timing = {
872 .pixelclock = { 34500000, 39600000, 50400000 },
873 .hactive = { 800, 800, 800 },
874 .hfront_porch = { 12, 112, 312 },
875 .hback_porch = { 87, 87, 48 },
876 .hsync_len = { 1, 1, 40 },
877 .vactive = { 600, 600, 600 },
878 .vfront_porch = { 1, 21, 61 },
879 .vback_porch = { 38, 38, 19 },
880 .vsync_len = { 1, 1, 20 },
881 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
882 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
883 DISPLAY_FLAGS_SYNC_POSEDGE,
886 static const struct panel_desc ampire_am800600p5tmqwtb8h = {
887 .timings = &ire_am800600p5tmqw_tb8h_timing,
894 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
895 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
896 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
897 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
898 .connector_type = DRM_MODE_CONNECTOR_DPI,
901 static const struct display_timing santek_st0700i5y_rbslw_f_timing = {
902 .pixelclock = { 26400000, 33300000, 46800000 },
903 .hactive = { 800, 800, 800 },
904 .hfront_porch = { 16, 210, 354 },
905 .hback_porch = { 45, 36, 6 },
906 .hsync_len = { 1, 10, 40 },
907 .vactive = { 480, 480, 480 },
908 .vfront_porch = { 7, 22, 147 },
909 .vback_porch = { 22, 13, 3 },
910 .vsync_len = { 1, 10, 20 },
911 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
912 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE
915 static const struct panel_desc armadeus_st0700_adapt = {
916 .timings = &santek_st0700i5y_rbslw_f_timing,
923 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
924 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
927 static const struct drm_display_mode auo_b101aw03_mode = {
930 .hsync_start = 1024 + 156,
931 .hsync_end = 1024 + 156 + 8,
932 .htotal = 1024 + 156 + 8 + 156,
934 .vsync_start = 600 + 16,
935 .vsync_end = 600 + 16 + 6,
936 .vtotal = 600 + 16 + 6 + 16,
939 static const struct panel_desc auo_b101aw03 = {
940 .modes = &auo_b101aw03_mode,
947 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
948 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
949 .connector_type = DRM_MODE_CONNECTOR_LVDS,
952 static const struct drm_display_mode auo_b101xtn01_mode = {
955 .hsync_start = 1366 + 20,
956 .hsync_end = 1366 + 20 + 70,
957 .htotal = 1366 + 20 + 70,
959 .vsync_start = 768 + 14,
960 .vsync_end = 768 + 14 + 42,
961 .vtotal = 768 + 14 + 42,
962 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
965 static const struct panel_desc auo_b101xtn01 = {
966 .modes = &auo_b101xtn01_mode,
975 static const struct display_timing auo_g070vvn01_timings = {
976 .pixelclock = { 33300000, 34209000, 45000000 },
977 .hactive = { 800, 800, 800 },
978 .hfront_porch = { 20, 40, 200 },
979 .hback_porch = { 87, 40, 1 },
980 .hsync_len = { 1, 48, 87 },
981 .vactive = { 480, 480, 480 },
982 .vfront_porch = { 5, 13, 200 },
983 .vback_porch = { 31, 31, 29 },
984 .vsync_len = { 1, 1, 3 },
987 static const struct panel_desc auo_g070vvn01 = {
988 .timings = &auo_g070vvn01_timings,
1003 static const struct drm_display_mode auo_g101evn010_mode = {
1006 .hsync_start = 1280 + 82,
1007 .hsync_end = 1280 + 82 + 2,
1008 .htotal = 1280 + 82 + 2 + 84,
1010 .vsync_start = 800 + 8,
1011 .vsync_end = 800 + 8 + 2,
1012 .vtotal = 800 + 8 + 2 + 6,
1015 static const struct panel_desc auo_g101evn010 = {
1016 .modes = &auo_g101evn010_mode,
1023 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1024 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1027 static const struct drm_display_mode auo_g104sn02_mode = {
1030 .hsync_start = 800 + 40,
1031 .hsync_end = 800 + 40 + 216,
1032 .htotal = 800 + 40 + 216 + 128,
1034 .vsync_start = 600 + 10,
1035 .vsync_end = 600 + 10 + 35,
1036 .vtotal = 600 + 10 + 35 + 2,
1039 static const struct panel_desc auo_g104sn02 = {
1040 .modes = &auo_g104sn02_mode,
1047 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1048 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1051 static const struct display_timing auo_g121ean01_timing = {
1052 .pixelclock = { 60000000, 74400000, 90000000 },
1053 .hactive = { 1280, 1280, 1280 },
1054 .hfront_porch = { 20, 50, 100 },
1055 .hback_porch = { 20, 50, 100 },
1056 .hsync_len = { 30, 100, 200 },
1057 .vactive = { 800, 800, 800 },
1058 .vfront_porch = { 2, 10, 25 },
1059 .vback_porch = { 2, 10, 25 },
1060 .vsync_len = { 4, 18, 50 },
1063 static const struct panel_desc auo_g121ean01 = {
1064 .timings = &auo_g121ean01_timing,
1071 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1072 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1075 static const struct display_timing auo_g133han01_timings = {
1076 .pixelclock = { 134000000, 141200000, 149000000 },
1077 .hactive = { 1920, 1920, 1920 },
1078 .hfront_porch = { 39, 58, 77 },
1079 .hback_porch = { 59, 88, 117 },
1080 .hsync_len = { 28, 42, 56 },
1081 .vactive = { 1080, 1080, 1080 },
1082 .vfront_porch = { 3, 8, 11 },
1083 .vback_porch = { 5, 14, 19 },
1084 .vsync_len = { 4, 14, 19 },
1087 static const struct panel_desc auo_g133han01 = {
1088 .timings = &auo_g133han01_timings,
1101 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
1102 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1105 static const struct drm_display_mode auo_g156xtn01_mode = {
1108 .hsync_start = 1366 + 33,
1109 .hsync_end = 1366 + 33 + 67,
1112 .vsync_start = 768 + 4,
1113 .vsync_end = 768 + 4 + 4,
1117 static const struct panel_desc auo_g156xtn01 = {
1118 .modes = &auo_g156xtn01_mode,
1125 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1126 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1129 static const struct display_timing auo_g185han01_timings = {
1130 .pixelclock = { 120000000, 144000000, 175000000 },
1131 .hactive = { 1920, 1920, 1920 },
1132 .hfront_porch = { 36, 120, 148 },
1133 .hback_porch = { 24, 88, 108 },
1134 .hsync_len = { 20, 48, 64 },
1135 .vactive = { 1080, 1080, 1080 },
1136 .vfront_porch = { 6, 10, 40 },
1137 .vback_porch = { 2, 5, 20 },
1138 .vsync_len = { 2, 5, 20 },
1141 static const struct panel_desc auo_g185han01 = {
1142 .timings = &auo_g185han01_timings,
1155 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1156 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1159 static const struct display_timing auo_g190ean01_timings = {
1160 .pixelclock = { 90000000, 108000000, 135000000 },
1161 .hactive = { 1280, 1280, 1280 },
1162 .hfront_porch = { 126, 184, 1266 },
1163 .hback_porch = { 84, 122, 844 },
1164 .hsync_len = { 70, 102, 704 },
1165 .vactive = { 1024, 1024, 1024 },
1166 .vfront_porch = { 4, 26, 76 },
1167 .vback_porch = { 2, 8, 25 },
1168 .vsync_len = { 2, 8, 25 },
1171 static const struct panel_desc auo_g190ean01 = {
1172 .timings = &auo_g190ean01_timings,
1185 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1186 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1189 static const struct display_timing auo_p320hvn03_timings = {
1190 .pixelclock = { 106000000, 148500000, 164000000 },
1191 .hactive = { 1920, 1920, 1920 },
1192 .hfront_porch = { 25, 50, 130 },
1193 .hback_porch = { 25, 50, 130 },
1194 .hsync_len = { 20, 40, 105 },
1195 .vactive = { 1080, 1080, 1080 },
1196 .vfront_porch = { 8, 17, 150 },
1197 .vback_porch = { 8, 17, 150 },
1198 .vsync_len = { 4, 11, 100 },
1201 static const struct panel_desc auo_p320hvn03 = {
1202 .timings = &auo_p320hvn03_timings,
1214 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1215 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1218 static const struct drm_display_mode auo_t215hvn01_mode = {
1221 .hsync_start = 1920 + 88,
1222 .hsync_end = 1920 + 88 + 44,
1223 .htotal = 1920 + 88 + 44 + 148,
1225 .vsync_start = 1080 + 4,
1226 .vsync_end = 1080 + 4 + 5,
1227 .vtotal = 1080 + 4 + 5 + 36,
1230 static const struct panel_desc auo_t215hvn01 = {
1231 .modes = &auo_t215hvn01_mode,
1242 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1243 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1246 static const struct drm_display_mode avic_tm070ddh03_mode = {
1249 .hsync_start = 1024 + 160,
1250 .hsync_end = 1024 + 160 + 4,
1251 .htotal = 1024 + 160 + 4 + 156,
1253 .vsync_start = 600 + 17,
1254 .vsync_end = 600 + 17 + 1,
1255 .vtotal = 600 + 17 + 1 + 17,
1258 static const struct panel_desc avic_tm070ddh03 = {
1259 .modes = &avic_tm070ddh03_mode,
1273 static const struct drm_display_mode bananapi_s070wv20_ct16_mode = {
1276 .hsync_start = 800 + 40,
1277 .hsync_end = 800 + 40 + 48,
1278 .htotal = 800 + 40 + 48 + 40,
1280 .vsync_start = 480 + 13,
1281 .vsync_end = 480 + 13 + 3,
1282 .vtotal = 480 + 13 + 3 + 29,
1285 static const struct panel_desc bananapi_s070wv20_ct16 = {
1286 .modes = &bananapi_s070wv20_ct16_mode,
1295 static const struct display_timing boe_ev121wxm_n10_1850_timing = {
1296 .pixelclock = { 69922000, 71000000, 72293000 },
1297 .hactive = { 1280, 1280, 1280 },
1298 .hfront_porch = { 48, 48, 48 },
1299 .hback_porch = { 80, 80, 80 },
1300 .hsync_len = { 32, 32, 32 },
1301 .vactive = { 800, 800, 800 },
1302 .vfront_porch = { 3, 3, 3 },
1303 .vback_porch = { 14, 14, 14 },
1304 .vsync_len = { 6, 6, 6 },
1307 static const struct panel_desc boe_ev121wxm_n10_1850 = {
1308 .timings = &boe_ev121wxm_n10_1850_timing,
1321 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1322 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1323 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1326 static const struct drm_display_mode boe_hv070wsa_mode = {
1329 .hsync_start = 1024 + 30,
1330 .hsync_end = 1024 + 30 + 30,
1331 .htotal = 1024 + 30 + 30 + 30,
1333 .vsync_start = 600 + 10,
1334 .vsync_end = 600 + 10 + 10,
1335 .vtotal = 600 + 10 + 10 + 10,
1338 static const struct panel_desc boe_hv070wsa = {
1339 .modes = &boe_hv070wsa_mode,
1346 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1347 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1348 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1351 static const struct drm_display_mode cdtech_s043wq26h_ct7_mode = {
1354 .hsync_start = 480 + 5,
1355 .hsync_end = 480 + 5 + 5,
1356 .htotal = 480 + 5 + 5 + 40,
1358 .vsync_start = 272 + 8,
1359 .vsync_end = 272 + 8 + 8,
1360 .vtotal = 272 + 8 + 8 + 8,
1361 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1364 static const struct panel_desc cdtech_s043wq26h_ct7 = {
1365 .modes = &cdtech_s043wq26h_ct7_mode,
1372 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1375 /* S070PWS19HP-FC21 2017/04/22 */
1376 static const struct drm_display_mode cdtech_s070pws19hp_fc21_mode = {
1379 .hsync_start = 1024 + 160,
1380 .hsync_end = 1024 + 160 + 20,
1381 .htotal = 1024 + 160 + 20 + 140,
1383 .vsync_start = 600 + 12,
1384 .vsync_end = 600 + 12 + 3,
1385 .vtotal = 600 + 12 + 3 + 20,
1386 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1389 static const struct panel_desc cdtech_s070pws19hp_fc21 = {
1390 .modes = &cdtech_s070pws19hp_fc21_mode,
1397 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1398 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1399 .connector_type = DRM_MODE_CONNECTOR_DPI,
1402 /* S070SWV29HG-DC44 2017/09/21 */
1403 static const struct drm_display_mode cdtech_s070swv29hg_dc44_mode = {
1406 .hsync_start = 800 + 210,
1407 .hsync_end = 800 + 210 + 2,
1408 .htotal = 800 + 210 + 2 + 44,
1410 .vsync_start = 480 + 22,
1411 .vsync_end = 480 + 22 + 2,
1412 .vtotal = 480 + 22 + 2 + 21,
1413 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1416 static const struct panel_desc cdtech_s070swv29hg_dc44 = {
1417 .modes = &cdtech_s070swv29hg_dc44_mode,
1424 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1425 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
1426 .connector_type = DRM_MODE_CONNECTOR_DPI,
1429 static const struct drm_display_mode cdtech_s070wv95_ct16_mode = {
1432 .hsync_start = 800 + 40,
1433 .hsync_end = 800 + 40 + 40,
1434 .htotal = 800 + 40 + 40 + 48,
1436 .vsync_start = 480 + 29,
1437 .vsync_end = 480 + 29 + 13,
1438 .vtotal = 480 + 29 + 13 + 3,
1439 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1442 static const struct panel_desc cdtech_s070wv95_ct16 = {
1443 .modes = &cdtech_s070wv95_ct16_mode,
1452 static const struct display_timing chefree_ch101olhlwh_002_timing = {
1453 .pixelclock = { 68900000, 71100000, 73400000 },
1454 .hactive = { 1280, 1280, 1280 },
1455 .hfront_porch = { 65, 80, 95 },
1456 .hback_porch = { 64, 79, 94 },
1457 .hsync_len = { 1, 1, 1 },
1458 .vactive = { 800, 800, 800 },
1459 .vfront_porch = { 7, 11, 14 },
1460 .vback_porch = { 7, 11, 14 },
1461 .vsync_len = { 1, 1, 1 },
1462 .flags = DISPLAY_FLAGS_DE_HIGH,
1465 static const struct panel_desc chefree_ch101olhlwh_002 = {
1466 .timings = &chefree_ch101olhlwh_002_timing,
1477 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1478 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1479 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1482 static const struct drm_display_mode chunghwa_claa070wp03xg_mode = {
1485 .hsync_start = 800 + 49,
1486 .hsync_end = 800 + 49 + 33,
1487 .htotal = 800 + 49 + 33 + 17,
1489 .vsync_start = 1280 + 1,
1490 .vsync_end = 1280 + 1 + 7,
1491 .vtotal = 1280 + 1 + 7 + 15,
1492 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1495 static const struct panel_desc chunghwa_claa070wp03xg = {
1496 .modes = &chunghwa_claa070wp03xg_mode,
1503 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1504 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1505 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1508 static const struct drm_display_mode chunghwa_claa101wa01a_mode = {
1511 .hsync_start = 1366 + 58,
1512 .hsync_end = 1366 + 58 + 58,
1513 .htotal = 1366 + 58 + 58 + 58,
1515 .vsync_start = 768 + 4,
1516 .vsync_end = 768 + 4 + 4,
1517 .vtotal = 768 + 4 + 4 + 4,
1520 static const struct panel_desc chunghwa_claa101wa01a = {
1521 .modes = &chunghwa_claa101wa01a_mode,
1528 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1529 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1530 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1533 static const struct drm_display_mode chunghwa_claa101wb01_mode = {
1536 .hsync_start = 1366 + 48,
1537 .hsync_end = 1366 + 48 + 32,
1538 .htotal = 1366 + 48 + 32 + 20,
1540 .vsync_start = 768 + 16,
1541 .vsync_end = 768 + 16 + 8,
1542 .vtotal = 768 + 16 + 8 + 16,
1545 static const struct panel_desc chunghwa_claa101wb01 = {
1546 .modes = &chunghwa_claa101wb01_mode,
1553 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1554 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
1555 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1558 static const struct display_timing dataimage_fg040346dsswbg04_timing = {
1559 .pixelclock = { 5000000, 9000000, 12000000 },
1560 .hactive = { 480, 480, 480 },
1561 .hfront_porch = { 12, 12, 12 },
1562 .hback_porch = { 12, 12, 12 },
1563 .hsync_len = { 21, 21, 21 },
1564 .vactive = { 272, 272, 272 },
1565 .vfront_porch = { 4, 4, 4 },
1566 .vback_porch = { 4, 4, 4 },
1567 .vsync_len = { 8, 8, 8 },
1570 static const struct panel_desc dataimage_fg040346dsswbg04 = {
1571 .timings = &dataimage_fg040346dsswbg04_timing,
1578 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1579 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1580 .connector_type = DRM_MODE_CONNECTOR_DPI,
1583 static const struct display_timing dataimage_fg1001l0dsswmg01_timing = {
1584 .pixelclock = { 68900000, 71110000, 73400000 },
1585 .hactive = { 1280, 1280, 1280 },
1586 .vactive = { 800, 800, 800 },
1587 .hback_porch = { 100, 100, 100 },
1588 .hfront_porch = { 100, 100, 100 },
1589 .vback_porch = { 5, 5, 5 },
1590 .vfront_porch = { 5, 5, 5 },
1591 .hsync_len = { 24, 24, 24 },
1592 .vsync_len = { 3, 3, 3 },
1593 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
1594 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
1597 static const struct panel_desc dataimage_fg1001l0dsswmg01 = {
1598 .timings = &dataimage_fg1001l0dsswmg01_timing,
1607 static const struct drm_display_mode dataimage_scf0700c48ggu18_mode = {
1610 .hsync_start = 800 + 40,
1611 .hsync_end = 800 + 40 + 128,
1612 .htotal = 800 + 40 + 128 + 88,
1614 .vsync_start = 480 + 10,
1615 .vsync_end = 480 + 10 + 2,
1616 .vtotal = 480 + 10 + 2 + 33,
1617 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1620 static const struct panel_desc dataimage_scf0700c48ggu18 = {
1621 .modes = &dataimage_scf0700c48ggu18_mode,
1628 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1629 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1632 static const struct display_timing dlc_dlc0700yzg_1_timing = {
1633 .pixelclock = { 45000000, 51200000, 57000000 },
1634 .hactive = { 1024, 1024, 1024 },
1635 .hfront_porch = { 100, 106, 113 },
1636 .hback_porch = { 100, 106, 113 },
1637 .hsync_len = { 100, 108, 114 },
1638 .vactive = { 600, 600, 600 },
1639 .vfront_porch = { 8, 11, 15 },
1640 .vback_porch = { 8, 11, 15 },
1641 .vsync_len = { 9, 13, 15 },
1642 .flags = DISPLAY_FLAGS_DE_HIGH,
1645 static const struct panel_desc dlc_dlc0700yzg_1 = {
1646 .timings = &dlc_dlc0700yzg_1_timing,
1658 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
1659 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1662 static const struct display_timing dlc_dlc1010gig_timing = {
1663 .pixelclock = { 68900000, 71100000, 73400000 },
1664 .hactive = { 1280, 1280, 1280 },
1665 .hfront_porch = { 43, 53, 63 },
1666 .hback_porch = { 43, 53, 63 },
1667 .hsync_len = { 44, 54, 64 },
1668 .vactive = { 800, 800, 800 },
1669 .vfront_porch = { 5, 8, 11 },
1670 .vback_porch = { 5, 8, 11 },
1671 .vsync_len = { 5, 7, 11 },
1672 .flags = DISPLAY_FLAGS_DE_HIGH,
1675 static const struct panel_desc dlc_dlc1010gig = {
1676 .timings = &dlc_dlc1010gig_timing,
1689 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1690 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1693 static const struct drm_display_mode edt_et035012dm6_mode = {
1696 .hsync_start = 320 + 20,
1697 .hsync_end = 320 + 20 + 30,
1698 .htotal = 320 + 20 + 68,
1700 .vsync_start = 240 + 4,
1701 .vsync_end = 240 + 4 + 4,
1702 .vtotal = 240 + 4 + 4 + 14,
1703 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1706 static const struct panel_desc edt_et035012dm6 = {
1707 .modes = &edt_et035012dm6_mode,
1714 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1715 .bus_flags = DRM_BUS_FLAG_DE_LOW | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1718 static const struct drm_display_mode edt_etm0350g0dh6_mode = {
1721 .hsync_start = 320 + 20,
1722 .hsync_end = 320 + 20 + 68,
1723 .htotal = 320 + 20 + 68,
1725 .vsync_start = 240 + 4,
1726 .vsync_end = 240 + 4 + 18,
1727 .vtotal = 240 + 4 + 18,
1728 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1731 static const struct panel_desc edt_etm0350g0dh6 = {
1732 .modes = &edt_etm0350g0dh6_mode,
1739 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1740 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1741 .connector_type = DRM_MODE_CONNECTOR_DPI,
1744 static const struct drm_display_mode edt_etm043080dh6gp_mode = {
1747 .hsync_start = 480 + 8,
1748 .hsync_end = 480 + 8 + 4,
1749 .htotal = 480 + 8 + 4 + 41,
1752 * IWG22M: Y resolution changed for "dc_linuxfb" module crashing while
1757 .vsync_start = 288 + 2,
1758 .vsync_end = 288 + 2 + 4,
1759 .vtotal = 288 + 2 + 4 + 10,
1762 static const struct panel_desc edt_etm043080dh6gp = {
1763 .modes = &edt_etm043080dh6gp_mode,
1770 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1771 .connector_type = DRM_MODE_CONNECTOR_DPI,
1774 static const struct drm_display_mode edt_etm0430g0dh6_mode = {
1777 .hsync_start = 480 + 2,
1778 .hsync_end = 480 + 2 + 41,
1779 .htotal = 480 + 2 + 41 + 2,
1781 .vsync_start = 272 + 2,
1782 .vsync_end = 272 + 2 + 10,
1783 .vtotal = 272 + 2 + 10 + 2,
1784 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1787 static const struct panel_desc edt_etm0430g0dh6 = {
1788 .modes = &edt_etm0430g0dh6_mode,
1795 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1796 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1797 .connector_type = DRM_MODE_CONNECTOR_DPI,
1800 static const struct drm_display_mode edt_et057090dhu_mode = {
1803 .hsync_start = 640 + 16,
1804 .hsync_end = 640 + 16 + 30,
1805 .htotal = 640 + 16 + 30 + 114,
1807 .vsync_start = 480 + 10,
1808 .vsync_end = 480 + 10 + 3,
1809 .vtotal = 480 + 10 + 3 + 32,
1810 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
1813 static const struct panel_desc edt_et057090dhu = {
1814 .modes = &edt_et057090dhu_mode,
1821 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1822 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1823 .connector_type = DRM_MODE_CONNECTOR_DPI,
1826 static const struct drm_display_mode edt_etm0700g0dh6_mode = {
1829 .hsync_start = 800 + 40,
1830 .hsync_end = 800 + 40 + 128,
1831 .htotal = 800 + 40 + 128 + 88,
1833 .vsync_start = 480 + 10,
1834 .vsync_end = 480 + 10 + 2,
1835 .vtotal = 480 + 10 + 2 + 33,
1836 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
1839 static const struct panel_desc edt_etm0700g0dh6 = {
1840 .modes = &edt_etm0700g0dh6_mode,
1847 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1848 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1849 .connector_type = DRM_MODE_CONNECTOR_DPI,
1852 static const struct panel_desc edt_etm0700g0bdh6 = {
1853 .modes = &edt_etm0700g0dh6_mode,
1860 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
1861 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1862 .connector_type = DRM_MODE_CONNECTOR_DPI,
1865 static const struct display_timing edt_etml0700y5dha_timing = {
1866 .pixelclock = { 40800000, 51200000, 67200000 },
1867 .hactive = { 1024, 1024, 1024 },
1868 .hfront_porch = { 30, 106, 125 },
1869 .hback_porch = { 30, 106, 125 },
1870 .hsync_len = { 30, 108, 126 },
1871 .vactive = { 600, 600, 600 },
1872 .vfront_porch = { 3, 12, 67},
1873 .vback_porch = { 3, 12, 67 },
1874 .vsync_len = { 4, 11, 66 },
1875 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1876 DISPLAY_FLAGS_DE_HIGH,
1879 static const struct panel_desc edt_etml0700y5dha = {
1880 .timings = &edt_etml0700y5dha_timing,
1887 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
1888 .connector_type = DRM_MODE_CONNECTOR_LVDS,
1891 static const struct drm_display_mode edt_etmv570g2dhu_mode = {
1895 .hsync_end = 640 + 16,
1896 .htotal = 640 + 16 + 30 + 114,
1898 .vsync_start = 480 + 10,
1899 .vsync_end = 480 + 10 + 3,
1900 .vtotal = 480 + 10 + 3 + 35,
1901 .flags = DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_PHSYNC,
1904 static const struct panel_desc edt_etmv570g2dhu = {
1905 .modes = &edt_etmv570g2dhu_mode,
1912 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1913 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
1914 .connector_type = DRM_MODE_CONNECTOR_DPI,
1917 static const struct display_timing eink_vb3300_kca_timing = {
1918 .pixelclock = { 40000000, 40000000, 40000000 },
1919 .hactive = { 334, 334, 334 },
1920 .hfront_porch = { 1, 1, 1 },
1921 .hback_porch = { 1, 1, 1 },
1922 .hsync_len = { 1, 1, 1 },
1923 .vactive = { 1405, 1405, 1405 },
1924 .vfront_porch = { 1, 1, 1 },
1925 .vback_porch = { 1, 1, 1 },
1926 .vsync_len = { 1, 1, 1 },
1927 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
1928 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
1931 static const struct panel_desc eink_vb3300_kca = {
1932 .timings = &eink_vb3300_kca_timing,
1939 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1940 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
1941 .connector_type = DRM_MODE_CONNECTOR_DPI,
1944 static const struct display_timing evervision_vgg804821_timing = {
1945 .pixelclock = { 27600000, 33300000, 50000000 },
1946 .hactive = { 800, 800, 800 },
1947 .hfront_porch = { 40, 66, 70 },
1948 .hback_porch = { 40, 67, 70 },
1949 .hsync_len = { 40, 67, 70 },
1950 .vactive = { 480, 480, 480 },
1951 .vfront_porch = { 6, 10, 10 },
1952 .vback_porch = { 7, 11, 11 },
1953 .vsync_len = { 7, 11, 11 },
1954 .flags = DISPLAY_FLAGS_HSYNC_HIGH | DISPLAY_FLAGS_VSYNC_HIGH |
1955 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
1956 DISPLAY_FLAGS_SYNC_NEGEDGE,
1959 static const struct panel_desc evervision_vgg804821 = {
1960 .timings = &evervision_vgg804821_timing,
1967 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1968 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
1971 static const struct drm_display_mode foxlink_fl500wvr00_a0t_mode = {
1974 .hsync_start = 800 + 168,
1975 .hsync_end = 800 + 168 + 64,
1976 .htotal = 800 + 168 + 64 + 88,
1978 .vsync_start = 480 + 37,
1979 .vsync_end = 480 + 37 + 2,
1980 .vtotal = 480 + 37 + 2 + 8,
1983 static const struct panel_desc foxlink_fl500wvr00_a0t = {
1984 .modes = &foxlink_fl500wvr00_a0t_mode,
1991 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
1994 static const struct drm_display_mode frida_frd350h54004_modes[] = {
1998 .hsync_start = 320 + 44,
1999 .hsync_end = 320 + 44 + 16,
2000 .htotal = 320 + 44 + 16 + 20,
2002 .vsync_start = 240 + 2,
2003 .vsync_end = 240 + 2 + 6,
2004 .vtotal = 240 + 2 + 6 + 2,
2005 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2010 .hsync_start = 320 + 56,
2011 .hsync_end = 320 + 56 + 16,
2012 .htotal = 320 + 56 + 16 + 40,
2014 .vsync_start = 240 + 2,
2015 .vsync_end = 240 + 2 + 6,
2016 .vtotal = 240 + 2 + 6 + 2,
2017 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2021 static const struct panel_desc frida_frd350h54004 = {
2022 .modes = frida_frd350h54004_modes,
2023 .num_modes = ARRAY_SIZE(frida_frd350h54004_modes),
2029 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2030 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2031 .connector_type = DRM_MODE_CONNECTOR_DPI,
2034 static const struct drm_display_mode friendlyarm_hd702e_mode = {
2037 .hsync_start = 800 + 20,
2038 .hsync_end = 800 + 20 + 24,
2039 .htotal = 800 + 20 + 24 + 20,
2041 .vsync_start = 1280 + 4,
2042 .vsync_end = 1280 + 4 + 8,
2043 .vtotal = 1280 + 4 + 8 + 4,
2044 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2047 static const struct panel_desc friendlyarm_hd702e = {
2048 .modes = &friendlyarm_hd702e_mode,
2056 static const struct drm_display_mode giantplus_gpg482739qs5_mode = {
2059 .hsync_start = 480 + 5,
2060 .hsync_end = 480 + 5 + 1,
2061 .htotal = 480 + 5 + 1 + 40,
2063 .vsync_start = 272 + 8,
2064 .vsync_end = 272 + 8 + 1,
2065 .vtotal = 272 + 8 + 1 + 8,
2068 static const struct panel_desc giantplus_gpg482739qs5 = {
2069 .modes = &giantplus_gpg482739qs5_mode,
2076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2079 static const struct display_timing giantplus_gpm940b0_timing = {
2080 .pixelclock = { 13500000, 27000000, 27500000 },
2081 .hactive = { 320, 320, 320 },
2082 .hfront_porch = { 14, 686, 718 },
2083 .hback_porch = { 50, 70, 255 },
2084 .hsync_len = { 1, 1, 1 },
2085 .vactive = { 240, 240, 240 },
2086 .vfront_porch = { 1, 1, 179 },
2087 .vback_porch = { 1, 21, 31 },
2088 .vsync_len = { 1, 1, 6 },
2089 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
2092 static const struct panel_desc giantplus_gpm940b0 = {
2093 .timings = &giantplus_gpm940b0_timing,
2100 .bus_format = MEDIA_BUS_FMT_RGB888_3X8,
2101 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
2104 static const struct display_timing hannstar_hsd070pww1_timing = {
2105 .pixelclock = { 64300000, 71100000, 82000000 },
2106 .hactive = { 1280, 1280, 1280 },
2107 .hfront_porch = { 1, 1, 10 },
2108 .hback_porch = { 1, 1, 10 },
2110 * According to the data sheet, the minimum horizontal blanking interval
2111 * is 54 clocks (1 + 52 + 1), but tests with a Nitrogen6X have shown the
2112 * minimum working horizontal blanking interval to be 60 clocks.
2114 .hsync_len = { 58, 158, 661 },
2115 .vactive = { 800, 800, 800 },
2116 .vfront_porch = { 1, 1, 10 },
2117 .vback_porch = { 1, 1, 10 },
2118 .vsync_len = { 1, 21, 203 },
2119 .flags = DISPLAY_FLAGS_DE_HIGH,
2122 static const struct panel_desc hannstar_hsd070pww1 = {
2123 .timings = &hannstar_hsd070pww1_timing,
2130 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2131 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2134 static const struct display_timing hannstar_hsd100pxn1_timing = {
2135 .pixelclock = { 55000000, 65000000, 75000000 },
2136 .hactive = { 1024, 1024, 1024 },
2137 .hfront_porch = { 40, 40, 40 },
2138 .hback_porch = { 220, 220, 220 },
2139 .hsync_len = { 20, 60, 100 },
2140 .vactive = { 768, 768, 768 },
2141 .vfront_porch = { 7, 7, 7 },
2142 .vback_porch = { 21, 21, 21 },
2143 .vsync_len = { 10, 10, 10 },
2144 .flags = DISPLAY_FLAGS_DE_HIGH,
2147 static const struct panel_desc hannstar_hsd100pxn1 = {
2148 .timings = &hannstar_hsd100pxn1_timing,
2155 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2156 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2159 static const struct display_timing hannstar_hsd101pww2_timing = {
2160 .pixelclock = { 64300000, 71100000, 82000000 },
2161 .hactive = { 1280, 1280, 1280 },
2162 .hfront_porch = { 1, 1, 10 },
2163 .hback_porch = { 1, 1, 10 },
2164 .hsync_len = { 58, 158, 661 },
2165 .vactive = { 800, 800, 800 },
2166 .vfront_porch = { 1, 1, 10 },
2167 .vback_porch = { 1, 1, 10 },
2168 .vsync_len = { 1, 21, 203 },
2169 .flags = DISPLAY_FLAGS_DE_HIGH,
2172 static const struct panel_desc hannstar_hsd101pww2 = {
2173 .timings = &hannstar_hsd101pww2_timing,
2180 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2181 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2184 static const struct drm_display_mode hitachi_tx23d38vm0caa_mode = {
2187 .hsync_start = 800 + 85,
2188 .hsync_end = 800 + 85 + 86,
2189 .htotal = 800 + 85 + 86 + 85,
2191 .vsync_start = 480 + 16,
2192 .vsync_end = 480 + 16 + 13,
2193 .vtotal = 480 + 16 + 13 + 16,
2196 static const struct panel_desc hitachi_tx23d38vm0caa = {
2197 .modes = &hitachi_tx23d38vm0caa_mode,
2210 static const struct drm_display_mode innolux_at043tn24_mode = {
2213 .hsync_start = 480 + 2,
2214 .hsync_end = 480 + 2 + 41,
2215 .htotal = 480 + 2 + 41 + 2,
2217 .vsync_start = 272 + 2,
2218 .vsync_end = 272 + 2 + 10,
2219 .vtotal = 272 + 2 + 10 + 2,
2220 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2223 static const struct panel_desc innolux_at043tn24 = {
2224 .modes = &innolux_at043tn24_mode,
2231 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2232 .connector_type = DRM_MODE_CONNECTOR_DPI,
2233 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2236 static const struct drm_display_mode innolux_at070tn92_mode = {
2239 .hsync_start = 800 + 210,
2240 .hsync_end = 800 + 210 + 20,
2241 .htotal = 800 + 210 + 20 + 46,
2243 .vsync_start = 480 + 22,
2244 .vsync_end = 480 + 22 + 10,
2245 .vtotal = 480 + 22 + 23 + 10,
2248 static const struct panel_desc innolux_at070tn92 = {
2249 .modes = &innolux_at070tn92_mode,
2255 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2258 static const struct display_timing innolux_g070ace_l01_timing = {
2259 .pixelclock = { 25200000, 35000000, 35700000 },
2260 .hactive = { 800, 800, 800 },
2261 .hfront_porch = { 30, 32, 87 },
2262 .hback_porch = { 30, 32, 87 },
2263 .hsync_len = { 1, 1, 1 },
2264 .vactive = { 480, 480, 480 },
2265 .vfront_porch = { 3, 3, 3 },
2266 .vback_porch = { 13, 13, 13 },
2267 .vsync_len = { 1, 1, 4 },
2268 .flags = DISPLAY_FLAGS_DE_HIGH,
2271 static const struct panel_desc innolux_g070ace_l01 = {
2272 .timings = &innolux_g070ace_l01_timing,
2285 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2286 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2287 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2290 static const struct display_timing innolux_g070y2_l01_timing = {
2291 .pixelclock = { 28000000, 29500000, 32000000 },
2292 .hactive = { 800, 800, 800 },
2293 .hfront_porch = { 61, 91, 141 },
2294 .hback_porch = { 60, 90, 140 },
2295 .hsync_len = { 12, 12, 12 },
2296 .vactive = { 480, 480, 480 },
2297 .vfront_porch = { 4, 9, 30 },
2298 .vback_porch = { 4, 8, 28 },
2299 .vsync_len = { 2, 2, 2 },
2300 .flags = DISPLAY_FLAGS_DE_HIGH,
2303 static const struct panel_desc innolux_g070y2_l01 = {
2304 .timings = &innolux_g070y2_l01_timing,
2317 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2318 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2319 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2322 static const struct drm_display_mode innolux_g070y2_t02_mode = {
2325 .hsync_start = 800 + 210,
2326 .hsync_end = 800 + 210 + 20,
2327 .htotal = 800 + 210 + 20 + 46,
2329 .vsync_start = 480 + 22,
2330 .vsync_end = 480 + 22 + 10,
2331 .vtotal = 480 + 22 + 23 + 10,
2334 static const struct panel_desc innolux_g070y2_t02 = {
2335 .modes = &innolux_g070y2_t02_mode,
2342 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2343 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
2344 .connector_type = DRM_MODE_CONNECTOR_DPI,
2347 static const struct display_timing innolux_g101ice_l01_timing = {
2348 .pixelclock = { 60400000, 71100000, 74700000 },
2349 .hactive = { 1280, 1280, 1280 },
2350 .hfront_porch = { 41, 80, 100 },
2351 .hback_porch = { 40, 79, 99 },
2352 .hsync_len = { 1, 1, 1 },
2353 .vactive = { 800, 800, 800 },
2354 .vfront_porch = { 5, 11, 14 },
2355 .vback_porch = { 4, 11, 14 },
2356 .vsync_len = { 1, 1, 1 },
2357 .flags = DISPLAY_FLAGS_DE_HIGH,
2360 static const struct panel_desc innolux_g101ice_l01 = {
2361 .timings = &innolux_g101ice_l01_timing,
2372 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2373 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2376 static const struct display_timing innolux_g121i1_l01_timing = {
2377 .pixelclock = { 67450000, 71000000, 74550000 },
2378 .hactive = { 1280, 1280, 1280 },
2379 .hfront_porch = { 40, 80, 160 },
2380 .hback_porch = { 39, 79, 159 },
2381 .hsync_len = { 1, 1, 1 },
2382 .vactive = { 800, 800, 800 },
2383 .vfront_porch = { 5, 11, 100 },
2384 .vback_porch = { 4, 11, 99 },
2385 .vsync_len = { 1, 1, 1 },
2388 static const struct panel_desc innolux_g121i1_l01 = {
2389 .timings = &innolux_g121i1_l01_timing,
2400 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2401 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2404 static const struct drm_display_mode innolux_g121x1_l03_mode = {
2407 .hsync_start = 1024 + 0,
2408 .hsync_end = 1024 + 1,
2409 .htotal = 1024 + 0 + 1 + 320,
2411 .vsync_start = 768 + 38,
2412 .vsync_end = 768 + 38 + 1,
2413 .vtotal = 768 + 38 + 1 + 0,
2414 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2417 static const struct panel_desc innolux_g121x1_l03 = {
2418 .modes = &innolux_g121x1_l03_mode,
2432 static const struct display_timing innolux_g156hce_l01_timings = {
2433 .pixelclock = { 120000000, 141860000, 150000000 },
2434 .hactive = { 1920, 1920, 1920 },
2435 .hfront_porch = { 80, 90, 100 },
2436 .hback_porch = { 80, 90, 100 },
2437 .hsync_len = { 20, 30, 30 },
2438 .vactive = { 1080, 1080, 1080 },
2439 .vfront_porch = { 3, 10, 20 },
2440 .vback_porch = { 3, 10, 20 },
2441 .vsync_len = { 4, 10, 10 },
2444 static const struct panel_desc innolux_g156hce_l01 = {
2445 .timings = &innolux_g156hce_l01_timings,
2453 .prepare = 1, /* T1+T2 */
2454 .enable = 450, /* T5 */
2455 .disable = 200, /* T6 */
2456 .unprepare = 10, /* T3+T7 */
2458 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2459 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2460 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2463 static const struct drm_display_mode innolux_n156bge_l21_mode = {
2466 .hsync_start = 1366 + 16,
2467 .hsync_end = 1366 + 16 + 34,
2468 .htotal = 1366 + 16 + 34 + 50,
2470 .vsync_start = 768 + 2,
2471 .vsync_end = 768 + 2 + 6,
2472 .vtotal = 768 + 2 + 6 + 12,
2475 static const struct panel_desc innolux_n156bge_l21 = {
2476 .modes = &innolux_n156bge_l21_mode,
2483 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2484 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2485 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2488 static const struct drm_display_mode innolux_zj070na_01p_mode = {
2491 .hsync_start = 1024 + 128,
2492 .hsync_end = 1024 + 128 + 64,
2493 .htotal = 1024 + 128 + 64 + 128,
2495 .vsync_start = 600 + 16,
2496 .vsync_end = 600 + 16 + 4,
2497 .vtotal = 600 + 16 + 4 + 16,
2500 static const struct panel_desc innolux_zj070na_01p = {
2501 .modes = &innolux_zj070na_01p_mode,
2510 static const struct display_timing koe_tx14d24vm1bpa_timing = {
2511 .pixelclock = { 5580000, 5850000, 6200000 },
2512 .hactive = { 320, 320, 320 },
2513 .hfront_porch = { 30, 30, 30 },
2514 .hback_porch = { 30, 30, 30 },
2515 .hsync_len = { 1, 5, 17 },
2516 .vactive = { 240, 240, 240 },
2517 .vfront_porch = { 6, 6, 6 },
2518 .vback_porch = { 5, 5, 5 },
2519 .vsync_len = { 1, 2, 11 },
2520 .flags = DISPLAY_FLAGS_DE_HIGH,
2523 static const struct panel_desc koe_tx14d24vm1bpa = {
2524 .timings = &koe_tx14d24vm1bpa_timing,
2533 static const struct display_timing koe_tx26d202vm0bwa_timing = {
2534 .pixelclock = { 151820000, 156720000, 159780000 },
2535 .hactive = { 1920, 1920, 1920 },
2536 .hfront_porch = { 105, 130, 142 },
2537 .hback_porch = { 45, 70, 82 },
2538 .hsync_len = { 30, 30, 30 },
2539 .vactive = { 1200, 1200, 1200},
2540 .vfront_porch = { 3, 5, 10 },
2541 .vback_porch = { 2, 5, 10 },
2542 .vsync_len = { 5, 5, 5 },
2545 static const struct panel_desc koe_tx26d202vm0bwa = {
2546 .timings = &koe_tx26d202vm0bwa_timing,
2559 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2560 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2561 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2564 static const struct display_timing koe_tx31d200vm0baa_timing = {
2565 .pixelclock = { 39600000, 43200000, 48000000 },
2566 .hactive = { 1280, 1280, 1280 },
2567 .hfront_porch = { 16, 36, 56 },
2568 .hback_porch = { 16, 36, 56 },
2569 .hsync_len = { 8, 8, 8 },
2570 .vactive = { 480, 480, 480 },
2571 .vfront_porch = { 6, 21, 33 },
2572 .vback_porch = { 6, 21, 33 },
2573 .vsync_len = { 8, 8, 8 },
2574 .flags = DISPLAY_FLAGS_DE_HIGH,
2577 static const struct panel_desc koe_tx31d200vm0baa = {
2578 .timings = &koe_tx31d200vm0baa_timing,
2585 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
2586 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2589 static const struct display_timing kyo_tcg121xglp_timing = {
2590 .pixelclock = { 52000000, 65000000, 71000000 },
2591 .hactive = { 1024, 1024, 1024 },
2592 .hfront_porch = { 2, 2, 2 },
2593 .hback_porch = { 2, 2, 2 },
2594 .hsync_len = { 86, 124, 244 },
2595 .vactive = { 768, 768, 768 },
2596 .vfront_porch = { 2, 2, 2 },
2597 .vback_porch = { 2, 2, 2 },
2598 .vsync_len = { 6, 34, 73 },
2599 .flags = DISPLAY_FLAGS_DE_HIGH,
2602 static const struct panel_desc kyo_tcg121xglp = {
2603 .timings = &kyo_tcg121xglp_timing,
2610 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2611 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2614 static const struct drm_display_mode lemaker_bl035_rgb_002_mode = {
2617 .hsync_start = 320 + 20,
2618 .hsync_end = 320 + 20 + 30,
2619 .htotal = 320 + 20 + 30 + 38,
2621 .vsync_start = 240 + 4,
2622 .vsync_end = 240 + 4 + 3,
2623 .vtotal = 240 + 4 + 3 + 15,
2626 static const struct panel_desc lemaker_bl035_rgb_002 = {
2627 .modes = &lemaker_bl035_rgb_002_mode,
2633 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2634 .bus_flags = DRM_BUS_FLAG_DE_LOW,
2637 static const struct drm_display_mode lg_lb070wv8_mode = {
2640 .hsync_start = 800 + 88,
2641 .hsync_end = 800 + 88 + 80,
2642 .htotal = 800 + 88 + 80 + 88,
2644 .vsync_start = 480 + 10,
2645 .vsync_end = 480 + 10 + 25,
2646 .vtotal = 480 + 10 + 25 + 10,
2649 static const struct panel_desc lg_lb070wv8 = {
2650 .modes = &lg_lb070wv8_mode,
2657 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2658 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2661 static const struct display_timing logictechno_lt161010_2nh_timing = {
2662 .pixelclock = { 26400000, 33300000, 46800000 },
2663 .hactive = { 800, 800, 800 },
2664 .hfront_porch = { 16, 210, 354 },
2665 .hback_porch = { 46, 46, 46 },
2666 .hsync_len = { 1, 20, 40 },
2667 .vactive = { 480, 480, 480 },
2668 .vfront_porch = { 7, 22, 147 },
2669 .vback_porch = { 23, 23, 23 },
2670 .vsync_len = { 1, 10, 20 },
2671 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2672 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2673 DISPLAY_FLAGS_SYNC_POSEDGE,
2676 static const struct panel_desc logictechno_lt161010_2nh = {
2677 .timings = &logictechno_lt161010_2nh_timing,
2684 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
2685 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2686 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2687 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2688 .connector_type = DRM_MODE_CONNECTOR_DPI,
2691 static const struct display_timing logictechno_lt170410_2whc_timing = {
2692 .pixelclock = { 68900000, 71100000, 73400000 },
2693 .hactive = { 1280, 1280, 1280 },
2694 .hfront_porch = { 23, 60, 71 },
2695 .hback_porch = { 23, 60, 71 },
2696 .hsync_len = { 15, 40, 47 },
2697 .vactive = { 800, 800, 800 },
2698 .vfront_porch = { 5, 7, 10 },
2699 .vback_porch = { 5, 7, 10 },
2700 .vsync_len = { 6, 9, 12 },
2701 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2702 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2703 DISPLAY_FLAGS_SYNC_POSEDGE,
2706 static const struct panel_desc logictechno_lt170410_2whc = {
2707 .timings = &logictechno_lt170410_2whc_timing,
2714 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2715 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2716 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2719 static const struct drm_display_mode logictechno_lttd800480070_l2rt_mode = {
2722 .hsync_start = 800 + 112,
2723 .hsync_end = 800 + 112 + 3,
2724 .htotal = 800 + 112 + 3 + 85,
2726 .vsync_start = 480 + 38,
2727 .vsync_end = 480 + 38 + 3,
2728 .vtotal = 480 + 38 + 3 + 29,
2729 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2732 static const struct panel_desc logictechno_lttd800480070_l2rt = {
2733 .modes = &logictechno_lttd800480070_l2rt_mode,
2746 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2747 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2748 .connector_type = DRM_MODE_CONNECTOR_DPI,
2751 static const struct drm_display_mode logictechno_lttd800480070_l6wh_rt_mode = {
2754 .hsync_start = 800 + 154,
2755 .hsync_end = 800 + 154 + 3,
2756 .htotal = 800 + 154 + 3 + 43,
2758 .vsync_start = 480 + 47,
2759 .vsync_end = 480 + 47 + 3,
2760 .vtotal = 480 + 47 + 3 + 20,
2761 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
2764 static const struct panel_desc logictechno_lttd800480070_l6wh_rt = {
2765 .modes = &logictechno_lttd800480070_l6wh_rt_mode,
2778 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2779 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2780 .connector_type = DRM_MODE_CONNECTOR_DPI,
2783 static const struct drm_display_mode logicpd_type_28_mode = {
2786 .hsync_start = 480 + 3,
2787 .hsync_end = 480 + 3 + 42,
2788 .htotal = 480 + 3 + 42 + 2,
2791 .vsync_start = 272 + 2,
2792 .vsync_end = 272 + 2 + 11,
2793 .vtotal = 272 + 2 + 11 + 3,
2794 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2797 static const struct panel_desc logicpd_type_28 = {
2798 .modes = &logicpd_type_28_mode,
2811 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2812 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
2813 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE,
2814 .connector_type = DRM_MODE_CONNECTOR_DPI,
2817 static const struct drm_display_mode mitsubishi_aa070mc01_mode = {
2820 .hsync_start = 800 + 0,
2821 .hsync_end = 800 + 1,
2822 .htotal = 800 + 0 + 1 + 160,
2824 .vsync_start = 480 + 0,
2825 .vsync_end = 480 + 48 + 1,
2826 .vtotal = 480 + 48 + 1 + 0,
2827 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
2830 static const struct panel_desc mitsubishi_aa070mc01 = {
2831 .modes = &mitsubishi_aa070mc01_mode,
2844 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2845 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2846 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2849 static const struct drm_display_mode mitsubishi_aa084xe01_mode = {
2852 .hsync_start = 1024 + 24,
2853 .hsync_end = 1024 + 24 + 63,
2854 .htotal = 1024 + 24 + 63 + 1,
2856 .vsync_start = 768 + 3,
2857 .vsync_end = 768 + 3 + 6,
2858 .vtotal = 768 + 3 + 6 + 1,
2859 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
2862 static const struct panel_desc mitsubishi_aa084xe01 = {
2863 .modes = &mitsubishi_aa084xe01_mode,
2870 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
2871 .connector_type = DRM_MODE_CONNECTOR_DPI,
2872 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
2875 static const struct display_timing multi_inno_mi0700s4t_6_timing = {
2876 .pixelclock = { 29000000, 33000000, 38000000 },
2877 .hactive = { 800, 800, 800 },
2878 .hfront_porch = { 180, 210, 240 },
2879 .hback_porch = { 16, 16, 16 },
2880 .hsync_len = { 30, 30, 30 },
2881 .vactive = { 480, 480, 480 },
2882 .vfront_porch = { 12, 22, 32 },
2883 .vback_porch = { 10, 10, 10 },
2884 .vsync_len = { 13, 13, 13 },
2885 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2886 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2887 DISPLAY_FLAGS_SYNC_POSEDGE,
2890 static const struct panel_desc multi_inno_mi0700s4t_6 = {
2891 .timings = &multi_inno_mi0700s4t_6_timing,
2898 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2899 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2900 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2901 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2902 .connector_type = DRM_MODE_CONNECTOR_DPI,
2905 static const struct display_timing multi_inno_mi0800ft_9_timing = {
2906 .pixelclock = { 32000000, 40000000, 50000000 },
2907 .hactive = { 800, 800, 800 },
2908 .hfront_porch = { 16, 210, 354 },
2909 .hback_porch = { 6, 26, 45 },
2910 .hsync_len = { 1, 20, 40 },
2911 .vactive = { 600, 600, 600 },
2912 .vfront_porch = { 1, 12, 77 },
2913 .vback_porch = { 3, 13, 22 },
2914 .vsync_len = { 1, 10, 20 },
2915 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2916 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
2917 DISPLAY_FLAGS_SYNC_POSEDGE,
2920 static const struct panel_desc multi_inno_mi0800ft_9 = {
2921 .timings = &multi_inno_mi0800ft_9_timing,
2928 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
2929 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
2930 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
2931 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
2932 .connector_type = DRM_MODE_CONNECTOR_DPI,
2935 static const struct display_timing multi_inno_mi1010ait_1cp_timing = {
2936 .pixelclock = { 68900000, 70000000, 73400000 },
2937 .hactive = { 1280, 1280, 1280 },
2938 .hfront_porch = { 30, 60, 71 },
2939 .hback_porch = { 30, 60, 71 },
2940 .hsync_len = { 10, 10, 48 },
2941 .vactive = { 800, 800, 800 },
2942 .vfront_porch = { 5, 10, 10 },
2943 .vback_porch = { 5, 10, 10 },
2944 .vsync_len = { 5, 6, 13 },
2945 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
2946 DISPLAY_FLAGS_DE_HIGH,
2949 static const struct panel_desc multi_inno_mi1010ait_1cp = {
2950 .timings = &multi_inno_mi1010ait_1cp_timing,
2961 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2962 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
2963 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2966 static const struct display_timing nec_nl12880bc20_05_timing = {
2967 .pixelclock = { 67000000, 71000000, 75000000 },
2968 .hactive = { 1280, 1280, 1280 },
2969 .hfront_porch = { 2, 30, 30 },
2970 .hback_porch = { 6, 100, 100 },
2971 .hsync_len = { 2, 30, 30 },
2972 .vactive = { 800, 800, 800 },
2973 .vfront_porch = { 5, 5, 5 },
2974 .vback_porch = { 11, 11, 11 },
2975 .vsync_len = { 7, 7, 7 },
2978 static const struct panel_desc nec_nl12880bc20_05 = {
2979 .timings = &nec_nl12880bc20_05_timing,
2990 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
2991 .connector_type = DRM_MODE_CONNECTOR_LVDS,
2994 static const struct drm_display_mode nec_nl4827hc19_05b_mode = {
2997 .hsync_start = 480 + 2,
2998 .hsync_end = 480 + 2 + 41,
2999 .htotal = 480 + 2 + 41 + 2,
3001 .vsync_start = 272 + 2,
3002 .vsync_end = 272 + 2 + 4,
3003 .vtotal = 272 + 2 + 4 + 2,
3004 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3007 static const struct panel_desc nec_nl4827hc19_05b = {
3008 .modes = &nec_nl4827hc19_05b_mode,
3015 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3016 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3019 static const struct drm_display_mode netron_dy_e231732_mode = {
3022 .hsync_start = 1024 + 160,
3023 .hsync_end = 1024 + 160 + 70,
3024 .htotal = 1024 + 160 + 70 + 90,
3026 .vsync_start = 600 + 127,
3027 .vsync_end = 600 + 127 + 20,
3028 .vtotal = 600 + 127 + 20 + 3,
3031 static const struct panel_desc netron_dy_e231732 = {
3032 .modes = &netron_dy_e231732_mode,
3038 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3041 static const struct drm_display_mode newhaven_nhd_43_480272ef_atxl_mode = {
3044 .hsync_start = 480 + 2,
3045 .hsync_end = 480 + 2 + 41,
3046 .htotal = 480 + 2 + 41 + 2,
3048 .vsync_start = 272 + 2,
3049 .vsync_end = 272 + 2 + 10,
3050 .vtotal = 272 + 2 + 10 + 2,
3051 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3054 static const struct panel_desc newhaven_nhd_43_480272ef_atxl = {
3055 .modes = &newhaven_nhd_43_480272ef_atxl_mode,
3062 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3063 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3064 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3065 .connector_type = DRM_MODE_CONNECTOR_DPI,
3068 static const struct display_timing nlt_nl192108ac18_02d_timing = {
3069 .pixelclock = { 130000000, 148350000, 163000000 },
3070 .hactive = { 1920, 1920, 1920 },
3071 .hfront_porch = { 80, 100, 100 },
3072 .hback_porch = { 100, 120, 120 },
3073 .hsync_len = { 50, 60, 60 },
3074 .vactive = { 1080, 1080, 1080 },
3075 .vfront_porch = { 12, 30, 30 },
3076 .vback_porch = { 4, 10, 10 },
3077 .vsync_len = { 4, 5, 5 },
3080 static const struct panel_desc nlt_nl192108ac18_02d = {
3081 .timings = &nlt_nl192108ac18_02d_timing,
3091 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3092 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3095 static const struct drm_display_mode nvd_9128_mode = {
3098 .hsync_start = 800 + 130,
3099 .hsync_end = 800 + 130 + 98,
3100 .htotal = 800 + 0 + 130 + 98,
3102 .vsync_start = 480 + 10,
3103 .vsync_end = 480 + 10 + 50,
3104 .vtotal = 480 + 0 + 10 + 50,
3107 static const struct panel_desc nvd_9128 = {
3108 .modes = &nvd_9128_mode,
3115 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3116 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3119 static const struct display_timing okaya_rs800480t_7x0gp_timing = {
3120 .pixelclock = { 30000000, 30000000, 40000000 },
3121 .hactive = { 800, 800, 800 },
3122 .hfront_porch = { 40, 40, 40 },
3123 .hback_porch = { 40, 40, 40 },
3124 .hsync_len = { 1, 48, 48 },
3125 .vactive = { 480, 480, 480 },
3126 .vfront_porch = { 13, 13, 13 },
3127 .vback_porch = { 29, 29, 29 },
3128 .vsync_len = { 3, 3, 3 },
3129 .flags = DISPLAY_FLAGS_DE_HIGH,
3132 static const struct panel_desc okaya_rs800480t_7x0gp = {
3133 .timings = &okaya_rs800480t_7x0gp_timing,
3146 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3149 static const struct drm_display_mode olimex_lcd_olinuxino_43ts_mode = {
3152 .hsync_start = 480 + 5,
3153 .hsync_end = 480 + 5 + 30,
3154 .htotal = 480 + 5 + 30 + 10,
3156 .vsync_start = 272 + 8,
3157 .vsync_end = 272 + 8 + 5,
3158 .vtotal = 272 + 8 + 5 + 3,
3161 static const struct panel_desc olimex_lcd_olinuxino_43ts = {
3162 .modes = &olimex_lcd_olinuxino_43ts_mode,
3168 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3172 * 800x480 CVT. The panel appears to be quite accepting, at least as far as
3173 * pixel clocks, but this is the timing that was being used in the Adafruit
3174 * installation instructions.
3176 static const struct drm_display_mode ontat_yx700wv03_mode = {
3186 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3191 * https://www.adafruit.com/images/product-files/2406/c3163.pdf
3193 static const struct panel_desc ontat_yx700wv03 = {
3194 .modes = &ontat_yx700wv03_mode,
3201 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3204 static const struct drm_display_mode ortustech_com37h3m_mode = {
3207 .hsync_start = 480 + 40,
3208 .hsync_end = 480 + 40 + 10,
3209 .htotal = 480 + 40 + 10 + 40,
3211 .vsync_start = 640 + 4,
3212 .vsync_end = 640 + 4 + 2,
3213 .vtotal = 640 + 4 + 2 + 4,
3214 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3217 static const struct panel_desc ortustech_com37h3m = {
3218 .modes = &ortustech_com37h3m_mode,
3222 .width = 56, /* 56.16mm */
3223 .height = 75, /* 74.88mm */
3225 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3226 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3227 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3230 static const struct drm_display_mode ortustech_com43h4m85ulc_mode = {
3233 .hsync_start = 480 + 10,
3234 .hsync_end = 480 + 10 + 10,
3235 .htotal = 480 + 10 + 10 + 15,
3237 .vsync_start = 800 + 3,
3238 .vsync_end = 800 + 3 + 3,
3239 .vtotal = 800 + 3 + 3 + 3,
3242 static const struct panel_desc ortustech_com43h4m85ulc = {
3243 .modes = &ortustech_com43h4m85ulc_mode,
3250 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3251 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3252 .connector_type = DRM_MODE_CONNECTOR_DPI,
3255 static const struct drm_display_mode osddisplays_osd070t1718_19ts_mode = {
3258 .hsync_start = 800 + 210,
3259 .hsync_end = 800 + 210 + 30,
3260 .htotal = 800 + 210 + 30 + 16,
3262 .vsync_start = 480 + 22,
3263 .vsync_end = 480 + 22 + 13,
3264 .vtotal = 480 + 22 + 13 + 10,
3265 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3268 static const struct panel_desc osddisplays_osd070t1718_19ts = {
3269 .modes = &osddisplays_osd070t1718_19ts_mode,
3276 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3277 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE |
3278 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3279 .connector_type = DRM_MODE_CONNECTOR_DPI,
3282 static const struct drm_display_mode pda_91_00156_a0_mode = {
3285 .hsync_start = 800 + 1,
3286 .hsync_end = 800 + 1 + 64,
3287 .htotal = 800 + 1 + 64 + 64,
3289 .vsync_start = 480 + 1,
3290 .vsync_end = 480 + 1 + 23,
3291 .vtotal = 480 + 1 + 23 + 22,
3294 static const struct panel_desc pda_91_00156_a0 = {
3295 .modes = &pda_91_00156_a0_mode,
3301 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3304 static const struct drm_display_mode powertip_ph800480t013_idf02_mode = {
3307 .hsync_start = 800 + 54,
3308 .hsync_end = 800 + 54 + 2,
3309 .htotal = 800 + 54 + 2 + 44,
3311 .vsync_start = 480 + 49,
3312 .vsync_end = 480 + 49 + 2,
3313 .vtotal = 480 + 49 + 2 + 22,
3314 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3317 static const struct panel_desc powertip_ph800480t013_idf02 = {
3318 .modes = &powertip_ph800480t013_idf02_mode,
3325 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3326 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3327 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3328 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3329 .connector_type = DRM_MODE_CONNECTOR_DPI,
3332 static const struct drm_display_mode qd43003c0_40_mode = {
3335 .hsync_start = 480 + 8,
3336 .hsync_end = 480 + 8 + 4,
3337 .htotal = 480 + 8 + 4 + 39,
3339 .vsync_start = 272 + 4,
3340 .vsync_end = 272 + 4 + 10,
3341 .vtotal = 272 + 4 + 10 + 2,
3344 static const struct panel_desc qd43003c0_40 = {
3345 .modes = &qd43003c0_40_mode,
3352 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3355 static const struct drm_display_mode qishenglong_gopher2b_lcd_modes[] = {
3359 .hsync_start = 480 + 77,
3360 .hsync_end = 480 + 77 + 41,
3361 .htotal = 480 + 77 + 41 + 2,
3363 .vsync_start = 272 + 16,
3364 .vsync_end = 272 + 16 + 10,
3365 .vtotal = 272 + 16 + 10 + 2,
3366 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3371 .hsync_start = 480 + 17,
3372 .hsync_end = 480 + 17 + 41,
3373 .htotal = 480 + 17 + 41 + 2,
3375 .vsync_start = 272 + 116,
3376 .vsync_end = 272 + 116 + 10,
3377 .vtotal = 272 + 116 + 10 + 2,
3378 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3382 static const struct panel_desc qishenglong_gopher2b_lcd = {
3383 .modes = qishenglong_gopher2b_lcd_modes,
3384 .num_modes = ARRAY_SIZE(qishenglong_gopher2b_lcd_modes),
3390 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3391 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3392 .connector_type = DRM_MODE_CONNECTOR_DPI,
3395 static const struct display_timing rocktech_rk043fn48h_timing = {
3396 .pixelclock = { 6000000, 9000000, 12000000 },
3397 .hactive = { 480, 480, 480 },
3398 .hback_porch = { 8, 43, 43 },
3399 .hfront_porch = { 2, 8, 8 },
3400 .hsync_len = { 1, 1, 1 },
3401 .vactive = { 272, 272, 272 },
3402 .vback_porch = { 2, 12, 12 },
3403 .vfront_porch = { 1, 4, 4 },
3404 .vsync_len = { 1, 10, 10 },
3405 .flags = DISPLAY_FLAGS_VSYNC_LOW | DISPLAY_FLAGS_HSYNC_LOW |
3406 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3409 static const struct panel_desc rocktech_rk043fn48h = {
3410 .timings = &rocktech_rk043fn48h_timing,
3417 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3418 .connector_type = DRM_MODE_CONNECTOR_DPI,
3421 static const struct display_timing rocktech_rk070er9427_timing = {
3422 .pixelclock = { 26400000, 33300000, 46800000 },
3423 .hactive = { 800, 800, 800 },
3424 .hfront_porch = { 16, 210, 354 },
3425 .hback_porch = { 46, 46, 46 },
3426 .hsync_len = { 1, 1, 1 },
3427 .vactive = { 480, 480, 480 },
3428 .vfront_porch = { 7, 22, 147 },
3429 .vback_porch = { 23, 23, 23 },
3430 .vsync_len = { 1, 1, 1 },
3431 .flags = DISPLAY_FLAGS_DE_HIGH,
3434 static const struct panel_desc rocktech_rk070er9427 = {
3435 .timings = &rocktech_rk070er9427_timing,
3448 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3451 static const struct drm_display_mode rocktech_rk101ii01d_ct_mode = {
3454 .hsync_start = 1280 + 48,
3455 .hsync_end = 1280 + 48 + 32,
3456 .htotal = 1280 + 48 + 32 + 80,
3458 .vsync_start = 800 + 2,
3459 .vsync_end = 800 + 2 + 5,
3460 .vtotal = 800 + 2 + 5 + 16,
3463 static const struct panel_desc rocktech_rk101ii01d_ct = {
3464 .modes = &rocktech_rk101ii01d_ct_mode,
3475 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3476 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3477 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3480 static const struct display_timing samsung_ltl101al01_timing = {
3481 .pixelclock = { 66663000, 66663000, 66663000 },
3482 .hactive = { 1280, 1280, 1280 },
3483 .hfront_porch = { 18, 18, 18 },
3484 .hback_porch = { 36, 36, 36 },
3485 .hsync_len = { 16, 16, 16 },
3486 .vactive = { 800, 800, 800 },
3487 .vfront_porch = { 4, 4, 4 },
3488 .vback_porch = { 16, 16, 16 },
3489 .vsync_len = { 3, 3, 3 },
3490 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
3493 static const struct panel_desc samsung_ltl101al01 = {
3494 .timings = &samsung_ltl101al01_timing,
3507 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3508 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3511 static const struct drm_display_mode samsung_ltn101nt05_mode = {
3514 .hsync_start = 1024 + 24,
3515 .hsync_end = 1024 + 24 + 136,
3516 .htotal = 1024 + 24 + 136 + 160,
3518 .vsync_start = 600 + 3,
3519 .vsync_end = 600 + 3 + 6,
3520 .vtotal = 600 + 3 + 6 + 61,
3523 static const struct panel_desc samsung_ltn101nt05 = {
3524 .modes = &samsung_ltn101nt05_mode,
3531 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
3532 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3533 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3536 static const struct display_timing satoz_sat050at40h12r2_timing = {
3537 .pixelclock = {33300000, 33300000, 50000000},
3538 .hactive = {800, 800, 800},
3539 .hfront_porch = {16, 210, 354},
3540 .hback_porch = {46, 46, 46},
3541 .hsync_len = {1, 1, 40},
3542 .vactive = {480, 480, 480},
3543 .vfront_porch = {7, 22, 147},
3544 .vback_porch = {23, 23, 23},
3545 .vsync_len = {1, 1, 20},
3548 static const struct panel_desc satoz_sat050at40h12r2 = {
3549 .timings = &satoz_sat050at40h12r2_timing,
3556 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3557 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3560 static const struct drm_display_mode sharp_lq070y3dg3b_mode = {
3563 .hsync_start = 800 + 64,
3564 .hsync_end = 800 + 64 + 128,
3565 .htotal = 800 + 64 + 128 + 64,
3567 .vsync_start = 480 + 8,
3568 .vsync_end = 480 + 8 + 2,
3569 .vtotal = 480 + 8 + 2 + 35,
3570 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3573 static const struct panel_desc sharp_lq070y3dg3b = {
3574 .modes = &sharp_lq070y3dg3b_mode,
3578 .width = 152, /* 152.4mm */
3579 .height = 91, /* 91.4mm */
3581 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3582 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3583 DRM_BUS_FLAG_SYNC_DRIVE_POSEDGE,
3586 static const struct drm_display_mode sharp_lq035q7db03_mode = {
3589 .hsync_start = 240 + 16,
3590 .hsync_end = 240 + 16 + 7,
3591 .htotal = 240 + 16 + 7 + 5,
3593 .vsync_start = 320 + 9,
3594 .vsync_end = 320 + 9 + 1,
3595 .vtotal = 320 + 9 + 1 + 7,
3598 static const struct panel_desc sharp_lq035q7db03 = {
3599 .modes = &sharp_lq035q7db03_mode,
3606 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3609 static const struct display_timing sharp_lq101k1ly04_timing = {
3610 .pixelclock = { 60000000, 65000000, 80000000 },
3611 .hactive = { 1280, 1280, 1280 },
3612 .hfront_porch = { 20, 20, 20 },
3613 .hback_porch = { 20, 20, 20 },
3614 .hsync_len = { 10, 10, 10 },
3615 .vactive = { 800, 800, 800 },
3616 .vfront_porch = { 4, 4, 4 },
3617 .vback_porch = { 4, 4, 4 },
3618 .vsync_len = { 4, 4, 4 },
3619 .flags = DISPLAY_FLAGS_PIXDATA_POSEDGE,
3622 static const struct panel_desc sharp_lq101k1ly04 = {
3623 .timings = &sharp_lq101k1ly04_timing,
3630 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3631 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3634 static const struct drm_display_mode sharp_ls020b1dd01d_modes[] = {
3638 .hsync_start = 240 + 58,
3639 .hsync_end = 240 + 58 + 1,
3640 .htotal = 240 + 58 + 1 + 1,
3642 .vsync_start = 160 + 24,
3643 .vsync_end = 160 + 24 + 10,
3644 .vtotal = 160 + 24 + 10 + 6,
3645 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3650 .hsync_start = 240 + 8,
3651 .hsync_end = 240 + 8 + 1,
3652 .htotal = 240 + 8 + 1 + 1,
3654 .vsync_start = 160 + 24,
3655 .vsync_end = 160 + 24 + 10,
3656 .vtotal = 160 + 24 + 10 + 6,
3657 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC,
3661 static const struct panel_desc sharp_ls020b1dd01d = {
3662 .modes = sharp_ls020b1dd01d_modes,
3663 .num_modes = ARRAY_SIZE(sharp_ls020b1dd01d_modes),
3669 .bus_format = MEDIA_BUS_FMT_RGB565_1X16,
3670 .bus_flags = DRM_BUS_FLAG_DE_HIGH
3671 | DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE
3672 | DRM_BUS_FLAG_SHARP_SIGNALS,
3675 static const struct drm_display_mode shelly_sca07010_bfn_lnn_mode = {
3678 .hsync_start = 800 + 1,
3679 .hsync_end = 800 + 1 + 64,
3680 .htotal = 800 + 1 + 64 + 64,
3682 .vsync_start = 480 + 1,
3683 .vsync_end = 480 + 1 + 23,
3684 .vtotal = 480 + 1 + 23 + 22,
3687 static const struct panel_desc shelly_sca07010_bfn_lnn = {
3688 .modes = &shelly_sca07010_bfn_lnn_mode,
3694 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
3697 static const struct drm_display_mode starry_kr070pe2t_mode = {
3700 .hsync_start = 800 + 209,
3701 .hsync_end = 800 + 209 + 1,
3702 .htotal = 800 + 209 + 1 + 45,
3704 .vsync_start = 480 + 22,
3705 .vsync_end = 480 + 22 + 1,
3706 .vtotal = 480 + 22 + 1 + 22,
3709 static const struct panel_desc starry_kr070pe2t = {
3710 .modes = &starry_kr070pe2t_mode,
3717 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3718 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE,
3719 .connector_type = DRM_MODE_CONNECTOR_DPI,
3722 static const struct display_timing startek_kd070wvfpa_mode = {
3723 .pixelclock = { 25200000, 27200000, 30500000 },
3724 .hactive = { 800, 800, 800 },
3725 .hfront_porch = { 19, 44, 115 },
3726 .hback_porch = { 5, 16, 101 },
3727 .hsync_len = { 1, 2, 100 },
3728 .vactive = { 480, 480, 480 },
3729 .vfront_porch = { 5, 43, 67 },
3730 .vback_porch = { 5, 5, 67 },
3731 .vsync_len = { 1, 2, 66 },
3732 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3733 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE |
3734 DISPLAY_FLAGS_SYNC_POSEDGE,
3737 static const struct panel_desc startek_kd070wvfpa = {
3738 .timings = &startek_kd070wvfpa_mode,
3750 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3751 .connector_type = DRM_MODE_CONNECTOR_DPI,
3752 .bus_flags = DRM_BUS_FLAG_DE_HIGH |
3753 DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE |
3754 DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE,
3757 static const struct display_timing tsd_tst043015cmhx_timing = {
3758 .pixelclock = { 5000000, 9000000, 12000000 },
3759 .hactive = { 480, 480, 480 },
3760 .hfront_porch = { 4, 5, 65 },
3761 .hback_porch = { 36, 40, 255 },
3762 .hsync_len = { 1, 1, 1 },
3763 .vactive = { 272, 272, 272 },
3764 .vfront_porch = { 2, 8, 97 },
3765 .vback_porch = { 3, 8, 31 },
3766 .vsync_len = { 1, 1, 1 },
3768 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
3769 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_POSEDGE,
3772 static const struct panel_desc tsd_tst043015cmhx = {
3773 .timings = &tsd_tst043015cmhx_timing,
3780 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3781 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3784 static const struct drm_display_mode tfc_s9700rtwv43tr_01b_mode = {
3787 .hsync_start = 800 + 39,
3788 .hsync_end = 800 + 39 + 47,
3789 .htotal = 800 + 39 + 47 + 39,
3791 .vsync_start = 480 + 13,
3792 .vsync_end = 480 + 13 + 2,
3793 .vtotal = 480 + 13 + 2 + 29,
3796 static const struct panel_desc tfc_s9700rtwv43tr_01b = {
3797 .modes = &tfc_s9700rtwv43tr_01b_mode,
3804 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3805 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3808 static const struct display_timing tianma_tm070jdhg30_timing = {
3809 .pixelclock = { 62600000, 68200000, 78100000 },
3810 .hactive = { 1280, 1280, 1280 },
3811 .hfront_porch = { 15, 64, 159 },
3812 .hback_porch = { 5, 5, 5 },
3813 .hsync_len = { 1, 1, 256 },
3814 .vactive = { 800, 800, 800 },
3815 .vfront_porch = { 3, 40, 99 },
3816 .vback_porch = { 2, 2, 2 },
3817 .vsync_len = { 1, 1, 128 },
3818 .flags = DISPLAY_FLAGS_DE_HIGH,
3821 static const struct panel_desc tianma_tm070jdhg30 = {
3822 .timings = &tianma_tm070jdhg30_timing,
3829 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3830 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3833 static const struct panel_desc tianma_tm070jvhg33 = {
3834 .timings = &tianma_tm070jdhg30_timing,
3841 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3842 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3845 static const struct display_timing tianma_tm070rvhg71_timing = {
3846 .pixelclock = { 27700000, 29200000, 39600000 },
3847 .hactive = { 800, 800, 800 },
3848 .hfront_porch = { 12, 40, 212 },
3849 .hback_porch = { 88, 88, 88 },
3850 .hsync_len = { 1, 1, 40 },
3851 .vactive = { 480, 480, 480 },
3852 .vfront_porch = { 1, 13, 88 },
3853 .vback_porch = { 32, 32, 32 },
3854 .vsync_len = { 1, 1, 3 },
3855 .flags = DISPLAY_FLAGS_DE_HIGH,
3858 static const struct panel_desc tianma_tm070rvhg71 = {
3859 .timings = &tianma_tm070rvhg71_timing,
3866 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
3867 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3870 static const struct drm_display_mode ti_nspire_cx_lcd_mode[] = {
3874 .hsync_start = 320 + 50,
3875 .hsync_end = 320 + 50 + 6,
3876 .htotal = 320 + 50 + 6 + 38,
3878 .vsync_start = 240 + 3,
3879 .vsync_end = 240 + 3 + 1,
3880 .vtotal = 240 + 3 + 1 + 17,
3881 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
3885 static const struct panel_desc ti_nspire_cx_lcd_panel = {
3886 .modes = ti_nspire_cx_lcd_mode,
3893 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
3894 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE,
3897 static const struct drm_display_mode ti_nspire_classic_lcd_mode[] = {
3901 .hsync_start = 320 + 6,
3902 .hsync_end = 320 + 6 + 6,
3903 .htotal = 320 + 6 + 6 + 6,
3905 .vsync_start = 240 + 0,
3906 .vsync_end = 240 + 0 + 1,
3907 .vtotal = 240 + 0 + 1 + 0,
3908 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
3912 static const struct panel_desc ti_nspire_classic_lcd_panel = {
3913 .modes = ti_nspire_classic_lcd_mode,
3915 /* The grayscale panel has 8 bit for the color .. Y (black) */
3921 /* This is the grayscale bus format */
3922 .bus_format = MEDIA_BUS_FMT_Y8_1X8,
3923 .bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
3926 static const struct drm_display_mode toshiba_lt089ac29000_mode = {
3929 .hsync_start = 1280 + 192,
3930 .hsync_end = 1280 + 192 + 128,
3931 .htotal = 1280 + 192 + 128 + 64,
3933 .vsync_start = 768 + 20,
3934 .vsync_end = 768 + 20 + 7,
3935 .vtotal = 768 + 20 + 7 + 3,
3938 static const struct panel_desc toshiba_lt089ac29000 = {
3939 .modes = &toshiba_lt089ac29000_mode,
3945 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
3946 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
3947 .connector_type = DRM_MODE_CONNECTOR_LVDS,
3950 static const struct drm_display_mode tpk_f07a_0102_mode = {
3953 .hsync_start = 800 + 40,
3954 .hsync_end = 800 + 40 + 128,
3955 .htotal = 800 + 40 + 128 + 88,
3957 .vsync_start = 480 + 10,
3958 .vsync_end = 480 + 10 + 2,
3959 .vtotal = 480 + 10 + 2 + 33,
3962 static const struct panel_desc tpk_f07a_0102 = {
3963 .modes = &tpk_f07a_0102_mode,
3969 .bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE,
3972 static const struct drm_display_mode tpk_f10a_0102_mode = {
3975 .hsync_start = 1024 + 176,
3976 .hsync_end = 1024 + 176 + 5,
3977 .htotal = 1024 + 176 + 5 + 88,
3979 .vsync_start = 600 + 20,
3980 .vsync_end = 600 + 20 + 5,
3981 .vtotal = 600 + 20 + 5 + 25,
3984 static const struct panel_desc tpk_f10a_0102 = {
3985 .modes = &tpk_f10a_0102_mode,
3993 static const struct display_timing urt_umsh_8596md_timing = {
3994 .pixelclock = { 33260000, 33260000, 33260000 },
3995 .hactive = { 800, 800, 800 },
3996 .hfront_porch = { 41, 41, 41 },
3997 .hback_porch = { 216 - 128, 216 - 128, 216 - 128 },
3998 .hsync_len = { 71, 128, 128 },
3999 .vactive = { 480, 480, 480 },
4000 .vfront_porch = { 10, 10, 10 },
4001 .vback_porch = { 35 - 2, 35 - 2, 35 - 2 },
4002 .vsync_len = { 2, 2, 2 },
4003 .flags = DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_PIXDATA_NEGEDGE |
4004 DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW,
4007 static const struct panel_desc urt_umsh_8596md_lvds = {
4008 .timings = &urt_umsh_8596md_timing,
4015 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4016 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4019 static const struct panel_desc urt_umsh_8596md_parallel = {
4020 .timings = &urt_umsh_8596md_timing,
4027 .bus_format = MEDIA_BUS_FMT_RGB666_1X18,
4030 static const struct drm_display_mode vivax_tpc9150_panel_mode = {
4033 .hsync_start = 1024 + 160,
4034 .hsync_end = 1024 + 160 + 100,
4035 .htotal = 1024 + 160 + 100 + 60,
4037 .vsync_start = 600 + 12,
4038 .vsync_end = 600 + 12 + 10,
4039 .vtotal = 600 + 12 + 10 + 13,
4042 static const struct panel_desc vivax_tpc9150_panel = {
4043 .modes = &vivax_tpc9150_panel_mode,
4050 .bus_format = MEDIA_BUS_FMT_RGB666_1X7X3_SPWG,
4051 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4052 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4055 static const struct drm_display_mode vl050_8048nt_c01_mode = {
4058 .hsync_start = 800 + 210,
4059 .hsync_end = 800 + 210 + 20,
4060 .htotal = 800 + 210 + 20 + 46,
4062 .vsync_start = 480 + 22,
4063 .vsync_end = 480 + 22 + 10,
4064 .vtotal = 480 + 22 + 10 + 23,
4065 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4068 static const struct panel_desc vl050_8048nt_c01 = {
4069 .modes = &vl050_8048nt_c01_mode,
4076 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4077 .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
4080 static const struct drm_display_mode winstar_wf35ltiacd_mode = {
4083 .hsync_start = 320 + 20,
4084 .hsync_end = 320 + 20 + 30,
4085 .htotal = 320 + 20 + 30 + 38,
4087 .vsync_start = 240 + 4,
4088 .vsync_end = 240 + 4 + 3,
4089 .vtotal = 240 + 4 + 3 + 15,
4090 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4093 static const struct panel_desc winstar_wf35ltiacd = {
4094 .modes = &winstar_wf35ltiacd_mode,
4101 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4104 static const struct drm_display_mode yes_optoelectronics_ytc700tlag_05_201c_mode = {
4107 .hsync_start = 1024 + 100,
4108 .hsync_end = 1024 + 100 + 100,
4109 .htotal = 1024 + 100 + 100 + 120,
4111 .vsync_start = 600 + 10,
4112 .vsync_end = 600 + 10 + 10,
4113 .vtotal = 600 + 10 + 10 + 15,
4114 .flags = DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC,
4117 static const struct panel_desc yes_optoelectronics_ytc700tlag_05_201c = {
4118 .modes = &yes_optoelectronics_ytc700tlag_05_201c_mode,
4125 .bus_flags = DRM_BUS_FLAG_DE_HIGH,
4126 .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
4127 .connector_type = DRM_MODE_CONNECTOR_LVDS,
4130 static const struct drm_display_mode arm_rtsm_mode[] = {
4134 .hsync_start = 1024 + 24,
4135 .hsync_end = 1024 + 24 + 136,
4136 .htotal = 1024 + 24 + 136 + 160,
4138 .vsync_start = 768 + 3,
4139 .vsync_end = 768 + 3 + 6,
4140 .vtotal = 768 + 3 + 6 + 29,
4141 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4145 static const struct panel_desc arm_rtsm = {
4146 .modes = arm_rtsm_mode,
4153 .bus_format = MEDIA_BUS_FMT_RGB888_1X24,
4156 static const struct of_device_id platform_of_match[] = {
4158 .compatible = "ampire,am-1280800n3tzqw-t00h",
4159 .data = &ire_am_1280800n3tzqw_t00h,
4161 .compatible = "ampire,am-480272h3tmqw-t01h",
4162 .data = &ire_am_480272h3tmqw_t01h,
4164 .compatible = "ampire,am-800480l1tmqw-t00h",
4165 .data = &ire_am_800480l1tmqw_t00h,
4167 .compatible = "ampire,am800480r3tmqwa1h",
4168 .data = &ire_am800480r3tmqwa1h,
4170 .compatible = "ampire,am800600p5tmqw-tb8h",
4171 .data = &ire_am800600p5tmqwtb8h,
4173 .compatible = "arm,rtsm-display",
4176 .compatible = "armadeus,st0700-adapt",
4177 .data = &armadeus_st0700_adapt,
4179 .compatible = "auo,b101aw03",
4180 .data = &auo_b101aw03,
4182 .compatible = "auo,b101xtn01",
4183 .data = &auo_b101xtn01,
4185 .compatible = "auo,g070vvn01",
4186 .data = &auo_g070vvn01,
4188 .compatible = "auo,g101evn010",
4189 .data = &auo_g101evn010,
4191 .compatible = "auo,g104sn02",
4192 .data = &auo_g104sn02,
4194 .compatible = "auo,g121ean01",
4195 .data = &auo_g121ean01,
4197 .compatible = "auo,g133han01",
4198 .data = &auo_g133han01,
4200 .compatible = "auo,g156xtn01",
4201 .data = &auo_g156xtn01,
4203 .compatible = "auo,g185han01",
4204 .data = &auo_g185han01,
4206 .compatible = "auo,g190ean01",
4207 .data = &auo_g190ean01,
4209 .compatible = "auo,p320hvn03",
4210 .data = &auo_p320hvn03,
4212 .compatible = "auo,t215hvn01",
4213 .data = &auo_t215hvn01,
4215 .compatible = "avic,tm070ddh03",
4216 .data = &avic_tm070ddh03,
4218 .compatible = "bananapi,s070wv20-ct16",
4219 .data = &bananapi_s070wv20_ct16,
4221 .compatible = "boe,ev121wxm-n10-1850",
4222 .data = &boe_ev121wxm_n10_1850,
4224 .compatible = "boe,hv070wsa-100",
4225 .data = &boe_hv070wsa
4227 .compatible = "cdtech,s043wq26h-ct7",
4228 .data = &cdtech_s043wq26h_ct7,
4230 .compatible = "cdtech,s070pws19hp-fc21",
4231 .data = &cdtech_s070pws19hp_fc21,
4233 .compatible = "cdtech,s070swv29hg-dc44",
4234 .data = &cdtech_s070swv29hg_dc44,
4236 .compatible = "cdtech,s070wv95-ct16",
4237 .data = &cdtech_s070wv95_ct16,
4239 .compatible = "chefree,ch101olhlwh-002",
4240 .data = &chefree_ch101olhlwh_002,
4242 .compatible = "chunghwa,claa070wp03xg",
4243 .data = &chunghwa_claa070wp03xg,
4245 .compatible = "chunghwa,claa101wa01a",
4246 .data = &chunghwa_claa101wa01a
4248 .compatible = "chunghwa,claa101wb01",
4249 .data = &chunghwa_claa101wb01
4251 .compatible = "dataimage,fg040346dsswbg04",
4252 .data = &dataimage_fg040346dsswbg04,
4254 .compatible = "dataimage,fg1001l0dsswmg01",
4255 .data = &dataimage_fg1001l0dsswmg01,
4257 .compatible = "dataimage,scf0700c48ggu18",
4258 .data = &dataimage_scf0700c48ggu18,
4260 .compatible = "dlc,dlc0700yzg-1",
4261 .data = &dlc_dlc0700yzg_1,
4263 .compatible = "dlc,dlc1010gig",
4264 .data = &dlc_dlc1010gig,
4266 .compatible = "edt,et035012dm6",
4267 .data = &edt_et035012dm6,
4269 .compatible = "edt,etm0350g0dh6",
4270 .data = &edt_etm0350g0dh6,
4272 .compatible = "edt,etm043080dh6gp",
4273 .data = &edt_etm043080dh6gp,
4275 .compatible = "edt,etm0430g0dh6",
4276 .data = &edt_etm0430g0dh6,
4278 .compatible = "edt,et057090dhu",
4279 .data = &edt_et057090dhu,
4281 .compatible = "edt,et070080dh6",
4282 .data = &edt_etm0700g0dh6,
4284 .compatible = "edt,etm0700g0dh6",
4285 .data = &edt_etm0700g0dh6,
4287 .compatible = "edt,etm0700g0bdh6",
4288 .data = &edt_etm0700g0bdh6,
4290 .compatible = "edt,etm0700g0edh6",
4291 .data = &edt_etm0700g0bdh6,
4293 .compatible = "edt,etml0700y5dha",
4294 .data = &edt_etml0700y5dha,
4296 .compatible = "edt,etmv570g2dhu",
4297 .data = &edt_etmv570g2dhu,
4299 .compatible = "eink,vb3300-kca",
4300 .data = &eink_vb3300_kca,
4302 .compatible = "evervision,vgg804821",
4303 .data = &evervision_vgg804821,
4305 .compatible = "foxlink,fl500wvr00-a0t",
4306 .data = &foxlink_fl500wvr00_a0t,
4308 .compatible = "frida,frd350h54004",
4309 .data = &frida_frd350h54004,
4311 .compatible = "friendlyarm,hd702e",
4312 .data = &friendlyarm_hd702e,
4314 .compatible = "giantplus,gpg482739qs5",
4315 .data = &giantplus_gpg482739qs5
4317 .compatible = "giantplus,gpm940b0",
4318 .data = &giantplus_gpm940b0,
4320 .compatible = "hannstar,hsd070pww1",
4321 .data = &hannstar_hsd070pww1,
4323 .compatible = "hannstar,hsd100pxn1",
4324 .data = &hannstar_hsd100pxn1,
4326 .compatible = "hannstar,hsd101pww2",
4327 .data = &hannstar_hsd101pww2,
4329 .compatible = "hit,tx23d38vm0caa",
4330 .data = &hitachi_tx23d38vm0caa
4332 .compatible = "innolux,at043tn24",
4333 .data = &innolux_at043tn24,
4335 .compatible = "innolux,at070tn92",
4336 .data = &innolux_at070tn92,
4338 .compatible = "innolux,g070ace-l01",
4339 .data = &innolux_g070ace_l01,
4341 .compatible = "innolux,g070y2-l01",
4342 .data = &innolux_g070y2_l01,
4344 .compatible = "innolux,g070y2-t02",
4345 .data = &innolux_g070y2_t02,
4347 .compatible = "innolux,g101ice-l01",
4348 .data = &innolux_g101ice_l01
4350 .compatible = "innolux,g121i1-l01",
4351 .data = &innolux_g121i1_l01
4353 .compatible = "innolux,g121x1-l03",
4354 .data = &innolux_g121x1_l03,
4356 .compatible = "innolux,g156hce-l01",
4357 .data = &innolux_g156hce_l01,
4359 .compatible = "innolux,n156bge-l21",
4360 .data = &innolux_n156bge_l21,
4362 .compatible = "innolux,zj070na-01p",
4363 .data = &innolux_zj070na_01p,
4365 .compatible = "koe,tx14d24vm1bpa",
4366 .data = &koe_tx14d24vm1bpa,
4368 .compatible = "koe,tx26d202vm0bwa",
4369 .data = &koe_tx26d202vm0bwa,
4371 .compatible = "koe,tx31d200vm0baa",
4372 .data = &koe_tx31d200vm0baa,
4374 .compatible = "kyo,tcg121xglp",
4375 .data = &kyo_tcg121xglp,
4377 .compatible = "lemaker,bl035-rgb-002",
4378 .data = &lemaker_bl035_rgb_002,
4380 .compatible = "lg,lb070wv8",
4381 .data = &lg_lb070wv8,
4383 .compatible = "logicpd,type28",
4384 .data = &logicpd_type_28,
4386 .compatible = "logictechno,lt161010-2nhc",
4387 .data = &logictechno_lt161010_2nh,
4389 .compatible = "logictechno,lt161010-2nhr",
4390 .data = &logictechno_lt161010_2nh,
4392 .compatible = "logictechno,lt170410-2whc",
4393 .data = &logictechno_lt170410_2whc,
4395 .compatible = "logictechno,lttd800480070-l2rt",
4396 .data = &logictechno_lttd800480070_l2rt,
4398 .compatible = "logictechno,lttd800480070-l6wh-rt",
4399 .data = &logictechno_lttd800480070_l6wh_rt,
4401 .compatible = "mitsubishi,aa070mc01-ca1",
4402 .data = &mitsubishi_aa070mc01,
4404 .compatible = "mitsubishi,aa084xe01",
4405 .data = &mitsubishi_aa084xe01,
4407 .compatible = "multi-inno,mi0700s4t-6",
4408 .data = &multi_inno_mi0700s4t_6,
4410 .compatible = "multi-inno,mi0800ft-9",
4411 .data = &multi_inno_mi0800ft_9,
4413 .compatible = "multi-inno,mi1010ait-1cp",
4414 .data = &multi_inno_mi1010ait_1cp,
4416 .compatible = "nec,nl12880bc20-05",
4417 .data = &nec_nl12880bc20_05,
4419 .compatible = "nec,nl4827hc19-05b",
4420 .data = &nec_nl4827hc19_05b,
4422 .compatible = "netron-dy,e231732",
4423 .data = &netron_dy_e231732,
4425 .compatible = "newhaven,nhd-4.3-480272ef-atxl",
4426 .data = &newhaven_nhd_43_480272ef_atxl,
4428 .compatible = "nlt,nl192108ac18-02d",
4429 .data = &nlt_nl192108ac18_02d,
4431 .compatible = "nvd,9128",
4434 .compatible = "okaya,rs800480t-7x0gp",
4435 .data = &okaya_rs800480t_7x0gp,
4437 .compatible = "olimex,lcd-olinuxino-43-ts",
4438 .data = &olimex_lcd_olinuxino_43ts,
4440 .compatible = "ontat,yx700wv03",
4441 .data = &ontat_yx700wv03,
4443 .compatible = "ortustech,com37h3m05dtc",
4444 .data = &ortustech_com37h3m,
4446 .compatible = "ortustech,com37h3m99dtc",
4447 .data = &ortustech_com37h3m,
4449 .compatible = "ortustech,com43h4m85ulc",
4450 .data = &ortustech_com43h4m85ulc,
4452 .compatible = "osddisplays,osd070t1718-19ts",
4453 .data = &osddisplays_osd070t1718_19ts,
4455 .compatible = "pda,91-00156-a0",
4456 .data = &pda_91_00156_a0,
4458 .compatible = "powertip,ph800480t013-idf02",
4459 .data = &powertip_ph800480t013_idf02,
4461 .compatible = "qiaodian,qd43003c0-40",
4462 .data = &qd43003c0_40,
4464 .compatible = "qishenglong,gopher2b-lcd",
4465 .data = &qishenglong_gopher2b_lcd,
4467 .compatible = "rocktech,rk043fn48h",
4468 .data = &rocktech_rk043fn48h,
4470 .compatible = "rocktech,rk070er9427",
4471 .data = &rocktech_rk070er9427,
4473 .compatible = "rocktech,rk101ii01d-ct",
4474 .data = &rocktech_rk101ii01d_ct,
4476 .compatible = "samsung,ltl101al01",
4477 .data = &samsung_ltl101al01,
4479 .compatible = "samsung,ltn101nt05",
4480 .data = &samsung_ltn101nt05,
4482 .compatible = "satoz,sat050at40h12r2",
4483 .data = &satoz_sat050at40h12r2,
4485 .compatible = "sharp,lq035q7db03",
4486 .data = &sharp_lq035q7db03,
4488 .compatible = "sharp,lq070y3dg3b",
4489 .data = &sharp_lq070y3dg3b,
4491 .compatible = "sharp,lq101k1ly04",
4492 .data = &sharp_lq101k1ly04,
4494 .compatible = "sharp,ls020b1dd01d",
4495 .data = &sharp_ls020b1dd01d,
4497 .compatible = "shelly,sca07010-bfn-lnn",
4498 .data = &shelly_sca07010_bfn_lnn,
4500 .compatible = "starry,kr070pe2t",
4501 .data = &starry_kr070pe2t,
4503 .compatible = "startek,kd070wvfpa",
4504 .data = &startek_kd070wvfpa,
4506 .compatible = "team-source-display,tst043015cmhx",
4507 .data = &tsd_tst043015cmhx,
4509 .compatible = "tfc,s9700rtwv43tr-01b",
4510 .data = &tfc_s9700rtwv43tr_01b,
4512 .compatible = "tianma,tm070jdhg30",
4513 .data = &tianma_tm070jdhg30,
4515 .compatible = "tianma,tm070jvhg33",
4516 .data = &tianma_tm070jvhg33,
4518 .compatible = "tianma,tm070rvhg71",
4519 .data = &tianma_tm070rvhg71,
4521 .compatible = "ti,nspire-cx-lcd-panel",
4522 .data = &ti_nspire_cx_lcd_panel,
4524 .compatible = "ti,nspire-classic-lcd-panel",
4525 .data = &ti_nspire_classic_lcd_panel,
4527 .compatible = "toshiba,lt089ac29000",
4528 .data = &toshiba_lt089ac29000,
4530 .compatible = "tpk,f07a-0102",
4531 .data = &tpk_f07a_0102,
4533 .compatible = "tpk,f10a-0102",
4534 .data = &tpk_f10a_0102,
4536 .compatible = "urt,umsh-8596md-t",
4537 .data = &urt_umsh_8596md_parallel,
4539 .compatible = "urt,umsh-8596md-1t",
4540 .data = &urt_umsh_8596md_parallel,
4542 .compatible = "urt,umsh-8596md-7t",
4543 .data = &urt_umsh_8596md_parallel,
4545 .compatible = "urt,umsh-8596md-11t",
4546 .data = &urt_umsh_8596md_lvds,
4548 .compatible = "urt,umsh-8596md-19t",
4549 .data = &urt_umsh_8596md_lvds,
4551 .compatible = "urt,umsh-8596md-20t",
4552 .data = &urt_umsh_8596md_parallel,
4554 .compatible = "vivax,tpc9150-panel",
4555 .data = &vivax_tpc9150_panel,
4557 .compatible = "vxt,vl050-8048nt-c01",
4558 .data = &vl050_8048nt_c01,
4560 .compatible = "winstar,wf35ltiacd",
4561 .data = &winstar_wf35ltiacd,
4563 .compatible = "yes-optoelectronics,ytc700tlag-05-201c",
4564 .data = &yes_optoelectronics_ytc700tlag_05_201c,
4566 /* Must be the last entry */
4567 .compatible = "panel-dpi",
4573 MODULE_DEVICE_TABLE(of, platform_of_match);
4575 static int panel_simple_platform_probe(struct platform_device *pdev)
4577 const struct panel_desc *desc;
4579 desc = of_device_get_match_data(&pdev->dev);
4583 return panel_simple_probe(&pdev->dev, desc);
4586 static void panel_simple_platform_remove(struct platform_device *pdev)
4588 panel_simple_remove(&pdev->dev);
4591 static void panel_simple_platform_shutdown(struct platform_device *pdev)
4593 panel_simple_shutdown(&pdev->dev);
4596 static const struct dev_pm_ops panel_simple_pm_ops = {
4597 SET_RUNTIME_PM_OPS(panel_simple_suspend, panel_simple_resume, NULL)
4598 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
4599 pm_runtime_force_resume)
4602 static struct platform_driver panel_simple_platform_driver = {
4604 .name = "panel-simple",
4605 .of_match_table = platform_of_match,
4606 .pm = &panel_simple_pm_ops,
4608 .probe = panel_simple_platform_probe,
4609 .remove_new = panel_simple_platform_remove,
4610 .shutdown = panel_simple_platform_shutdown,
4613 struct panel_desc_dsi {
4614 struct panel_desc desc;
4616 unsigned long flags;
4617 enum mipi_dsi_pixel_format format;
4621 static const struct drm_display_mode auo_b080uan01_mode = {
4624 .hsync_start = 1200 + 62,
4625 .hsync_end = 1200 + 62 + 4,
4626 .htotal = 1200 + 62 + 4 + 62,
4628 .vsync_start = 1920 + 9,
4629 .vsync_end = 1920 + 9 + 2,
4630 .vtotal = 1920 + 9 + 2 + 8,
4633 static const struct panel_desc_dsi auo_b080uan01 = {
4635 .modes = &auo_b080uan01_mode,
4642 .connector_type = DRM_MODE_CONNECTOR_DSI,
4644 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4645 .format = MIPI_DSI_FMT_RGB888,
4649 static const struct drm_display_mode boe_tv080wum_nl0_mode = {
4652 .hsync_start = 1200 + 120,
4653 .hsync_end = 1200 + 120 + 20,
4654 .htotal = 1200 + 120 + 20 + 21,
4656 .vsync_start = 1920 + 21,
4657 .vsync_end = 1920 + 21 + 3,
4658 .vtotal = 1920 + 21 + 3 + 18,
4659 .flags = DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC,
4662 static const struct panel_desc_dsi boe_tv080wum_nl0 = {
4664 .modes = &boe_tv080wum_nl0_mode,
4670 .connector_type = DRM_MODE_CONNECTOR_DSI,
4672 .flags = MIPI_DSI_MODE_VIDEO |
4673 MIPI_DSI_MODE_VIDEO_BURST |
4674 MIPI_DSI_MODE_VIDEO_SYNC_PULSE,
4675 .format = MIPI_DSI_FMT_RGB888,
4679 static const struct drm_display_mode lg_ld070wx3_sl01_mode = {
4682 .hsync_start = 800 + 32,
4683 .hsync_end = 800 + 32 + 1,
4684 .htotal = 800 + 32 + 1 + 57,
4686 .vsync_start = 1280 + 28,
4687 .vsync_end = 1280 + 28 + 1,
4688 .vtotal = 1280 + 28 + 1 + 14,
4691 static const struct panel_desc_dsi lg_ld070wx3_sl01 = {
4693 .modes = &lg_ld070wx3_sl01_mode,
4700 .connector_type = DRM_MODE_CONNECTOR_DSI,
4702 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_CLOCK_NON_CONTINUOUS,
4703 .format = MIPI_DSI_FMT_RGB888,
4707 static const struct drm_display_mode lg_lh500wx1_sd03_mode = {
4710 .hsync_start = 720 + 12,
4711 .hsync_end = 720 + 12 + 4,
4712 .htotal = 720 + 12 + 4 + 112,
4714 .vsync_start = 1280 + 8,
4715 .vsync_end = 1280 + 8 + 4,
4716 .vtotal = 1280 + 8 + 4 + 12,
4719 static const struct panel_desc_dsi lg_lh500wx1_sd03 = {
4721 .modes = &lg_lh500wx1_sd03_mode,
4728 .connector_type = DRM_MODE_CONNECTOR_DSI,
4730 .flags = MIPI_DSI_MODE_VIDEO,
4731 .format = MIPI_DSI_FMT_RGB888,
4735 static const struct drm_display_mode panasonic_vvx10f004b00_mode = {
4738 .hsync_start = 1920 + 154,
4739 .hsync_end = 1920 + 154 + 16,
4740 .htotal = 1920 + 154 + 16 + 32,
4742 .vsync_start = 1200 + 17,
4743 .vsync_end = 1200 + 17 + 2,
4744 .vtotal = 1200 + 17 + 2 + 16,
4747 static const struct panel_desc_dsi panasonic_vvx10f004b00 = {
4749 .modes = &panasonic_vvx10f004b00_mode,
4756 .connector_type = DRM_MODE_CONNECTOR_DSI,
4758 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4759 MIPI_DSI_CLOCK_NON_CONTINUOUS,
4760 .format = MIPI_DSI_FMT_RGB888,
4764 static const struct drm_display_mode lg_acx467akm_7_mode = {
4767 .hsync_start = 1080 + 2,
4768 .hsync_end = 1080 + 2 + 2,
4769 .htotal = 1080 + 2 + 2 + 2,
4771 .vsync_start = 1920 + 2,
4772 .vsync_end = 1920 + 2 + 2,
4773 .vtotal = 1920 + 2 + 2 + 2,
4776 static const struct panel_desc_dsi lg_acx467akm_7 = {
4778 .modes = &lg_acx467akm_7_mode,
4785 .connector_type = DRM_MODE_CONNECTOR_DSI,
4788 .format = MIPI_DSI_FMT_RGB888,
4792 static const struct drm_display_mode osd101t2045_53ts_mode = {
4795 .hsync_start = 1920 + 112,
4796 .hsync_end = 1920 + 112 + 16,
4797 .htotal = 1920 + 112 + 16 + 32,
4799 .vsync_start = 1200 + 16,
4800 .vsync_end = 1200 + 16 + 2,
4801 .vtotal = 1200 + 16 + 2 + 16,
4802 .flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
4805 static const struct panel_desc_dsi osd101t2045_53ts = {
4807 .modes = &osd101t2045_53ts_mode,
4814 .connector_type = DRM_MODE_CONNECTOR_DSI,
4816 .flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
4817 MIPI_DSI_MODE_VIDEO_SYNC_PULSE |
4818 MIPI_DSI_MODE_NO_EOT_PACKET,
4819 .format = MIPI_DSI_FMT_RGB888,
4823 static const struct of_device_id dsi_of_match[] = {
4825 .compatible = "auo,b080uan01",
4826 .data = &auo_b080uan01
4828 .compatible = "boe,tv080wum-nl0",
4829 .data = &boe_tv080wum_nl0
4831 .compatible = "lg,ld070wx3-sl01",
4832 .data = &lg_ld070wx3_sl01
4834 .compatible = "lg,lh500wx1-sd03",
4835 .data = &lg_lh500wx1_sd03
4837 .compatible = "panasonic,vvx10f004b00",
4838 .data = &panasonic_vvx10f004b00
4840 .compatible = "lg,acx467akm-7",
4841 .data = &lg_acx467akm_7
4843 .compatible = "osddisplays,osd101t2045-53ts",
4844 .data = &osd101t2045_53ts
4849 MODULE_DEVICE_TABLE(of, dsi_of_match);
4851 static int panel_simple_dsi_probe(struct mipi_dsi_device *dsi)
4853 const struct panel_desc_dsi *desc;
4856 desc = of_device_get_match_data(&dsi->dev);
4860 err = panel_simple_probe(&dsi->dev, &desc->desc);
4864 dsi->mode_flags = desc->flags;
4865 dsi->format = desc->format;
4866 dsi->lanes = desc->lanes;
4868 err = mipi_dsi_attach(dsi);
4870 struct panel_simple *panel = mipi_dsi_get_drvdata(dsi);
4872 drm_panel_remove(&panel->base);
4878 static void panel_simple_dsi_remove(struct mipi_dsi_device *dsi)
4882 err = mipi_dsi_detach(dsi);
4884 dev_err(&dsi->dev, "failed to detach from DSI host: %d\n", err);
4886 panel_simple_remove(&dsi->dev);
4889 static void panel_simple_dsi_shutdown(struct mipi_dsi_device *dsi)
4891 panel_simple_shutdown(&dsi->dev);
4894 static struct mipi_dsi_driver panel_simple_dsi_driver = {
4896 .name = "panel-simple-dsi",
4897 .of_match_table = dsi_of_match,
4898 .pm = &panel_simple_pm_ops,
4900 .probe = panel_simple_dsi_probe,
4901 .remove = panel_simple_dsi_remove,
4902 .shutdown = panel_simple_dsi_shutdown,
4905 static int __init panel_simple_init(void)
4909 err = platform_driver_register(&panel_simple_platform_driver);
4913 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
4914 err = mipi_dsi_driver_register(&panel_simple_dsi_driver);
4916 goto err_did_platform_register;
4921 err_did_platform_register:
4922 platform_driver_unregister(&panel_simple_platform_driver);
4926 module_init(panel_simple_init);
4928 static void __exit panel_simple_exit(void)
4930 if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
4931 mipi_dsi_driver_unregister(&panel_simple_dsi_driver);
4933 platform_driver_unregister(&panel_simple_platform_driver);
4935 module_exit(panel_simple_exit);
4937 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
4938 MODULE_DESCRIPTION("DRM Driver for Simple Panels");
4939 MODULE_LICENSE("GPL and additional rights");