drivers/gpu/drm/nouveau/nouveau_state.c

   1 /*
   2  * Copyright 2005 Stephane Marchesin
   3  * Copyright 2008 Stuart Bennett
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  */
  25
  26 #include <linux/swab.h>
  27 #include <linux/slab.h>
  28 #include "drmP.h"
  29 #include "drm.h"
  30 #include "drm_sarea.h"
  31 #include "drm_crtc_helper.h"
  32 #include <linux/vgaarb.h>
  33 #include <linux/vga_switcheroo.h>
  34
  35 #include "nouveau_drv.h"
  36 #include "nouveau_drm.h"
  37 #include "nouveau_fbcon.h"
  38 #include "nouveau_ramht.h"
  39 #include "nouveau_gpio.h"
  40 #include "nouveau_pm.h"
  41 #include "nv50_display.h"
  42
  43 static void nouveau_stub_takedown(struct drm_device *dev) {}
  44 static int nouveau_stub_init(struct drm_device *dev) { return 0; }
  45
  46 static int nouveau_init_engine_ptrs(struct drm_device *dev)
  47 {
  48         struct drm_nouveau_private *dev_priv = dev->dev_private;
  49         struct nouveau_engine *engine = &dev_priv->engine;
  50
  51         switch (dev_priv->chipset & 0xf0) {
  52         case 0x00:
  53                 engine->instmem.init            = nv04_instmem_init;
  54                 engine->instmem.takedown        = nv04_instmem_takedown;
  55                 engine->instmem.suspend         = nv04_instmem_suspend;
  56                 engine->instmem.resume          = nv04_instmem_resume;
  57                 engine->instmem.get             = nv04_instmem_get;
  58                 engine->instmem.put             = nv04_instmem_put;
  59                 engine->instmem.map             = nv04_instmem_map;
  60                 engine->instmem.unmap           = nv04_instmem_unmap;
  61                 engine->instmem.flush           = nv04_instmem_flush;
  62                 engine->mc.init                 = nv04_mc_init;
  63                 engine->mc.takedown             = nv04_mc_takedown;
  64                 engine->timer.init              = nv04_timer_init;
  65                 engine->timer.read              = nv04_timer_read;
  66                 engine->timer.takedown          = nv04_timer_takedown;
  67                 engine->fb.init                 = nv04_fb_init;
  68                 engine->fb.takedown             = nv04_fb_takedown;
  69                 engine->fifo.channels           = 16;
  70                 engine->fifo.init               = nv04_fifo_init;
  71                 engine->fifo.takedown           = nv04_fifo_fini;
  72                 engine->fifo.disable            = nv04_fifo_disable;
  73                 engine->fifo.enable             = nv04_fifo_enable;
  74                 engine->fifo.reassign           = nv04_fifo_reassign;
  75                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
  76                 engine->fifo.channel_id         = nv04_fifo_channel_id;
  77                 engine->fifo.create_context     = nv04_fifo_create_context;
  78                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
  79                 engine->fifo.load_context       = nv04_fifo_load_context;
  80                 engine->fifo.unload_context     = nv04_fifo_unload_context;
  81                 engine->display.early_init      = nv04_display_early_init;
  82                 engine->display.late_takedown   = nv04_display_late_takedown;
  83                 engine->display.create          = nv04_display_create;
  84                 engine->display.destroy         = nv04_display_destroy;
  85                 engine->display.init            = nv04_display_init;
  86                 engine->display.fini            = nv04_display_fini;
  87                 engine->pm.clocks_get           = nv04_pm_clocks_get;
  88                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
  89                 engine->pm.clocks_set           = nv04_pm_clocks_set;
  90                 engine->vram.init               = nouveau_mem_detect;
  91                 engine->vram.takedown           = nouveau_stub_takedown;
  92                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
  93                 break;
  94         case 0x10:
  95                 engine->instmem.init            = nv04_instmem_init;
  96                 engine->instmem.takedown        = nv04_instmem_takedown;
  97                 engine->instmem.suspend         = nv04_instmem_suspend;
  98                 engine->instmem.resume          = nv04_instmem_resume;
  99                 engine->instmem.get             = nv04_instmem_get;
 100                 engine->instmem.put             = nv04_instmem_put;
 101                 engine->instmem.map             = nv04_instmem_map;
 102                 engine->instmem.unmap           = nv04_instmem_unmap;
 103                 engine->instmem.flush           = nv04_instmem_flush;
 104                 engine->mc.init                 = nv04_mc_init;
 105                 engine->mc.takedown             = nv04_mc_takedown;
 106                 engine->timer.init              = nv04_timer_init;
 107                 engine->timer.read              = nv04_timer_read;
 108                 engine->timer.takedown          = nv04_timer_takedown;
 109                 engine->fb.init                 = nv10_fb_init;
 110                 engine->fb.takedown             = nv10_fb_takedown;
 111                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 112                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 113                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 114                 engine->fifo.channels           = 32;
 115                 engine->fifo.init               = nv10_fifo_init;
 116                 engine->fifo.takedown           = nv04_fifo_fini;
 117                 engine->fifo.disable            = nv04_fifo_disable;
 118                 engine->fifo.enable             = nv04_fifo_enable;
 119                 engine->fifo.reassign           = nv04_fifo_reassign;
 120                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 121                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 122                 engine->fifo.create_context     = nv10_fifo_create_context;
 123                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 124                 engine->fifo.load_context       = nv10_fifo_load_context;
 125                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 126                 engine->display.early_init      = nv04_display_early_init;
 127                 engine->display.late_takedown   = nv04_display_late_takedown;
 128                 engine->display.create          = nv04_display_create;
 129                 engine->display.destroy         = nv04_display_destroy;
 130                 engine->display.init            = nv04_display_init;
 131                 engine->display.fini            = nv04_display_fini;
 132                 engine->gpio.drive              = nv10_gpio_drive;
 133                 engine->gpio.sense              = nv10_gpio_sense;
 134                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 135                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 136                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 137                 engine->vram.init               = nouveau_mem_detect;
 138                 engine->vram.takedown           = nouveau_stub_takedown;
 139                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 140                 break;
 141         case 0x20:
 142                 engine->instmem.init            = nv04_instmem_init;
 143                 engine->instmem.takedown        = nv04_instmem_takedown;
 144                 engine->instmem.suspend         = nv04_instmem_suspend;
 145                 engine->instmem.resume          = nv04_instmem_resume;
 146                 engine->instmem.get             = nv04_instmem_get;
 147                 engine->instmem.put             = nv04_instmem_put;
 148                 engine->instmem.map             = nv04_instmem_map;
 149                 engine->instmem.unmap           = nv04_instmem_unmap;
 150                 engine->instmem.flush           = nv04_instmem_flush;
 151                 engine->mc.init                 = nv04_mc_init;
 152                 engine->mc.takedown             = nv04_mc_takedown;
 153                 engine->timer.init              = nv04_timer_init;
 154                 engine->timer.read              = nv04_timer_read;
 155                 engine->timer.takedown          = nv04_timer_takedown;
 156                 engine->fb.init                 = nv10_fb_init;
 157                 engine->fb.takedown             = nv10_fb_takedown;
 158                 engine->fb.init_tile_region     = nv10_fb_init_tile_region;
 159                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 160                 engine->fb.free_tile_region     = nv10_fb_free_tile_region;
 161                 engine->fifo.channels           = 32;
 162                 engine->fifo.init               = nv10_fifo_init;
 163                 engine->fifo.takedown           = nv04_fifo_fini;
 164                 engine->fifo.disable            = nv04_fifo_disable;
 165                 engine->fifo.enable             = nv04_fifo_enable;
 166                 engine->fifo.reassign           = nv04_fifo_reassign;
 167                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 168                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 169                 engine->fifo.create_context     = nv10_fifo_create_context;
 170                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 171                 engine->fifo.load_context       = nv10_fifo_load_context;
 172                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 173                 engine->display.early_init      = nv04_display_early_init;
 174                 engine->display.late_takedown   = nv04_display_late_takedown;
 175                 engine->display.create          = nv04_display_create;
 176                 engine->display.destroy         = nv04_display_destroy;
 177                 engine->display.init            = nv04_display_init;
 178                 engine->display.fini            = nv04_display_fini;
 179                 engine->gpio.drive              = nv10_gpio_drive;
 180                 engine->gpio.sense              = nv10_gpio_sense;
 181                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 182                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 183                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 184                 engine->vram.init               = nouveau_mem_detect;
 185                 engine->vram.takedown           = nouveau_stub_takedown;
 186                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 187                 break;
 188         case 0x30:
 189                 engine->instmem.init            = nv04_instmem_init;
 190                 engine->instmem.takedown        = nv04_instmem_takedown;
 191                 engine->instmem.suspend         = nv04_instmem_suspend;
 192                 engine->instmem.resume          = nv04_instmem_resume;
 193                 engine->instmem.get             = nv04_instmem_get;
 194                 engine->instmem.put             = nv04_instmem_put;
 195                 engine->instmem.map             = nv04_instmem_map;
 196                 engine->instmem.unmap           = nv04_instmem_unmap;
 197                 engine->instmem.flush           = nv04_instmem_flush;
 198                 engine->mc.init                 = nv04_mc_init;
 199                 engine->mc.takedown             = nv04_mc_takedown;
 200                 engine->timer.init              = nv04_timer_init;
 201                 engine->timer.read              = nv04_timer_read;
 202                 engine->timer.takedown          = nv04_timer_takedown;
 203                 engine->fb.init                 = nv30_fb_init;
 204                 engine->fb.takedown             = nv30_fb_takedown;
 205                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 206                 engine->fb.set_tile_region      = nv10_fb_set_tile_region;
 207                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 208                 engine->fifo.channels           = 32;
 209                 engine->fifo.init               = nv10_fifo_init;
 210                 engine->fifo.takedown           = nv04_fifo_fini;
 211                 engine->fifo.disable            = nv04_fifo_disable;
 212                 engine->fifo.enable             = nv04_fifo_enable;
 213                 engine->fifo.reassign           = nv04_fifo_reassign;
 214                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 215                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 216                 engine->fifo.create_context     = nv10_fifo_create_context;
 217                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 218                 engine->fifo.load_context       = nv10_fifo_load_context;
 219                 engine->fifo.unload_context     = nv10_fifo_unload_context;
 220                 engine->display.early_init      = nv04_display_early_init;
 221                 engine->display.late_takedown   = nv04_display_late_takedown;
 222                 engine->display.create          = nv04_display_create;
 223                 engine->display.destroy         = nv04_display_destroy;
 224                 engine->display.init            = nv04_display_init;
 225                 engine->display.fini            = nv04_display_fini;
 226                 engine->gpio.drive              = nv10_gpio_drive;
 227                 engine->gpio.sense              = nv10_gpio_sense;
 228                 engine->pm.clocks_get           = nv04_pm_clocks_get;
 229                 engine->pm.clocks_pre           = nv04_pm_clocks_pre;
 230                 engine->pm.clocks_set           = nv04_pm_clocks_set;
 231                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 232                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 233                 engine->vram.init               = nouveau_mem_detect;
 234                 engine->vram.takedown           = nouveau_stub_takedown;
 235                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 236                 break;
 237         case 0x40:
 238         case 0x60:
 239                 engine->instmem.init            = nv04_instmem_init;
 240                 engine->instmem.takedown        = nv04_instmem_takedown;
 241                 engine->instmem.suspend         = nv04_instmem_suspend;
 242                 engine->instmem.resume          = nv04_instmem_resume;
 243                 engine->instmem.get             = nv04_instmem_get;
 244                 engine->instmem.put             = nv04_instmem_put;
 245                 engine->instmem.map             = nv04_instmem_map;
 246                 engine->instmem.unmap           = nv04_instmem_unmap;
 247                 engine->instmem.flush           = nv04_instmem_flush;
 248                 engine->mc.init                 = nv40_mc_init;
 249                 engine->mc.takedown             = nv40_mc_takedown;
 250                 engine->timer.init              = nv04_timer_init;
 251                 engine->timer.read              = nv04_timer_read;
 252                 engine->timer.takedown          = nv04_timer_takedown;
 253                 engine->fb.init                 = nv40_fb_init;
 254                 engine->fb.takedown             = nv40_fb_takedown;
 255                 engine->fb.init_tile_region     = nv30_fb_init_tile_region;
 256                 engine->fb.set_tile_region      = nv40_fb_set_tile_region;
 257                 engine->fb.free_tile_region     = nv30_fb_free_tile_region;
 258                 engine->fifo.channels           = 32;
 259                 engine->fifo.init               = nv40_fifo_init;
 260                 engine->fifo.takedown           = nv04_fifo_fini;
 261                 engine->fifo.disable            = nv04_fifo_disable;
 262                 engine->fifo.enable             = nv04_fifo_enable;
 263                 engine->fifo.reassign           = nv04_fifo_reassign;
 264                 engine->fifo.cache_pull         = nv04_fifo_cache_pull;
 265                 engine->fifo.channel_id         = nv10_fifo_channel_id;
 266                 engine->fifo.create_context     = nv40_fifo_create_context;
 267                 engine->fifo.destroy_context    = nv04_fifo_destroy_context;
 268                 engine->fifo.load_context       = nv40_fifo_load_context;
 269                 engine->fifo.unload_context     = nv40_fifo_unload_context;
 270                 engine->display.early_init      = nv04_display_early_init;
 271                 engine->display.late_takedown   = nv04_display_late_takedown;
 272                 engine->display.create          = nv04_display_create;
 273                 engine->display.destroy         = nv04_display_destroy;
 274                 engine->display.init            = nv04_display_init;
 275                 engine->display.fini            = nv04_display_fini;
 276                 engine->gpio.init               = nv10_gpio_init;
 277                 engine->gpio.fini               = nv10_gpio_fini;
 278                 engine->gpio.drive              = nv10_gpio_drive;
 279                 engine->gpio.sense              = nv10_gpio_sense;
 280                 engine->gpio.irq_enable         = nv10_gpio_irq_enable;
 281                 engine->pm.clocks_get           = nv40_pm_clocks_get;
 282                 engine->pm.clocks_pre           = nv40_pm_clocks_pre;
 283                 engine->pm.clocks_set           = nv40_pm_clocks_set;
 284                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 285                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 286                 engine->pm.temp_get             = nv40_temp_get;
 287                 engine->pm.pwm_get              = nv40_pm_pwm_get;
 288                 engine->pm.pwm_set              = nv40_pm_pwm_set;
 289                 engine->vram.init               = nouveau_mem_detect;
 290                 engine->vram.takedown           = nouveau_stub_takedown;
 291                 engine->vram.flags_valid        = nouveau_mem_flags_valid;
 292                 break;
 293         case 0x50:
 294         case 0x80: /* gotta love NVIDIA's consistency.. */
 295         case 0x90:
 296         case 0xa0:
 297                 engine->instmem.init            = nv50_instmem_init;
 298                 engine->instmem.takedown        = nv50_instmem_takedown;
 299                 engine->instmem.suspend         = nv50_instmem_suspend;
 300                 engine->instmem.resume          = nv50_instmem_resume;
 301                 engine->instmem.get             = nv50_instmem_get;
 302                 engine->instmem.put             = nv50_instmem_put;
 303                 engine->instmem.map             = nv50_instmem_map;
 304                 engine->instmem.unmap           = nv50_instmem_unmap;
 305                 if (dev_priv->chipset == 0x50)
 306                         engine->instmem.flush   = nv50_instmem_flush;
 307                 else
 308                         engine->instmem.flush   = nv84_instmem_flush;
 309                 engine->mc.init                 = nv50_mc_init;
 310                 engine->mc.takedown             = nv50_mc_takedown;
 311                 engine->timer.init              = nv04_timer_init;
 312                 engine->timer.read              = nv04_timer_read;
 313                 engine->timer.takedown          = nv04_timer_takedown;
 314                 engine->fb.init                 = nv50_fb_init;
 315                 engine->fb.takedown             = nv50_fb_takedown;
 316                 engine->fifo.channels           = 128;
 317                 engine->fifo.init               = nv50_fifo_init;
 318                 engine->fifo.takedown           = nv50_fifo_takedown;
 319                 engine->fifo.disable            = nv04_fifo_disable;
 320                 engine->fifo.enable             = nv04_fifo_enable;
 321                 engine->fifo.reassign           = nv04_fifo_reassign;
 322                 engine->fifo.channel_id         = nv50_fifo_channel_id;
 323                 engine->fifo.create_context     = nv50_fifo_create_context;
 324                 engine->fifo.destroy_context    = nv50_fifo_destroy_context;
 325                 engine->fifo.load_context       = nv50_fifo_load_context;
 326                 engine->fifo.unload_context     = nv50_fifo_unload_context;
 327                 engine->fifo.tlb_flush          = nv50_fifo_tlb_flush;
 328                 engine->display.early_init      = nv50_display_early_init;
 329                 engine->display.late_takedown   = nv50_display_late_takedown;
 330                 engine->display.create          = nv50_display_create;
 331                 engine->display.destroy         = nv50_display_destroy;
 332                 engine->display.init            = nv50_display_init;
 333                 engine->display.fini            = nv50_display_fini;
 334                 engine->gpio.init               = nv50_gpio_init;
 335                 engine->gpio.fini               = nv50_gpio_fini;
 336                 engine->gpio.drive              = nv50_gpio_drive;
 337                 engine->gpio.sense              = nv50_gpio_sense;
 338                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 339                 switch (dev_priv->chipset) {
 340                 case 0x84:
 341                 case 0x86:
 342                 case 0x92:
 343                 case 0x94:
 344                 case 0x96:
 345                 case 0x98:
 346                 case 0xa0:
 347                 case 0xaa:
 348                 case 0xac:
 349                 case 0x50:
 350                         engine->pm.clocks_get   = nv50_pm_clocks_get;
 351                         engine->pm.clocks_pre   = nv50_pm_clocks_pre;
 352                         engine->pm.clocks_set   = nv50_pm_clocks_set;
 353                         break;
 354                 default:
 355                         engine->pm.clocks_get   = nva3_pm_clocks_get;
 356                         engine->pm.clocks_pre   = nva3_pm_clocks_pre;
 357                         engine->pm.clocks_set   = nva3_pm_clocks_set;
 358                         break;
 359                 }
 360                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 361                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 362                 if (dev_priv->chipset >= 0x84)
 363                         engine->pm.temp_get     = nv84_temp_get;
 364                 else
 365                         engine->pm.temp_get     = nv40_temp_get;
 366                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 367                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 368                 engine->vram.init               = nv50_vram_init;
 369                 engine->vram.takedown           = nv50_vram_fini;
 370                 engine->vram.get                = nv50_vram_new;
 371                 engine->vram.put                = nv50_vram_del;
 372                 engine->vram.flags_valid        = nv50_vram_flags_valid;
 373                 break;
 374         case 0xc0:
 375                 engine->instmem.init            = nvc0_instmem_init;
 376                 engine->instmem.takedown        = nvc0_instmem_takedown;
 377                 engine->instmem.suspend         = nvc0_instmem_suspend;
 378                 engine->instmem.resume          = nvc0_instmem_resume;
 379                 engine->instmem.get             = nv50_instmem_get;
 380                 engine->instmem.put             = nv50_instmem_put;
 381                 engine->instmem.map             = nv50_instmem_map;
 382                 engine->instmem.unmap           = nv50_instmem_unmap;
 383                 engine->instmem.flush           = nv84_instmem_flush;
 384                 engine->mc.init                 = nv50_mc_init;
 385                 engine->mc.takedown             = nv50_mc_takedown;
 386                 engine->timer.init              = nv04_timer_init;
 387                 engine->timer.read              = nv04_timer_read;
 388                 engine->timer.takedown          = nv04_timer_takedown;
 389                 engine->fb.init                 = nvc0_fb_init;
 390                 engine->fb.takedown             = nvc0_fb_takedown;
 391                 engine->fifo.channels           = 128;
 392                 engine->fifo.init               = nvc0_fifo_init;
 393                 engine->fifo.takedown           = nvc0_fifo_takedown;
 394                 engine->fifo.disable            = nvc0_fifo_disable;
 395                 engine->fifo.enable             = nvc0_fifo_enable;
 396                 engine->fifo.reassign           = nvc0_fifo_reassign;
 397                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 398                 engine->fifo.create_context     = nvc0_fifo_create_context;
 399                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 400                 engine->fifo.load_context       = nvc0_fifo_load_context;
 401                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 402                 engine->display.early_init      = nv50_display_early_init;
 403                 engine->display.late_takedown   = nv50_display_late_takedown;
 404                 engine->display.create          = nv50_display_create;
 405                 engine->display.destroy         = nv50_display_destroy;
 406                 engine->display.init            = nv50_display_init;
 407                 engine->display.fini            = nv50_display_fini;
 408                 engine->gpio.init               = nv50_gpio_init;
 409                 engine->gpio.fini               = nv50_gpio_fini;
 410                 engine->gpio.drive              = nv50_gpio_drive;
 411                 engine->gpio.sense              = nv50_gpio_sense;
 412                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 413                 engine->vram.init               = nvc0_vram_init;
 414                 engine->vram.takedown           = nv50_vram_fini;
 415                 engine->vram.get                = nvc0_vram_new;
 416                 engine->vram.put                = nv50_vram_del;
 417                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 418                 engine->pm.temp_get             = nv84_temp_get;
 419                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 420                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 421                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 422                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 423                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 424                 engine->pm.pwm_get              = nv50_pm_pwm_get;
 425                 engine->pm.pwm_set              = nv50_pm_pwm_set;
 426                 break;
 427         case 0xd0:
 428                 engine->instmem.init            = nvc0_instmem_init;
 429                 engine->instmem.takedown        = nvc0_instmem_takedown;
 430                 engine->instmem.suspend         = nvc0_instmem_suspend;
 431                 engine->instmem.resume          = nvc0_instmem_resume;
 432                 engine->instmem.get             = nv50_instmem_get;
 433                 engine->instmem.put             = nv50_instmem_put;
 434                 engine->instmem.map             = nv50_instmem_map;
 435                 engine->instmem.unmap           = nv50_instmem_unmap;
 436                 engine->instmem.flush           = nv84_instmem_flush;
 437                 engine->mc.init                 = nv50_mc_init;
 438                 engine->mc.takedown             = nv50_mc_takedown;
 439                 engine->timer.init              = nv04_timer_init;
 440                 engine->timer.read              = nv04_timer_read;
 441                 engine->timer.takedown          = nv04_timer_takedown;
 442                 engine->fb.init                 = nvc0_fb_init;
 443                 engine->fb.takedown             = nvc0_fb_takedown;
 444                 engine->fifo.channels           = 128;
 445                 engine->fifo.init               = nvc0_fifo_init;
 446                 engine->fifo.takedown           = nvc0_fifo_takedown;
 447                 engine->fifo.disable            = nvc0_fifo_disable;
 448                 engine->fifo.enable             = nvc0_fifo_enable;
 449                 engine->fifo.reassign           = nvc0_fifo_reassign;
 450                 engine->fifo.channel_id         = nvc0_fifo_channel_id;
 451                 engine->fifo.create_context     = nvc0_fifo_create_context;
 452                 engine->fifo.destroy_context    = nvc0_fifo_destroy_context;
 453                 engine->fifo.load_context       = nvc0_fifo_load_context;
 454                 engine->fifo.unload_context     = nvc0_fifo_unload_context;
 455                 engine->display.early_init      = nouveau_stub_init;
 456                 engine->display.late_takedown   = nouveau_stub_takedown;
 457                 engine->display.create          = nvd0_display_create;
 458                 engine->display.destroy         = nvd0_display_destroy;
 459                 engine->display.init            = nvd0_display_init;
 460                 engine->display.fini            = nvd0_display_fini;
 461                 engine->gpio.init               = nv50_gpio_init;
 462                 engine->gpio.fini               = nv50_gpio_fini;
 463                 engine->gpio.drive              = nvd0_gpio_drive;
 464                 engine->gpio.sense              = nvd0_gpio_sense;
 465                 engine->gpio.irq_enable         = nv50_gpio_irq_enable;
 466                 engine->vram.init               = nvc0_vram_init;
 467                 engine->vram.takedown           = nv50_vram_fini;
 468                 engine->vram.get                = nvc0_vram_new;
 469                 engine->vram.put                = nv50_vram_del;
 470                 engine->vram.flags_valid        = nvc0_vram_flags_valid;
 471                 engine->pm.temp_get             = nv84_temp_get;
 472                 engine->pm.clocks_get           = nvc0_pm_clocks_get;
 473                 engine->pm.clocks_pre           = nvc0_pm_clocks_pre;
 474                 engine->pm.clocks_set           = nvc0_pm_clocks_set;
 475                 engine->pm.voltage_get          = nouveau_voltage_gpio_get;
 476                 engine->pm.voltage_set          = nouveau_voltage_gpio_set;
 477                 break;
 478         default:
 479                 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
 480                 return 1;
 481         }
 482
 483         /* headless mode */
 484         if (nouveau_modeset == 2) {
 485                 engine->display.early_init = nouveau_stub_init;
 486                 engine->display.late_takedown = nouveau_stub_takedown;
 487                 engine->display.create = nouveau_stub_init;
 488                 engine->display.init = nouveau_stub_init;
 489                 engine->display.destroy = nouveau_stub_takedown;
 490         }
 491
 492         return 0;
 493 }
 494
 495 static unsigned int
 496 nouveau_vga_set_decode(void *priv, bool state)
 497 {
 498         struct drm_device *dev = priv;
 499         struct drm_nouveau_private *dev_priv = dev->dev_private;
 500
 501         if (dev_priv->chipset >= 0x40)
 502                 nv_wr32(dev, 0x88054, state);
 503         else
 504                 nv_wr32(dev, 0x1854, state);
 505
 506         if (state)
 507                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 508                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 509         else
 510                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 511 }
 512
 513 static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
 514                                          enum vga_switcheroo_state state)
 515 {
 516         struct drm_device *dev = pci_get_drvdata(pdev);
 517         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 518         if (state == VGA_SWITCHEROO_ON) {
 519                 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
 520                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 521                 nouveau_pci_resume(pdev);
 522                 drm_kms_helper_poll_enable(dev);
 523                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 524         } else {
 525                 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
 526                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 527                 drm_kms_helper_poll_disable(dev);
 528                 nouveau_switcheroo_optimus_dsm();
 529                 nouveau_pci_suspend(pdev, pmm);
 530                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 531         }
 532 }
 533
 534 static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
 535 {
 536         struct drm_device *dev = pci_get_drvdata(pdev);
 537         nouveau_fbcon_output_poll_changed(dev);
 538 }
 539
 540 static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
 541 {
 542         struct drm_device *dev = pci_get_drvdata(pdev);
 543         bool can_switch;
 544
 545         spin_lock(&dev->count_lock);
 546         can_switch = (dev->open_count == 0);
 547         spin_unlock(&dev->count_lock);
 548         return can_switch;
 549 }
 550
 551 int
 552 nouveau_card_init(struct drm_device *dev)
 553 {
 554         struct drm_nouveau_private *dev_priv = dev->dev_private;
 555         struct nouveau_engine *engine;
 556         int ret, e = 0;
 557
 558         vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
 559         vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
 560                                        nouveau_switcheroo_reprobe,
 561                                        nouveau_switcheroo_can_switch);
 562
 563         /* Initialise internal driver API hooks */
 564         ret = nouveau_init_engine_ptrs(dev);
 565         if (ret)
 566                 goto out;
 567         engine = &dev_priv->engine;
 568         spin_lock_init(&dev_priv->channels.lock);
 569         spin_lock_init(&dev_priv->tile.lock);
 570         spin_lock_init(&dev_priv->context_switch_lock);
 571         spin_lock_init(&dev_priv->vm_lock);
 572
 573         /* Make the CRTCs and I2C buses accessible */
 574         ret = engine->display.early_init(dev);
 575         if (ret)
 576                 goto out;
 577
 578         /* Parse BIOS tables / Run init tables if card not POSTed */
 579         ret = nouveau_bios_init(dev);
 580         if (ret)
 581                 goto out_display_early;
 582
 583         /* workaround an odd issue on nvc1 by disabling the device's
 584          * nosnoop capability.  hopefully won't cause issues until a
 585          * better fix is found - assuming there is one...
 586          */
 587         if (dev_priv->chipset == 0xc1) {
 588                 nv_mask(dev, 0x00088080, 0x00000800, 0x00000000);
 589         }
 590
 591         nouveau_pm_init(dev);
 592
 593         ret = engine->vram.init(dev);
 594         if (ret)
 595                 goto out_bios;
 596
 597         ret = nouveau_gpuobj_init(dev);
 598         if (ret)
 599                 goto out_vram;
 600
 601         ret = engine->instmem.init(dev);
 602         if (ret)
 603                 goto out_gpuobj;
 604
 605         ret = nouveau_mem_vram_init(dev);
 606         if (ret)
 607                 goto out_instmem;
 608
 609         ret = nouveau_mem_gart_init(dev);
 610         if (ret)
 611                 goto out_ttmvram;
 612
 613         /* PMC */
 614         ret = engine->mc.init(dev);
 615         if (ret)
 616                 goto out_gart;
 617
 618         /* PGPIO */
 619         ret = nouveau_gpio_create(dev);
 620         if (ret)
 621                 goto out_mc;
 622
 623         /* PTIMER */
 624         ret = engine->timer.init(dev);
 625         if (ret)
 626                 goto out_gpio;
 627
 628         /* PFB */
 629         ret = engine->fb.init(dev);
 630         if (ret)
 631                 goto out_timer;
 632
 633         if (!dev_priv->noaccel) {
 634                 switch (dev_priv->card_type) {
 635                 case NV_04:
 636                         nv04_graph_create(dev);
 637                         break;
 638                 case NV_10:
 639                         nv10_graph_create(dev);
 640                         break;
 641                 case NV_20:
 642                 case NV_30:
 643                         nv20_graph_create(dev);
 644                         break;
 645                 case NV_40:
 646                         nv40_graph_create(dev);
 647                         break;
 648                 case NV_50:
 649                         nv50_graph_create(dev);
 650                         break;
 651                 case NV_C0:
 652                 case NV_D0:
 653                         nvc0_graph_create(dev);
 654                         break;
 655                 default:
 656                         break;
 657                 }
 658
 659                 switch (dev_priv->chipset) {
 660                 case 0x84:
 661                 case 0x86:
 662                 case 0x92:
 663                 case 0x94:
 664                 case 0x96:
 665                 case 0xa0:
 666                         nv84_crypt_create(dev);
 667                         break;
 668                 case 0x98:
 669                 case 0xaa:
 670                 case 0xac:
 671                         nv98_crypt_create(dev);
 672                         break;
 673                 }
 674
 675                 switch (dev_priv->card_type) {
 676                 case NV_50:
 677                         switch (dev_priv->chipset) {
 678                         case 0xa3:
 679                         case 0xa5:
 680                         case 0xa8:
 681                         case 0xaf:
 682                                 nva3_copy_create(dev);
 683                                 break;
 684                         }
 685                         break;
 686                 case NV_C0:
 687                         nvc0_copy_create(dev, 0);
 688                         nvc0_copy_create(dev, 1);
 689                         break;
 690                 default:
 691                         break;
 692                 }
 693
 694                 if (dev_priv->chipset >= 0xa3 || dev_priv->chipset == 0x98) {
 695                         nv84_bsp_create(dev);
 696                         nv84_vp_create(dev);
 697                         nv98_ppp_create(dev);
 698                 } else
 699                 if (dev_priv->chipset >= 0x84) {
 700                         nv50_mpeg_create(dev);
 701                         nv84_bsp_create(dev);
 702                         nv84_vp_create(dev);
 703                 } else
 704                 if (dev_priv->chipset >= 0x50) {
 705                         nv50_mpeg_create(dev);
 706                 } else
 707                 if (dev_priv->card_type == NV_40 ||
 708                     dev_priv->chipset == 0x31 ||
 709                     dev_priv->chipset == 0x34 ||
 710                     dev_priv->chipset == 0x36) {
 711                         nv31_mpeg_create(dev);
 712                 }
 713
 714                 for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
 715                         if (dev_priv->eng[e]) {
 716                                 ret = dev_priv->eng[e]->init(dev, e);
 717                                 if (ret)
 718                                         goto out_engine;
 719                         }
 720                 }
 721
 722                 /* PFIFO */
 723                 ret = engine->fifo.init(dev);
 724                 if (ret)
 725                         goto out_engine;
 726         }
 727
 728         ret = nouveau_irq_init(dev);
 729         if (ret)
 730                 goto out_fifo;
 731
 732         ret = nouveau_display_create(dev);
 733         if (ret)
 734                 goto out_irq;
 735
 736         nouveau_backlight_init(dev);
 737
 738         if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
 739                 ret = nouveau_fence_init(dev);
 740                 if (ret)
 741                         goto out_disp;
 742
 743                 ret = nouveau_channel_alloc(dev, &dev_priv->channel, NULL,
 744                                             NvDmaFB, NvDmaTT);
 745                 if (ret)
 746                         goto out_fence;
 747
 748                 mutex_unlock(&dev_priv->channel->mutex);
 749         }
 750
 751         if (dev->mode_config.num_crtc) {
 752                 ret = nouveau_display_init(dev);
 753                 if (ret)
 754                         goto out_chan;
 755
 756                 nouveau_fbcon_init(dev);
 757         }
 758
 759         return 0;
 760
 761 out_chan:
 762         nouveau_channel_put_unlocked(&dev_priv->channel);
 763 out_fence:
 764         nouveau_fence_fini(dev);
 765 out_disp:
 766         nouveau_backlight_exit(dev);
 767         nouveau_display_destroy(dev);
 768 out_irq:
 769         nouveau_irq_fini(dev);
 770 out_fifo:
 771         if (!dev_priv->noaccel)
 772                 engine->fifo.takedown(dev);
 773 out_engine:
 774         if (!dev_priv->noaccel) {
 775                 for (e = e - 1; e >= 0; e--) {
 776                         if (!dev_priv->eng[e])
 777                                 continue;
 778                         dev_priv->eng[e]->fini(dev, e, false);
 779                         dev_priv->eng[e]->destroy(dev,e );
 780                 }
 781         }
 782
 783         engine->fb.takedown(dev);
 784 out_timer:
 785         engine->timer.takedown(dev);
 786 out_gpio:
 787         nouveau_gpio_destroy(dev);
 788 out_mc:
 789         engine->mc.takedown(dev);
 790 out_gart:
 791         nouveau_mem_gart_fini(dev);
 792 out_ttmvram:
 793         nouveau_mem_vram_fini(dev);
 794 out_instmem:
 795         engine->instmem.takedown(dev);
 796 out_gpuobj:
 797         nouveau_gpuobj_takedown(dev);
 798 out_vram:
 799         engine->vram.takedown(dev);
 800 out_bios:
 801         nouveau_pm_fini(dev);
 802         nouveau_bios_takedown(dev);
 803 out_display_early:
 804         engine->display.late_takedown(dev);
 805 out:
 806         vga_client_register(dev->pdev, NULL, NULL, NULL);
 807         return ret;
 808 }
 809
 810 static void nouveau_card_takedown(struct drm_device *dev)
 811 {
 812         struct drm_nouveau_private *dev_priv = dev->dev_private;
 813         struct nouveau_engine *engine = &dev_priv->engine;
 814         int e;
 815
 816         if (dev->mode_config.num_crtc) {
 817                 nouveau_fbcon_fini(dev);
 818                 nouveau_display_fini(dev);
 819         }
 820
 821         if (dev_priv->channel) {
 822                 nouveau_channel_put_unlocked(&dev_priv->channel);
 823                 nouveau_fence_fini(dev);
 824         }
 825
 826         nouveau_backlight_exit(dev);
 827         nouveau_display_destroy(dev);
 828
 829         if (!dev_priv->noaccel) {
 830                 engine->fifo.takedown(dev);
 831                 for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
 832                         if (dev_priv->eng[e]) {
 833                                 dev_priv->eng[e]->fini(dev, e, false);
 834                                 dev_priv->eng[e]->destroy(dev,e );
 835                         }
 836                 }
 837         }
 838         engine->fb.takedown(dev);
 839         engine->timer.takedown(dev);
 840         nouveau_gpio_destroy(dev);
 841         engine->mc.takedown(dev);
 842         engine->display.late_takedown(dev);
 843
 844         if (dev_priv->vga_ram) {
 845                 nouveau_bo_unpin(dev_priv->vga_ram);
 846                 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
 847         }
 848
 849         mutex_lock(&dev->struct_mutex);
 850         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
 851         ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
 852         mutex_unlock(&dev->struct_mutex);
 853         nouveau_mem_gart_fini(dev);
 854         nouveau_mem_vram_fini(dev);
 855
 856         engine->instmem.takedown(dev);
 857         nouveau_gpuobj_takedown(dev);
 858         engine->vram.takedown(dev);
 859
 860         nouveau_irq_fini(dev);
 861
 862         nouveau_pm_fini(dev);
 863         nouveau_bios_takedown(dev);
 864
 865         vga_client_register(dev->pdev, NULL, NULL, NULL);
 866 }
 867
 868 int
 869 nouveau_open(struct drm_device *dev, struct drm_file *file_priv)
 870 {
 871         struct drm_nouveau_private *dev_priv = dev->dev_private;
 872         struct nouveau_fpriv *fpriv;
 873         int ret;
 874
 875         fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 876         if (unlikely(!fpriv))
 877                 return -ENOMEM;
 878
 879         spin_lock_init(&fpriv->lock);
 880         INIT_LIST_HEAD(&fpriv->channels);
 881
 882         if (dev_priv->card_type == NV_50) {
 883                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0020000000ULL,
 884                                      &fpriv->vm);
 885                 if (ret) {
 886                         kfree(fpriv);
 887                         return ret;
 888                 }
 889         } else
 890         if (dev_priv->card_type >= NV_C0) {
 891                 ret = nouveau_vm_new(dev, 0, (1ULL << 40), 0x0008000000ULL,
 892                                      &fpriv->vm);
 893                 if (ret) {
 894                         kfree(fpriv);
 895                         return ret;
 896                 }
 897         }
 898
 899         file_priv->driver_priv = fpriv;
 900         return 0;
 901 }
 902
 903 /* here a client dies, release the stuff that was allocated for its
 904  * file_priv */
 905 void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
 906 {
 907         nouveau_channel_cleanup(dev, file_priv);
 908 }
 909
 910 void
 911 nouveau_postclose(struct drm_device *dev, struct drm_file *file_priv)
 912 {
 913         struct nouveau_fpriv *fpriv = nouveau_fpriv(file_priv);
 914         nouveau_vm_ref(NULL, &fpriv->vm, NULL);
 915         kfree(fpriv);
 916 }
 917
 918 /* first module load, setup the mmio/fb mapping */
 919 /* KMS: we need mmio at load time, not when the first drm client opens. */
 920 int nouveau_firstopen(struct drm_device *dev)
 921 {
 922         return 0;
 923 }
 924
 925 /* if we have an OF card, copy vbios to RAMIN */
 926 static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
 927 {
 928 #if defined(__powerpc__)
 929         int size, i;
 930         const uint32_t *bios;
 931         struct device_node *dn = pci_device_to_OF_node(dev->pdev);
 932         if (!dn) {
 933                 NV_INFO(dev, "Unable to get the OF node\n");
 934                 return;
 935         }
 936
 937         bios = of_get_property(dn, "NVDA,BMP", &size);
 938         if (bios) {
 939                 for (i = 0; i < size; i += 4)
 940                         nv_wi32(dev, i, bios[i/4]);
 941                 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
 942         } else {
 943                 NV_INFO(dev, "Unable to get the OF bios\n");
 944         }
 945 #endif
 946 }
 947
 948 static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
 949 {
 950         struct pci_dev *pdev = dev->pdev;
 951         struct apertures_struct *aper = alloc_apertures(3);
 952         if (!aper)
 953                 return NULL;
 954
 955         aper->ranges[0].base = pci_resource_start(pdev, 1);
 956         aper->ranges[0].size = pci_resource_len(pdev, 1);
 957         aper->count = 1;
 958
 959         if (pci_resource_len(pdev, 2)) {
 960                 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
 961                 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
 962                 aper->count++;
 963         }
 964
 965         if (pci_resource_len(pdev, 3)) {
 966                 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
 967                 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
 968                 aper->count++;
 969         }
 970
 971         return aper;
 972 }
 973
 974 static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
 975 {
 976         struct drm_nouveau_private *dev_priv = dev->dev_private;
 977         bool primary = false;
 978         dev_priv->apertures = nouveau_get_apertures(dev);
 979         if (!dev_priv->apertures)
 980                 return -ENOMEM;
 981
 982 #ifdef CONFIG_X86
 983         primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 984 #endif
 985
 986         remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
 987         return 0;
 988 }
 989
 990 int nouveau_load(struct drm_device *dev, unsigned long flags)
 991 {
 992         struct drm_nouveau_private *dev_priv;
 993         uint32_t reg0, strap;
 994         resource_size_t mmio_start_offs;
 995         int ret;
 996
 997         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 998         if (!dev_priv) {
 999                 ret = -ENOMEM;
1000                 goto err_out;
1001         }
1002         dev->dev_private = dev_priv;
1003         dev_priv->dev = dev;
1004
1005         dev_priv->flags = flags & NOUVEAU_FLAGS;
1006
1007         NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
1008                  dev->pci_vendor, dev->pci_device, dev->pdev->class);
1009
1010         /* resource 0 is mmio regs */
1011         /* resource 1 is linear FB */
1012         /* resource 2 is RAMIN (mmio regs + 0x1000000) */
1013         /* resource 6 is bios */
1014
1015         /* map the mmio regs */
1016         mmio_start_offs = pci_resource_start(dev->pdev, 0);
1017         dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
1018         if (!dev_priv->mmio) {
1019                 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
1020                          "Please report your setup to " DRIVER_EMAIL "\n");
1021                 ret = -EINVAL;
1022                 goto err_priv;
1023         }
1024         NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
1025                                         (unsigned long long)mmio_start_offs);
1026
1027 #ifdef __BIG_ENDIAN
1028         /* Put the card in BE mode if it's not */
1029         if (nv_rd32(dev, NV03_PMC_BOOT_1) != 0x01000001)
1030                 nv_wr32(dev, NV03_PMC_BOOT_1, 0x01000001);
1031
1032         DRM_MEMORYBARRIER();
1033 #endif
1034
1035         /* Time to determine the card architecture */
1036         reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
1037
1038         /* We're dealing with >=NV10 */
1039         if ((reg0 & 0x0f000000) > 0) {
1040                 /* Bit 27-20 contain the architecture in hex */
1041                 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
1042         /* NV04 or NV05 */
1043         } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1044                 if (reg0 & 0x00f00000)
1045                         dev_priv->chipset = 0x05;
1046                 else
1047                         dev_priv->chipset = 0x04;
1048         } else
1049                 dev_priv->chipset = 0xff;
1050
1051         switch (dev_priv->chipset & 0xf0) {
1052         case 0x00:
1053         case 0x10:
1054         case 0x20:
1055         case 0x30:
1056                 dev_priv->card_type = dev_priv->chipset & 0xf0;
1057                 break;
1058         case 0x40:
1059         case 0x60:
1060                 dev_priv->card_type = NV_40;
1061                 break;
1062         case 0x50:
1063         case 0x80:
1064         case 0x90:
1065         case 0xa0:
1066                 dev_priv->card_type = NV_50;
1067                 break;
1068         case 0xc0:
1069                 dev_priv->card_type = NV_C0;
1070                 break;
1071         case 0xd0:
1072                 dev_priv->card_type = NV_D0;
1073                 break;
1074         default:
1075                 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
1076                 ret = -EINVAL;
1077                 goto err_mmio;
1078         }
1079
1080         NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
1081                 dev_priv->card_type, reg0);
1082
1083         /* determine frequency of timing crystal */
1084         strap = nv_rd32(dev, 0x101000);
1085         if ( dev_priv->chipset < 0x17 ||
1086             (dev_priv->chipset >= 0x20 && dev_priv->chipset <= 0x25))
1087                 strap &= 0x00000040;
1088         else
1089                 strap &= 0x00400040;
1090
1091         switch (strap) {
1092         case 0x00000000: dev_priv->crystal = 13500; break;
1093         case 0x00000040: dev_priv->crystal = 14318; break;
1094         case 0x00400000: dev_priv->crystal = 27000; break;
1095         case 0x00400040: dev_priv->crystal = 25000; break;
1096         }
1097
1098         NV_DEBUG(dev, "crystal freq: %dKHz\n", dev_priv->crystal);
1099
1100         /* Determine whether we'll attempt acceleration or not, some
1101          * cards are disabled by default here due to them being known
1102          * non-functional, or never been tested due to lack of hw.
1103          */
1104         dev_priv->noaccel = !!nouveau_noaccel;
1105         if (nouveau_noaccel == -1) {
1106                 switch (dev_priv->chipset) {
1107                 case 0xd9: /* known broken */
1108                         NV_INFO(dev, "acceleration disabled by default, pass "
1109                                      "noaccel=0 to force enable\n");
1110                         dev_priv->noaccel = true;
1111                         break;
1112                 default:
1113                         dev_priv->noaccel = false;
1114                         break;
1115                 }
1116         }
1117
1118         ret = nouveau_remove_conflicting_drivers(dev);
1119         if (ret)
1120                 goto err_mmio;
1121
1122         /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
1123         if (dev_priv->card_type >= NV_40) {
1124                 int ramin_bar = 2;
1125                 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
1126                         ramin_bar = 3;
1127
1128                 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
1129                 dev_priv->ramin =
1130                         ioremap(pci_resource_start(dev->pdev, ramin_bar),
1131                                 dev_priv->ramin_size);
1132                 if (!dev_priv->ramin) {
1133                         NV_ERROR(dev, "Failed to map PRAMIN BAR\n");
1134                         ret = -ENOMEM;
1135                         goto err_mmio;
1136                 }
1137         } else {
1138                 dev_priv->ramin_size = 1 * 1024 * 1024;
1139                 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
1140                                           dev_priv->ramin_size);
1141                 if (!dev_priv->ramin) {
1142                         NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
1143                         ret = -ENOMEM;
1144                         goto err_mmio;
1145                 }
1146         }
1147
1148         nouveau_OF_copy_vbios_to_ramin(dev);
1149
1150         /* Special flags */
1151         if (dev->pci_device == 0x01a0)
1152                 dev_priv->flags |= NV_NFORCE;
1153         else if (dev->pci_device == 0x01f0)
1154                 dev_priv->flags |= NV_NFORCE2;
1155
1156         /* For kernel modesetting, init card now and bring up fbcon */
1157         ret = nouveau_card_init(dev);
1158         if (ret)
1159                 goto err_ramin;
1160
1161         return 0;
1162
1163 err_ramin:
1164         iounmap(dev_priv->ramin);
1165 err_mmio:
1166         iounmap(dev_priv->mmio);
1167 err_priv:
1168         kfree(dev_priv);
1169         dev->dev_private = NULL;
1170 err_out:
1171         return ret;
1172 }
1173
1174 void nouveau_lastclose(struct drm_device *dev)
1175 {
1176         vga_switcheroo_process_delayed_switch();
1177 }
1178
1179 int nouveau_unload(struct drm_device *dev)
1180 {
1181         struct drm_nouveau_private *dev_priv = dev->dev_private;
1182
1183         nouveau_card_takedown(dev);
1184
1185         iounmap(dev_priv->mmio);
1186         iounmap(dev_priv->ramin);
1187
1188         kfree(dev_priv);
1189         dev->dev_private = NULL;
1190         return 0;
1191 }
1192
1193 int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1194                                                 struct drm_file *file_priv)
1195 {
1196         struct drm_nouveau_private *dev_priv = dev->dev_private;
1197         struct drm_nouveau_getparam *getparam = data;
1198
1199         switch (getparam->param) {
1200         case NOUVEAU_GETPARAM_CHIPSET_ID:
1201                 getparam->value = dev_priv->chipset;
1202                 break;
1203         case NOUVEAU_GETPARAM_PCI_VENDOR:
1204                 getparam->value = dev->pci_vendor;
1205                 break;
1206         case NOUVEAU_GETPARAM_PCI_DEVICE:
1207                 getparam->value = dev->pci_device;
1208                 break;
1209         case NOUVEAU_GETPARAM_BUS_TYPE:
1210                 if (drm_pci_device_is_agp(dev))
1211                         getparam->value = NV_AGP;
1212                 else if (pci_is_pcie(dev->pdev))
1213                         getparam->value = NV_PCIE;
1214                 else
1215                         getparam->value = NV_PCI;
1216                 break;
1217         case NOUVEAU_GETPARAM_FB_SIZE:
1218                 getparam->value = dev_priv->fb_available_size;
1219                 break;
1220         case NOUVEAU_GETPARAM_AGP_SIZE:
1221                 getparam->value = dev_priv->gart_info.aper_size;
1222                 break;
1223         case NOUVEAU_GETPARAM_VM_VRAM_BASE:
1224                 getparam->value = 0; /* deprecated */
1225                 break;
1226         case NOUVEAU_GETPARAM_PTIMER_TIME:
1227                 getparam->value = dev_priv->engine.timer.read(dev);
1228                 break;
1229         case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1230                 getparam->value = 1;
1231                 break;
1232         case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
1233                 getparam->value = 1;
1234                 break;
1235         case NOUVEAU_GETPARAM_GRAPH_UNITS:
1236                 /* NV40 and NV50 versions are quite different, but register
1237                  * address is the same. User is supposed to know the card
1238                  * family anyway... */
1239                 if (dev_priv->chipset >= 0x40) {
1240                         getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1241                         break;
1242                 }
1243                 /* FALLTHRU */
1244         default:
1245                 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
1246                 return -EINVAL;
1247         }
1248
1249         return 0;
1250 }
1251
1252 int
1253 nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1254                        struct drm_file *file_priv)
1255 {
1256         struct drm_nouveau_setparam *setparam = data;
1257
1258         switch (setparam->param) {
1259         default:
1260                 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
1261                 return -EINVAL;
1262         }
1263
1264         return 0;
1265 }
1266
1267 /* Wait until (value(reg) & mask) == val, up until timeout has hit */
1268 bool
1269 nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1270                 uint32_t reg, uint32_t mask, uint32_t val)
1271 {
1272         struct drm_nouveau_private *dev_priv = dev->dev_private;
1273         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1274         uint64_t start = ptimer->read(dev);
1275
1276         do {
1277                 if ((nv_rd32(dev, reg) & mask) == val)
1278                         return true;
1279         } while (ptimer->read(dev) - start < timeout);
1280
1281         return false;
1282 }
1283
1284 /* Wait until (value(reg) & mask) != val, up until timeout has hit */
1285 bool
1286 nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1287                 uint32_t reg, uint32_t mask, uint32_t val)
1288 {
1289         struct drm_nouveau_private *dev_priv = dev->dev_private;
1290         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1291         uint64_t start = ptimer->read(dev);
1292
1293         do {
1294                 if ((nv_rd32(dev, reg) & mask) != val)
1295                         return true;
1296         } while (ptimer->read(dev) - start < timeout);
1297
1298         return false;
1299 }
1300
1301 /* Wait until cond(data) == true, up until timeout has hit */
1302 bool
1303 nouveau_wait_cb(struct drm_device *dev, u64 timeout,
1304                 bool (*cond)(void *), void *data)
1305 {
1306         struct drm_nouveau_private *dev_priv = dev->dev_private;
1307         struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1308         u64 start = ptimer->read(dev);
1309
1310         do {
1311                 if (cond(data) == true)
1312                         return true;
1313         } while (ptimer->read(dev) - start < timeout);
1314
1315         return false;
1316 }
1317
1318 /* Waits for PGRAPH to go completely idle */
1319 bool nouveau_wait_for_idle(struct drm_device *dev)
1320 {
1321         struct drm_nouveau_private *dev_priv = dev->dev_private;
1322         uint32_t mask = ~0;
1323
1324         if (dev_priv->card_type == NV_40)
1325                 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1326
1327         if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
1328                 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1329                          nv_rd32(dev, NV04_PGRAPH_STATUS));
1330                 return false;
1331         }
1332
1333         return true;
1334 }
1335