drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h

   1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__
   2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl2080_ctrl2080internal_h__
   3
   4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.54.03 */
   5
   6 /*
   7  * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
   8  * SPDX-License-Identifier: MIT
   9  *
  10  * Permission is hereby granted, free of charge, to any person obtaining a
  11  * copy of this software and associated documentation files (the "Software"),
  12  * to deal in the Software without restriction, including without limitation
  13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  14  * and/or sell copies of the Software, and to permit persons to whom the
  15  * Software is furnished to do so, subject to the following conditions:
  16  *
  17  * The above copyright notice and this permission notice shall be included in
  18  * all copies or substantial portions of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  */
  28
  29 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO (0x20800a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS_MESSAGE_ID" */
  30
  31 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
  32     NvU32  feHwSysCap;
  33     NvU32  windowPresentMask;
  34     NvBool bFbRemapperEnabled;
  35     NvU32  numHeads;
  36     NvBool bPrimaryVga;
  37     NvU32  i2cPort;
  38     NvU32  internalDispActiveMask;
  39 } NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
  40
  41 #define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES         8
  42
  43 #define NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT 0x19
  44
  45 typedef struct NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO {
  46     NvU32 size;
  47     NvU32 alignment;
  48 } NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO;
  49
  50 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
  51     NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
  52 } NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
  53
  54 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
  55     NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
  56 } NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
  57
  58 #define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
  59
  60 typedef struct NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO {
  61     NvU32 engDesc;
  62     NvU32 ctxAttr;
  63     NvU32 ctxBufferSize;
  64     NvU32 addrSpaceList;
  65     NvU32 registerBase;
  66 } NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO;
  67 #define NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS     0x40
  68
  69 #define NV2080_CTRL_CMD_INTERNAL_GET_CONSTRUCTED_FALCON_INFO (0x20800a42) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS_MESSAGE_ID" */
  70
  71 typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
  72     NvU32                                        numConstructedFalcons;
  73     NV2080_CTRL_INTERNAL_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_CMD_INTERNAL_MAX_CONSTRUCTED_FALCONS];
  74 } NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
  75
  76 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM (0x20800a49) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS_MESSAGE_ID" */
  77
  78 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS {
  79     NV_DECLARE_ALIGNED(NvU64 instMemPhysAddr, 8);
  80     NV_DECLARE_ALIGNED(NvU64 instMemSize, 8);
  81     NvU32 instMemAddrSpace;
  82     NvU32 instMemCpuCacheAttr;
  83 } NV2080_CTRL_INTERNAL_DISPLAY_WRITE_INST_MEM_PARAMS;
  84
  85 #define NV2080_CTRL_CMD_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER (0x20800a58) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS_MESSAGE_ID" */
  86
  87 typedef struct NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS {
  88     NvU32  addressSpace;
  89     NV_DECLARE_ALIGNED(NvU64 physicalAddr, 8);
  90     NV_DECLARE_ALIGNED(NvU64 limit, 8);
  91     NvU32  cacheSnoop;
  92     NvU32  hclass;
  93     NvU32  channelInstance;
  94     NvBool valid;
  95 } NV2080_CTRL_INTERNAL_DISPLAY_CHANNEL_PUSHBUFFER_PARAMS;
  96
  97 #define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
  98
  99 #define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE       128
 100
 101 typedef enum NV2080_INTR_CATEGORY {
 102     NV2080_INTR_CATEGORY_DEFAULT = 0,
 103     NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
 104     NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
 105     NV2080_INTR_CATEGORY_RUNLIST = 3,
 106     NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
 107     NV2080_INTR_CATEGORY_UVM_OWNED = 5,
 108     NV2080_INTR_CATEGORY_UVM_SHARED = 6,
 109     NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
 110 } NV2080_INTR_CATEGORY;
 111
 112 typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
 113     NvU8 subtreeStart;
 114     NvU8 subtreeEnd;
 115 } NV2080_INTR_CATEGORY_SUBTREE_MAP;
 116
 117 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
 118     NvU16 engineIdx;
 119     NvU32 pmcIntrMask;
 120     NvU32 vectorStall;
 121     NvU32 vectorNonStall;
 122 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY;
 123
 124 typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
 125     NvU32                                            tableLen;
 126     NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
 127     NV2080_INTR_CATEGORY_SUBTREE_MAP                 subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
 128 } NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
 129
 130 #define NV2080_CTRL_CMD_INTERNAL_FBSR_INIT (0x20800ac2) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS_MESSAGE_ID" */
 131
 132 typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
 133     NvU32    fbsrType;
 134     NvU32    numRegions;
 135     NvHandle hClient;
 136     NvHandle hSysMem;
 137     NV_DECLARE_ALIGNED(NvU64 gspFbAllocsSysOffset, 8);
 138     NvBool   bEnteringGcoffState;
 139 } NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
 140
 141 #define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
 142
 143 typedef struct NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS {
 144     NvU32    fbsrType;
 145     NvHandle hClient;
 146     NvHandle hVidMem;
 147     NV_DECLARE_ALIGNED(NvU64 vidOffset, 8);
 148     NV_DECLARE_ALIGNED(NvU64 sysOffset, 8);
 149     NV_DECLARE_ALIGNED(NvU64 size, 8);
 150 } NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS;
 151
 152 #define NV2080_CTRL_CMD_INTERNAL_INIT_BRIGHTC_STATE_LOAD (0x20800ac6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS_MESSAGE_ID" */
 153
 154 #define NV2080_CTRL_ACPI_DSM_READ_SIZE                   (0x1000) /* finn: Evaluated from "(4 * 1024)" */
 155
 156 typedef struct NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS {
 157     NvU32 status;
 158     NvU16 backLightDataSize;
 159     NvU8  backLightData[NV2080_CTRL_ACPI_DSM_READ_SIZE];
 160 } NV2080_CTRL_INTERNAL_INIT_BRIGHTC_STATE_LOAD_PARAMS;
 161
 162 #endif