1 #ifndef __src_nvidia_generated_g_kernel_fifo_nvoc_h__
2 #define __src_nvidia_generated_g_kernel_fifo_nvoc_h__
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
7 * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8 * SPDX-License-Identifier: MIT
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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26 * DEALINGS IN THE SOFTWARE.
31 /* *************************************************************************
33 * THINK BEFORE CHANGING ENUM ORDER HERE.
34 * VGPU-guest uses this same ordering. Because this enum is not versioned,
35 * changing the order here WILL BREAK old-guest-on-newer-host compatibility.
36 * ************************************************************************/
38 // *ENG_XYZ, e.g.: ENG_GR, ENG_CE etc.,
39 ENGINE_INFO_TYPE_ENG_DESC = 0,
42 ENGINE_INFO_TYPE_FIFO_TAG,
45 ENGINE_INFO_TYPE_RM_ENGINE_TYPE,
48 // runlist id (meaning varies by GPU)
49 // Valid only for Esched-driven engines
51 ENGINE_INFO_TYPE_RUNLIST,
53 // NV_PFIFO_INTR_MMU_FAULT_ENG_ID_*
54 ENGINE_INFO_TYPE_MMU_FAULT_ID,
57 ENGINE_INFO_TYPE_RC_MASK,
59 // Reset Bit Position. On Ampere, only valid if not _INVALID
60 ENGINE_INFO_TYPE_RESET,
62 // Interrupt Bit Position
63 ENGINE_INFO_TYPE_INTR,
68 // The DEV_TYPE_ENUM for this engine
69 ENGINE_INFO_TYPE_DEV_TYPE_ENUM,
71 // The particular instance of this engine type
72 ENGINE_INFO_TYPE_INSTANCE_ID,
75 // The base address for this engine's NV_RUNLIST. Valid only on Ampere+
76 // Valid only for Esched-driven engines
78 ENGINE_INFO_TYPE_RUNLIST_PRI_BASE,
81 // If this entry is a host-driven engine.
82 // Update _isEngineInfoTypeValidForOnlyHostDriven when adding any new entry.
84 ENGINE_INFO_TYPE_IS_HOST_DRIVEN_ENGINE,
87 // The index into the per-engine NV_RUNLIST registers. Valid only on Ampere+
88 // Valid only for Esched-driven engines
90 ENGINE_INFO_TYPE_RUNLIST_ENGINE_ID,
93 // The base address for this engine's NV_CHRAM registers. Valid only on
96 // Valid only for Esched-driven engines
98 ENGINE_INFO_TYPE_CHRAM_PRI_BASE,
100 // This entry added to copy data at RMCTRL_EXPORT() call for Kernel RM
101 ENGINE_INFO_TYPE_KERNEL_RM_MAX,
102 // Used for iterating the engine info table by the index passed.
103 ENGINE_INFO_TYPE_INVALID = ENGINE_INFO_TYPE_KERNEL_RM_MAX,
105 // Size of FIFO_ENGINE_LIST.engineData
106 ENGINE_INFO_TYPE_ENGINE_DATA_ARRAY_SIZE = ENGINE_INFO_TYPE_INVALID,
108 // Input-only parameter for kfifoEngineInfoXlate.
109 ENGINE_INFO_TYPE_PBDMA_ID
111 /* *************************************************************************
113 * THINK BEFORE CHANGING ENUM ORDER HERE.
114 * VGPU-guest uses this same ordering. Because this enum is not versioned,
115 * changing the order here WILL BREAK old-guest-on-newer-host compatibility.
116 * ************************************************************************/