1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016-2018, 2020-2021 The Linux Foundation. All rights reserved.
4 * Copyright (C) 2013 Red Hat
5 * Author: Rob Clark <robdclark@gmail.com>
8 #include <linux/dma-mapping.h>
9 #include <linux/kthread.h>
10 #include <linux/sched/mm.h>
11 #include <linux/uaccess.h>
12 #include <uapi/linux/sched/types.h>
14 #include <drm/drm_drv.h>
15 #include <drm/drm_file.h>
16 #include <drm/drm_ioctl.h>
17 #include <drm/drm_prime.h>
18 #include <drm/drm_of.h>
19 #include <drm/drm_vblank.h>
21 #include "disp/msm_disp_snapshot.h"
23 #include "msm_debugfs.h"
24 #include "msm_fence.h"
28 #include "adreno/adreno_gpu.h"
32 * - 1.0.0 - initial interface
33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers
34 * - 1.2.0 - adds explicit fence support for submit ioctl
35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW +
36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for
38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get
39 * GEM object's debug name
40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
41 * - 1.6.0 - Syncobj support
42 * - 1.7.0 - Add MSM_PARAM_SUSPENDS to access suspend count
43 * - 1.8.0 - Add MSM_BO_CACHED_COHERENT for supported GPUs (a6xx)
45 #define MSM_VERSION_MAJOR 1
46 #define MSM_VERSION_MINOR 8
47 #define MSM_VERSION_PATCHLEVEL 0
49 static const struct drm_mode_config_funcs mode_config_funcs = {
50 .fb_create = msm_framebuffer_create,
51 .output_poll_changed = drm_fb_helper_output_poll_changed,
52 .atomic_check = drm_atomic_helper_check,
53 .atomic_commit = drm_atomic_helper_commit,
56 static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = {
57 .atomic_commit_tail = msm_atomic_commit_tail,
60 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
62 MODULE_PARM_DESC(reglog, "Enable register read/write logging");
63 module_param(reglog, bool, 0600);
68 #ifdef CONFIG_DRM_FBDEV_EMULATION
69 static bool fbdev = true;
70 MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
71 module_param(fbdev, bool, 0600);
74 static char *vram = "16m";
75 MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)");
76 module_param(vram, charp, 0);
79 MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors");
80 module_param(dumpstate, bool, 0600);
82 static bool modeset = true;
83 MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)");
84 module_param(modeset, bool, 0600);
90 struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count,
96 snprintf(n, sizeof(n), "%s_clk", name);
98 for (i = 0; bulk && i < count; i++) {
99 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n))
107 struct clk *msm_clk_get(struct platform_device *pdev, const char *name)
112 clk = devm_clk_get(&pdev->dev, name);
113 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER)
116 snprintf(name2, sizeof(name2), "%s_clk", name);
118 clk = devm_clk_get(&pdev->dev, name2);
120 dev_warn(&pdev->dev, "Using legacy clk name binding. Use "
121 "\"%s\" instead of \"%s\"\n", name, name2);
126 static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name,
127 const char *dbgname, bool quiet, phys_addr_t *psize)
129 struct resource *res;
134 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
136 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
140 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name);
141 return ERR_PTR(-EINVAL);
144 size = resource_size(res);
146 ptr = devm_ioremap(&pdev->dev, res->start, size);
149 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name);
150 return ERR_PTR(-ENOMEM);
154 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
162 void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
165 return _msm_ioremap(pdev, name, dbgname, false, NULL);
168 void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name,
171 return _msm_ioremap(pdev, name, dbgname, true, NULL);
174 void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name,
175 const char *dbgname, phys_addr_t *psize)
177 return _msm_ioremap(pdev, name, dbgname, false, psize);
180 void msm_writel(u32 data, void __iomem *addr)
183 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
187 u32 msm_readl(const void __iomem *addr)
189 u32 val = readl(addr);
191 pr_err("IO:R %p %08x\n", addr, val);
195 void msm_rmw(void __iomem *addr, u32 mask, u32 or)
197 u32 val = msm_readl(addr);
200 msm_writel(val | or, addr);
203 static enum hrtimer_restart msm_hrtimer_worktimer(struct hrtimer *t)
205 struct msm_hrtimer_work *work = container_of(t,
206 struct msm_hrtimer_work, timer);
208 kthread_queue_work(work->worker, &work->work);
210 return HRTIMER_NORESTART;
213 void msm_hrtimer_queue_work(struct msm_hrtimer_work *work,
215 enum hrtimer_mode mode)
217 hrtimer_start(&work->timer, wakeup_time, mode);
220 void msm_hrtimer_work_init(struct msm_hrtimer_work *work,
221 struct kthread_worker *worker,
222 kthread_work_func_t fn,
224 enum hrtimer_mode mode)
226 hrtimer_init(&work->timer, clock_id, mode);
227 work->timer.function = msm_hrtimer_worktimer;
228 work->worker = worker;
229 kthread_init_work(&work->work, fn);
232 static irqreturn_t msm_irq(int irq, void *arg)
234 struct drm_device *dev = arg;
235 struct msm_drm_private *priv = dev->dev_private;
236 struct msm_kms *kms = priv->kms;
240 return kms->funcs->irq(kms);
243 static void msm_irq_preinstall(struct drm_device *dev)
245 struct msm_drm_private *priv = dev->dev_private;
246 struct msm_kms *kms = priv->kms;
250 kms->funcs->irq_preinstall(kms);
253 static int msm_irq_postinstall(struct drm_device *dev)
255 struct msm_drm_private *priv = dev->dev_private;
256 struct msm_kms *kms = priv->kms;
260 if (kms->funcs->irq_postinstall)
261 return kms->funcs->irq_postinstall(kms);
266 static int msm_irq_install(struct drm_device *dev, unsigned int irq)
270 if (irq == IRQ_NOTCONNECTED)
273 msm_irq_preinstall(dev);
275 ret = request_irq(irq, msm_irq, 0, dev->driver->name, dev);
279 ret = msm_irq_postinstall(dev);
288 static void msm_irq_uninstall(struct drm_device *dev)
290 struct msm_drm_private *priv = dev->dev_private;
291 struct msm_kms *kms = priv->kms;
293 kms->funcs->irq_uninstall(kms);
294 free_irq(kms->irq, dev);
297 struct msm_vblank_work {
298 struct work_struct work;
301 struct msm_drm_private *priv;
304 static void vblank_ctrl_worker(struct work_struct *work)
306 struct msm_vblank_work *vbl_work = container_of(work,
307 struct msm_vblank_work, work);
308 struct msm_drm_private *priv = vbl_work->priv;
309 struct msm_kms *kms = priv->kms;
311 if (vbl_work->enable)
312 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
314 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]);
319 static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
320 int crtc_id, bool enable)
322 struct msm_vblank_work *vbl_work;
324 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC);
328 INIT_WORK(&vbl_work->work, vblank_ctrl_worker);
330 vbl_work->crtc_id = crtc_id;
331 vbl_work->enable = enable;
332 vbl_work->priv = priv;
334 queue_work(priv->wq, &vbl_work->work);
339 static int msm_drm_uninit(struct device *dev)
341 struct platform_device *pdev = to_platform_device(dev);
342 struct msm_drm_private *priv = platform_get_drvdata(pdev);
343 struct drm_device *ddev = priv->dev;
344 struct msm_kms *kms = priv->kms;
348 * Shutdown the hw if we're far enough along where things might be on.
349 * If we run this too early, we'll end up panicking in any variety of
350 * places. Since we don't register the drm device until late in
351 * msm_drm_init, drm_dev->registered is used as an indicator that the
352 * shutdown will be successful.
354 if (ddev->registered) {
355 drm_dev_unregister(ddev);
356 drm_atomic_helper_shutdown(ddev);
359 /* We must cancel and cleanup any pending vblank enable/disable
360 * work before msm_irq_uninstall() to avoid work re-enabling an
361 * irq after uninstall has disabled it.
364 flush_workqueue(priv->wq);
366 /* clean up event worker threads */
367 for (i = 0; i < priv->num_crtcs; i++) {
368 if (priv->event_thread[i].worker)
369 kthread_destroy_worker(priv->event_thread[i].worker);
372 msm_gem_shrinker_cleanup(ddev);
374 drm_kms_helper_poll_fini(ddev);
376 msm_perf_debugfs_cleanup(priv);
377 msm_rd_debugfs_cleanup(priv);
379 #ifdef CONFIG_DRM_FBDEV_EMULATION
380 if (fbdev && priv->fbdev)
381 msm_fbdev_free(ddev);
384 msm_disp_snapshot_destroy(ddev);
386 drm_mode_config_cleanup(ddev);
388 pm_runtime_get_sync(dev);
389 msm_irq_uninstall(ddev);
390 pm_runtime_put_sync(dev);
392 if (kms && kms->funcs)
393 kms->funcs->destroy(kms);
395 if (priv->vram.paddr) {
396 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING;
397 drm_mm_takedown(&priv->vram.mm);
398 dma_free_attrs(dev, priv->vram.size, NULL,
399 priv->vram.paddr, attrs);
402 component_unbind_all(dev, ddev);
404 ddev->dev_private = NULL;
407 destroy_workqueue(priv->wq);
416 static int get_mdp_ver(struct platform_device *pdev)
418 struct device *dev = &pdev->dev;
420 return (int) (unsigned long) of_device_get_match_data(dev);
423 #include <linux/of_address.h>
425 bool msm_use_mmu(struct drm_device *dev)
427 struct msm_drm_private *priv = dev->dev_private;
429 /* a2xx comes with its own MMU */
430 return priv->is_a2xx || iommu_present(&platform_bus_type);
433 static int msm_init_vram(struct drm_device *dev)
435 struct msm_drm_private *priv = dev->dev_private;
436 struct device_node *node;
437 unsigned long size = 0;
440 /* In the device-tree world, we could have a 'memory-region'
441 * phandle, which gives us a link to our "vram". Allocating
442 * is all nicely abstracted behind the dma api, but we need
443 * to know the entire size to allocate it all in one go. There
445 * 1) device with no IOMMU, in which case we need exclusive
446 * access to a VRAM carveout big enough for all gpu
448 * 2) device with IOMMU, but where the bootloader puts up
449 * a splash screen. In this case, the VRAM carveout
450 * need only be large enough for fbdev fb. But we need
451 * exclusive access to the buffer to avoid the kernel
452 * using those pages for other purposes (which appears
453 * as corruption on screen before we have a chance to
454 * load and do initial modeset)
457 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
460 ret = of_address_to_resource(node, 0, &r);
464 size = r.end - r.start + 1;
465 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
467 /* if we have no IOMMU, then we need to use carveout allocator.
468 * Grab the entire CMA chunk carved out in early startup in
471 } else if (!msm_use_mmu(dev)) {
472 DRM_INFO("using %s VRAM carveout\n", vram);
473 size = memparse(vram, NULL);
477 unsigned long attrs = 0;
480 priv->vram.size = size;
482 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
483 spin_lock_init(&priv->vram.lock);
485 attrs |= DMA_ATTR_NO_KERNEL_MAPPING;
486 attrs |= DMA_ATTR_WRITE_COMBINE;
488 /* note that for no-kernel-mapping, the vaddr returned
489 * is bogus, but non-null if allocation succeeded:
491 p = dma_alloc_attrs(dev->dev, size,
492 &priv->vram.paddr, GFP_KERNEL, attrs);
494 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n");
495 priv->vram.paddr = 0;
499 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n",
500 (uint32_t)priv->vram.paddr,
501 (uint32_t)(priv->vram.paddr + size));
507 static int msm_drm_init(struct device *dev, const struct drm_driver *drv)
509 struct platform_device *pdev = to_platform_device(dev);
510 struct msm_drm_private *priv = dev_get_drvdata(dev);
511 struct drm_device *ddev;
515 ddev = drm_dev_alloc(drv, dev);
517 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n");
518 return PTR_ERR(ddev);
520 ddev->dev_private = priv;
523 priv->wq = alloc_ordered_workqueue("msm", 0);
524 priv->hangcheck_period = DRM_MSM_HANGCHECK_DEFAULT_PERIOD;
526 INIT_LIST_HEAD(&priv->objects);
527 mutex_init(&priv->obj_lock);
529 INIT_LIST_HEAD(&priv->inactive_willneed);
530 INIT_LIST_HEAD(&priv->inactive_dontneed);
531 INIT_LIST_HEAD(&priv->inactive_unpinned);
532 mutex_init(&priv->mm_lock);
534 /* Teach lockdep about lock ordering wrt. shrinker: */
535 fs_reclaim_acquire(GFP_KERNEL);
536 might_lock(&priv->mm_lock);
537 fs_reclaim_release(GFP_KERNEL);
539 drm_mode_config_init(ddev);
541 ret = msm_init_vram(ddev);
545 /* Bind all our sub-components: */
546 ret = component_bind_all(dev, ddev);
550 dma_set_max_seg_size(dev, UINT_MAX);
552 msm_gem_shrinker_init(ddev);
554 switch (get_mdp_ver(pdev)) {
556 kms = mdp4_kms_init(ddev);
560 kms = mdp5_kms_init(ddev);
563 kms = dpu_kms_init(ddev);
567 /* valid only for the dummy headless case, where of_node=NULL */
568 WARN_ON(dev->of_node);
574 DRM_DEV_ERROR(dev, "failed to load kms\n");
580 /* Enable normalization of plane zpos */
581 ddev->mode_config.normalize_zpos = true;
585 ret = kms->funcs->hw_init(kms);
587 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret);
592 ddev->mode_config.funcs = &mode_config_funcs;
593 ddev->mode_config.helper_private = &mode_config_helper_funcs;
595 for (i = 0; i < priv->num_crtcs; i++) {
596 /* initialize event thread */
597 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id;
598 priv->event_thread[i].dev = ddev;
599 priv->event_thread[i].worker = kthread_create_worker(0,
600 "crtc_event:%d", priv->event_thread[i].crtc_id);
601 if (IS_ERR(priv->event_thread[i].worker)) {
602 ret = PTR_ERR(priv->event_thread[i].worker);
603 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n");
604 ret = PTR_ERR(priv->event_thread[i].worker);
608 sched_set_fifo(priv->event_thread[i].worker->task);
611 ret = drm_vblank_init(ddev, priv->num_crtcs);
613 DRM_DEV_ERROR(dev, "failed to initialize vblank\n");
618 pm_runtime_get_sync(dev);
619 ret = msm_irq_install(ddev, kms->irq);
620 pm_runtime_put_sync(dev);
622 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n");
627 ret = drm_dev_register(ddev, 0);
632 ret = msm_disp_snapshot_init(ddev);
634 DRM_DEV_ERROR(dev, "msm_disp_snapshot_init failed ret = %d\n", ret);
636 drm_mode_config_reset(ddev);
638 #ifdef CONFIG_DRM_FBDEV_EMULATION
640 priv->fbdev = msm_fbdev_init(ddev);
643 ret = msm_debugfs_late_init(ddev);
647 drm_kms_helper_poll_init(ddev);
660 static void load_gpu(struct drm_device *dev)
662 static DEFINE_MUTEX(init_lock);
663 struct msm_drm_private *priv = dev->dev_private;
665 mutex_lock(&init_lock);
668 priv->gpu = adreno_load_gpu(dev);
670 mutex_unlock(&init_lock);
673 static int context_init(struct drm_device *dev, struct drm_file *file)
675 static atomic_t ident = ATOMIC_INIT(0);
676 struct msm_drm_private *priv = dev->dev_private;
677 struct msm_file_private *ctx;
679 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
683 INIT_LIST_HEAD(&ctx->submitqueues);
684 rwlock_init(&ctx->queuelock);
686 kref_init(&ctx->ref);
687 msm_submitqueue_init(dev, ctx);
689 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current);
690 file->driver_priv = ctx;
692 ctx->seqno = atomic_inc_return(&ident);
697 static int msm_open(struct drm_device *dev, struct drm_file *file)
699 /* For now, load gpu on open.. to avoid the requirement of having
700 * firmware in the initrd.
704 return context_init(dev, file);
707 static void context_close(struct msm_file_private *ctx)
709 msm_submitqueue_close(ctx);
710 msm_file_private_put(ctx);
713 static void msm_postclose(struct drm_device *dev, struct drm_file *file)
715 struct msm_file_private *ctx = file->driver_priv;
720 int msm_crtc_enable_vblank(struct drm_crtc *crtc)
722 struct drm_device *dev = crtc->dev;
723 unsigned int pipe = crtc->index;
724 struct msm_drm_private *priv = dev->dev_private;
725 struct msm_kms *kms = priv->kms;
728 drm_dbg_vbl(dev, "crtc=%u", pipe);
729 return vblank_ctrl_queue_work(priv, pipe, true);
732 void msm_crtc_disable_vblank(struct drm_crtc *crtc)
734 struct drm_device *dev = crtc->dev;
735 unsigned int pipe = crtc->index;
736 struct msm_drm_private *priv = dev->dev_private;
737 struct msm_kms *kms = priv->kms;
740 drm_dbg_vbl(dev, "crtc=%u", pipe);
741 vblank_ctrl_queue_work(priv, pipe, false);
748 static int msm_ioctl_get_param(struct drm_device *dev, void *data,
749 struct drm_file *file)
751 struct msm_drm_private *priv = dev->dev_private;
752 struct drm_msm_param *args = data;
755 /* for now, we just have 3d pipe.. eventually this would need to
756 * be more clever to dispatch to appropriate gpu module:
758 if (args->pipe != MSM_PIPE_3D0)
766 return gpu->funcs->get_param(gpu, args->param, &args->value);
769 static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
770 struct drm_file *file)
772 struct drm_msm_gem_new *args = data;
774 if (args->flags & ~MSM_BO_FLAGS) {
775 DRM_ERROR("invalid flags: %08x\n", args->flags);
779 return msm_gem_new_handle(dev, file, args->size,
780 args->flags, &args->handle, NULL);
783 static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
785 return ktime_set(timeout.tv_sec, timeout.tv_nsec);
788 static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
789 struct drm_file *file)
791 struct drm_msm_gem_cpu_prep *args = data;
792 struct drm_gem_object *obj;
793 ktime_t timeout = to_ktime(args->timeout);
796 if (args->op & ~MSM_PREP_FLAGS) {
797 DRM_ERROR("invalid op: %08x\n", args->op);
801 obj = drm_gem_object_lookup(file, args->handle);
805 ret = msm_gem_cpu_prep(obj, args->op, &timeout);
807 drm_gem_object_put(obj);
812 static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
813 struct drm_file *file)
815 struct drm_msm_gem_cpu_fini *args = data;
816 struct drm_gem_object *obj;
819 obj = drm_gem_object_lookup(file, args->handle);
823 ret = msm_gem_cpu_fini(obj);
825 drm_gem_object_put(obj);
830 static int msm_ioctl_gem_info_iova(struct drm_device *dev,
831 struct drm_file *file, struct drm_gem_object *obj,
834 struct msm_drm_private *priv = dev->dev_private;
835 struct msm_file_private *ctx = file->driver_priv;
841 * Don't pin the memory here - just get an address so that userspace can
844 return msm_gem_get_iova(obj, ctx->aspace, iova);
847 static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
848 struct drm_file *file)
850 struct drm_msm_gem_info *args = data;
851 struct drm_gem_object *obj;
852 struct msm_gem_object *msm_obj;
858 switch (args->info) {
859 case MSM_INFO_GET_OFFSET:
860 case MSM_INFO_GET_IOVA:
861 /* value returned as immediate, not pointer, so len==0: */
865 case MSM_INFO_SET_NAME:
866 case MSM_INFO_GET_NAME:
872 obj = drm_gem_object_lookup(file, args->handle);
876 msm_obj = to_msm_bo(obj);
878 switch (args->info) {
879 case MSM_INFO_GET_OFFSET:
880 args->value = msm_gem_mmap_offset(obj);
882 case MSM_INFO_GET_IOVA:
883 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value);
885 case MSM_INFO_SET_NAME:
886 /* length check should leave room for terminating null: */
887 if (args->len >= sizeof(msm_obj->name)) {
891 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value),
893 msm_obj->name[0] = '\0';
897 msm_obj->name[args->len] = '\0';
898 for (i = 0; i < args->len; i++) {
899 if (!isprint(msm_obj->name[i])) {
900 msm_obj->name[i] = '\0';
905 case MSM_INFO_GET_NAME:
906 if (args->value && (args->len < strlen(msm_obj->name))) {
910 args->len = strlen(msm_obj->name);
912 if (copy_to_user(u64_to_user_ptr(args->value),
913 msm_obj->name, args->len))
919 drm_gem_object_put(obj);
924 static int wait_fence(struct msm_gpu_submitqueue *queue, uint32_t fence_id,
927 struct dma_fence *fence;
930 if (fence_after(fence_id, queue->last_fence)) {
931 DRM_ERROR_RATELIMITED("waiting on invalid fence: %u (of %u)\n",
932 fence_id, queue->last_fence);
937 * Map submitqueue scoped "seqno" (which is actually an idr key)
938 * back to underlying dma-fence
940 * The fence is removed from the fence_idr when the submit is
941 * retired, so if the fence is not found it means there is nothing
944 ret = mutex_lock_interruptible(&queue->lock);
947 fence = idr_find(&queue->fence_idr, fence_id);
949 fence = dma_fence_get_rcu(fence);
950 mutex_unlock(&queue->lock);
955 ret = dma_fence_wait_timeout(fence, true, timeout_to_jiffies(&timeout));
958 } else if (ret != -ERESTARTSYS) {
962 dma_fence_put(fence);
967 static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
968 struct drm_file *file)
970 struct msm_drm_private *priv = dev->dev_private;
971 struct drm_msm_wait_fence *args = data;
972 struct msm_gpu_submitqueue *queue;
976 DRM_ERROR("invalid pad: %08x\n", args->pad);
983 queue = msm_submitqueue_get(file->driver_priv, args->queueid);
987 ret = wait_fence(queue, args->fence, to_ktime(args->timeout));
989 msm_submitqueue_put(queue);
994 static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data,
995 struct drm_file *file)
997 struct drm_msm_gem_madvise *args = data;
998 struct drm_gem_object *obj;
1001 switch (args->madv) {
1002 case MSM_MADV_DONTNEED:
1003 case MSM_MADV_WILLNEED:
1009 obj = drm_gem_object_lookup(file, args->handle);
1014 ret = msm_gem_madvise(obj, args->madv);
1016 args->retained = ret;
1020 drm_gem_object_put(obj);
1026 static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data,
1027 struct drm_file *file)
1029 struct drm_msm_submitqueue *args = data;
1031 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS)
1034 return msm_submitqueue_create(dev, file->driver_priv, args->prio,
1035 args->flags, &args->id);
1038 static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data,
1039 struct drm_file *file)
1041 return msm_submitqueue_query(dev, file->driver_priv, data);
1044 static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data,
1045 struct drm_file *file)
1047 u32 id = *(u32 *) data;
1049 return msm_submitqueue_remove(file->driver_priv, id);
1052 static const struct drm_ioctl_desc msm_ioctls[] = {
1053 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW),
1054 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW),
1055 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW),
1056 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW),
1057 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW),
1058 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW),
1059 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW),
1060 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW),
1061 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW),
1062 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW),
1063 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW),
1066 DEFINE_DRM_GEM_FOPS(fops);
1068 static const struct drm_driver msm_driver = {
1069 .driver_features = DRIVER_GEM |
1075 .postclose = msm_postclose,
1076 .lastclose = drm_fb_helper_lastclose,
1077 .dumb_create = msm_gem_dumb_create,
1078 .dumb_map_offset = msm_gem_dumb_map_offset,
1079 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1080 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1081 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
1082 .gem_prime_mmap = drm_gem_prime_mmap,
1083 #ifdef CONFIG_DEBUG_FS
1084 .debugfs_init = msm_debugfs_init,
1086 .ioctls = msm_ioctls,
1087 .num_ioctls = ARRAY_SIZE(msm_ioctls),
1090 .desc = "MSM Snapdragon DRM",
1092 .major = MSM_VERSION_MAJOR,
1093 .minor = MSM_VERSION_MINOR,
1094 .patchlevel = MSM_VERSION_PATCHLEVEL,
1097 static int __maybe_unused msm_runtime_suspend(struct device *dev)
1099 struct msm_drm_private *priv = dev_get_drvdata(dev);
1100 struct msm_mdss *mdss = priv->mdss;
1104 if (mdss && mdss->funcs)
1105 return mdss->funcs->disable(mdss);
1110 static int __maybe_unused msm_runtime_resume(struct device *dev)
1112 struct msm_drm_private *priv = dev_get_drvdata(dev);
1113 struct msm_mdss *mdss = priv->mdss;
1117 if (mdss && mdss->funcs)
1118 return mdss->funcs->enable(mdss);
1123 static int __maybe_unused msm_pm_suspend(struct device *dev)
1126 if (pm_runtime_suspended(dev))
1129 return msm_runtime_suspend(dev);
1132 static int __maybe_unused msm_pm_resume(struct device *dev)
1134 if (pm_runtime_suspended(dev))
1137 return msm_runtime_resume(dev);
1140 static int __maybe_unused msm_pm_prepare(struct device *dev)
1142 struct msm_drm_private *priv = dev_get_drvdata(dev);
1143 struct drm_device *ddev = priv ? priv->dev : NULL;
1145 if (!priv || !priv->kms)
1148 return drm_mode_config_helper_suspend(ddev);
1151 static void __maybe_unused msm_pm_complete(struct device *dev)
1153 struct msm_drm_private *priv = dev_get_drvdata(dev);
1154 struct drm_device *ddev = priv ? priv->dev : NULL;
1156 if (!priv || !priv->kms)
1159 drm_mode_config_helper_resume(ddev);
1162 static const struct dev_pm_ops msm_pm_ops = {
1163 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
1164 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL)
1165 .prepare = msm_pm_prepare,
1166 .complete = msm_pm_complete,
1170 * Componentized driver support:
1174 * NOTE: duplication of the same code as exynos or imx (or probably any other).
1175 * so probably some room for some helpers
1177 static int compare_of(struct device *dev, void *data)
1179 return dev->of_node == data;
1183 * Identify what components need to be added by parsing what remote-endpoints
1184 * our MDP output ports are connected to. In the case of LVDS on MDP4, there
1185 * is no external component that we need to add since LVDS is within MDP4
1188 static int add_components_mdp(struct device *mdp_dev,
1189 struct component_match **matchptr)
1191 struct device_node *np = mdp_dev->of_node;
1192 struct device_node *ep_node;
1193 struct device *master_dev;
1196 * on MDP4 based platforms, the MDP platform device is the component
1197 * master that adds other display interface components to itself.
1199 * on MDP5 based platforms, the MDSS platform device is the component
1200 * master that adds MDP5 and other display interface components to
1203 if (of_device_is_compatible(np, "qcom,mdp4"))
1204 master_dev = mdp_dev;
1206 master_dev = mdp_dev->parent;
1208 for_each_endpoint_of_node(np, ep_node) {
1209 struct device_node *intf;
1210 struct of_endpoint ep;
1213 ret = of_graph_parse_endpoint(ep_node, &ep);
1215 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n");
1216 of_node_put(ep_node);
1221 * The LCDC/LVDS port on MDP4 is a speacial case where the
1222 * remote-endpoint isn't a component that we need to add
1224 if (of_device_is_compatible(np, "qcom,mdp4") &&
1229 * It's okay if some of the ports don't have a remote endpoint
1230 * specified. It just means that the port isn't connected to
1231 * any external interface.
1233 intf = of_graph_get_remote_port_parent(ep_node);
1237 if (of_device_is_available(intf))
1238 drm_of_component_match_add(master_dev, matchptr,
1247 static int find_mdp_node(struct device *dev, void *data)
1249 return of_match_node(dpu_dt_match, dev->of_node) ||
1250 of_match_node(mdp5_dt_match, dev->of_node);
1253 static int add_display_components(struct platform_device *pdev,
1254 struct component_match **matchptr)
1256 struct device *mdp_dev;
1257 struct device *dev = &pdev->dev;
1261 * MDP5/DPU based devices don't have a flat hierarchy. There is a top
1262 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc.
1263 * Populate the children devices, find the MDP5/DPU node, and then add
1264 * the interfaces to our components list.
1266 switch (get_mdp_ver(pdev)) {
1269 ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
1271 DRM_DEV_ERROR(dev, "failed to populate children devices\n");
1275 mdp_dev = device_find_child(dev, NULL, find_mdp_node);
1277 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n");
1278 of_platform_depopulate(dev);
1282 put_device(mdp_dev);
1284 /* add the MDP component itself */
1285 drm_of_component_match_add(dev, matchptr, compare_of,
1294 ret = add_components_mdp(mdp_dev, matchptr);
1296 of_platform_depopulate(dev);
1302 * We don't know what's the best binding to link the gpu with the drm device.
1303 * Fow now, we just hunt for all the possible gpus that we support, and add them
1306 static const struct of_device_id msm_gpu_match[] = {
1307 { .compatible = "qcom,adreno" },
1308 { .compatible = "qcom,adreno-3xx" },
1309 { .compatible = "amd,imageon" },
1310 { .compatible = "qcom,kgsl-3d0" },
1314 static int add_gpu_components(struct device *dev,
1315 struct component_match **matchptr)
1317 struct device_node *np;
1319 np = of_find_matching_node(NULL, msm_gpu_match);
1323 if (of_device_is_available(np))
1324 drm_of_component_match_add(dev, matchptr, compare_of, np);
1331 static int msm_drm_bind(struct device *dev)
1333 return msm_drm_init(dev, &msm_driver);
1336 static void msm_drm_unbind(struct device *dev)
1338 msm_drm_uninit(dev);
1341 static const struct component_master_ops msm_drm_ops = {
1342 .bind = msm_drm_bind,
1343 .unbind = msm_drm_unbind,
1350 static int msm_pdev_probe(struct platform_device *pdev)
1352 struct component_match *match = NULL;
1353 struct msm_drm_private *priv;
1356 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1360 platform_set_drvdata(pdev, priv);
1362 switch (get_mdp_ver(pdev)) {
1364 ret = mdp5_mdss_init(pdev);
1367 ret = dpu_mdss_init(pdev);
1374 platform_set_drvdata(pdev, NULL);
1378 if (get_mdp_ver(pdev)) {
1379 ret = add_display_components(pdev, &match);
1384 ret = add_gpu_components(&pdev->dev, &match);
1388 /* on all devices that I am aware of, iommu's which can map
1389 * any address the cpu can see are used:
1391 ret = dma_set_mask_and_coherent(&pdev->dev, ~0);
1395 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
1402 of_platform_depopulate(&pdev->dev);
1404 if (priv->mdss && priv->mdss->funcs)
1405 priv->mdss->funcs->destroy(priv->mdss);
1410 static int msm_pdev_remove(struct platform_device *pdev)
1412 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1413 struct msm_mdss *mdss = priv->mdss;
1415 component_master_del(&pdev->dev, &msm_drm_ops);
1416 of_platform_depopulate(&pdev->dev);
1418 if (mdss && mdss->funcs)
1419 mdss->funcs->destroy(mdss);
1424 static void msm_pdev_shutdown(struct platform_device *pdev)
1426 struct msm_drm_private *priv = platform_get_drvdata(pdev);
1427 struct drm_device *drm = priv ? priv->dev : NULL;
1429 if (!priv || !priv->kms)
1432 drm_atomic_helper_shutdown(drm);
1435 static const struct of_device_id dt_match[] = {
1436 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 },
1437 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
1438 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
1439 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
1440 { .compatible = "qcom,sc7280-mdss", .data = (void *)KMS_DPU },
1441 { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
1442 { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
1445 MODULE_DEVICE_TABLE(of, dt_match);
1447 static struct platform_driver msm_platform_driver = {
1448 .probe = msm_pdev_probe,
1449 .remove = msm_pdev_remove,
1450 .shutdown = msm_pdev_shutdown,
1453 .of_match_table = dt_match,
1458 static int __init msm_drm_register(void)
1467 msm_hdmi_register();
1470 return platform_driver_register(&msm_platform_driver);
1473 static void __exit msm_drm_unregister(void)
1476 platform_driver_unregister(&msm_platform_driver);
1477 msm_dp_unregister();
1478 msm_hdmi_unregister();
1479 adreno_unregister();
1480 msm_dsi_unregister();
1481 msm_mdp_unregister();
1482 msm_dpu_unregister();
1485 module_init(msm_drm_register);
1486 module_exit(msm_drm_unregister);
1488 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1489 MODULE_DESCRIPTION("MSM DRM Driver");
1490 MODULE_LICENSE("GPL");