drivers/gpu/drm/msm/mdp/mdp5/mdp5_plane.c

   1 /*
   2  * Copyright (C) 2014-2015 The Linux Foundation. All rights reserved.
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <robdclark@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published by
   8  * the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <drm/drm_print.h>
  20 #include "mdp5_kms.h"
  21
  22 struct mdp5_plane {
  23         struct drm_plane base;
  24
  25         uint32_t nformats;
  26         uint32_t formats[32];
  27 };
  28 #define to_mdp5_plane(x) container_of(x, struct mdp5_plane, base)
  29
  30 static int mdp5_plane_mode_set(struct drm_plane *plane,
  31                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
  32                 int crtc_x, int crtc_y,
  33                 unsigned int crtc_w, unsigned int crtc_h,
  34                 uint32_t src_x, uint32_t src_y,
  35                 uint32_t src_w, uint32_t src_h);
  36
  37 static void set_scanout_locked(struct drm_plane *plane,
  38                 struct drm_framebuffer *fb);
  39
  40 static struct mdp5_kms *get_kms(struct drm_plane *plane)
  41 {
  42         struct msm_drm_private *priv = plane->dev->dev_private;
  43         return to_mdp5_kms(to_mdp_kms(priv->kms));
  44 }
  45
  46 static bool plane_enabled(struct drm_plane_state *state)
  47 {
  48         return state->fb && state->crtc;
  49 }
  50
  51 static void mdp5_plane_destroy(struct drm_plane *plane)
  52 {
  53         struct mdp5_plane *mdp5_plane = to_mdp5_plane(plane);
  54
  55         drm_plane_helper_disable(plane);
  56         drm_plane_cleanup(plane);
  57
  58         kfree(mdp5_plane);
  59 }
  60
  61 static void mdp5_plane_install_rotation_property(struct drm_device *dev,
  62                 struct drm_plane *plane)
  63 {
  64         drm_plane_create_rotation_property(plane,
  65                                            DRM_ROTATE_0,
  66                                            DRM_ROTATE_0 |
  67                                            DRM_ROTATE_180 |
  68                                            DRM_REFLECT_X |
  69                                            DRM_REFLECT_Y);
  70 }
  71
  72 /* helper to install properties which are common to planes and crtcs */
  73 static void mdp5_plane_install_properties(struct drm_plane *plane,
  74                 struct drm_mode_object *obj)
  75 {
  76         struct drm_device *dev = plane->dev;
  77         struct msm_drm_private *dev_priv = dev->dev_private;
  78         struct drm_property *prop;
  79
  80 #define INSTALL_PROPERTY(name, NAME, init_val, fnc, ...) do { \
  81                 prop = dev_priv->plane_property[PLANE_PROP_##NAME]; \
  82                 if (!prop) { \
  83                         prop = drm_property_##fnc(dev, 0, #name, \
  84                                 ##__VA_ARGS__); \
  85                         if (!prop) { \
  86                                 dev_warn(dev->dev, \
  87                                         "Create property %s failed\n", \
  88                                         #name); \
  89                                 return; \
  90                         } \
  91                         dev_priv->plane_property[PLANE_PROP_##NAME] = prop; \
  92                 } \
  93                 drm_object_attach_property(&plane->base, prop, init_val); \
  94         } while (0)
  95
  96 #define INSTALL_RANGE_PROPERTY(name, NAME, min, max, init_val) \
  97                 INSTALL_PROPERTY(name, NAME, init_val, \
  98                                 create_range, min, max)
  99
 100 #define INSTALL_ENUM_PROPERTY(name, NAME, init_val) \
 101                 INSTALL_PROPERTY(name, NAME, init_val, \
 102                                 create_enum, name##_prop_enum_list, \
 103                                 ARRAY_SIZE(name##_prop_enum_list))
 104
 105         INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
 106
 107         mdp5_plane_install_rotation_property(dev, plane);
 108
 109 #undef INSTALL_RANGE_PROPERTY
 110 #undef INSTALL_ENUM_PROPERTY
 111 #undef INSTALL_PROPERTY
 112 }
 113
 114 static int mdp5_plane_atomic_set_property(struct drm_plane *plane,
 115                 struct drm_plane_state *state, struct drm_property *property,
 116                 uint64_t val)
 117 {
 118         struct drm_device *dev = plane->dev;
 119         struct mdp5_plane_state *pstate;
 120         struct msm_drm_private *dev_priv = dev->dev_private;
 121         int ret = 0;
 122
 123         pstate = to_mdp5_plane_state(state);
 124
 125 #define SET_PROPERTY(name, NAME, type) do { \
 126                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 127                         pstate->name = (type)val; \
 128                         DBG("Set property %s %d", #name, (type)val); \
 129                         goto done; \
 130                 } \
 131         } while (0)
 132
 133         SET_PROPERTY(zpos, ZPOS, uint8_t);
 134
 135         dev_err(dev->dev, "Invalid property\n");
 136         ret = -EINVAL;
 137 done:
 138         return ret;
 139 #undef SET_PROPERTY
 140 }
 141
 142 static int mdp5_plane_atomic_get_property(struct drm_plane *plane,
 143                 const struct drm_plane_state *state,
 144                 struct drm_property *property, uint64_t *val)
 145 {
 146         struct drm_device *dev = plane->dev;
 147         struct mdp5_plane_state *pstate;
 148         struct msm_drm_private *dev_priv = dev->dev_private;
 149         int ret = 0;
 150
 151         pstate = to_mdp5_plane_state(state);
 152
 153 #define GET_PROPERTY(name, NAME, type) do { \
 154                 if (dev_priv->plane_property[PLANE_PROP_##NAME] == property) { \
 155                         *val = pstate->name; \
 156                         DBG("Get property %s %lld", #name, *val); \
 157                         goto done; \
 158                 } \
 159         } while (0)
 160
 161         GET_PROPERTY(zpos, ZPOS, uint8_t);
 162
 163         dev_err(dev->dev, "Invalid property\n");
 164         ret = -EINVAL;
 165 done:
 166         return ret;
 167 #undef SET_PROPERTY
 168 }
 169
 170 static void
 171 mdp5_plane_atomic_print_state(struct drm_printer *p,
 172                 const struct drm_plane_state *state)
 173 {
 174         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 175
 176         drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
 177                         pstate->hwpipe->name : "(null)");
 178         drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
 179         drm_printf(p, "\tzpos=%u\n", pstate->zpos);
 180         drm_printf(p, "\talpha=%u\n", pstate->alpha);
 181         drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
 182         drm_printf(p, "\tpending=%u\n", pstate->pending);
 183 }
 184
 185 static void mdp5_plane_reset(struct drm_plane *plane)
 186 {
 187         struct mdp5_plane_state *mdp5_state;
 188
 189         if (plane->state && plane->state->fb)
 190                 drm_framebuffer_unreference(plane->state->fb);
 191
 192         kfree(to_mdp5_plane_state(plane->state));
 193         mdp5_state = kzalloc(sizeof(*mdp5_state), GFP_KERNEL);
 194
 195         /* assign default blend parameters */
 196         mdp5_state->alpha = 255;
 197         mdp5_state->premultiplied = 0;
 198
 199         if (plane->type == DRM_PLANE_TYPE_PRIMARY)
 200                 mdp5_state->zpos = STAGE_BASE;
 201         else
 202                 mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
 203
 204         mdp5_state->base.plane = plane;
 205
 206         plane->state = &mdp5_state->base;
 207 }
 208
 209 static struct drm_plane_state *
 210 mdp5_plane_duplicate_state(struct drm_plane *plane)
 211 {
 212         struct mdp5_plane_state *mdp5_state;
 213
 214         if (WARN_ON(!plane->state))
 215                 return NULL;
 216
 217         mdp5_state = kmemdup(to_mdp5_plane_state(plane->state),
 218                         sizeof(*mdp5_state), GFP_KERNEL);
 219
 220         if (mdp5_state && mdp5_state->base.fb)
 221                 drm_framebuffer_reference(mdp5_state->base.fb);
 222
 223         mdp5_state->pending = false;
 224
 225         return &mdp5_state->base;
 226 }
 227
 228 static void mdp5_plane_destroy_state(struct drm_plane *plane,
 229                 struct drm_plane_state *state)
 230 {
 231         struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
 232
 233         if (state->fb)
 234                 drm_framebuffer_unreference(state->fb);
 235
 236         kfree(pstate);
 237 }
 238
 239 static const struct drm_plane_funcs mdp5_plane_funcs = {
 240                 .update_plane = drm_atomic_helper_update_plane,
 241                 .disable_plane = drm_atomic_helper_disable_plane,
 242                 .destroy = mdp5_plane_destroy,
 243                 .set_property = drm_atomic_helper_plane_set_property,
 244                 .atomic_set_property = mdp5_plane_atomic_set_property,
 245                 .atomic_get_property = mdp5_plane_atomic_get_property,
 246                 .reset = mdp5_plane_reset,
 247                 .atomic_duplicate_state = mdp5_plane_duplicate_state,
 248                 .atomic_destroy_state = mdp5_plane_destroy_state,
 249                 .atomic_print_state = mdp5_plane_atomic_print_state,
 250 };
 251
 252 static int mdp5_plane_prepare_fb(struct drm_plane *plane,
 253                                  struct drm_plane_state *new_state)
 254 {
 255         struct mdp5_kms *mdp5_kms = get_kms(plane);
 256         struct drm_framebuffer *fb = new_state->fb;
 257
 258         if (!new_state->fb)
 259                 return 0;
 260
 261         DBG("%s: prepare: FB[%u]", plane->name, fb->base.id);
 262         return msm_framebuffer_prepare(fb, mdp5_kms->id);
 263 }
 264
 265 static void mdp5_plane_cleanup_fb(struct drm_plane *plane,
 266                                   struct drm_plane_state *old_state)
 267 {
 268         struct mdp5_kms *mdp5_kms = get_kms(plane);
 269         struct drm_framebuffer *fb = old_state->fb;
 270
 271         if (!fb)
 272                 return;
 273
 274         DBG("%s: cleanup: FB[%u]", plane->name, fb->base.id);
 275         msm_framebuffer_cleanup(fb, mdp5_kms->id);
 276 }
 277
 278 static int mdp5_plane_atomic_check(struct drm_plane *plane,
 279                 struct drm_plane_state *state)
 280 {
 281         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 282         struct drm_plane_state *old_state = plane->state;
 283         bool new_hwpipe = false;
 284         uint32_t caps = 0;
 285
 286         DBG("%s: check (%d -> %d)", plane->name,
 287                         plane_enabled(old_state), plane_enabled(state));
 288
 289         /* We don't allow faster-than-vblank updates.. if we did add this
 290          * some day, we would need to disallow in cases where hwpipe
 291          * changes
 292          */
 293         if (WARN_ON(to_mdp5_plane_state(old_state)->pending))
 294                 return -EBUSY;
 295
 296         if (plane_enabled(state)) {
 297                 unsigned int rotation;
 298                 const struct mdp_format *format;
 299
 300                 format = to_mdp_format(msm_framebuffer_format(state->fb));
 301                 if (MDP_FORMAT_IS_YUV(format))
 302                         caps |= MDP_PIPE_CAP_SCALE | MDP_PIPE_CAP_CSC;
 303
 304                 if (((state->src_w >> 16) != state->crtc_w) ||
 305                                 ((state->src_h >> 16) != state->crtc_h))
 306                         caps |= MDP_PIPE_CAP_SCALE;
 307
 308                 rotation = drm_rotation_simplify(state->rotation,
 309                                                  DRM_ROTATE_0 |
 310                                                  DRM_REFLECT_X |
 311                                                  DRM_REFLECT_Y);
 312
 313                 if (rotation & DRM_REFLECT_X)
 314                         caps |= MDP_PIPE_CAP_HFLIP;
 315
 316                 if (rotation & DRM_REFLECT_Y)
 317                         caps |= MDP_PIPE_CAP_VFLIP;
 318
 319                 /* (re)allocate hw pipe if we don't have one or caps-mismatch: */
 320                 if (!mdp5_state->hwpipe || (caps & ~mdp5_state->hwpipe->caps))
 321                         new_hwpipe = true;
 322
 323                 if (plane_enabled(old_state)) {
 324                         bool full_modeset = false;
 325                         if (state->fb->pixel_format != old_state->fb->pixel_format) {
 326                                 DBG("%s: pixel_format change!", plane->name);
 327                                 full_modeset = true;
 328                         }
 329                         if (state->src_w != old_state->src_w) {
 330                                 DBG("%s: src_w change!", plane->name);
 331                                 full_modeset = true;
 332                         }
 333                         if (full_modeset) {
 334                                 /* cannot change SMP block allocation during
 335                                  * scanout:
 336                                  */
 337                                 if (get_kms(plane)->smp)
 338                                         new_hwpipe = true;
 339                         }
 340                 }
 341
 342                 /* (re)assign hwpipe if needed, otherwise keep old one: */
 343                 if (new_hwpipe) {
 344                         /* TODO maybe we want to re-assign hwpipe sometimes
 345                          * in cases when we no-longer need some caps to make
 346                          * it available for other planes?
 347                          */
 348                         struct mdp5_hw_pipe *old_hwpipe = mdp5_state->hwpipe;
 349                         mdp5_state->hwpipe =
 350                                 mdp5_pipe_assign(state->state, plane, caps);
 351                         if (IS_ERR(mdp5_state->hwpipe)) {
 352                                 DBG("%s: failed to assign hwpipe!", plane->name);
 353                                 return PTR_ERR(mdp5_state->hwpipe);
 354                         }
 355                         mdp5_pipe_release(state->state, old_hwpipe);
 356                 }
 357         }
 358
 359         return 0;
 360 }
 361
 362 static void mdp5_plane_atomic_update(struct drm_plane *plane,
 363                                      struct drm_plane_state *old_state)
 364 {
 365         struct drm_plane_state *state = plane->state;
 366         struct mdp5_plane_state *mdp5_state = to_mdp5_plane_state(state);
 367
 368         DBG("%s: update", plane->name);
 369
 370         mdp5_state->pending = true;
 371
 372         if (plane_enabled(state)) {
 373                 int ret;
 374
 375                 ret = mdp5_plane_mode_set(plane,
 376                                 state->crtc, state->fb,
 377                                 state->crtc_x, state->crtc_y,
 378                                 state->crtc_w, state->crtc_h,
 379                                 state->src_x,  state->src_y,
 380                                 state->src_w, state->src_h);
 381                 /* atomic_check should have ensured that this doesn't fail */
 382                 WARN_ON(ret < 0);
 383         }
 384 }
 385
 386 static const struct drm_plane_helper_funcs mdp5_plane_helper_funcs = {
 387                 .prepare_fb = mdp5_plane_prepare_fb,
 388                 .cleanup_fb = mdp5_plane_cleanup_fb,
 389                 .atomic_check = mdp5_plane_atomic_check,
 390                 .atomic_update = mdp5_plane_atomic_update,
 391 };
 392
 393 static void set_scanout_locked(struct drm_plane *plane,
 394                 struct drm_framebuffer *fb)
 395 {
 396         struct mdp5_kms *mdp5_kms = get_kms(plane);
 397         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(plane->state)->hwpipe;
 398         enum mdp5_pipe pipe = hwpipe->pipe;
 399
 400         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_A(pipe),
 401                         MDP5_PIPE_SRC_STRIDE_A_P0(fb->pitches[0]) |
 402                         MDP5_PIPE_SRC_STRIDE_A_P1(fb->pitches[1]));
 403
 404         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_STRIDE_B(pipe),
 405                         MDP5_PIPE_SRC_STRIDE_B_P2(fb->pitches[2]) |
 406                         MDP5_PIPE_SRC_STRIDE_B_P3(fb->pitches[3]));
 407
 408         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC0_ADDR(pipe),
 409                         msm_framebuffer_iova(fb, mdp5_kms->id, 0));
 410         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC1_ADDR(pipe),
 411                         msm_framebuffer_iova(fb, mdp5_kms->id, 1));
 412         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC2_ADDR(pipe),
 413                         msm_framebuffer_iova(fb, mdp5_kms->id, 2));
 414         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC3_ADDR(pipe),
 415                         msm_framebuffer_iova(fb, mdp5_kms->id, 3));
 416
 417         plane->fb = fb;
 418 }
 419
 420 /* Note: mdp5_plane->pipe_lock must be locked */
 421 static void csc_disable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe)
 422 {
 423         uint32_t value = mdp5_read(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe)) &
 424                          ~MDP5_PIPE_OP_MODE_CSC_1_EN;
 425
 426         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), value);
 427 }
 428
 429 /* Note: mdp5_plane->pipe_lock must be locked */
 430 static void csc_enable(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 431                 struct csc_cfg *csc)
 432 {
 433         uint32_t  i, mode = 0; /* RGB, no CSC */
 434         uint32_t *matrix;
 435
 436         if (unlikely(!csc))
 437                 return;
 438
 439         if ((csc->type == CSC_YUV2RGB) || (CSC_YUV2YUV == csc->type))
 440                 mode |= MDP5_PIPE_OP_MODE_CSC_SRC_DATA_FORMAT(DATA_FORMAT_YUV);
 441         if ((csc->type == CSC_RGB2YUV) || (CSC_YUV2YUV == csc->type))
 442                 mode |= MDP5_PIPE_OP_MODE_CSC_DST_DATA_FORMAT(DATA_FORMAT_YUV);
 443         mode |= MDP5_PIPE_OP_MODE_CSC_1_EN;
 444         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OP_MODE(pipe), mode);
 445
 446         matrix = csc->matrix;
 447         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(pipe),
 448                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_11(matrix[0]) |
 449                         MDP5_PIPE_CSC_1_MATRIX_COEFF_0_COEFF_12(matrix[1]));
 450         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(pipe),
 451                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_13(matrix[2]) |
 452                         MDP5_PIPE_CSC_1_MATRIX_COEFF_1_COEFF_21(matrix[3]));
 453         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(pipe),
 454                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_22(matrix[4]) |
 455                         MDP5_PIPE_CSC_1_MATRIX_COEFF_2_COEFF_23(matrix[5]));
 456         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(pipe),
 457                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_31(matrix[6]) |
 458                         MDP5_PIPE_CSC_1_MATRIX_COEFF_3_COEFF_32(matrix[7]));
 459         mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(pipe),
 460                         MDP5_PIPE_CSC_1_MATRIX_COEFF_4_COEFF_33(matrix[8]));
 461
 462         for (i = 0; i < ARRAY_SIZE(csc->pre_bias); i++) {
 463                 uint32_t *pre_clamp = csc->pre_clamp;
 464                 uint32_t *post_clamp = csc->post_clamp;
 465
 466                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_CLAMP(pipe, i),
 467                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_HIGH(pre_clamp[2*i+1]) |
 468                         MDP5_PIPE_CSC_1_PRE_CLAMP_REG_LOW(pre_clamp[2*i]));
 469
 470                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_CLAMP(pipe, i),
 471                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_HIGH(post_clamp[2*i+1]) |
 472                         MDP5_PIPE_CSC_1_POST_CLAMP_REG_LOW(post_clamp[2*i]));
 473
 474                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_PRE_BIAS(pipe, i),
 475                         MDP5_PIPE_CSC_1_PRE_BIAS_REG_VALUE(csc->pre_bias[i]));
 476
 477                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_CSC_1_POST_BIAS(pipe, i),
 478                         MDP5_PIPE_CSC_1_POST_BIAS_REG_VALUE(csc->post_bias[i]));
 479         }
 480 }
 481
 482 #define PHASE_STEP_SHIFT        21
 483 #define DOWN_SCALE_RATIO_MAX    32      /* 2^(26-21) */
 484
 485 static int calc_phase_step(uint32_t src, uint32_t dst, uint32_t *out_phase)
 486 {
 487         uint32_t unit;
 488
 489         if (src == 0 || dst == 0)
 490                 return -EINVAL;
 491
 492         /*
 493          * PHASE_STEP_X/Y is coded on 26 bits (25:0),
 494          * where 2^21 represents the unity "1" in fixed-point hardware design.
 495          * This leaves 5 bits for the integer part (downscale case):
 496          *      -> maximum downscale ratio = 0b1_1111 = 31
 497          */
 498         if (src > (dst * DOWN_SCALE_RATIO_MAX))
 499                 return -EOVERFLOW;
 500
 501         unit = 1 << PHASE_STEP_SHIFT;
 502         *out_phase = mult_frac(unit, src, dst);
 503
 504         return 0;
 505 }
 506
 507 static int calc_scalex_steps(struct drm_plane *plane,
 508                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 509                 uint32_t phasex_steps[COMP_MAX])
 510 {
 511         struct mdp5_kms *mdp5_kms = get_kms(plane);
 512         struct device *dev = mdp5_kms->dev->dev;
 513         uint32_t phasex_step;
 514         unsigned int hsub;
 515         int ret;
 516
 517         ret = calc_phase_step(src, dest, &phasex_step);
 518         if (ret) {
 519                 dev_err(dev, "X scaling (%d->%d) failed: %d\n", src, dest, ret);
 520                 return ret;
 521         }
 522
 523         hsub = drm_format_horz_chroma_subsampling(pixel_format);
 524
 525         phasex_steps[COMP_0]   = phasex_step;
 526         phasex_steps[COMP_3]   = phasex_step;
 527         phasex_steps[COMP_1_2] = phasex_step / hsub;
 528
 529         return 0;
 530 }
 531
 532 static int calc_scaley_steps(struct drm_plane *plane,
 533                 uint32_t pixel_format, uint32_t src, uint32_t dest,
 534                 uint32_t phasey_steps[COMP_MAX])
 535 {
 536         struct mdp5_kms *mdp5_kms = get_kms(plane);
 537         struct device *dev = mdp5_kms->dev->dev;
 538         uint32_t phasey_step;
 539         unsigned int vsub;
 540         int ret;
 541
 542         ret = calc_phase_step(src, dest, &phasey_step);
 543         if (ret) {
 544                 dev_err(dev, "Y scaling (%d->%d) failed: %d\n", src, dest, ret);
 545                 return ret;
 546         }
 547
 548         vsub = drm_format_vert_chroma_subsampling(pixel_format);
 549
 550         phasey_steps[COMP_0]   = phasey_step;
 551         phasey_steps[COMP_3]   = phasey_step;
 552         phasey_steps[COMP_1_2] = phasey_step / vsub;
 553
 554         return 0;
 555 }
 556
 557 static uint32_t get_scale_config(const struct mdp_format *format,
 558                 uint32_t src, uint32_t dst, bool horz)
 559 {
 560         bool scaling = format->is_yuv ? true : (src != dst);
 561         uint32_t sub, pix_fmt = format->base.pixel_format;
 562         uint32_t ya_filter, uv_filter;
 563         bool yuv = format->is_yuv;
 564
 565         if (!scaling)
 566                 return 0;
 567
 568         if (yuv) {
 569                 sub = horz ? drm_format_horz_chroma_subsampling(pix_fmt) :
 570                              drm_format_vert_chroma_subsampling(pix_fmt);
 571                 uv_filter = ((src / sub) <= dst) ?
 572                                    SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 573         }
 574         ya_filter = (src <= dst) ? SCALE_FILTER_BIL : SCALE_FILTER_PCMN;
 575
 576         if (horz)
 577                 return  MDP5_PIPE_SCALE_CONFIG_SCALEX_EN |
 578                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_0(ya_filter) |
 579                         MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_3(ya_filter) |
 580                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEX_FILTER_COMP_1_2(uv_filter));
 581         else
 582                 return  MDP5_PIPE_SCALE_CONFIG_SCALEY_EN |
 583                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_0(ya_filter) |
 584                         MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_3(ya_filter) |
 585                         COND(yuv, MDP5_PIPE_SCALE_CONFIG_SCALEY_FILTER_COMP_1_2(uv_filter));
 586 }
 587
 588 static void calc_pixel_ext(const struct mdp_format *format,
 589                 uint32_t src, uint32_t dst, uint32_t phase_step[2],
 590                 int pix_ext_edge1[COMP_MAX], int pix_ext_edge2[COMP_MAX],
 591                 bool horz)
 592 {
 593         bool scaling = format->is_yuv ? true : (src != dst);
 594         int i;
 595
 596         /*
 597          * Note:
 598          * We assume here that:
 599          *     1. PCMN filter is used for downscale
 600          *     2. bilinear filter is used for upscale
 601          *     3. we are in a single pipe configuration
 602          */
 603
 604         for (i = 0; i < COMP_MAX; i++) {
 605                 pix_ext_edge1[i] = 0;
 606                 pix_ext_edge2[i] = scaling ? 1 : 0;
 607         }
 608 }
 609
 610 static void mdp5_write_pixel_ext(struct mdp5_kms *mdp5_kms, enum mdp5_pipe pipe,
 611         const struct mdp_format *format,
 612         uint32_t src_w, int pe_left[COMP_MAX], int pe_right[COMP_MAX],
 613         uint32_t src_h, int pe_top[COMP_MAX], int pe_bottom[COMP_MAX])
 614 {
 615         uint32_t pix_fmt = format->base.pixel_format;
 616         uint32_t lr, tb, req;
 617         int i;
 618
 619         for (i = 0; i < COMP_MAX; i++) {
 620                 uint32_t roi_w = src_w;
 621                 uint32_t roi_h = src_h;
 622
 623                 if (format->is_yuv && i == COMP_1_2) {
 624                         roi_w /= drm_format_horz_chroma_subsampling(pix_fmt);
 625                         roi_h /= drm_format_vert_chroma_subsampling(pix_fmt);
 626                 }
 627
 628                 lr  = (pe_left[i] >= 0) ?
 629                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT(pe_left[i]) :
 630                         MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF(pe_left[i]);
 631
 632                 lr |= (pe_right[i] >= 0) ?
 633                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT(pe_right[i]) :
 634                         MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF(pe_right[i]);
 635
 636                 tb  = (pe_top[i] >= 0) ?
 637                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT(pe_top[i]) :
 638                         MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF(pe_top[i]);
 639
 640                 tb |= (pe_bottom[i] >= 0) ?
 641                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT(pe_bottom[i]) :
 642                         MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF(pe_bottom[i]);
 643
 644                 req  = MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT(roi_w +
 645                                 pe_left[i] + pe_right[i]);
 646
 647                 req |= MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM(roi_h +
 648                                 pe_top[i] + pe_bottom[i]);
 649
 650                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_LR(pipe, i), lr);
 651                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_TB(pipe, i), tb);
 652                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(pipe, i), req);
 653
 654                 DBG("comp-%d (L/R): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 655                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT),
 656                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT),
 657                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF),
 658                         FIELD(lr,  MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF),
 659                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT));
 660
 661                 DBG("comp-%d (T/B): rpt=%d/%d, ovf=%d/%d, req=%d", i,
 662                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT),
 663                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT),
 664                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF),
 665                         FIELD(tb,  MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF),
 666                         FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM));
 667         }
 668 }
 669
 670
 671 static int mdp5_plane_mode_set(struct drm_plane *plane,
 672                 struct drm_crtc *crtc, struct drm_framebuffer *fb,
 673                 int crtc_x, int crtc_y,
 674                 unsigned int crtc_w, unsigned int crtc_h,
 675                 uint32_t src_x, uint32_t src_y,
 676                 uint32_t src_w, uint32_t src_h)
 677 {
 678         struct drm_plane_state *pstate = plane->state;
 679         struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
 680         struct mdp5_kms *mdp5_kms = get_kms(plane);
 681         enum mdp5_pipe pipe = hwpipe->pipe;
 682         const struct mdp_format *format;
 683         uint32_t nplanes, config = 0;
 684         uint32_t phasex_step[COMP_MAX] = {0,}, phasey_step[COMP_MAX] = {0,};
 685         bool pe = hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT;
 686         int pe_left[COMP_MAX], pe_right[COMP_MAX];
 687         int pe_top[COMP_MAX], pe_bottom[COMP_MAX];
 688         uint32_t hdecm = 0, vdecm = 0;
 689         uint32_t pix_format;
 690         unsigned int rotation;
 691         bool vflip, hflip;
 692         unsigned long flags;
 693         int ret;
 694
 695         nplanes = drm_format_num_planes(fb->pixel_format);
 696
 697         /* bad formats should already be rejected: */
 698         if (WARN_ON(nplanes > pipe2nclients(pipe)))
 699                 return -EINVAL;
 700
 701         format = to_mdp_format(msm_framebuffer_format(fb));
 702         pix_format = format->base.pixel_format;
 703
 704         /* src values are in Q16 fixed point, convert to integer: */
 705         src_x = src_x >> 16;
 706         src_y = src_y >> 16;
 707         src_w = src_w >> 16;
 708         src_h = src_h >> 16;
 709
 710         DBG("%s: FB[%u] %u,%u,%u,%u -> CRTC[%u] %d,%d,%u,%u", plane->name,
 711                         fb->base.id, src_x, src_y, src_w, src_h,
 712                         crtc->base.id, crtc_x, crtc_y, crtc_w, crtc_h);
 713
 714         /* Request some memory from the SMP: */
 715         if (mdp5_kms->smp) {
 716                 ret = mdp5_smp_request(mdp5_kms->smp, pipe,
 717                                 format, src_w, false);
 718                 if (ret)
 719                         return ret;
 720         }
 721
 722         /*
 723          * Currently we update the hw for allocations/requests immediately,
 724          * but once atomic modeset/pageflip is in place, the allocation
 725          * would move into atomic->check_plane_state(), while updating the
 726          * hw would remain here:
 727          */
 728         if (mdp5_kms->smp)
 729                 mdp5_smp_configure(mdp5_kms->smp, pipe);
 730
 731         ret = calc_scalex_steps(plane, pix_format, src_w, crtc_w, phasex_step);
 732         if (ret)
 733                 return ret;
 734
 735         ret = calc_scaley_steps(plane, pix_format, src_h, crtc_h, phasey_step);
 736         if (ret)
 737                 return ret;
 738
 739         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT) {
 740                 calc_pixel_ext(format, src_w, crtc_w, phasex_step,
 741                                          pe_left, pe_right, true);
 742                 calc_pixel_ext(format, src_h, crtc_h, phasey_step,
 743                                         pe_top, pe_bottom, false);
 744         }
 745
 746         /* TODO calc hdecm, vdecm */
 747
 748         /* SCALE is used to both scale and up-sample chroma components */
 749         config |= get_scale_config(format, src_w, crtc_w, true);
 750         config |= get_scale_config(format, src_h, crtc_h, false);
 751         DBG("scale config = %x", config);
 752
 753         rotation = drm_rotation_simplify(pstate->rotation,
 754                                          DRM_ROTATE_0 |
 755                                          DRM_REFLECT_X |
 756                                          DRM_REFLECT_Y);
 757         hflip = !!(rotation & DRM_REFLECT_X);
 758         vflip = !!(rotation & DRM_REFLECT_Y);
 759
 760         spin_lock_irqsave(&hwpipe->pipe_lock, flags);
 761
 762         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_IMG_SIZE(pipe),
 763                         MDP5_PIPE_SRC_IMG_SIZE_WIDTH(min(fb->width, src_w)) |
 764                         MDP5_PIPE_SRC_IMG_SIZE_HEIGHT(min(fb->height, src_h)));
 765
 766         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_SIZE(pipe),
 767                         MDP5_PIPE_SRC_SIZE_WIDTH(src_w) |
 768                         MDP5_PIPE_SRC_SIZE_HEIGHT(src_h));
 769
 770         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_XY(pipe),
 771                         MDP5_PIPE_SRC_XY_X(src_x) |
 772                         MDP5_PIPE_SRC_XY_Y(src_y));
 773
 774         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_SIZE(pipe),
 775                         MDP5_PIPE_OUT_SIZE_WIDTH(crtc_w) |
 776                         MDP5_PIPE_OUT_SIZE_HEIGHT(crtc_h));
 777
 778         mdp5_write(mdp5_kms, REG_MDP5_PIPE_OUT_XY(pipe),
 779                         MDP5_PIPE_OUT_XY_X(crtc_x) |
 780                         MDP5_PIPE_OUT_XY_Y(crtc_y));
 781
 782         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_FORMAT(pipe),
 783                         MDP5_PIPE_SRC_FORMAT_A_BPC(format->bpc_a) |
 784                         MDP5_PIPE_SRC_FORMAT_R_BPC(format->bpc_r) |
 785                         MDP5_PIPE_SRC_FORMAT_G_BPC(format->bpc_g) |
 786                         MDP5_PIPE_SRC_FORMAT_B_BPC(format->bpc_b) |
 787                         COND(format->alpha_enable, MDP5_PIPE_SRC_FORMAT_ALPHA_ENABLE) |
 788                         MDP5_PIPE_SRC_FORMAT_CPP(format->cpp - 1) |
 789                         MDP5_PIPE_SRC_FORMAT_UNPACK_COUNT(format->unpack_count - 1) |
 790                         COND(format->unpack_tight, MDP5_PIPE_SRC_FORMAT_UNPACK_TIGHT) |
 791                         MDP5_PIPE_SRC_FORMAT_FETCH_TYPE(format->fetch_type) |
 792                         MDP5_PIPE_SRC_FORMAT_CHROMA_SAMP(format->chroma_sample));
 793
 794         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_UNPACK(pipe),
 795                         MDP5_PIPE_SRC_UNPACK_ELEM0(format->unpack[0]) |
 796                         MDP5_PIPE_SRC_UNPACK_ELEM1(format->unpack[1]) |
 797                         MDP5_PIPE_SRC_UNPACK_ELEM2(format->unpack[2]) |
 798                         MDP5_PIPE_SRC_UNPACK_ELEM3(format->unpack[3]));
 799
 800         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_OP_MODE(pipe),
 801                         (hflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_LR : 0) |
 802                         (vflip ? MDP5_PIPE_SRC_OP_MODE_FLIP_UD : 0) |
 803                         COND(pe, MDP5_PIPE_SRC_OP_MODE_SW_PIX_EXT_OVERRIDE) |
 804                         MDP5_PIPE_SRC_OP_MODE_BWC(BWC_LOSSLESS));
 805
 806         /* not using secure mode: */
 807         mdp5_write(mdp5_kms, REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(pipe), 0);
 808
 809         if (hwpipe->caps & MDP_PIPE_CAP_SW_PIX_EXT)
 810                 mdp5_write_pixel_ext(mdp5_kms, pipe, format,
 811                                 src_w, pe_left, pe_right,
 812                                 src_h, pe_top, pe_bottom);
 813
 814         if (hwpipe->caps & MDP_PIPE_CAP_SCALE) {
 815                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_X(pipe),
 816                                 phasex_step[COMP_0]);
 817                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(pipe),
 818                                 phasey_step[COMP_0]);
 819                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(pipe),
 820                                 phasex_step[COMP_1_2]);
 821                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(pipe),
 822                                 phasey_step[COMP_1_2]);
 823                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_DECIMATION(pipe),
 824                                 MDP5_PIPE_DECIMATION_VERT(vdecm) |
 825                                 MDP5_PIPE_DECIMATION_HORZ(hdecm));
 826                 mdp5_write(mdp5_kms, REG_MDP5_PIPE_SCALE_CONFIG(pipe), config);
 827         }
 828
 829         if (hwpipe->caps & MDP_PIPE_CAP_CSC) {
 830                 if (MDP_FORMAT_IS_YUV(format))
 831                         csc_enable(mdp5_kms, pipe,
 832                                         mdp_get_default_csc_cfg(CSC_YUV2RGB));
 833                 else
 834                         csc_disable(mdp5_kms, pipe);
 835         }
 836
 837         set_scanout_locked(plane, fb);
 838
 839         spin_unlock_irqrestore(&hwpipe->pipe_lock, flags);
 840
 841         return ret;
 842 }
 843
 844 enum mdp5_pipe mdp5_plane_pipe(struct drm_plane *plane)
 845 {
 846         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
 847
 848         if (WARN_ON(!pstate->hwpipe))
 849                 return 0;
 850
 851         return pstate->hwpipe->pipe;
 852 }
 853
 854 uint32_t mdp5_plane_get_flush(struct drm_plane *plane)
 855 {
 856         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
 857
 858         if (WARN_ON(!pstate->hwpipe))
 859                 return 0;
 860
 861         return pstate->hwpipe->flush_mask;
 862 }
 863
 864 /* called after vsync in thread context */
 865 void mdp5_plane_complete_commit(struct drm_plane *plane,
 866         struct drm_plane_state *state)
 867 {
 868         struct mdp5_kms *mdp5_kms = get_kms(plane);
 869         struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
 870
 871         if (mdp5_kms->smp && pstate->hwpipe) {
 872                 enum mdp5_pipe pipe = pstate->hwpipe->pipe;
 873
 874                 if (plane_enabled(plane->state)) {
 875                         DBG("%s: complete flip", plane->name);
 876                         mdp5_smp_commit(mdp5_kms->smp, pipe);
 877                 } else {
 878                         DBG("%s: free SMP", plane->name);
 879                         mdp5_smp_release(mdp5_kms->smp, pipe);
 880                 }
 881         }
 882
 883         pstate->pending = false;
 884 }
 885
 886 /* initialize plane */
 887 struct drm_plane *mdp5_plane_init(struct drm_device *dev, bool primary)
 888 {
 889         struct drm_plane *plane = NULL;
 890         struct mdp5_plane *mdp5_plane;
 891         int ret;
 892         enum drm_plane_type type;
 893
 894         mdp5_plane = kzalloc(sizeof(*mdp5_plane), GFP_KERNEL);
 895         if (!mdp5_plane) {
 896                 ret = -ENOMEM;
 897                 goto fail;
 898         }
 899
 900         plane = &mdp5_plane->base;
 901
 902         mdp5_plane->nformats = mdp_get_formats(mdp5_plane->formats,
 903                 ARRAY_SIZE(mdp5_plane->formats), false);
 904
 905         type = primary ? DRM_PLANE_TYPE_PRIMARY : DRM_PLANE_TYPE_OVERLAY;
 906         ret = drm_universal_plane_init(dev, plane, 0xff, &mdp5_plane_funcs,
 907                                  mdp5_plane->formats, mdp5_plane->nformats,
 908                                  type, NULL);
 909         if (ret)
 910                 goto fail;
 911
 912         drm_plane_helper_add(plane, &mdp5_plane_helper_funcs);
 913
 914         mdp5_plane_install_properties(plane, &plane->base);
 915
 916         return plane;
 917
 918 fail:
 919         if (plane)
 920                 mdp5_plane_destroy(plane);
 921
 922         return ERR_PTR(ret);
 923 }