1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
7 #include <linux/delay.h>
8 #include <linux/dma-mapping.h>
10 #include <linux/gpio/consumer.h>
11 #include <linux/interrupt.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_irq.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/pm_opp.h>
18 #include <linux/regmap.h>
19 #include <linux/regulator/consumer.h>
20 #include <linux/spinlock.h>
22 #include <video/mipi_display.h>
24 #include <drm/display/drm_dsc_helper.h>
25 #include <drm/drm_of.h>
31 #include "msm_dsc_helper.h"
34 #include "phy/dsi_phy.h"
36 #define DSI_RESET_TOGGLE_DELAY_MS 20
38 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc);
40 static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
48 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0
49 * makes all other registers 4-byte shifted down.
51 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and
52 * older, we read the DSI_VERSION register without any shift(offset
53 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In
54 * the case of DSI6G, this has to be zero (the offset points to a
55 * scratch register which we never touch)
58 ver = msm_readl(base + REG_DSI_VERSION);
60 /* older dsi host, there is no register shift */
61 ver = FIELD(ver, DSI_VERSION_MAJOR);
62 if (ver <= MSM_DSI_VER_MAJOR_V2) {
72 * newer host, offset 0 has 6G_HW_VERSION, the rest of the
73 * registers are shifted down, read DSI_VERSION again with
76 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION);
77 ver = FIELD(ver, DSI_VERSION_MAJOR);
78 if (ver == MSM_DSI_VER_MAJOR_6G) {
81 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION);
89 #define DSI_ERR_STATE_ACK 0x0000
90 #define DSI_ERR_STATE_TIMEOUT 0x0001
91 #define DSI_ERR_STATE_DLN0_PHY 0x0002
92 #define DSI_ERR_STATE_FIFO 0x0004
93 #define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008
94 #define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010
95 #define DSI_ERR_STATE_PLL_UNLOCKED 0x0020
97 #define DSI_CLK_CTRL_ENABLE_CLKS \
98 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \
99 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \
100 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \
101 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK)
103 struct msm_dsi_host {
104 struct mipi_dsi_host base;
106 struct platform_device *pdev;
107 struct drm_device *dev;
111 void __iomem *ctrl_base;
112 phys_addr_t ctrl_size;
113 struct regulator_bulk_data *supplies;
116 struct clk_bulk_data bus_clks[DSI_BUS_CLK_MAX];
118 struct clk *byte_clk;
120 struct clk *pixel_clk;
121 struct clk *byte_intf_clk;
123 unsigned long byte_clk_rate;
124 unsigned long byte_intf_clk_rate;
125 unsigned long pixel_clk_rate;
126 unsigned long esc_clk_rate;
128 /* DSI v2 specific clocks */
131 unsigned long src_clk_rate;
133 struct gpio_desc *disp_en_gpio;
134 struct gpio_desc *te_gpio;
136 const struct msm_dsi_cfg_handler *cfg_hnd;
138 struct completion dma_comp;
139 struct completion video_comp;
140 struct mutex dev_mutex;
141 struct mutex cmd_mutex;
142 spinlock_t intr_lock; /* Protect interrupt ctrl register */
145 struct work_struct err_work;
146 struct workqueue_struct *workqueue;
148 /* DSI 6G TX buffer*/
149 struct drm_gem_object *tx_gem_obj;
151 /* DSI v2 TX buffer */
153 dma_addr_t tx_buf_paddr;
161 struct drm_display_mode *mode;
162 struct drm_dsc_config *dsc;
164 /* connected device info */
165 unsigned int channel;
167 enum mipi_dsi_pixel_format format;
168 unsigned long mode_flags;
170 /* lane data parsed via DT */
177 u32 dma_cmd_ctrl_restore;
185 static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt)
188 case MIPI_DSI_FMT_RGB565: return 16;
189 case MIPI_DSI_FMT_RGB666_PACKED: return 18;
190 case MIPI_DSI_FMT_RGB666:
191 case MIPI_DSI_FMT_RGB888:
196 static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg)
198 return msm_readl(msm_host->ctrl_base + reg);
200 static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data)
202 msm_writel(data, msm_host->ctrl_base + reg);
205 static const struct msm_dsi_cfg_handler *dsi_get_config(
206 struct msm_dsi_host *msm_host)
208 const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
209 struct device *dev = &msm_host->pdev->dev;
212 u32 major = 0, minor = 0;
214 ahb_clk = msm_clk_get(msm_host->pdev, "iface");
215 if (IS_ERR(ahb_clk)) {
216 pr_err("%s: cannot get interface clock\n", __func__);
220 pm_runtime_get_sync(dev);
222 ret = clk_prepare_enable(ahb_clk);
224 pr_err("%s: unable to enable ahb_clk\n", __func__);
228 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor);
230 pr_err("%s: Invalid version\n", __func__);
234 cfg_hnd = msm_dsi_cfg_get(major, minor);
236 DBG("%s: Version %x:%x\n", __func__, major, minor);
239 clk_disable_unprepare(ahb_clk);
241 pm_runtime_put_sync(dev);
246 static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host)
248 return container_of(host, struct msm_dsi_host, base);
251 int dsi_clk_init_v2(struct msm_dsi_host *msm_host)
253 struct platform_device *pdev = msm_host->pdev;
256 msm_host->src_clk = msm_clk_get(pdev, "src");
258 if (IS_ERR(msm_host->src_clk)) {
259 ret = PTR_ERR(msm_host->src_clk);
260 pr_err("%s: can't find src clock. ret=%d\n",
262 msm_host->src_clk = NULL;
269 int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host)
271 struct platform_device *pdev = msm_host->pdev;
274 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf");
275 if (IS_ERR(msm_host->byte_intf_clk)) {
276 ret = PTR_ERR(msm_host->byte_intf_clk);
277 pr_err("%s: can't find byte_intf clock. ret=%d\n",
284 static int dsi_clk_init(struct msm_dsi_host *msm_host)
286 struct platform_device *pdev = msm_host->pdev;
287 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
288 const struct msm_dsi_config *cfg = cfg_hnd->cfg;
292 for (i = 0; i < cfg->num_bus_clks; i++)
293 msm_host->bus_clks[i].id = cfg->bus_clk_names[i];
294 msm_host->num_bus_clks = cfg->num_bus_clks;
296 ret = devm_clk_bulk_get(&pdev->dev, msm_host->num_bus_clks, msm_host->bus_clks);
298 dev_err(&pdev->dev, "Unable to get clocks, ret = %d\n", ret);
302 /* get link and source clocks */
303 msm_host->byte_clk = msm_clk_get(pdev, "byte");
304 if (IS_ERR(msm_host->byte_clk)) {
305 ret = PTR_ERR(msm_host->byte_clk);
306 pr_err("%s: can't find dsi_byte clock. ret=%d\n",
308 msm_host->byte_clk = NULL;
312 msm_host->pixel_clk = msm_clk_get(pdev, "pixel");
313 if (IS_ERR(msm_host->pixel_clk)) {
314 ret = PTR_ERR(msm_host->pixel_clk);
315 pr_err("%s: can't find dsi_pixel clock. ret=%d\n",
317 msm_host->pixel_clk = NULL;
321 msm_host->esc_clk = msm_clk_get(pdev, "core");
322 if (IS_ERR(msm_host->esc_clk)) {
323 ret = PTR_ERR(msm_host->esc_clk);
324 pr_err("%s: can't find dsi_esc clock. ret=%d\n",
326 msm_host->esc_clk = NULL;
330 if (cfg_hnd->ops->clk_init_ver)
331 ret = cfg_hnd->ops->clk_init_ver(msm_host);
336 int msm_dsi_runtime_suspend(struct device *dev)
338 struct platform_device *pdev = to_platform_device(dev);
339 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
340 struct mipi_dsi_host *host = msm_dsi->host;
341 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
343 if (!msm_host->cfg_hnd)
346 clk_bulk_disable_unprepare(msm_host->num_bus_clks, msm_host->bus_clks);
351 int msm_dsi_runtime_resume(struct device *dev)
353 struct platform_device *pdev = to_platform_device(dev);
354 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev);
355 struct mipi_dsi_host *host = msm_dsi->host;
356 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
358 if (!msm_host->cfg_hnd)
361 return clk_bulk_prepare_enable(msm_host->num_bus_clks, msm_host->bus_clks);
364 int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host)
368 DBG("Set clk rates: pclk=%d, byteclk=%lu",
369 msm_host->mode->clock, msm_host->byte_clk_rate);
371 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev,
372 msm_host->byte_clk_rate);
374 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret);
378 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
380 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
384 if (msm_host->byte_intf_clk) {
385 ret = clk_set_rate(msm_host->byte_intf_clk, msm_host->byte_intf_clk_rate);
387 pr_err("%s: Failed to set rate byte intf clk, %d\n",
397 int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host)
401 ret = clk_prepare_enable(msm_host->esc_clk);
403 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
407 ret = clk_prepare_enable(msm_host->byte_clk);
409 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
413 ret = clk_prepare_enable(msm_host->pixel_clk);
415 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
419 ret = clk_prepare_enable(msm_host->byte_intf_clk);
421 pr_err("%s: Failed to enable byte intf clk\n",
423 goto byte_intf_clk_err;
429 clk_disable_unprepare(msm_host->pixel_clk);
431 clk_disable_unprepare(msm_host->byte_clk);
433 clk_disable_unprepare(msm_host->esc_clk);
438 int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host)
442 DBG("Set clk rates: pclk=%d, byteclk=%lu, esc_clk=%lu, dsi_src_clk=%lu",
443 msm_host->mode->clock, msm_host->byte_clk_rate,
444 msm_host->esc_clk_rate, msm_host->src_clk_rate);
446 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate);
448 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret);
452 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate);
454 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret);
458 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate);
460 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret);
464 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate);
466 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret);
473 int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host)
477 ret = clk_prepare_enable(msm_host->byte_clk);
479 pr_err("%s: Failed to enable dsi byte clk\n", __func__);
483 ret = clk_prepare_enable(msm_host->esc_clk);
485 pr_err("%s: Failed to enable dsi esc clk\n", __func__);
489 ret = clk_prepare_enable(msm_host->src_clk);
491 pr_err("%s: Failed to enable dsi src clk\n", __func__);
495 ret = clk_prepare_enable(msm_host->pixel_clk);
497 pr_err("%s: Failed to enable dsi pixel clk\n", __func__);
504 clk_disable_unprepare(msm_host->src_clk);
506 clk_disable_unprepare(msm_host->esc_clk);
508 clk_disable_unprepare(msm_host->byte_clk);
513 void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host)
515 /* Drop the performance state vote */
516 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0);
517 clk_disable_unprepare(msm_host->esc_clk);
518 clk_disable_unprepare(msm_host->pixel_clk);
519 clk_disable_unprepare(msm_host->byte_intf_clk);
520 clk_disable_unprepare(msm_host->byte_clk);
523 void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host)
525 clk_disable_unprepare(msm_host->pixel_clk);
526 clk_disable_unprepare(msm_host->src_clk);
527 clk_disable_unprepare(msm_host->esc_clk);
528 clk_disable_unprepare(msm_host->byte_clk);
531 static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode,
532 const struct drm_dsc_config *dsc)
534 int new_hdisplay = DIV_ROUND_UP(mode->hdisplay * drm_dsc_get_bpp_int(dsc),
535 dsc->bits_per_component * 3);
537 int new_htotal = mode->htotal - mode->hdisplay + new_hdisplay;
539 return new_htotal * mode->vtotal * drm_mode_vrefresh(mode);
542 static unsigned long dsi_get_pclk_rate(const struct drm_display_mode *mode,
543 const struct drm_dsc_config *dsc, bool is_bonded_dsi)
545 unsigned long pclk_rate;
547 pclk_rate = mode->clock * 1000;
550 pclk_rate = dsi_adjust_pclk_for_compression(mode, dsc);
553 * For bonded DSI mode, the current DRM mode has the complete width of the
554 * panel. Since, the complete panel is driven by two DSI controllers,
555 * the clock rates have to be split between the two dsi controllers.
556 * Adjust the byte and pixel clock rates for each dsi host accordingly.
564 unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_dsi,
565 const struct drm_display_mode *mode)
567 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
568 u8 lanes = msm_host->lanes;
569 u32 bpp = dsi_get_bpp(msm_host->format);
570 unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi);
571 unsigned long pclk_bpp;
574 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__);
578 /* CPHY "byte_clk" is in units of 16 bits */
579 if (msm_host->cphy_mode)
580 pclk_bpp = mult_frac(pclk_rate, bpp, 16 * lanes);
582 pclk_bpp = mult_frac(pclk_rate, bpp, 8 * lanes);
587 static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
589 msm_host->pixel_clk_rate = dsi_get_pclk_rate(msm_host->mode, msm_host->dsc, is_bonded_dsi);
590 msm_host->byte_clk_rate = dsi_byte_clk_get_rate(&msm_host->base, is_bonded_dsi,
593 DBG("pclk=%lu, bclk=%lu", msm_host->pixel_clk_rate,
594 msm_host->byte_clk_rate);
598 int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
600 if (!msm_host->mode) {
601 pr_err("%s: mode not set\n", __func__);
605 dsi_calc_pclk(msm_host, is_bonded_dsi);
606 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk);
610 int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
612 u32 bpp = dsi_get_bpp(msm_host->format);
613 unsigned int esc_mhz, esc_div;
614 unsigned long byte_mhz;
616 dsi_calc_pclk(msm_host, is_bonded_dsi);
618 msm_host->src_clk_rate = mult_frac(msm_host->pixel_clk_rate, bpp, 8);
621 * esc clock is byte clock followed by a 4 bit divider,
622 * we need to find an escape clock frequency within the
623 * mipi DSI spec range within the maximum divider limit
624 * We iterate here between an escape clock frequencey
625 * between 20 Mhz to 5 Mhz and pick up the first one
626 * that can be supported by our divider
629 byte_mhz = msm_host->byte_clk_rate / 1000000;
631 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) {
632 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz);
635 * TODO: Ideally, we shouldn't know what sort of divider
636 * is available in mmss_cc, we're just assuming that
637 * it'll always be a 4 bit divider. Need to come up with
640 if (esc_div >= 1 && esc_div <= 16)
647 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div;
649 DBG("esc=%lu, src=%lu", msm_host->esc_clk_rate,
650 msm_host->src_clk_rate);
655 static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable)
660 spin_lock_irqsave(&msm_host->intr_lock, flags);
661 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
668 DBG("intr=%x enable=%d", intr, enable);
670 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr);
671 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
674 static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags)
676 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
678 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
679 return NON_BURST_SYNCH_PULSE;
681 return NON_BURST_SYNCH_EVENT;
684 static inline enum dsi_vid_dst_format dsi_get_vid_fmt(
685 const enum mipi_dsi_pixel_format mipi_fmt)
688 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888;
689 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE;
690 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666;
691 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565;
692 default: return VID_DST_FORMAT_RGB888;
696 static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt(
697 const enum mipi_dsi_pixel_format mipi_fmt)
700 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888;
701 case MIPI_DSI_FMT_RGB666_PACKED:
702 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666;
703 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565;
704 default: return CMD_DST_FORMAT_RGB888;
708 static void dsi_ctrl_disable(struct msm_dsi_host *msm_host)
710 dsi_write(msm_host, REG_DSI_CTRL, 0);
713 static void dsi_ctrl_enable(struct msm_dsi_host *msm_host,
714 struct msm_dsi_phy_shared_timings *phy_shared_timings, struct msm_dsi_phy *phy)
716 u32 flags = msm_host->mode_flags;
717 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
718 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
719 u32 data = 0, lane_ctrl = 0;
721 if (flags & MIPI_DSI_MODE_VIDEO) {
722 if (flags & MIPI_DSI_MODE_VIDEO_HSE)
723 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE;
724 if (flags & MIPI_DSI_MODE_VIDEO_NO_HFP)
725 data |= DSI_VID_CFG0_HFP_POWER_STOP;
726 if (flags & MIPI_DSI_MODE_VIDEO_NO_HBP)
727 data |= DSI_VID_CFG0_HBP_POWER_STOP;
728 if (flags & MIPI_DSI_MODE_VIDEO_NO_HSA)
729 data |= DSI_VID_CFG0_HSA_POWER_STOP;
730 /* Always set low power stop mode for BLLP
731 * to let command engine send packets
733 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP |
734 DSI_VID_CFG0_BLLP_POWER_STOP;
735 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags));
736 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt));
737 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel);
738 dsi_write(msm_host, REG_DSI_VID_CFG0, data);
740 /* Do not swap RGB colors */
741 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB);
742 dsi_write(msm_host, REG_DSI_VID_CFG1, 0);
744 /* Do not swap RGB colors */
745 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB);
746 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt));
747 dsi_write(msm_host, REG_DSI_CMD_CFG0, data);
749 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) |
750 DSI_CMD_CFG1_WR_MEM_CONTINUE(
751 MIPI_DCS_WRITE_MEMORY_CONTINUE);
752 /* Always insert DCS command */
753 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND;
754 dsi_write(msm_host, REG_DSI_CMD_CFG1, data);
757 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL,
758 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER |
759 DSI_CMD_DMA_CTRL_LOW_POWER);
762 /* Always assume dedicated TE pin */
763 data |= DSI_TRIG_CTRL_TE;
764 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE);
765 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW);
766 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel);
767 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
768 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2))
769 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME;
770 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data);
772 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) |
773 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre);
774 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data);
776 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
777 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) &&
778 phy_shared_timings->clk_pre_inc_by_2)
779 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND,
780 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK);
783 if (!(flags & MIPI_DSI_MODE_NO_EOT_PACKET))
784 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND;
785 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data);
787 /* allow only ack-err-status to generate interrupt */
788 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0);
790 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
792 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
794 data = DSI_CTRL_CLK_EN;
796 DBG("lane number=%d", msm_host->lanes);
797 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0);
799 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
800 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
802 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
803 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
805 if (msm_dsi_phy_set_continuous_clock(phy, true))
806 lane_ctrl &= ~DSI_LANE_CTRL_HS_REQ_SEL_PHY;
808 dsi_write(msm_host, REG_DSI_LANE_CTRL,
809 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
812 data |= DSI_CTRL_ENABLE;
814 dsi_write(msm_host, REG_DSI_CTRL, data);
816 if (msm_host->cphy_mode)
817 dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
820 static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mode, u32 hdisplay)
822 struct drm_dsc_config *dsc = msm_host->dsc;
823 u32 reg, reg_ctrl, reg_ctrl2;
824 u32 slice_per_intf, total_bytes_per_intf;
828 /* first calculate dsc parameters and then program
829 * compress mode registers
831 slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay);
833 total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf;
835 eol_byte_num = total_bytes_per_intf % 3;
838 * Typically, pkt_per_line = slice_per_intf * slice_per_pkt.
840 * Since the current driver only supports slice_per_pkt = 1,
841 * pkt_per_line will be equal to slice per intf for now.
843 pkt_per_line = slice_per_intf;
845 if (is_cmd_mode) /* packet data type */
846 reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);
848 reg = DSI_VIDEO_COMPRESSION_MODE_CTRL_DATATYPE(MIPI_DSI_COMPRESSED_PIXEL_STREAM);
850 /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE
851 * registers have similar offsets, so for below common code use
852 * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits
854 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1);
855 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num);
856 reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EN;
859 reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
860 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
865 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK;
866 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size);
868 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl);
869 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
871 dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
875 static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
877 struct drm_display_mode *mode = msm_host->mode;
878 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */
879 u32 h_total = mode->htotal;
880 u32 v_total = mode->vtotal;
881 u32 hs_end = mode->hsync_end - mode->hsync_start;
882 u32 vs_end = mode->vsync_end - mode->vsync_start;
883 u32 ha_start = h_total - mode->hsync_start;
884 u32 ha_end = ha_start + mode->hdisplay;
885 u32 va_start = v_total - mode->vsync_start;
886 u32 va_end = va_start + mode->vdisplay;
887 u32 hdisplay = mode->hdisplay;
894 * For bonded DSI mode, the current DRM mode has
895 * the complete width of the panel. Since, the complete
896 * panel is driven by two DSI controllers, the horizontal
897 * timings have to be split between the two dsi controllers.
898 * Adjust the DSI host timing values accordingly.
909 struct drm_dsc_config *dsc = msm_host->dsc;
911 /* update dsc params with timing params */
912 if (!dsc || !mode->hdisplay || !mode->vdisplay) {
913 pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n",
914 mode->hdisplay, mode->vdisplay);
918 dsc->pic_width = mode->hdisplay;
919 dsc->pic_height = mode->vdisplay;
920 DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height);
922 /* we do the calculations for dsc parameters here so that
923 * panel can use these parameters
925 ret = dsi_populate_dsc_params(msm_host, dsc);
929 /* Divide the display by 3 but keep back/font porch and
933 hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3);
935 ha_end = ha_start + hdisplay;
938 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
940 dsi_update_dsc_timing(msm_host, false, mode->hdisplay);
942 dsi_write(msm_host, REG_DSI_ACTIVE_H,
943 DSI_ACTIVE_H_START(ha_start) |
944 DSI_ACTIVE_H_END(ha_end));
945 dsi_write(msm_host, REG_DSI_ACTIVE_V,
946 DSI_ACTIVE_V_START(va_start) |
947 DSI_ACTIVE_V_END(va_end));
948 dsi_write(msm_host, REG_DSI_TOTAL,
949 DSI_TOTAL_H_TOTAL(h_total - 1) |
950 DSI_TOTAL_V_TOTAL(v_total - 1));
952 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC,
953 DSI_ACTIVE_HSYNC_START(hs_start) |
954 DSI_ACTIVE_HSYNC_END(hs_end));
955 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0);
956 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS,
957 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
958 DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
959 } else { /* command mode */
961 dsi_update_dsc_timing(msm_host, true, mode->hdisplay);
963 /* image data and 1 byte write_memory_start cmd */
965 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
968 * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1.
969 * Currently, the driver only supports default value of slice_per_pkt = 1
971 * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info
972 * and adjust DSC math to account for slice_per_pkt.
974 wc = msm_host->dsc->slice_chunk_size + 1;
976 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
977 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
978 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL(
980 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE(
981 MIPI_DSI_DCS_LONG_WRITE));
983 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL,
984 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) |
985 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay));
989 static void dsi_sw_reset(struct msm_dsi_host *msm_host)
993 ctrl = dsi_read(msm_host, REG_DSI_CTRL);
995 if (ctrl & DSI_CTRL_ENABLE) {
996 dsi_write(msm_host, REG_DSI_CTRL, ctrl & ~DSI_CTRL_ENABLE);
998 * dsi controller need to be disabled before
1004 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS);
1005 wmb(); /* clocks need to be enabled before reset */
1007 /* dsi controller can only be reset while clocks are running */
1008 dsi_write(msm_host, REG_DSI_RESET, 1);
1009 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */
1010 dsi_write(msm_host, REG_DSI_RESET, 0);
1011 wmb(); /* controller out of reset */
1013 if (ctrl & DSI_CTRL_ENABLE) {
1014 dsi_write(msm_host, REG_DSI_CTRL, ctrl);
1015 wmb(); /* make sure dsi controller enabled again */
1019 static void dsi_op_mode_config(struct msm_dsi_host *msm_host,
1020 bool video_mode, bool enable)
1024 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL);
1027 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN |
1028 DSI_CTRL_CMD_MODE_EN);
1029 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE |
1030 DSI_IRQ_MASK_VIDEO_DONE, 0);
1033 dsi_ctrl |= DSI_CTRL_VID_MODE_EN;
1034 } else { /* command mode */
1035 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN;
1036 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1);
1038 dsi_ctrl |= DSI_CTRL_ENABLE;
1041 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl);
1044 static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host)
1048 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL);
1051 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER;
1053 data |= DSI_CMD_DMA_CTRL_LOW_POWER;
1055 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data);
1058 static void dsi_wait4video_done(struct msm_dsi_host *msm_host)
1061 struct device *dev = &msm_host->pdev->dev;
1063 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1);
1065 reinit_completion(&msm_host->video_comp);
1067 ret = wait_for_completion_timeout(&msm_host->video_comp,
1068 msecs_to_jiffies(70));
1071 DRM_DEV_ERROR(dev, "wait for video done timed out\n");
1073 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0);
1076 static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host)
1078 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO))
1081 if (msm_host->power_on && msm_host->enabled) {
1082 dsi_wait4video_done(msm_host);
1083 /* delay 4 ms to skip BLLP */
1084 usleep_range(2000, 4000);
1088 int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size)
1090 struct drm_device *dev = msm_host->dev;
1091 struct msm_drm_private *priv = dev->dev_private;
1095 data = msm_gem_kernel_new(dev, size, MSM_BO_WC,
1097 &msm_host->tx_gem_obj, &iova);
1100 msm_host->tx_gem_obj = NULL;
1101 return PTR_ERR(data);
1104 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem");
1106 msm_host->tx_size = msm_host->tx_gem_obj->size;
1111 int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size)
1113 struct drm_device *dev = msm_host->dev;
1115 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size,
1116 &msm_host->tx_buf_paddr, GFP_KERNEL);
1117 if (!msm_host->tx_buf)
1120 msm_host->tx_size = size;
1125 static void dsi_tx_buf_free(struct msm_dsi_host *msm_host)
1127 struct drm_device *dev = msm_host->dev;
1128 struct msm_drm_private *priv;
1131 * This is possible if we're tearing down before we've had a chance to
1132 * fully initialize. A very real possibility if our probe is deferred,
1133 * in which case we'll hit msm_dsi_host_destroy() without having run
1134 * through the dsi_tx_buf_alloc().
1139 priv = dev->dev_private;
1140 if (msm_host->tx_gem_obj) {
1141 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace);
1142 drm_gem_object_put(msm_host->tx_gem_obj);
1143 msm_host->tx_gem_obj = NULL;
1146 if (msm_host->tx_buf)
1147 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf,
1148 msm_host->tx_buf_paddr);
1151 void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host)
1153 return msm_gem_get_vaddr(msm_host->tx_gem_obj);
1156 void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host)
1158 return msm_host->tx_buf;
1161 void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host)
1163 msm_gem_put_vaddr(msm_host->tx_gem_obj);
1167 * prepare cmd buffer to be txed
1169 static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host,
1170 const struct mipi_dsi_msg *msg)
1172 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1173 struct mipi_dsi_packet packet;
1178 ret = mipi_dsi_create_packet(&packet, msg);
1180 pr_err("%s: create packet failed, %d\n", __func__, ret);
1183 len = (packet.size + 3) & (~0x3);
1185 if (len > msm_host->tx_size) {
1186 pr_err("%s: packet size is too big\n", __func__);
1190 data = cfg_hnd->ops->tx_buf_get(msm_host);
1192 ret = PTR_ERR(data);
1193 pr_err("%s: get vaddr failed, %d\n", __func__, ret);
1197 /* MSM specific command format in memory */
1198 data[0] = packet.header[1];
1199 data[1] = packet.header[2];
1200 data[2] = packet.header[0];
1201 data[3] = BIT(7); /* Last packet */
1202 if (mipi_dsi_packet_format_is_long(msg->type))
1204 if (msg->rx_buf && msg->rx_len)
1208 if (packet.payload && packet.payload_length)
1209 memcpy(data + 4, packet.payload, packet.payload_length);
1211 /* Append 0xff to the end */
1212 if (packet.size < len)
1213 memset(data + packet.size, 0xff, len - packet.size);
1215 if (cfg_hnd->ops->tx_buf_put)
1216 cfg_hnd->ops->tx_buf_put(msm_host);
1222 * dsi_short_read1_resp: 1 parameter
1224 static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1226 u8 *data = msg->rx_buf;
1227 if (data && (msg->rx_len >= 1)) {
1228 *data = buf[1]; /* strip out dcs type */
1231 pr_err("%s: read data does not match with rx_buf len %zu\n",
1232 __func__, msg->rx_len);
1238 * dsi_short_read2_resp: 2 parameter
1240 static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1242 u8 *data = msg->rx_buf;
1243 if (data && (msg->rx_len >= 2)) {
1244 data[0] = buf[1]; /* strip out dcs type */
1248 pr_err("%s: read data does not match with rx_buf len %zu\n",
1249 __func__, msg->rx_len);
1254 static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg)
1256 /* strip out 4 byte dcs header */
1257 if (msg->rx_buf && msg->rx_len)
1258 memcpy(msg->rx_buf, buf + 4, msg->rx_len);
1263 int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1265 struct drm_device *dev = msm_host->dev;
1266 struct msm_drm_private *priv = dev->dev_private;
1271 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj,
1272 priv->kms->aspace, dma_base);
1275 int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base)
1280 *dma_base = msm_host->tx_buf_paddr;
1284 static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len)
1286 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1291 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base);
1293 pr_err("%s: failed to get iova: %d\n", __func__, ret);
1297 reinit_completion(&msm_host->dma_comp);
1299 dsi_wait4video_eng_busy(msm_host);
1301 triggered = msm_dsi_manager_cmd_xfer_trigger(
1302 msm_host->id, dma_base, len);
1304 ret = wait_for_completion_timeout(&msm_host->dma_comp,
1305 msecs_to_jiffies(200));
1317 static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host,
1318 u8 *buf, int rx_byte, int pkt_size)
1324 int repeated_bytes = 0;
1325 int buf_offset = buf - msm_host->rx_buf;
1328 cnt = (rx_byte + 3) >> 2;
1330 cnt = 4; /* 4 x 32 bits registers only */
1335 read_cnt = pkt_size + 6;
1338 * In case of multiple reads from the panel, after the first read, there
1339 * is possibility that there are some bytes in the payload repeating in
1340 * the RDBK_DATA registers. Since we read all the parameters from the
1341 * panel right from the first byte for every pass. We need to skip the
1342 * repeating bytes and then append the new parameters to the rx buffer.
1344 if (read_cnt > 16) {
1346 /* Any data more than 16 bytes will be shifted out.
1347 * The temp read buffer should already contain these bytes.
1348 * The remaining bytes in read buffer are the repeated bytes.
1350 bytes_shifted = read_cnt - 16;
1351 repeated_bytes = buf_offset - bytes_shifted;
1354 for (i = cnt - 1; i >= 0; i--) {
1355 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i));
1356 *temp++ = ntohl(data); /* to host byte order */
1357 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data));
1360 for (i = repeated_bytes; i < 16; i++)
1366 static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host,
1367 const struct mipi_dsi_msg *msg)
1370 int bllp_len = msm_host->mode->hdisplay *
1371 dsi_get_bpp(msm_host->format) / 8;
1373 len = dsi_cmd_dma_add(msm_host, msg);
1375 pr_err("%s: failed to add cmd type = 0x%x\n",
1376 __func__, msg->type);
1380 /* for video mode, do not send cmds more than
1381 * one pixel line, since it only transmit it
1384 /* TODO: if the command is sent in LP mode, the bit rate is only
1385 * half of esc clk rate. In this case, if the video is already
1386 * actively streaming, we need to check more carefully if the
1387 * command can be fit into one BLLP.
1389 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) {
1390 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n",
1395 ret = dsi_cmd_dma_tx(msm_host, len);
1397 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n",
1398 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret);
1400 } else if (ret < len) {
1401 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n",
1402 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len);
1409 static void dsi_err_worker(struct work_struct *work)
1411 struct msm_dsi_host *msm_host =
1412 container_of(work, struct msm_dsi_host, err_work);
1413 u32 status = msm_host->err_work_state;
1415 pr_err_ratelimited("%s: status=%x\n", __func__, status);
1416 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW)
1417 dsi_sw_reset(msm_host);
1419 /* It is safe to clear here because error irq is disabled. */
1420 msm_host->err_work_state = 0;
1422 /* enable dsi error interrupt */
1423 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1);
1426 static void dsi_ack_err_status(struct msm_dsi_host *msm_host)
1430 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS);
1433 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status);
1434 /* Writing of an extra 0 needed to clear error bits */
1435 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0);
1436 msm_host->err_work_state |= DSI_ERR_STATE_ACK;
1440 static void dsi_timeout_status(struct msm_dsi_host *msm_host)
1444 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS);
1447 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status);
1448 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT;
1452 static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host)
1456 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR);
1458 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC |
1459 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC |
1460 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL |
1461 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 |
1462 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) {
1463 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status);
1464 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY;
1468 static void dsi_fifo_status(struct msm_dsi_host *msm_host)
1472 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS);
1474 /* fifo underflow, overflow */
1476 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status);
1477 msm_host->err_work_state |= DSI_ERR_STATE_FIFO;
1478 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW)
1479 msm_host->err_work_state |=
1480 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW;
1484 static void dsi_status(struct msm_dsi_host *msm_host)
1488 status = dsi_read(msm_host, REG_DSI_STATUS0);
1490 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) {
1491 dsi_write(msm_host, REG_DSI_STATUS0, status);
1492 msm_host->err_work_state |=
1493 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION;
1497 static void dsi_clk_status(struct msm_dsi_host *msm_host)
1501 status = dsi_read(msm_host, REG_DSI_CLK_STATUS);
1503 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) {
1504 dsi_write(msm_host, REG_DSI_CLK_STATUS, status);
1505 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED;
1509 static void dsi_error(struct msm_dsi_host *msm_host)
1511 /* disable dsi error interrupt */
1512 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0);
1514 dsi_clk_status(msm_host);
1515 dsi_fifo_status(msm_host);
1516 dsi_ack_err_status(msm_host);
1517 dsi_timeout_status(msm_host);
1518 dsi_status(msm_host);
1519 dsi_dln0_phy_err(msm_host);
1521 queue_work(msm_host->workqueue, &msm_host->err_work);
1524 static irqreturn_t dsi_host_irq(int irq, void *ptr)
1526 struct msm_dsi_host *msm_host = ptr;
1528 unsigned long flags;
1530 if (!msm_host->ctrl_base)
1533 spin_lock_irqsave(&msm_host->intr_lock, flags);
1534 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL);
1535 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr);
1536 spin_unlock_irqrestore(&msm_host->intr_lock, flags);
1538 DBG("isr=0x%x, id=%d", isr, msm_host->id);
1540 if (isr & DSI_IRQ_ERROR)
1541 dsi_error(msm_host);
1543 if (isr & DSI_IRQ_VIDEO_DONE)
1544 complete(&msm_host->video_comp);
1546 if (isr & DSI_IRQ_CMD_DMA_DONE)
1547 complete(&msm_host->dma_comp);
1552 static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host,
1553 struct device *panel_device)
1555 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device,
1558 if (IS_ERR(msm_host->disp_en_gpio)) {
1559 DBG("cannot get disp-enable-gpios %ld",
1560 PTR_ERR(msm_host->disp_en_gpio));
1561 return PTR_ERR(msm_host->disp_en_gpio);
1564 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te",
1566 if (IS_ERR(msm_host->te_gpio)) {
1567 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio));
1568 return PTR_ERR(msm_host->te_gpio);
1574 static int dsi_host_attach(struct mipi_dsi_host *host,
1575 struct mipi_dsi_device *dsi)
1577 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1580 if (dsi->lanes > msm_host->num_data_lanes)
1583 msm_host->channel = dsi->channel;
1584 msm_host->lanes = dsi->lanes;
1585 msm_host->format = dsi->format;
1586 msm_host->mode_flags = dsi->mode_flags;
1588 msm_host->dsc = dsi->dsc;
1590 /* Some gpios defined in panel DT need to be controlled by host */
1591 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev);
1595 ret = dsi_dev_attach(msm_host->pdev);
1599 DBG("id=%d", msm_host->id);
1604 static int dsi_host_detach(struct mipi_dsi_host *host,
1605 struct mipi_dsi_device *dsi)
1607 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1609 dsi_dev_detach(msm_host->pdev);
1611 DBG("id=%d", msm_host->id);
1616 static ssize_t dsi_host_transfer(struct mipi_dsi_host *host,
1617 const struct mipi_dsi_msg *msg)
1619 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1622 if (!msg || !msm_host->power_on)
1625 mutex_lock(&msm_host->cmd_mutex);
1626 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg);
1627 mutex_unlock(&msm_host->cmd_mutex);
1632 static const struct mipi_dsi_host_ops dsi_host_ops = {
1633 .attach = dsi_host_attach,
1634 .detach = dsi_host_detach,
1635 .transfer = dsi_host_transfer,
1639 * List of supported physical to logical lane mappings.
1640 * For example, the 2nd entry represents the following mapping:
1642 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3;
1644 static const int supported_data_lane_swaps[][4] = {
1655 static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
1656 struct device_node *ep)
1658 struct device *dev = &msm_host->pdev->dev;
1659 struct property *prop;
1661 int ret, i, len, num_lanes;
1663 prop = of_find_property(ep, "data-lanes", &len);
1666 "failed to find data lane mapping, using default\n");
1667 /* Set the number of date lanes to 4 by default. */
1668 msm_host->num_data_lanes = 4;
1672 num_lanes = drm_of_get_data_lanes_count(ep, 1, 4);
1673 if (num_lanes < 0) {
1674 DRM_DEV_ERROR(dev, "bad number of data lanes\n");
1678 msm_host->num_data_lanes = num_lanes;
1680 ret = of_property_read_u32_array(ep, "data-lanes", lane_map,
1683 DRM_DEV_ERROR(dev, "failed to read lane data\n");
1688 * compare DT specified physical-logical lane mappings with the ones
1689 * supported by hardware
1691 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) {
1692 const int *swap = supported_data_lane_swaps[i];
1696 * the data-lanes array we get from DT has a logical->physical
1697 * mapping. The "data lane swap" register field represents
1698 * supported configurations in a physical->logical mapping.
1699 * Translate the DT mapping to what we understand and find a
1700 * configuration that works.
1702 for (j = 0; j < num_lanes; j++) {
1703 if (lane_map[j] < 0 || lane_map[j] > 3)
1704 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n",
1707 if (swap[lane_map[j]] != j)
1711 if (j == num_lanes) {
1712 msm_host->dlane_swap = i;
1720 static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc)
1724 if (dsc->bits_per_pixel & 0xf) {
1725 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n");
1729 if (dsc->bits_per_component != 8) {
1730 DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support bits_per_component != 8 yet\n");
1734 dsc->simple_422 = 0;
1735 dsc->convert_rgb = 1;
1736 dsc->vbr_enable = 0;
1738 drm_dsc_set_const_params(dsc);
1739 drm_dsc_set_rc_buf_thresh(dsc);
1741 /* handle only bpp = bpc = 8, pre-SCR panels */
1742 ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR);
1744 DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n");
1748 dsc->initial_scale_value = drm_dsc_initial_scale_value(dsc);
1749 dsc->line_buf_depth = dsc->bits_per_component + 1;
1751 return drm_dsc_compute_rc_parameters(dsc);
1754 static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
1756 struct device *dev = &msm_host->pdev->dev;
1757 struct device_node *np = dev->of_node;
1758 struct device_node *endpoint;
1762 * Get the endpoint of the output port of the DSI host. In our case,
1763 * this is mapped to port number with reg = 1. Don't return an error if
1764 * the remote endpoint isn't defined. It's possible that there is
1765 * nothing connected to the dsi output.
1767 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1769 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__);
1773 ret = dsi_host_parse_lane_data(msm_host, endpoint);
1775 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n",
1781 if (of_property_read_bool(np, "syscon-sfpb")) {
1782 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np,
1784 if (IS_ERR(msm_host->sfpb)) {
1785 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n",
1787 ret = PTR_ERR(msm_host->sfpb);
1792 of_node_put(endpoint);
1797 static int dsi_host_get_id(struct msm_dsi_host *msm_host)
1799 struct platform_device *pdev = msm_host->pdev;
1800 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg;
1801 struct resource *res;
1804 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl");
1808 for (i = 0; i < VARIANTS_MAX; i++)
1809 for (j = 0; j < DSI_MAX; j++)
1810 if (cfg->io_start[i][j] == res->start)
1816 int msm_dsi_host_init(struct msm_dsi *msm_dsi)
1818 struct msm_dsi_host *msm_host = NULL;
1819 struct platform_device *pdev = msm_dsi->pdev;
1820 const struct msm_dsi_config *cfg;
1823 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL);
1828 msm_host->pdev = pdev;
1829 msm_dsi->host = &msm_host->base;
1831 ret = dsi_host_parse_dt(msm_host);
1833 pr_err("%s: failed to parse dt\n", __func__);
1837 msm_host->ctrl_base = msm_ioremap_size(pdev, "dsi_ctrl", &msm_host->ctrl_size);
1838 if (IS_ERR(msm_host->ctrl_base)) {
1839 pr_err("%s: unable to map Dsi ctrl base\n", __func__);
1840 return PTR_ERR(msm_host->ctrl_base);
1843 pm_runtime_enable(&pdev->dev);
1845 msm_host->cfg_hnd = dsi_get_config(msm_host);
1846 if (!msm_host->cfg_hnd) {
1847 pr_err("%s: get config failed\n", __func__);
1850 cfg = msm_host->cfg_hnd->cfg;
1852 msm_host->id = dsi_host_get_id(msm_host);
1853 if (msm_host->id < 0) {
1854 pr_err("%s: unable to identify DSI host index\n", __func__);
1855 return msm_host->id;
1858 /* fixup base address by io offset */
1859 msm_host->ctrl_base += cfg->io_offset;
1861 ret = devm_regulator_bulk_get_const(&pdev->dev, cfg->num_regulators,
1862 cfg->regulator_data,
1863 &msm_host->supplies);
1867 ret = dsi_clk_init(msm_host);
1869 pr_err("%s: unable to initialize dsi clks\n", __func__);
1873 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL);
1874 if (!msm_host->rx_buf) {
1875 pr_err("%s: alloc rx temp buf failed\n", __func__);
1879 ret = devm_pm_opp_set_clkname(&pdev->dev, "byte");
1882 /* OPP table is optional */
1883 ret = devm_pm_opp_of_add_table(&pdev->dev);
1884 if (ret && ret != -ENODEV) {
1885 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1889 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1890 if (msm_host->irq < 0) {
1891 ret = msm_host->irq;
1892 dev_err(&pdev->dev, "failed to get irq: %d\n", ret);
1896 /* do not autoenable, will be enabled later */
1897 ret = devm_request_irq(&pdev->dev, msm_host->irq, dsi_host_irq,
1898 IRQF_TRIGGER_HIGH | IRQF_NO_AUTOEN,
1899 "dsi_isr", msm_host);
1901 dev_err(&pdev->dev, "failed to request IRQ%u: %d\n",
1902 msm_host->irq, ret);
1906 init_completion(&msm_host->dma_comp);
1907 init_completion(&msm_host->video_comp);
1908 mutex_init(&msm_host->dev_mutex);
1909 mutex_init(&msm_host->cmd_mutex);
1910 spin_lock_init(&msm_host->intr_lock);
1912 /* setup workqueue */
1913 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0);
1914 if (!msm_host->workqueue)
1917 INIT_WORK(&msm_host->err_work, dsi_err_worker);
1919 msm_dsi->id = msm_host->id;
1921 DBG("Dsi Host %d initialized", msm_host->id);
1925 void msm_dsi_host_destroy(struct mipi_dsi_host *host)
1927 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1930 dsi_tx_buf_free(msm_host);
1931 if (msm_host->workqueue) {
1932 destroy_workqueue(msm_host->workqueue);
1933 msm_host->workqueue = NULL;
1936 mutex_destroy(&msm_host->cmd_mutex);
1937 mutex_destroy(&msm_host->dev_mutex);
1939 pm_runtime_disable(&msm_host->pdev->dev);
1942 int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
1943 struct drm_device *dev)
1945 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1946 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1949 msm_host->dev = dev;
1951 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
1953 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
1960 int msm_dsi_host_register(struct mipi_dsi_host *host)
1962 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1965 /* Register mipi dsi host */
1966 if (!msm_host->registered) {
1967 host->dev = &msm_host->pdev->dev;
1968 host->ops = &dsi_host_ops;
1969 ret = mipi_dsi_host_register(host);
1973 msm_host->registered = true;
1979 void msm_dsi_host_unregister(struct mipi_dsi_host *host)
1981 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1983 if (msm_host->registered) {
1984 mipi_dsi_host_unregister(host);
1987 msm_host->registered = false;
1991 int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host,
1992 const struct mipi_dsi_msg *msg)
1994 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
1995 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
1997 /* TODO: make sure dsi_cmd_mdp is idle.
1998 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME
1999 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed.
2000 * How to handle the old versions? Wait for mdp cmd done?
2004 * mdss interrupt is generated in mdp core clock domain
2005 * mdp clock need to be enabled to receive dsi interrupt
2007 pm_runtime_get_sync(&msm_host->pdev->dev);
2008 cfg_hnd->ops->link_clk_set_rate(msm_host);
2009 cfg_hnd->ops->link_clk_enable(msm_host);
2011 /* TODO: vote for bus bandwidth */
2013 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2014 dsi_set_tx_power_mode(0, msm_host);
2016 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL);
2017 dsi_write(msm_host, REG_DSI_CTRL,
2018 msm_host->dma_cmd_ctrl_restore |
2019 DSI_CTRL_CMD_MODE_EN |
2021 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1);
2026 void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host,
2027 const struct mipi_dsi_msg *msg)
2029 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2030 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2032 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0);
2033 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore);
2035 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM))
2036 dsi_set_tx_power_mode(1, msm_host);
2038 /* TODO: unvote for bus bandwidth */
2040 cfg_hnd->ops->link_clk_disable(msm_host);
2041 pm_runtime_put(&msm_host->pdev->dev);
2044 int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host,
2045 const struct mipi_dsi_msg *msg)
2047 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2049 return dsi_cmds2buf_tx(msm_host, msg);
2052 int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host,
2053 const struct mipi_dsi_msg *msg)
2055 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2056 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2057 int data_byte, rx_byte, dlen, end;
2058 int short_response, diff, pkt_size, ret = 0;
2060 int rlen = msg->rx_len;
2069 data_byte = 10; /* first read */
2070 if (rlen < data_byte)
2073 pkt_size = data_byte;
2074 rx_byte = data_byte + 6; /* 4 header + 2 crc */
2077 buf = msm_host->rx_buf;
2080 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8};
2081 struct mipi_dsi_msg max_pkt_size_msg = {
2082 .channel = msg->channel,
2083 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE,
2088 DBG("rlen=%d pkt_size=%d rx_byte=%d",
2089 rlen, pkt_size, rx_byte);
2091 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg);
2093 pr_err("%s: Set max pkt size failed, %d\n",
2098 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) &&
2099 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) {
2100 /* Clear the RDBK_DATA registers */
2101 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL,
2102 DSI_RDBK_DATA_CTRL_CLR);
2103 wmb(); /* make sure the RDBK registers are cleared */
2104 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0);
2105 wmb(); /* release cleared status before transfer */
2108 ret = dsi_cmds2buf_tx(msm_host, msg);
2110 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret);
2112 } else if (ret < msg->tx_len) {
2113 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret);
2118 * once cmd_dma_done interrupt received,
2119 * return data from client is ready and stored
2120 * at RDBK_DATA register already
2121 * since rx fifo is 16 bytes, dcs header is kept at first loop,
2122 * after that dcs header lost during shift into registers
2124 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size);
2132 if (rlen <= data_byte) {
2133 diff = data_byte - rlen;
2141 dlen -= 2; /* 2 crc */
2143 buf += dlen; /* next start position */
2144 data_byte = 14; /* NOT first read */
2145 if (rlen < data_byte)
2148 pkt_size += data_byte;
2149 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff);
2154 * For single Long read, if the requested rlen < 10,
2155 * we need to shift the start position of rx
2156 * data buffer to skip the bytes which are not
2159 if (pkt_size < 10 && !short_response)
2160 buf = msm_host->rx_buf + (10 - rlen);
2162 buf = msm_host->rx_buf;
2166 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
2167 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__);
2170 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
2171 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
2172 ret = dsi_short_read1_resp(buf, msg);
2174 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
2175 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
2176 ret = dsi_short_read2_resp(buf, msg);
2178 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
2179 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
2180 ret = dsi_long_read_resp(buf, msg);
2183 pr_warn("%s:Invalid response cmd\n", __func__);
2190 void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base,
2193 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2195 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base);
2196 dsi_write(msm_host, REG_DSI_DMA_LEN, len);
2197 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1);
2199 /* Make sure trigger happens */
2203 void msm_dsi_host_set_phy_mode(struct mipi_dsi_host *host,
2204 struct msm_dsi_phy *src_phy)
2206 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2208 msm_host->cphy_mode = src_phy->cphy_mode;
2211 void msm_dsi_host_reset_phy(struct mipi_dsi_host *host)
2213 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2216 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET);
2217 /* Make sure fully reset */
2220 dsi_write(msm_host, REG_DSI_PHY_RESET, 0);
2224 void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host,
2225 struct msm_dsi_phy_clk_request *clk_req,
2228 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2229 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2232 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_bonded_dsi);
2234 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret);
2238 /* CPHY transmits 16 bits over 7 clock cycles
2239 * "byte_clk" is in units of 16-bits (see dsi_calc_pclk),
2240 * so multiply by 7 to get the "bitclk rate"
2242 if (msm_host->cphy_mode)
2243 clk_req->bitclk_rate = msm_host->byte_clk_rate * 7;
2245 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8;
2246 clk_req->escclk_rate = msm_host->esc_clk_rate;
2249 void msm_dsi_host_enable_irq(struct mipi_dsi_host *host)
2251 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2253 enable_irq(msm_host->irq);
2256 void msm_dsi_host_disable_irq(struct mipi_dsi_host *host)
2258 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2260 disable_irq(msm_host->irq);
2263 int msm_dsi_host_enable(struct mipi_dsi_host *host)
2265 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2267 dsi_op_mode_config(msm_host,
2268 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true);
2270 /* TODO: clock should be turned off for command mode,
2271 * and only turned on before MDP START.
2272 * This part of code should be enabled once mdp driver support it.
2274 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) {
2275 * dsi_link_clk_disable(msm_host);
2276 * pm_runtime_put(&msm_host->pdev->dev);
2279 msm_host->enabled = true;
2283 int msm_dsi_host_disable(struct mipi_dsi_host *host)
2285 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2287 msm_host->enabled = false;
2288 dsi_op_mode_config(msm_host,
2289 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false);
2291 /* Since we have disabled INTF, the video engine won't stop so that
2292 * the cmd engine will be blocked.
2293 * Reset to disable video engine so that we can send off cmd.
2295 dsi_sw_reset(msm_host);
2300 static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable)
2302 enum sfpb_ahb_arb_master_port_en en;
2304 if (!msm_host->sfpb)
2307 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE;
2309 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG,
2310 SFPB_GPREG_MASTER_PORT_EN__MASK,
2311 SFPB_GPREG_MASTER_PORT_EN(en));
2314 int msm_dsi_host_power_on(struct mipi_dsi_host *host,
2315 struct msm_dsi_phy_shared_timings *phy_shared_timings,
2316 bool is_bonded_dsi, struct msm_dsi_phy *phy)
2318 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2319 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2322 mutex_lock(&msm_host->dev_mutex);
2323 if (msm_host->power_on) {
2324 DBG("dsi host already on");
2328 msm_host->byte_intf_clk_rate = msm_host->byte_clk_rate;
2329 if (phy_shared_timings->byte_intf_clk_div_2)
2330 msm_host->byte_intf_clk_rate /= 2;
2332 msm_dsi_sfpb_config(msm_host, true);
2334 ret = regulator_bulk_enable(msm_host->cfg_hnd->cfg->num_regulators,
2335 msm_host->supplies);
2337 pr_err("%s:Failed to enable vregs.ret=%d\n",
2342 pm_runtime_get_sync(&msm_host->pdev->dev);
2343 ret = cfg_hnd->ops->link_clk_set_rate(msm_host);
2345 ret = cfg_hnd->ops->link_clk_enable(msm_host);
2347 pr_err("%s: failed to enable link clocks. ret=%d\n",
2349 goto fail_disable_reg;
2352 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev);
2354 pr_err("%s: failed to set pinctrl default state, %d\n",
2356 goto fail_disable_clk;
2359 dsi_timing_setup(msm_host, is_bonded_dsi);
2360 dsi_sw_reset(msm_host);
2361 dsi_ctrl_enable(msm_host, phy_shared_timings, phy);
2363 if (msm_host->disp_en_gpio)
2364 gpiod_set_value(msm_host->disp_en_gpio, 1);
2366 msm_host->power_on = true;
2367 mutex_unlock(&msm_host->dev_mutex);
2372 cfg_hnd->ops->link_clk_disable(msm_host);
2373 pm_runtime_put(&msm_host->pdev->dev);
2375 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2376 msm_host->supplies);
2378 mutex_unlock(&msm_host->dev_mutex);
2382 int msm_dsi_host_power_off(struct mipi_dsi_host *host)
2384 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2385 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
2387 mutex_lock(&msm_host->dev_mutex);
2388 if (!msm_host->power_on) {
2389 DBG("dsi host already off");
2393 dsi_ctrl_disable(msm_host);
2395 if (msm_host->disp_en_gpio)
2396 gpiod_set_value(msm_host->disp_en_gpio, 0);
2398 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev);
2400 cfg_hnd->ops->link_clk_disable(msm_host);
2401 pm_runtime_put(&msm_host->pdev->dev);
2403 regulator_bulk_disable(msm_host->cfg_hnd->cfg->num_regulators,
2404 msm_host->supplies);
2406 msm_dsi_sfpb_config(msm_host, false);
2410 msm_host->power_on = false;
2413 mutex_unlock(&msm_host->dev_mutex);
2417 int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
2418 const struct drm_display_mode *mode)
2420 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2422 if (msm_host->mode) {
2423 drm_mode_destroy(msm_host->dev, msm_host->mode);
2424 msm_host->mode = NULL;
2427 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode);
2428 if (!msm_host->mode) {
2429 pr_err("%s: cannot duplicate mode\n", __func__);
2436 enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
2437 const struct drm_display_mode *mode)
2439 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2440 struct drm_dsc_config *dsc = msm_host->dsc;
2441 int pic_width = mode->hdisplay;
2442 int pic_height = mode->vdisplay;
2447 if (pic_width % dsc->slice_width) {
2448 pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
2449 pic_width, dsc->slice_width);
2450 return MODE_H_ILLEGAL;
2453 if (pic_height % dsc->slice_height) {
2454 pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
2455 pic_height, dsc->slice_height);
2456 return MODE_V_ILLEGAL;
2462 unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host)
2464 return to_msm_dsi_host(host)->mode_flags;
2467 void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host)
2469 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2471 pm_runtime_get_sync(&msm_host->pdev->dev);
2473 msm_disp_snapshot_add_block(disp_state, msm_host->ctrl_size,
2474 msm_host->ctrl_base, "dsi%d_ctrl", msm_host->id);
2476 pm_runtime_put_sync(&msm_host->pdev->dev);
2479 static void msm_dsi_host_video_test_pattern_setup(struct msm_dsi_host *msm_host)
2483 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2485 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_VIDEO_INIT_VAL, 0xff);
2486 /* draw checkered rectangle pattern */
2487 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL,
2488 DSI_TPG_MAIN_CONTROL_CHECKERED_RECTANGLE_PATTERN);
2489 /* use 24-bit RGB test pttern */
2490 dsi_write(msm_host, REG_DSI_TPG_VIDEO_CONFIG,
2491 DSI_TPG_VIDEO_CONFIG_BPP(VIDEO_CONFIG_24BPP) |
2492 DSI_TPG_VIDEO_CONFIG_RGB);
2494 reg |= DSI_TEST_PATTERN_GEN_CTRL_VIDEO_PATTERN_SEL(VID_MDSS_GENERAL_PATTERN);
2495 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2497 DBG("Video test pattern setup done\n");
2500 static void msm_dsi_host_cmd_test_pattern_setup(struct msm_dsi_host *msm_host)
2504 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2506 /* initial value for test pattern */
2507 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_MDP_INIT_VAL0, 0xff);
2509 reg |= DSI_TEST_PATTERN_GEN_CTRL_CMD_MDP_STREAM0_PATTERN_SEL(CMD_MDP_MDSS_GENERAL_PATTERN);
2511 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, reg);
2512 /* draw checkered rectangle pattern */
2513 dsi_write(msm_host, REG_DSI_TPG_MAIN_CONTROL2,
2514 DSI_TPG_MAIN_CONTROL2_CMD_MDP0_CHECKERED_RECTANGLE_PATTERN);
2516 DBG("Cmd test pattern setup done\n");
2519 void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
2521 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2522 bool is_video_mode = !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO);
2526 msm_dsi_host_video_test_pattern_setup(msm_host);
2528 msm_dsi_host_cmd_test_pattern_setup(msm_host);
2530 reg = dsi_read(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL);
2531 /* enable the test pattern generator */
2532 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CTRL, (reg | DSI_TEST_PATTERN_GEN_CTRL_EN));
2534 /* for command mode need to trigger one frame from tpg */
2536 dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
2537 DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
2540 struct drm_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
2542 struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
2544 return msm_host->dsc;