drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   5  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
   6  *
   7  * Author: Rob Clark <robdclark@gmail.com>
   8  */
   9
  10 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  11
  12 #include <linux/debugfs.h>
  13 #include <linux/dma-buf.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/pm_opp.h>
  16
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_file.h>
  19 #include <drm/drm_framebuffer.h>
  20 #include <drm/drm_vblank.h>
  21 #include <drm/drm_writeback.h>
  22
  23 #include "msm_drv.h"
  24 #include "msm_mmu.h"
  25 #include "msm_gem.h"
  26 #include "disp/msm_disp_snapshot.h"
  27
  28 #include "dpu_core_irq.h"
  29 #include "dpu_crtc.h"
  30 #include "dpu_encoder.h"
  31 #include "dpu_formats.h"
  32 #include "dpu_hw_vbif.h"
  33 #include "dpu_kms.h"
  34 #include "dpu_plane.h"
  35 #include "dpu_vbif.h"
  36 #include "dpu_writeback.h"
  37
  38 #define CREATE_TRACE_POINTS
  39 #include "dpu_trace.h"
  40
  41 /*
  42  * To enable overall DRM driver logging
  43  * # echo 0x2 > /sys/module/drm/parameters/debug
  44  *
  45  * To enable DRM driver h/w logging
  46  * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  47  *
  48  * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
  49  */
  50 #define DPU_DEBUGFS_DIR "msm_dpu"
  51 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
  52
  53 static int dpu_kms_hw_init(struct msm_kms *kms);
  54 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
  55
  56 #ifdef CONFIG_DEBUG_FS
  57 static int _dpu_danger_signal_status(struct seq_file *s,
  58                 bool danger_status)
  59 {
  60         struct dpu_danger_safe_status status;
  61         struct dpu_kms *kms = s->private;
  62         int i;
  63
  64         if (!kms->hw_mdp) {
  65                 DPU_ERROR("invalid arg(s)\n");
  66                 return 0;
  67         }
  68
  69         memset(&status, 0, sizeof(struct dpu_danger_safe_status));
  70
  71         pm_runtime_get_sync(&kms->pdev->dev);
  72         if (danger_status) {
  73                 seq_puts(s, "\nDanger signal status:\n");
  74                 if (kms->hw_mdp->ops.get_danger_status)
  75                         kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
  76                                         &status);
  77         } else {
  78                 seq_puts(s, "\nSafe signal status:\n");
  79                 if (kms->hw_mdp->ops.get_safe_status)
  80                         kms->hw_mdp->ops.get_safe_status(kms->hw_mdp,
  81                                         &status);
  82         }
  83         pm_runtime_put_sync(&kms->pdev->dev);
  84
  85         seq_printf(s, "MDP     :  0x%x\n", status.mdp);
  86
  87         for (i = SSPP_VIG0; i < SSPP_MAX; i++)
  88                 seq_printf(s, "SSPP%d   :  0x%x  \n", i - SSPP_VIG0,
  89                                 status.sspp[i]);
  90         seq_puts(s, "\n");
  91
  92         return 0;
  93 }
  94
  95 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
  96 {
  97         return _dpu_danger_signal_status(s, true);
  98 }
  99 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
 100
 101 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
 102 {
 103         return _dpu_danger_signal_status(s, false);
 104 }
 105 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
 106
 107 static ssize_t _dpu_plane_danger_read(struct file *file,
 108                         char __user *buff, size_t count, loff_t *ppos)
 109 {
 110         struct dpu_kms *kms = file->private_data;
 111         int len;
 112         char buf[40];
 113
 114         len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
 115
 116         return simple_read_from_buffer(buff, count, ppos, buf, len);
 117 }
 118
 119 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
 120 {
 121         struct drm_plane *plane;
 122
 123         drm_for_each_plane(plane, kms->dev) {
 124                 if (plane->fb && plane->state) {
 125                         dpu_plane_danger_signal_ctrl(plane, enable);
 126                         DPU_DEBUG("plane:%d img:%dx%d ",
 127                                 plane->base.id, plane->fb->width,
 128                                 plane->fb->height);
 129                         DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
 130                                 plane->state->src_x >> 16,
 131                                 plane->state->src_y >> 16,
 132                                 plane->state->src_w >> 16,
 133                                 plane->state->src_h >> 16,
 134                                 plane->state->crtc_x, plane->state->crtc_y,
 135                                 plane->state->crtc_w, plane->state->crtc_h);
 136                 } else {
 137                         DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
 138                 }
 139         }
 140 }
 141
 142 static ssize_t _dpu_plane_danger_write(struct file *file,
 143                     const char __user *user_buf, size_t count, loff_t *ppos)
 144 {
 145         struct dpu_kms *kms = file->private_data;
 146         int disable_panic;
 147         int ret;
 148
 149         ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
 150         if (ret)
 151                 return ret;
 152
 153         if (disable_panic) {
 154                 /* Disable panic signal for all active pipes */
 155                 DPU_DEBUG("Disabling danger:\n");
 156                 _dpu_plane_set_danger_state(kms, false);
 157                 kms->has_danger_ctrl = false;
 158         } else {
 159                 /* Enable panic signal for all active pipes */
 160                 DPU_DEBUG("Enabling danger:\n");
 161                 kms->has_danger_ctrl = true;
 162                 _dpu_plane_set_danger_state(kms, true);
 163         }
 164
 165         return count;
 166 }
 167
 168 static const struct file_operations dpu_plane_danger_enable = {
 169         .open = simple_open,
 170         .read = _dpu_plane_danger_read,
 171         .write = _dpu_plane_danger_write,
 172 };
 173
 174 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
 175                 struct dentry *parent)
 176 {
 177         struct dentry *entry = debugfs_create_dir("danger", parent);
 178
 179         debugfs_create_file("danger_status", 0600, entry,
 180                         dpu_kms, &dpu_debugfs_danger_stats_fops);
 181         debugfs_create_file("safe_status", 0600, entry,
 182                         dpu_kms, &dpu_debugfs_safe_stats_fops);
 183         debugfs_create_file("disable_danger", 0600, entry,
 184                         dpu_kms, &dpu_plane_danger_enable);
 185
 186 }
 187
 188 /*
 189  * Companion structure for dpu_debugfs_create_regset32.
 190  */
 191 struct dpu_debugfs_regset32 {
 192         uint32_t offset;
 193         uint32_t blk_len;
 194         struct dpu_kms *dpu_kms;
 195 };
 196
 197 static int dpu_regset32_show(struct seq_file *s, void *data)
 198 {
 199         struct dpu_debugfs_regset32 *regset = s->private;
 200         struct dpu_kms *dpu_kms = regset->dpu_kms;
 201         void __iomem *base;
 202         uint32_t i, addr;
 203
 204         if (!dpu_kms->mmio)
 205                 return 0;
 206
 207         base = dpu_kms->mmio + regset->offset;
 208
 209         /* insert padding spaces, if needed */
 210         if (regset->offset & 0xF) {
 211                 seq_printf(s, "[%x]", regset->offset & ~0xF);
 212                 for (i = 0; i < (regset->offset & 0xF); i += 4)
 213                         seq_puts(s, "         ");
 214         }
 215
 216         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 217
 218         /* main register output */
 219         for (i = 0; i < regset->blk_len; i += 4) {
 220                 addr = regset->offset + i;
 221                 if ((addr & 0xF) == 0x0)
 222                         seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
 223                 seq_printf(s, " %08x", readl_relaxed(base + i));
 224         }
 225         seq_puts(s, "\n");
 226         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 227
 228         return 0;
 229 }
 230 DEFINE_SHOW_ATTRIBUTE(dpu_regset32);
 231
 232 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
 233                 void *parent,
 234                 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
 235 {
 236         struct dpu_debugfs_regset32 *regset;
 237
 238         if (WARN_ON(!name || !dpu_kms || !length))
 239                 return;
 240
 241         regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL);
 242         if (!regset)
 243                 return;
 244
 245         /* make sure offset is a multiple of 4 */
 246         regset->offset = round_down(offset, 4);
 247         regset->blk_len = length;
 248         regset->dpu_kms = dpu_kms;
 249
 250         debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
 251 }
 252
 253 static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
 254 {
 255         struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
 256         int i;
 257
 258         if (IS_ERR(entry))
 259                 return;
 260
 261         for (i = SSPP_NONE; i < SSPP_MAX; i++) {
 262                 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);
 263
 264                 if (!hw)
 265                         continue;
 266
 267                 _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);
 268         }
 269 }
 270
 271 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
 272 {
 273         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 274         void *p = dpu_hw_util_get_log_mask_ptr();
 275         struct dentry *entry;
 276         struct drm_device *dev;
 277         struct msm_drm_private *priv;
 278         int i;
 279
 280         if (!p)
 281                 return -EINVAL;
 282
 283         /* Only create a set of debugfs for the primary node, ignore render nodes */
 284         if (minor->type != DRM_MINOR_PRIMARY)
 285                 return 0;
 286
 287         dev = dpu_kms->dev;
 288         priv = dev->dev_private;
 289
 290         entry = debugfs_create_dir("debug", minor->debugfs_root);
 291
 292         debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
 293
 294         dpu_debugfs_danger_init(dpu_kms, entry);
 295         dpu_debugfs_vbif_init(dpu_kms, entry);
 296         dpu_debugfs_core_irq_init(dpu_kms, entry);
 297         dpu_debugfs_sspp_init(dpu_kms, entry);
 298
 299         for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
 300                 if (priv->dp[i])
 301                         msm_dp_debugfs_init(priv->dp[i], minor);
 302         }
 303
 304         return dpu_core_perf_debugfs_init(dpu_kms, entry);
 305 }
 306 #endif
 307
 308 /* Global/shared object state funcs */
 309
 310 /*
 311  * This is a helper that returns the private state currently in operation.
 312  * Note that this would return the "old_state" if called in the atomic check
 313  * path, and the "new_state" after the atomic swap has been done.
 314  */
 315 struct dpu_global_state *
 316 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
 317 {
 318         return to_dpu_global_state(dpu_kms->global_state.state);
 319 }
 320
 321 /*
 322  * This acquires the modeset lock set aside for global state, creates
 323  * a new duplicated private object state.
 324  */
 325 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
 326 {
 327         struct msm_drm_private *priv = s->dev->dev_private;
 328         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
 329         struct drm_private_state *priv_state;
 330         int ret;
 331
 332         ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
 333         if (ret)
 334                 return ERR_PTR(ret);
 335
 336         priv_state = drm_atomic_get_private_obj_state(s,
 337                                                 &dpu_kms->global_state);
 338         if (IS_ERR(priv_state))
 339                 return ERR_CAST(priv_state);
 340
 341         return to_dpu_global_state(priv_state);
 342 }
 343
 344 static struct drm_private_state *
 345 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
 346 {
 347         struct dpu_global_state *state;
 348
 349         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 350         if (!state)
 351                 return NULL;
 352
 353         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 354
 355         return &state->base;
 356 }
 357
 358 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
 359                                       struct drm_private_state *state)
 360 {
 361         struct dpu_global_state *dpu_state = to_dpu_global_state(state);
 362
 363         kfree(dpu_state);
 364 }
 365
 366 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
 367         .atomic_duplicate_state = dpu_kms_global_duplicate_state,
 368         .atomic_destroy_state = dpu_kms_global_destroy_state,
 369 };
 370
 371 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
 372 {
 373         struct dpu_global_state *state;
 374
 375         drm_modeset_lock_init(&dpu_kms->global_state_lock);
 376
 377         state = kzalloc(sizeof(*state), GFP_KERNEL);
 378         if (!state)
 379                 return -ENOMEM;
 380
 381         drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
 382                                     &state->base,
 383                                     &dpu_kms_global_state_funcs);
 384         return 0;
 385 }
 386
 387 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
 388 {
 389         struct icc_path *path0;
 390         struct icc_path *path1;
 391         struct drm_device *dev = dpu_kms->dev;
 392         struct device *dpu_dev = dev->dev;
 393
 394         path0 = msm_icc_get(dpu_dev, "mdp0-mem");
 395         path1 = msm_icc_get(dpu_dev, "mdp1-mem");
 396
 397         if (IS_ERR_OR_NULL(path0))
 398                 return PTR_ERR_OR_ZERO(path0);
 399
 400         dpu_kms->path[0] = path0;
 401         dpu_kms->num_paths = 1;
 402
 403         if (!IS_ERR_OR_NULL(path1)) {
 404                 dpu_kms->path[1] = path1;
 405                 dpu_kms->num_paths++;
 406         }
 407         return 0;
 408 }
 409
 410 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 411 {
 412         return dpu_crtc_vblank(crtc, true);
 413 }
 414
 415 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 416 {
 417         dpu_crtc_vblank(crtc, false);
 418 }
 419
 420 static void dpu_kms_enable_commit(struct msm_kms *kms)
 421 {
 422         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 423         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 424 }
 425
 426 static void dpu_kms_disable_commit(struct msm_kms *kms)
 427 {
 428         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 429         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 430 }
 431
 432 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
 433 {
 434         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 435         struct drm_crtc *crtc;
 436
 437         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
 438                 if (!crtc->state->active)
 439                         continue;
 440
 441                 trace_dpu_kms_commit(DRMID(crtc));
 442                 dpu_crtc_commit_kickoff(crtc);
 443         }
 444 }
 445
 446 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
 447 {
 448         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 449         struct drm_crtc *crtc;
 450
 451         DPU_ATRACE_BEGIN("kms_complete_commit");
 452
 453         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
 454                 dpu_crtc_complete_commit(crtc);
 455
 456         DPU_ATRACE_END("kms_complete_commit");
 457 }
 458
 459 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
 460                 struct drm_crtc *crtc)
 461 {
 462         struct drm_encoder *encoder;
 463         struct drm_device *dev;
 464         int ret;
 465
 466         if (!kms || !crtc || !crtc->state) {
 467                 DPU_ERROR("invalid params\n");
 468                 return;
 469         }
 470
 471         dev = crtc->dev;
 472
 473         if (!crtc->state->enable) {
 474                 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
 475                 return;
 476         }
 477
 478         if (!drm_atomic_crtc_effectively_active(crtc->state)) {
 479                 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
 480                 return;
 481         }
 482
 483         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 484                 if (encoder->crtc != crtc)
 485                         continue;
 486                 /*
 487                  * Wait for post-flush if necessary to delay before
 488                  * plane_cleanup. For example, wait for vsync in case of video
 489                  * mode panels. This may be a no-op for command mode panels.
 490                  */
 491                 trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
 492                 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
 493                 if (ret && ret != -EWOULDBLOCK) {
 494                         DPU_ERROR("wait for commit done returned %d\n", ret);
 495                         break;
 496                 }
 497         }
 498 }
 499
 500 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
 501 {
 502         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 503         struct drm_crtc *crtc;
 504
 505         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
 506                 dpu_kms_wait_for_commit_done(kms, crtc);
 507 }
 508
 509 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
 510                                     struct msm_drm_private *priv,
 511                                     struct dpu_kms *dpu_kms)
 512 {
 513         struct drm_encoder *encoder = NULL;
 514         struct msm_display_info info;
 515         int i, rc = 0;
 516
 517         if (!(priv->dsi[0] || priv->dsi[1]))
 518                 return rc;
 519
 520         /*
 521          * We support following confiurations:
 522          * - Single DSI host (dsi0 or dsi1)
 523          * - Two independent DSI hosts
 524          * - Bonded DSI0 and DSI1 hosts
 525          *
 526          * TODO: Support swapping DSI0 and DSI1 in the bonded setup.
 527          */
 528         for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
 529                 int other = (i + 1) % 2;
 530
 531                 if (!priv->dsi[i])
 532                         continue;
 533
 534                 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) &&
 535                     !msm_dsi_is_master_dsi(priv->dsi[i]))
 536                         continue;
 537
 538                 memset(&info, 0, sizeof(info));
 539                 info.intf_type = INTF_DSI;
 540
 541                 info.h_tile_instance[info.num_of_h_tiles++] = i;
 542                 if (msm_dsi_is_bonded_dsi(priv->dsi[i]))
 543                         info.h_tile_instance[info.num_of_h_tiles++] = other;
 544
 545                 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
 546
 547                 info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
 548
 549                 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI, &info);
 550                 if (IS_ERR(encoder)) {
 551                         DPU_ERROR("encoder init failed for dsi display\n");
 552                         return PTR_ERR(encoder);
 553                 }
 554
 555                 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
 556                 if (rc) {
 557                         DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
 558                                 i, rc);
 559                         break;
 560                 }
 561
 562                 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
 563                         rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
 564                         if (rc) {
 565                                 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
 566                                         other, rc);
 567                                 break;
 568                         }
 569                 }
 570         }
 571
 572         return rc;
 573 }
 574
 575 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
 576                                             struct msm_drm_private *priv,
 577                                             struct dpu_kms *dpu_kms)
 578 {
 579         struct drm_encoder *encoder = NULL;
 580         struct msm_display_info info;
 581         int rc;
 582         int i;
 583
 584         for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
 585                 if (!priv->dp[i])
 586                         continue;
 587
 588                 memset(&info, 0, sizeof(info));
 589                 info.num_of_h_tiles = 1;
 590                 info.h_tile_instance[0] = i;
 591                 info.intf_type = INTF_DP;
 592
 593                 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
 594                 if (IS_ERR(encoder)) {
 595                         DPU_ERROR("encoder init failed for dsi display\n");
 596                         return PTR_ERR(encoder);
 597                 }
 598
 599                 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder);
 600                 if (rc) {
 601                         DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
 602                         drm_encoder_cleanup(encoder);
 603                         return rc;
 604                 }
 605         }
 606
 607         return 0;
 608 }
 609
 610 static int _dpu_kms_initialize_hdmi(struct drm_device *dev,
 611                                     struct msm_drm_private *priv,
 612                                     struct dpu_kms *dpu_kms)
 613 {
 614         struct drm_encoder *encoder = NULL;
 615         struct msm_display_info info;
 616         int rc;
 617
 618         if (!priv->hdmi)
 619                 return 0;
 620
 621         memset(&info, 0, sizeof(info));
 622         info.num_of_h_tiles = 1;
 623         info.h_tile_instance[0] = 0;
 624         info.intf_type = INTF_HDMI;
 625
 626         encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS, &info);
 627         if (IS_ERR(encoder)) {
 628                 DPU_ERROR("encoder init failed for HDMI display\n");
 629                 return PTR_ERR(encoder);
 630         }
 631
 632         rc = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
 633         if (rc) {
 634                 DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
 635                 drm_encoder_cleanup(encoder);
 636                 return rc;
 637         }
 638
 639         return 0;
 640 }
 641
 642 static int _dpu_kms_initialize_writeback(struct drm_device *dev,
 643                 struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
 644                 const u32 *wb_formats, int n_formats)
 645 {
 646         struct drm_encoder *encoder = NULL;
 647         struct msm_display_info info;
 648         int rc;
 649
 650         memset(&info, 0, sizeof(info));
 651
 652         info.num_of_h_tiles = 1;
 653         /* use only WB idx 2 instance for DPU */
 654         info.h_tile_instance[0] = WB_2;
 655         info.intf_type = INTF_WB;
 656
 657         encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info);
 658         if (IS_ERR(encoder)) {
 659                 DPU_ERROR("encoder init failed for dsi display\n");
 660                 return PTR_ERR(encoder);
 661         }
 662
 663         rc = dpu_writeback_init(dev, encoder, wb_formats,
 664                         n_formats);
 665         if (rc) {
 666                 DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);
 667                 drm_encoder_cleanup(encoder);
 668                 return rc;
 669         }
 670
 671         return 0;
 672 }
 673
 674 /**
 675  * _dpu_kms_setup_displays - create encoders, bridges and connectors
 676  *                           for underlying displays
 677  * @dev:        Pointer to drm device structure
 678  * @priv:       Pointer to private drm device data
 679  * @dpu_kms:    Pointer to dpu kms structure
 680  * Returns:     Zero on success
 681  */
 682 static int _dpu_kms_setup_displays(struct drm_device *dev,
 683                                     struct msm_drm_private *priv,
 684                                     struct dpu_kms *dpu_kms)
 685 {
 686         int rc = 0;
 687         int i;
 688
 689         rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
 690         if (rc) {
 691                 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
 692                 return rc;
 693         }
 694
 695         rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
 696         if (rc) {
 697                 DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
 698                 return rc;
 699         }
 700
 701         rc = _dpu_kms_initialize_hdmi(dev, priv, dpu_kms);
 702         if (rc) {
 703                 DPU_ERROR("initialize HDMI failed, rc = %d\n", rc);
 704                 return rc;
 705         }
 706
 707         /* Since WB isn't a driver check the catalog before initializing */
 708         if (dpu_kms->catalog->wb_count) {
 709                 for (i = 0; i < dpu_kms->catalog->wb_count; i++) {
 710                         if (dpu_kms->catalog->wb[i].id == WB_2) {
 711                                 rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms,
 712                                                 dpu_kms->catalog->wb[i].format_list,
 713                                                 dpu_kms->catalog->wb[i].num_formats);
 714                                 if (rc) {
 715                                         DPU_ERROR("initialize_WB failed, rc = %d\n", rc);
 716                                         return rc;
 717                                 }
 718                         }
 719                 }
 720         }
 721
 722         return rc;
 723 }
 724
 725 #define MAX_PLANES 20
 726 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 727 {
 728         struct drm_device *dev;
 729         struct drm_plane *primary_planes[MAX_PLANES], *plane;
 730         struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
 731         struct drm_crtc *crtc;
 732         struct drm_encoder *encoder;
 733         unsigned int num_encoders;
 734
 735         struct msm_drm_private *priv;
 736         const struct dpu_mdss_cfg *catalog;
 737
 738         int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
 739         int max_crtc_count;
 740         dev = dpu_kms->dev;
 741         priv = dev->dev_private;
 742         catalog = dpu_kms->catalog;
 743
 744         /*
 745          * Create encoder and query display drivers to create
 746          * bridges and connectors
 747          */
 748         ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
 749         if (ret)
 750                 return ret;
 751
 752         num_encoders = 0;
 753         drm_for_each_encoder(encoder, dev)
 754                 num_encoders++;
 755
 756         max_crtc_count = min(catalog->mixer_count, num_encoders);
 757
 758         /* Create the planes, keeping track of one primary/cursor per crtc */
 759         for (i = 0; i < catalog->sspp_count; i++) {
 760                 enum drm_plane_type type;
 761
 762                 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
 763                         && cursor_planes_idx < max_crtc_count)
 764                         type = DRM_PLANE_TYPE_CURSOR;
 765                 else if (primary_planes_idx < max_crtc_count)
 766                         type = DRM_PLANE_TYPE_PRIMARY;
 767                 else
 768                         type = DRM_PLANE_TYPE_OVERLAY;
 769
 770                 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
 771                           type, catalog->sspp[i].features,
 772                           catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
 773
 774                 plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
 775                                        (1UL << max_crtc_count) - 1);
 776                 if (IS_ERR(plane)) {
 777                         DPU_ERROR("dpu_plane_init failed\n");
 778                         ret = PTR_ERR(plane);
 779                         return ret;
 780                 }
 781
 782                 if (type == DRM_PLANE_TYPE_CURSOR)
 783                         cursor_planes[cursor_planes_idx++] = plane;
 784                 else if (type == DRM_PLANE_TYPE_PRIMARY)
 785                         primary_planes[primary_planes_idx++] = plane;
 786         }
 787
 788         max_crtc_count = min(max_crtc_count, primary_planes_idx);
 789
 790         /* Create one CRTC per encoder */
 791         for (i = 0; i < max_crtc_count; i++) {
 792                 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
 793                 if (IS_ERR(crtc)) {
 794                         ret = PTR_ERR(crtc);
 795                         return ret;
 796                 }
 797                 priv->crtcs[priv->num_crtcs++] = crtc;
 798         }
 799
 800         /* All CRTCs are compatible with all encoders */
 801         drm_for_each_encoder(encoder, dev)
 802                 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
 803
 804         return 0;
 805 }
 806
 807 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
 808 {
 809         int i;
 810
 811         if (dpu_kms->hw_intr)
 812                 dpu_hw_intr_destroy(dpu_kms->hw_intr);
 813         dpu_kms->hw_intr = NULL;
 814
 815         /* safe to call these more than once during shutdown */
 816         _dpu_kms_mmu_destroy(dpu_kms);
 817
 818         if (dpu_kms->catalog) {
 819                 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
 820                         if (dpu_kms->hw_vbif[i]) {
 821                                 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[i]);
 822                                 dpu_kms->hw_vbif[i] = NULL;
 823                         }
 824                 }
 825         }
 826
 827         if (dpu_kms->rm_init)
 828                 dpu_rm_destroy(&dpu_kms->rm);
 829         dpu_kms->rm_init = false;
 830
 831         dpu_kms->catalog = NULL;
 832
 833         if (dpu_kms->vbif[VBIF_NRT])
 834                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
 835         dpu_kms->vbif[VBIF_NRT] = NULL;
 836
 837         if (dpu_kms->vbif[VBIF_RT])
 838                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
 839         dpu_kms->vbif[VBIF_RT] = NULL;
 840
 841         if (dpu_kms->hw_mdp)
 842                 dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
 843         dpu_kms->hw_mdp = NULL;
 844
 845         if (dpu_kms->mmio)
 846                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
 847         dpu_kms->mmio = NULL;
 848 }
 849
 850 static void dpu_kms_destroy(struct msm_kms *kms)
 851 {
 852         struct dpu_kms *dpu_kms;
 853
 854         if (!kms) {
 855                 DPU_ERROR("invalid kms\n");
 856                 return;
 857         }
 858
 859         dpu_kms = to_dpu_kms(kms);
 860
 861         _dpu_kms_hw_destroy(dpu_kms);
 862
 863         msm_kms_destroy(&dpu_kms->base);
 864
 865         if (dpu_kms->rpm_enabled)
 866                 pm_runtime_disable(&dpu_kms->pdev->dev);
 867 }
 868
 869 static int dpu_irq_postinstall(struct msm_kms *kms)
 870 {
 871         struct msm_drm_private *priv;
 872         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 873         int i;
 874
 875         if (!dpu_kms || !dpu_kms->dev)
 876                 return -EINVAL;
 877
 878         priv = dpu_kms->dev->dev_private;
 879         if (!priv)
 880                 return -EINVAL;
 881
 882         for (i = 0; i < ARRAY_SIZE(priv->dp); i++)
 883                 msm_dp_irq_postinstall(priv->dp[i]);
 884
 885         return 0;
 886 }
 887
 888 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
 889 {
 890         int i;
 891         struct dpu_kms *dpu_kms;
 892         const struct dpu_mdss_cfg *cat;
 893
 894         dpu_kms = to_dpu_kms(kms);
 895
 896         cat = dpu_kms->catalog;
 897
 898         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 899
 900         /* dump CTL sub-blocks HW regs info */
 901         for (i = 0; i < cat->ctl_count; i++)
 902                 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
 903                                 dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
 904
 905         /* dump DSPP sub-blocks HW regs info */
 906         for (i = 0; i < cat->dspp_count; i++)
 907                 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
 908                                 dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
 909
 910         /* dump INTF sub-blocks HW regs info */
 911         for (i = 0; i < cat->intf_count; i++)
 912                 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
 913                                 dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
 914
 915         /* dump PP sub-blocks HW regs info */
 916         for (i = 0; i < cat->pingpong_count; i++)
 917                 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
 918                                 dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
 919
 920         /* dump SSPP sub-blocks HW regs info */
 921         for (i = 0; i < cat->sspp_count; i++)
 922                 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
 923                                 dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
 924
 925         /* dump LM sub-blocks HW regs info */
 926         for (i = 0; i < cat->mixer_count; i++)
 927                 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
 928                                 dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i);
 929
 930         /* dump WB sub-blocks HW regs info */
 931         for (i = 0; i < cat->wb_count; i++)
 932                 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
 933                                 dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
 934
 935         if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
 936                 msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
 937                                 dpu_kms->mmio + cat->mdp[0].base, "top");
 938                 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
 939                                 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2");
 940         } else {
 941                 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
 942                                 dpu_kms->mmio + cat->mdp[0].base, "top");
 943         }
 944
 945         /* dump DSC sub-blocks HW regs info */
 946         for (i = 0; i < cat->dsc_count; i++)
 947                 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len,
 948                                 dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i);
 949
 950         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 951 }
 952
 953 static const struct msm_kms_funcs kms_funcs = {
 954         .hw_init         = dpu_kms_hw_init,
 955         .irq_preinstall  = dpu_core_irq_preinstall,
 956         .irq_postinstall = dpu_irq_postinstall,
 957         .irq_uninstall   = dpu_core_irq_uninstall,
 958         .irq             = dpu_core_irq,
 959         .enable_commit   = dpu_kms_enable_commit,
 960         .disable_commit  = dpu_kms_disable_commit,
 961         .flush_commit    = dpu_kms_flush_commit,
 962         .wait_flush      = dpu_kms_wait_flush,
 963         .complete_commit = dpu_kms_complete_commit,
 964         .enable_vblank   = dpu_kms_enable_vblank,
 965         .disable_vblank  = dpu_kms_disable_vblank,
 966         .check_modified_format = dpu_format_check_modified_format,
 967         .get_format      = dpu_get_msm_format,
 968         .destroy         = dpu_kms_destroy,
 969         .snapshot        = dpu_kms_mdp_snapshot,
 970 #ifdef CONFIG_DEBUG_FS
 971         .debugfs_init    = dpu_kms_debugfs_init,
 972 #endif
 973 };
 974
 975 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
 976 {
 977         struct msm_mmu *mmu;
 978
 979         if (!dpu_kms->base.aspace)
 980                 return;
 981
 982         mmu = dpu_kms->base.aspace->mmu;
 983
 984         mmu->funcs->detach(mmu);
 985         msm_gem_address_space_put(dpu_kms->base.aspace);
 986
 987         dpu_kms->base.aspace = NULL;
 988 }
 989
 990 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
 991 {
 992         struct msm_gem_address_space *aspace;
 993
 994         aspace = msm_kms_init_aspace(dpu_kms->dev);
 995         if (IS_ERR(aspace))
 996                 return PTR_ERR(aspace);
 997
 998         dpu_kms->base.aspace = aspace;
 999
1000         return 0;
1001 }
1002
1003 unsigned long dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
1004 {
1005         struct clk *clk;
1006
1007         clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name);
1008         if (!clk)
1009                 return 0;
1010
1011         return clk_get_rate(clk);
1012 }
1013
1014 static int dpu_kms_hw_init(struct msm_kms *kms)
1015 {
1016         struct dpu_kms *dpu_kms;
1017         struct drm_device *dev;
1018         int i, rc = -EINVAL;
1019         u32 core_rev;
1020
1021         if (!kms) {
1022                 DPU_ERROR("invalid kms\n");
1023                 return rc;
1024         }
1025
1026         dpu_kms = to_dpu_kms(kms);
1027         dev = dpu_kms->dev;
1028
1029         dev->mode_config.cursor_width = 512;
1030         dev->mode_config.cursor_height = 512;
1031
1032         rc = dpu_kms_global_obj_init(dpu_kms);
1033         if (rc)
1034                 return rc;
1035
1036         atomic_set(&dpu_kms->bandwidth_ref, 0);
1037
1038         dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp");
1039         if (IS_ERR(dpu_kms->mmio)) {
1040                 rc = PTR_ERR(dpu_kms->mmio);
1041                 DPU_ERROR("mdp register memory map failed: %d\n", rc);
1042                 dpu_kms->mmio = NULL;
1043                 goto error;
1044         }
1045         DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1046
1047         dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif");
1048         if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1049                 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1050                 DPU_ERROR("vbif register memory map failed: %d\n", rc);
1051                 dpu_kms->vbif[VBIF_RT] = NULL;
1052                 goto error;
1053         }
1054         dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt");
1055         if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1056                 dpu_kms->vbif[VBIF_NRT] = NULL;
1057                 DPU_DEBUG("VBIF NRT is not defined");
1058         }
1059
1060         dpu_kms_parse_data_bus_icc_path(dpu_kms);
1061
1062         rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);
1063         if (rc < 0)
1064                 goto error;
1065
1066         core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
1067
1068         pr_info("dpu hardware revision:0x%x\n", core_rev);
1069
1070         dpu_kms->catalog = of_device_get_match_data(dev->dev);
1071         if (!dpu_kms->catalog) {
1072                 DPU_ERROR("device config not known!\n");
1073                 rc = -EINVAL;
1074                 goto power_error;
1075         }
1076
1077         /*
1078          * Now we need to read the HW catalog and initialize resources such as
1079          * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
1080          */
1081         rc = _dpu_kms_mmu_init(dpu_kms);
1082         if (rc) {
1083                 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
1084                 goto power_error;
1085         }
1086
1087         rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
1088         if (rc) {
1089                 DPU_ERROR("rm init failed: %d\n", rc);
1090                 goto power_error;
1091         }
1092
1093         dpu_kms->rm_init = true;
1094
1095         dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
1096                                              dpu_kms->catalog);
1097         if (IS_ERR(dpu_kms->hw_mdp)) {
1098                 rc = PTR_ERR(dpu_kms->hw_mdp);
1099                 DPU_ERROR("failed to get hw_mdp: %d\n", rc);
1100                 dpu_kms->hw_mdp = NULL;
1101                 goto power_error;
1102         }
1103
1104         for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
1105                 struct dpu_hw_vbif *hw;
1106                 const struct dpu_vbif_cfg *vbif = &dpu_kms->catalog->vbif[i];
1107
1108                 hw = dpu_hw_vbif_init(vbif, dpu_kms->vbif[vbif->id]);
1109                 if (IS_ERR(hw)) {
1110                         rc = PTR_ERR(hw);
1111                         DPU_ERROR("failed to init vbif %d: %d\n", vbif->id, rc);
1112                         goto power_error;
1113                 }
1114
1115                 dpu_kms->hw_vbif[vbif->id] = hw;
1116         }
1117
1118         rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
1119                         msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core"));
1120         if (rc) {
1121                 DPU_ERROR("failed to init perf %d\n", rc);
1122                 goto perf_err;
1123         }
1124
1125         dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog);
1126         if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) {
1127                 rc = PTR_ERR(dpu_kms->hw_intr);
1128                 DPU_ERROR("hw_intr init failed: %d\n", rc);
1129                 dpu_kms->hw_intr = NULL;
1130                 goto hw_intr_init_err;
1131         }
1132
1133         dev->mode_config.min_width = 0;
1134         dev->mode_config.min_height = 0;
1135
1136         /*
1137          * max crtc width is equal to the max mixer width * 2 and max height is
1138          * is 4K
1139          */
1140         dev->mode_config.max_width =
1141                         dpu_kms->catalog->caps->max_mixer_width * 2;
1142         dev->mode_config.max_height = 4096;
1143
1144         dev->max_vblank_count = 0xffffffff;
1145         /* Disable vblank irqs aggressively for power-saving */
1146         dev->vblank_disable_immediate = true;
1147
1148         /*
1149          * _dpu_kms_drm_obj_init should create the DRM related objects
1150          * i.e. CRTCs, planes, encoders, connectors and so forth
1151          */
1152         rc = _dpu_kms_drm_obj_init(dpu_kms);
1153         if (rc) {
1154                 DPU_ERROR("modeset init failed: %d\n", rc);
1155                 goto drm_obj_init_err;
1156         }
1157
1158         dpu_vbif_init_memtypes(dpu_kms);
1159
1160         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1161
1162         return 0;
1163
1164 drm_obj_init_err:
1165         dpu_core_perf_destroy(&dpu_kms->perf);
1166 hw_intr_init_err:
1167 perf_err:
1168 power_error:
1169         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1170 error:
1171         _dpu_kms_hw_destroy(dpu_kms);
1172
1173         return rc;
1174 }
1175
1176 static int dpu_kms_init(struct drm_device *ddev)
1177 {
1178         struct msm_drm_private *priv = ddev->dev_private;
1179         struct device *dev = ddev->dev;
1180         struct platform_device *pdev = to_platform_device(dev);
1181         struct dpu_kms *dpu_kms;
1182         int irq;
1183         struct dev_pm_opp *opp;
1184         int ret = 0;
1185         unsigned long max_freq = ULONG_MAX;
1186
1187         dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
1188         if (!dpu_kms)
1189                 return -ENOMEM;
1190
1191         ret = devm_pm_opp_set_clkname(dev, "core");
1192         if (ret)
1193                 return ret;
1194         /* OPP table is optional */
1195         ret = devm_pm_opp_of_add_table(dev);
1196         if (ret && ret != -ENODEV) {
1197                 dev_err(dev, "invalid OPP table in device tree\n");
1198                 return ret;
1199         }
1200
1201         ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
1202         if (ret < 0) {
1203                 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1204                 return ret;
1205         }
1206         dpu_kms->num_clocks = ret;
1207
1208         opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1209         if (!IS_ERR(opp))
1210                 dev_pm_opp_put(opp);
1211
1212         dev_pm_opp_set_rate(dev, max_freq);
1213
1214         ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1215         if (ret) {
1216                 DPU_ERROR("failed to init kms, ret=%d\n", ret);
1217                 return ret;
1218         }
1219         dpu_kms->dev = ddev;
1220         dpu_kms->pdev = pdev;
1221
1222         pm_runtime_enable(&pdev->dev);
1223         dpu_kms->rpm_enabled = true;
1224
1225         priv->kms = &dpu_kms->base;
1226
1227         irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
1228         if (!irq) {
1229                 DPU_ERROR("failed to get irq\n");
1230                 return -EINVAL;
1231         }
1232         dpu_kms->base.irq = irq;
1233
1234         return 0;
1235 }
1236
1237 static int dpu_dev_probe(struct platform_device *pdev)
1238 {
1239         return msm_drv_probe(&pdev->dev, dpu_kms_init);
1240 }
1241
1242 static void dpu_dev_remove(struct platform_device *pdev)
1243 {
1244         component_master_del(&pdev->dev, &msm_drm_ops);
1245 }
1246
1247 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1248 {
1249         int i;
1250         struct platform_device *pdev = to_platform_device(dev);
1251         struct msm_drm_private *priv = platform_get_drvdata(pdev);
1252         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1253
1254         /* Drop the performance state vote */
1255         dev_pm_opp_set_rate(dev, 0);
1256         clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks);
1257
1258         for (i = 0; i < dpu_kms->num_paths; i++)
1259                 icc_set_bw(dpu_kms->path[i], 0, 0);
1260
1261         return 0;
1262 }
1263
1264 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1265 {
1266         int rc = -1;
1267         struct platform_device *pdev = to_platform_device(dev);
1268         struct msm_drm_private *priv = platform_get_drvdata(pdev);
1269         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1270         struct drm_encoder *encoder;
1271         struct drm_device *ddev;
1272
1273         ddev = dpu_kms->dev;
1274
1275         rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks);
1276         if (rc) {
1277                 DPU_ERROR("clock enable failed rc:%d\n", rc);
1278                 return rc;
1279         }
1280
1281         dpu_vbif_init_memtypes(dpu_kms);
1282
1283         drm_for_each_encoder(encoder, ddev)
1284                 dpu_encoder_virt_runtime_resume(encoder);
1285
1286         return rc;
1287 }
1288
1289 static const struct dev_pm_ops dpu_pm_ops = {
1290         SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1291         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1292                                 pm_runtime_force_resume)
1293         .prepare = msm_pm_prepare,
1294         .complete = msm_pm_complete,
1295 };
1296
1297 static const struct of_device_id dpu_dt_match[] = {
1298         { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1299         { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1300         { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1301         { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1302         { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1303         { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1304         { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1305         { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1306         { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
1307         { .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
1308         { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1309         { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1310         { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1311         { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1312         { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1313         {}
1314 };
1315 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1316
1317 static struct platform_driver dpu_driver = {
1318         .probe = dpu_dev_probe,
1319         .remove_new = dpu_dev_remove,
1320         .shutdown = msm_drv_shutdown,
1321         .driver = {
1322                 .name = "msm_dpu",
1323                 .of_match_table = dpu_dt_match,
1324                 .pm = &dpu_pm_ops,
1325         },
1326 };
1327
1328 void __init msm_dpu_register(void)
1329 {
1330         platform_driver_register(&dpu_driver);
1331 }
1332
1333 void __exit msm_dpu_unregister(void)
1334 {
1335         platform_driver_unregister(&dpu_driver);
1336 }