1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2016 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
10 #define __MESON_VCLK_H
13 MESON_VCLK_TARGET_CVBS = 0,
14 MESON_VCLK_TARGET_HDMI = 1,
15 MESON_VCLK_TARGET_DMT = 2,
18 /* 27MHz is the CVBS Pixel Clock */
19 #define MESON_VCLK_CVBS 27000
22 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq);
24 meson_vclk_vic_supported_freq(unsigned int freq);
26 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
27 unsigned int vclk_freq, unsigned int venc_freq,
28 unsigned int dac_freq, bool hdmi_use_enci);
30 #endif /* __MESON_VCLK_H */