drivers/gpu/drm/meson/meson_vclk.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Copyright (C) 2016 BayLibre, SAS
   4  * Author: Neil Armstrong <narmstrong@baylibre.com>
   5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   6  */
   7
   8 #include <linux/export.h>
   9
  10 #include <drm/drm_print.h>
  11
  12 #include "meson_drv.h"
  13 #include "meson_vclk.h"
  14
  15 /**
  16  * DOC: Video Clocks
  17  *
  18  * VCLK is the "Pixel Clock" frequency generator from a dedicated PLL.
  19  * We handle the following encodings :
  20  *
  21  * - CVBS 27MHz generator via the VCLK2 to the VENCI and VDAC blocks
  22  * - HDMI Pixel Clocks generation
  23  *
  24  * What is missing :
  25  *
  26  * - Genenate Pixel clocks for 2K/4K 10bit formats
  27  *
  28  * Clock generator scheme :
  29  *
  30  * .. code::
  31  *
  32  *    __________   _________            _____
  33  *   |          | |         |          |     |--ENCI
  34  *   | HDMI PLL |-| PLL_DIV |--- VCLK--|     |--ENCL
  35  *   |__________| |_________| \        | MUX |--ENCP
  36  *                             --VCLK2-|     |--VDAC
  37  *                                     |_____|--HDMI-TX
  38  *
  39  * Final clocks can take input for either VCLK or VCLK2, but
  40  * VCLK is the preferred path for HDMI clocking and VCLK2 is the
  41  * preferred path for CVBS VDAC clocking.
  42  *
  43  * VCLK and VCLK2 have fixed divided clocks paths for /1, /2, /4, /6 or /12.
  44  *
  45  * The PLL_DIV can achieve an additional fractional dividing like
  46  * 1.5, 3.5, 3.75... to generate special 2K and 4K 10bit clocks.
  47  */
  48
  49 /* HHI Registers */
  50 #define HHI_VID_PLL_CLK_DIV     0x1a0 /* 0x68 offset in data sheet */
  51 #define VID_PLL_EN              BIT(19)
  52 #define VID_PLL_BYPASS          BIT(18)
  53 #define VID_PLL_PRESET          BIT(15)
  54 #define HHI_VIID_CLK_DIV        0x128 /* 0x4a offset in data sheet */
  55 #define VCLK2_DIV_MASK          0xff
  56 #define VCLK2_DIV_EN            BIT(16)
  57 #define VCLK2_DIV_RESET         BIT(17)
  58 #define CTS_VDAC_SEL_MASK       (0xf << 28)
  59 #define CTS_VDAC_SEL_SHIFT      28
  60 #define HHI_VIID_CLK_CNTL       0x12c /* 0x4b offset in data sheet */
  61 #define VCLK2_EN                BIT(19)
  62 #define VCLK2_SEL_MASK          (0x7 << 16)
  63 #define VCLK2_SEL_SHIFT         16
  64 #define VCLK2_SOFT_RESET        BIT(15)
  65 #define VCLK2_DIV1_EN           BIT(0)
  66 #define HHI_VID_CLK_DIV         0x164 /* 0x59 offset in data sheet */
  67 #define VCLK_DIV_MASK           0xff
  68 #define VCLK_DIV_EN             BIT(16)
  69 #define VCLK_DIV_RESET          BIT(17)
  70 #define CTS_ENCP_SEL_MASK       (0xf << 24)
  71 #define CTS_ENCP_SEL_SHIFT      24
  72 #define CTS_ENCI_SEL_MASK       (0xf << 28)
  73 #define CTS_ENCI_SEL_SHIFT      28
  74 #define HHI_VID_CLK_CNTL        0x17c /* 0x5f offset in data sheet */
  75 #define VCLK_EN                 BIT(19)
  76 #define VCLK_SEL_MASK           (0x7 << 16)
  77 #define VCLK_SEL_SHIFT          16
  78 #define VCLK_SOFT_RESET         BIT(15)
  79 #define VCLK_DIV1_EN            BIT(0)
  80 #define VCLK_DIV2_EN            BIT(1)
  81 #define VCLK_DIV4_EN            BIT(2)
  82 #define VCLK_DIV6_EN            BIT(3)
  83 #define VCLK_DIV12_EN           BIT(4)
  84 #define HHI_VID_CLK_CNTL2       0x194 /* 0x65 offset in data sheet */
  85 #define CTS_ENCI_EN             BIT(0)
  86 #define CTS_ENCP_EN             BIT(2)
  87 #define CTS_VDAC_EN             BIT(4)
  88 #define HDMI_TX_PIXEL_EN        BIT(5)
  89 #define HHI_HDMI_CLK_CNTL       0x1cc /* 0x73 offset in data sheet */
  90 #define HDMI_TX_PIXEL_SEL_MASK  (0xf << 16)
  91 #define HDMI_TX_PIXEL_SEL_SHIFT 16
  92 #define CTS_HDMI_SYS_SEL_MASK   (0x7 << 9)
  93 #define CTS_HDMI_SYS_DIV_MASK   (0x7f)
  94 #define CTS_HDMI_SYS_EN         BIT(8)
  95
  96 #define HHI_VDAC_CNTL0          0x2F4 /* 0xbd offset in data sheet */
  97 #define HHI_VDAC_CNTL1          0x2F8 /* 0xbe offset in data sheet */
  98
  99 #define HHI_HDMI_PLL_CNTL       0x320 /* 0xc8 offset in data sheet */
 100 #define HHI_HDMI_PLL_CNTL_EN    BIT(30)
 101 #define HHI_HDMI_PLL_CNTL2      0x324 /* 0xc9 offset in data sheet */
 102 #define HHI_HDMI_PLL_CNTL3      0x328 /* 0xca offset in data sheet */
 103 #define HHI_HDMI_PLL_CNTL4      0x32C /* 0xcb offset in data sheet */
 104 #define HHI_HDMI_PLL_CNTL5      0x330 /* 0xcc offset in data sheet */
 105 #define HHI_HDMI_PLL_CNTL6      0x334 /* 0xcd offset in data sheet */
 106 #define HHI_HDMI_PLL_CNTL7      0x338 /* 0xce offset in data sheet */
 107
 108 #define HDMI_PLL_RESET          BIT(28)
 109 #define HDMI_PLL_RESET_G12A     BIT(29)
 110 #define HDMI_PLL_LOCK           BIT(31)
 111 #define HDMI_PLL_LOCK_G12A      (3 << 30)
 112
 113 #define FREQ_1000_1001(_freq)   DIV_ROUND_CLOSEST(_freq * 1000, 1001)
 114
 115 /* VID PLL Dividers */
 116 enum {
 117         VID_PLL_DIV_1 = 0,
 118         VID_PLL_DIV_2,
 119         VID_PLL_DIV_2p5,
 120         VID_PLL_DIV_3,
 121         VID_PLL_DIV_3p5,
 122         VID_PLL_DIV_3p75,
 123         VID_PLL_DIV_4,
 124         VID_PLL_DIV_5,
 125         VID_PLL_DIV_6,
 126         VID_PLL_DIV_6p25,
 127         VID_PLL_DIV_7,
 128         VID_PLL_DIV_7p5,
 129         VID_PLL_DIV_12,
 130         VID_PLL_DIV_14,
 131         VID_PLL_DIV_15,
 132 };
 133
 134 void meson_vid_pll_set(struct meson_drm *priv, unsigned int div)
 135 {
 136         unsigned int shift_val = 0;
 137         unsigned int shift_sel = 0;
 138
 139         /* Disable vid_pll output clock */
 140         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_EN, 0);
 141         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV, VID_PLL_PRESET, 0);
 142
 143         switch (div) {
 144         case VID_PLL_DIV_2:
 145                 shift_val = 0x0aaa;
 146                 shift_sel = 0;
 147                 break;
 148         case VID_PLL_DIV_2p5:
 149                 shift_val = 0x5294;
 150                 shift_sel = 2;
 151                 break;
 152         case VID_PLL_DIV_3:
 153                 shift_val = 0x0db6;
 154                 shift_sel = 0;
 155                 break;
 156         case VID_PLL_DIV_3p5:
 157                 shift_val = 0x36cc;
 158                 shift_sel = 1;
 159                 break;
 160         case VID_PLL_DIV_3p75:
 161                 shift_val = 0x6666;
 162                 shift_sel = 2;
 163                 break;
 164         case VID_PLL_DIV_4:
 165                 shift_val = 0x0ccc;
 166                 shift_sel = 0;
 167                 break;
 168         case VID_PLL_DIV_5:
 169                 shift_val = 0x739c;
 170                 shift_sel = 2;
 171                 break;
 172         case VID_PLL_DIV_6:
 173                 shift_val = 0x0e38;
 174                 shift_sel = 0;
 175                 break;
 176         case VID_PLL_DIV_6p25:
 177                 shift_val = 0x0000;
 178                 shift_sel = 3;
 179                 break;
 180         case VID_PLL_DIV_7:
 181                 shift_val = 0x3c78;
 182                 shift_sel = 1;
 183                 break;
 184         case VID_PLL_DIV_7p5:
 185                 shift_val = 0x78f0;
 186                 shift_sel = 2;
 187                 break;
 188         case VID_PLL_DIV_12:
 189                 shift_val = 0x0fc0;
 190                 shift_sel = 0;
 191                 break;
 192         case VID_PLL_DIV_14:
 193                 shift_val = 0x3f80;
 194                 shift_sel = 1;
 195                 break;
 196         case VID_PLL_DIV_15:
 197                 shift_val = 0x7f80;
 198                 shift_sel = 2;
 199                 break;
 200         }
 201
 202         if (div == VID_PLL_DIV_1)
 203                 /* Enable vid_pll bypass to HDMI pll */
 204                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 205                                    VID_PLL_BYPASS, VID_PLL_BYPASS);
 206         else {
 207                 /* Disable Bypass */
 208                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 209                                    VID_PLL_BYPASS, 0);
 210                 /* Clear sel */
 211                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 212                                    3 << 16, 0);
 213                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 214                                    VID_PLL_PRESET, 0);
 215                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 216                                    0x7fff, 0);
 217
 218                 /* Setup sel and val */
 219                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 220                                    3 << 16, shift_sel << 16);
 221                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 222                                    VID_PLL_PRESET, VID_PLL_PRESET);
 223                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 224                                    0x7fff, shift_val);
 225
 226                 regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 227                                    VID_PLL_PRESET, 0);
 228         }
 229
 230         /* Enable the vid_pll output clock */
 231         regmap_update_bits(priv->hhi, HHI_VID_PLL_CLK_DIV,
 232                                 VID_PLL_EN, VID_PLL_EN);
 233 }
 234
 235 /*
 236  * Setup VCLK2 for 27MHz, and enable clocks for ENCI and VDAC
 237  *
 238  * TOFIX: Refactor into table to also handle HDMI frequency and paths
 239  */
 240 static void meson_venci_cvbs_clock_config(struct meson_drm *priv)
 241 {
 242         unsigned int val;
 243
 244         /* Setup PLL to output 1.485GHz */
 245         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 246                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d);
 247                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00);
 248                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 249                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 250                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 251                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 252                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d);
 253
 254                 /* Poll for lock bit */
 255                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 256                                          (val & HDMI_PLL_LOCK), 10, 0);
 257         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 258                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 259                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b);
 260                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300);
 261                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0xa6212844);
 262                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c4d000c);
 263                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 264                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 265
 266                 /* Reset PLL */
 267                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 268                                         HDMI_PLL_RESET, HDMI_PLL_RESET);
 269                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 270                                         HDMI_PLL_RESET, 0);
 271
 272                 /* Poll for lock bit */
 273                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 274                                          (val & HDMI_PLL_LOCK), 10, 0);
 275         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 276                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 277                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000);
 278                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
 279                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x6a28dc00);
 280                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x65771290);
 281                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
 282                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x56540000);
 283                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7);
 284                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7);
 285
 286                 /* Poll for lock bit */
 287                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 288                         ((val & HDMI_PLL_LOCK_G12A) == HDMI_PLL_LOCK_G12A),
 289                         10, 0);
 290         }
 291
 292         /* Disable VCLK2 */
 293         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
 294
 295         /* Setup vid_pll to /1 */
 296         meson_vid_pll_set(priv, VID_PLL_DIV_1);
 297
 298         /* Setup the VCLK2 divider value to achieve 27MHz */
 299         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 300                                 VCLK2_DIV_MASK, (55 - 1));
 301
 302         /* select vid_pll for vclk2 */
 303         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 304                 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 305                                         VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
 306         else
 307                 regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 308                                         VCLK2_SEL_MASK, (4 << VCLK2_SEL_SHIFT));
 309
 310         /* enable vclk2 gate */
 311         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
 312
 313         /* select vclk_div1 for enci */
 314         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 315                                 CTS_ENCI_SEL_MASK, (8 << CTS_ENCI_SEL_SHIFT));
 316         /* select vclk_div1 for vdac */
 317         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 318                                 CTS_VDAC_SEL_MASK, (8 << CTS_VDAC_SEL_SHIFT));
 319
 320         /* release vclk2_div_reset and enable vclk2_div */
 321         regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
 322                                 VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
 323
 324         /* enable vclk2_div1 gate */
 325         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 326                                 VCLK2_DIV1_EN, VCLK2_DIV1_EN);
 327
 328         /* reset vclk2 */
 329         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 330                                 VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
 331         regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
 332                                 VCLK2_SOFT_RESET, 0);
 333
 334         /* enable enci_clk */
 335         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 336                                 CTS_ENCI_EN, CTS_ENCI_EN);
 337         /* enable vdac_clk */
 338         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 339                                 CTS_VDAC_EN, CTS_VDAC_EN);
 340 }
 341
 342 enum {
 343 /* PLL  O1 O2 O3 VP DV     EN TX */
 344 /* 4320 /4 /4 /1 /5 /1  => /2 /2 */
 345         MESON_VCLK_HDMI_ENCI_54000 = 0,
 346 /* 4320 /4 /4 /1 /5 /1  => /1 /2 */
 347         MESON_VCLK_HDMI_DDR_54000,
 348 /* 2970 /4 /1 /1 /5 /1  => /1 /2 */
 349         MESON_VCLK_HDMI_DDR_148500,
 350 /* 2970 /2 /2 /2 /5 /1  => /1 /1 */
 351         MESON_VCLK_HDMI_74250,
 352 /* 2970 /1 /2 /2 /5 /1  => /1 /1 */
 353         MESON_VCLK_HDMI_148500,
 354 /* 2970 /1 /1 /1 /5 /2  => /1 /1 */
 355         MESON_VCLK_HDMI_297000,
 356 /* 5940 /1 /1 /2 /5 /1  => /1 /1 */
 357         MESON_VCLK_HDMI_594000
 358 };
 359
 360 struct meson_vclk_params {
 361         unsigned int pixel_freq;
 362         unsigned int pll_base_freq;
 363         unsigned int pll_od1;
 364         unsigned int pll_od2;
 365         unsigned int pll_od3;
 366         unsigned int vid_pll_div;
 367         unsigned int vclk_div;
 368 } params[] = {
 369         [MESON_VCLK_HDMI_ENCI_54000] = {
 370                 .pixel_freq = 54000,
 371                 .pll_base_freq = 4320000,
 372                 .pll_od1 = 4,
 373                 .pll_od2 = 4,
 374                 .pll_od3 = 1,
 375                 .vid_pll_div = VID_PLL_DIV_5,
 376                 .vclk_div = 1,
 377         },
 378         [MESON_VCLK_HDMI_DDR_54000] = {
 379                 .pixel_freq = 54000,
 380                 .pll_base_freq = 4320000,
 381                 .pll_od1 = 4,
 382                 .pll_od2 = 4,
 383                 .pll_od3 = 1,
 384                 .vid_pll_div = VID_PLL_DIV_5,
 385                 .vclk_div = 1,
 386         },
 387         [MESON_VCLK_HDMI_DDR_148500] = {
 388                 .pixel_freq = 148500,
 389                 .pll_base_freq = 2970000,
 390                 .pll_od1 = 4,
 391                 .pll_od2 = 1,
 392                 .pll_od3 = 1,
 393                 .vid_pll_div = VID_PLL_DIV_5,
 394                 .vclk_div = 1,
 395         },
 396         [MESON_VCLK_HDMI_74250] = {
 397                 .pixel_freq = 74250,
 398                 .pll_base_freq = 2970000,
 399                 .pll_od1 = 2,
 400                 .pll_od2 = 2,
 401                 .pll_od3 = 2,
 402                 .vid_pll_div = VID_PLL_DIV_5,
 403                 .vclk_div = 1,
 404         },
 405         [MESON_VCLK_HDMI_148500] = {
 406                 .pixel_freq = 148500,
 407                 .pll_base_freq = 2970000,
 408                 .pll_od1 = 1,
 409                 .pll_od2 = 2,
 410                 .pll_od3 = 2,
 411                 .vid_pll_div = VID_PLL_DIV_5,
 412                 .vclk_div = 1,
 413         },
 414         [MESON_VCLK_HDMI_297000] = {
 415                 .pixel_freq = 297000,
 416                 .pll_base_freq = 5940000,
 417                 .pll_od1 = 2,
 418                 .pll_od2 = 1,
 419                 .pll_od3 = 1,
 420                 .vid_pll_div = VID_PLL_DIV_5,
 421                 .vclk_div = 2,
 422         },
 423         [MESON_VCLK_HDMI_594000] = {
 424                 .pixel_freq = 594000,
 425                 .pll_base_freq = 5940000,
 426                 .pll_od1 = 1,
 427                 .pll_od2 = 1,
 428                 .pll_od3 = 2,
 429                 .vid_pll_div = VID_PLL_DIV_5,
 430                 .vclk_div = 1,
 431         },
 432         { /* sentinel */ },
 433 };
 434
 435 static inline unsigned int pll_od_to_reg(unsigned int od)
 436 {
 437         switch (od) {
 438         case 1:
 439                 return 0;
 440         case 2:
 441                 return 1;
 442         case 4:
 443                 return 2;
 444         case 8:
 445                 return 3;
 446         }
 447
 448         /* Invalid */
 449         return 0;
 450 }
 451
 452 void meson_hdmi_pll_set_params(struct meson_drm *priv, unsigned int m,
 453                                unsigned int frac, unsigned int od1,
 454                                unsigned int od2, unsigned int od3)
 455 {
 456         unsigned int val;
 457
 458         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 459                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x58000200 | m);
 460                 if (frac)
 461                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
 462                                      0x00004000 | frac);
 463                 else
 464                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2,
 465                                      0x00000000);
 466                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x0d5c5091);
 467                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x801da72c);
 468                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x71486980);
 469                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x00000e55);
 470
 471                 /* Enable and unreset */
 472                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 473                                    0x7 << 28, HHI_HDMI_PLL_CNTL_EN);
 474
 475                 /* Poll for lock bit */
 476                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL,
 477                                          val, (val & HDMI_PLL_LOCK), 10, 0);
 478         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 479                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 480                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x40000200 | m);
 481                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac);
 482                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x860f30c4);
 483                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0c8e0000);
 484                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x001fa729);
 485                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x01a31500);
 486
 487                 /* Reset PLL */
 488                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 489                                 HDMI_PLL_RESET, HDMI_PLL_RESET);
 490                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 491                                 HDMI_PLL_RESET, 0);
 492
 493                 /* Poll for lock bit */
 494                 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val,
 495                                 (val & HDMI_PLL_LOCK), 10, 0);
 496         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 497                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x0b3a0400 | m);
 498
 499                 /* Enable and reset */
 500                 /* TODO: add specific macro for g12a here */
 501                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 502                                    0x3 << 28, 0x3 << 28);
 503
 504                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac);
 505                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL3, 0x00000000);
 506
 507                 /* G12A HDMI PLL Needs specific parameters for 5.4GHz */
 508                 if (m >= 0xf7) {
 509                         if (frac < 0x10000) {
 510                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
 511                                                         0x6a685c00);
 512                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
 513                                                         0x11551293);
 514                         } else {
 515                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4,
 516                                                         0xea68dc00);
 517                                 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5,
 518                                                         0x65771290);
 519                         }
 520                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39272000);
 521                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x55540000);
 522                 } else {
 523                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL4, 0x0a691c00);
 524                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL5, 0x33771290);
 525                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL6, 0x39270000);
 526                         regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL7, 0x50540000);
 527                 }
 528
 529                 do {
 530                         /* Reset PLL */
 531                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 532                                         HDMI_PLL_RESET_G12A, HDMI_PLL_RESET_G12A);
 533
 534                         /* UN-Reset PLL */
 535                         regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 536                                         HDMI_PLL_RESET_G12A, 0);
 537
 538                         /* Poll for lock bits */
 539                         if (!regmap_read_poll_timeout(priv->hhi,
 540                                                       HHI_HDMI_PLL_CNTL, val,
 541                                                       ((val & HDMI_PLL_LOCK_G12A)
 542                                                         == HDMI_PLL_LOCK_G12A),
 543                                                       10, 100))
 544                                 break;
 545                 } while(1);
 546         }
 547
 548         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 549                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 550                                 3 << 16, pll_od_to_reg(od1) << 16);
 551         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 552                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 553                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 554                                 3 << 21, pll_od_to_reg(od1) << 21);
 555         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 556                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 557                                 3 << 16, pll_od_to_reg(od1) << 16);
 558
 559         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 560                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 561                                 3 << 22, pll_od_to_reg(od2) << 22);
 562         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 563                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 564                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 565                                 3 << 23, pll_od_to_reg(od2) << 23);
 566         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 567                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 568                                 3 << 18, pll_od_to_reg(od2) << 18);
 569
 570         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 571                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2,
 572                                 3 << 18, pll_od_to_reg(od3) << 18);
 573         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 574                  meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
 575                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL3,
 576                                 3 << 19, pll_od_to_reg(od3) << 19);
 577         else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 578                 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL,
 579                                 3 << 20, pll_od_to_reg(od3) << 20);
 580 }
 581
 582 #define XTAL_FREQ 24000
 583
 584 static unsigned int meson_hdmi_pll_get_m(struct meson_drm *priv,
 585                                          unsigned int pll_freq)
 586 {
 587         /* The GXBB PLL has a /2 pre-multiplier */
 588         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
 589                 pll_freq /= 2;
 590
 591         return pll_freq / XTAL_FREQ;
 592 }
 593
 594 #define HDMI_FRAC_MAX_GXBB      4096
 595 #define HDMI_FRAC_MAX_GXL       1024
 596 #define HDMI_FRAC_MAX_G12A      131072
 597
 598 static unsigned int meson_hdmi_pll_get_frac(struct meson_drm *priv,
 599                                             unsigned int m,
 600                                             unsigned int pll_freq)
 601 {
 602         unsigned int parent_freq = XTAL_FREQ;
 603         unsigned int frac_max = HDMI_FRAC_MAX_GXL;
 604         unsigned int frac_m;
 605         unsigned int frac;
 606
 607         /* The GXBB PLL has a /2 pre-multiplier and a larger FRAC width */
 608         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 609                 frac_max = HDMI_FRAC_MAX_GXBB;
 610                 parent_freq *= 2;
 611         }
 612
 613         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
 614                 frac_max = HDMI_FRAC_MAX_G12A;
 615
 616         /* We can have a perfect match !*/
 617         if (pll_freq / m == parent_freq &&
 618             pll_freq % m == 0)
 619                 return 0;
 620
 621         frac = div_u64((u64)pll_freq * (u64)frac_max, parent_freq);
 622         frac_m = m * frac_max;
 623         if (frac_m > frac)
 624                 return frac_max;
 625         frac -= frac_m;
 626
 627         return min((u16)frac, (u16)(frac_max - 1));
 628 }
 629
 630 static bool meson_hdmi_pll_validate_params(struct meson_drm *priv,
 631                                            unsigned int m,
 632                                            unsigned int frac)
 633 {
 634         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 635                 /* Empiric supported min/max dividers */
 636                 if (m < 53 || m > 123)
 637                         return false;
 638                 if (frac >= HDMI_FRAC_MAX_GXBB)
 639                         return false;
 640         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 641                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 642                 /* Empiric supported min/max dividers */
 643                 if (m < 106 || m > 247)
 644                         return false;
 645                 if (frac >= HDMI_FRAC_MAX_GXL)
 646                         return false;
 647         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 648                 /* Empiric supported min/max dividers */
 649                 if (m < 106 || m > 247)
 650                         return false;
 651                 if (frac >= HDMI_FRAC_MAX_G12A)
 652                         return false;
 653         }
 654
 655         return true;
 656 }
 657
 658 static bool meson_hdmi_pll_find_params(struct meson_drm *priv,
 659                                        unsigned int freq,
 660                                        unsigned int *m,
 661                                        unsigned int *frac,
 662                                        unsigned int *od)
 663 {
 664         /* Cycle from /16 to /2 */
 665         for (*od = 16 ; *od > 1 ; *od >>= 1) {
 666                 *m = meson_hdmi_pll_get_m(priv, freq * *od);
 667                 if (!*m)
 668                         continue;
 669                 *frac = meson_hdmi_pll_get_frac(priv, *m, freq * *od);
 670
 671                 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d\n",
 672                                  freq, *m, *frac, *od);
 673
 674                 if (meson_hdmi_pll_validate_params(priv, *m, *frac))
 675                         return true;
 676         }
 677
 678         return false;
 679 }
 680
 681 /* pll_freq is the frequency after the OD dividers */
 682 enum drm_mode_status
 683 meson_vclk_dmt_supported_freq(struct meson_drm *priv, unsigned int freq)
 684 {
 685         unsigned int od, m, frac;
 686
 687         /* In DMT mode, path after PLL is always /10 */
 688         freq *= 10;
 689
 690         if (meson_hdmi_pll_find_params(priv, freq, &m, &frac, &od))
 691                 return MODE_OK;
 692
 693         return MODE_CLOCK_RANGE;
 694 }
 695 EXPORT_SYMBOL_GPL(meson_vclk_dmt_supported_freq);
 696
 697 /* pll_freq is the frequency after the OD dividers */
 698 static void meson_hdmi_pll_generic_set(struct meson_drm *priv,
 699                                        unsigned int pll_freq)
 700 {
 701         unsigned int od, m, frac, od1, od2, od3;
 702
 703         if (meson_hdmi_pll_find_params(priv, pll_freq, &m, &frac, &od)) {
 704                 od3 = 1;
 705                 if (od < 4) {
 706                         od1 = 2;
 707                         od2 = 1;
 708                 } else {
 709                         od2 = od / 4;
 710                         od1 = od / od2;
 711                 }
 712
 713                 DRM_DEBUG_DRIVER("PLL params for %dkHz: m=%x frac=%x od=%d/%d/%d\n",
 714                                  pll_freq, m, frac, od1, od2, od3);
 715
 716                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 717
 718                 return;
 719         }
 720
 721         DRM_ERROR("Fatal, unable to find parameters for PLL freq %d\n",
 722                   pll_freq);
 723 }
 724
 725 enum drm_mode_status
 726 meson_vclk_vic_supported_freq(unsigned int freq)
 727 {
 728         int i;
 729
 730         DRM_DEBUG_DRIVER("freq = %d\n", freq);
 731
 732         for (i = 0 ; params[i].pixel_freq ; ++i) {
 733                 DRM_DEBUG_DRIVER("i = %d pixel_freq = %d alt = %d\n",
 734                                  i, params[i].pixel_freq,
 735                                  FREQ_1000_1001(params[i].pixel_freq));
 736                 /* Match strict frequency */
 737                 if (freq == params[i].pixel_freq)
 738                         return MODE_OK;
 739                 /* Match 1000/1001 variant */
 740                 if (freq == FREQ_1000_1001(params[i].pixel_freq))
 741                         return MODE_OK;
 742         }
 743
 744         return MODE_CLOCK_RANGE;
 745 }
 746 EXPORT_SYMBOL_GPL(meson_vclk_vic_supported_freq);
 747
 748 static void meson_vclk_set(struct meson_drm *priv, unsigned int pll_base_freq,
 749                            unsigned int od1, unsigned int od2, unsigned int od3,
 750                            unsigned int vid_pll_div, unsigned int vclk_div,
 751                            unsigned int hdmi_tx_div, unsigned int venc_div,
 752                            bool hdmi_use_enci, bool vic_alternate_clock)
 753 {
 754         unsigned int m = 0, frac = 0;
 755
 756         /* Set HDMI-TX sys clock */
 757         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 758                            CTS_HDMI_SYS_SEL_MASK, 0);
 759         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 760                            CTS_HDMI_SYS_DIV_MASK, 0);
 761         regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 762                            CTS_HDMI_SYS_EN, CTS_HDMI_SYS_EN);
 763
 764         /* Set HDMI PLL rate */
 765         if (!od1 && !od2 && !od3) {
 766                 meson_hdmi_pll_generic_set(priv, pll_base_freq);
 767         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB)) {
 768                 switch (pll_base_freq) {
 769                 case 2970000:
 770                         m = 0x3d;
 771                         frac = vic_alternate_clock ? 0xd02 : 0xe00;
 772                         break;
 773                 case 4320000:
 774                         m = vic_alternate_clock ? 0x59 : 0x5a;
 775                         frac = vic_alternate_clock ? 0xe8f : 0;
 776                         break;
 777                 case 5940000:
 778                         m = 0x7b;
 779                         frac = vic_alternate_clock ? 0xa05 : 0xc00;
 780                         break;
 781                 }
 782
 783                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 784         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
 785                    meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL)) {
 786                 switch (pll_base_freq) {
 787                 case 2970000:
 788                         m = 0x7b;
 789                         frac = vic_alternate_clock ? 0x281 : 0x300;
 790                         break;
 791                 case 4320000:
 792                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 793                         frac = vic_alternate_clock ? 0x347 : 0;
 794                         break;
 795                 case 5940000:
 796                         m = 0xf7;
 797                         frac = vic_alternate_clock ? 0x102 : 0x200;
 798                         break;
 799                 }
 800
 801                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 802         } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 803                 switch (pll_base_freq) {
 804                 case 2970000:
 805                         m = 0x7b;
 806                         frac = vic_alternate_clock ? 0x140b4 : 0x18000;
 807                         break;
 808                 case 4320000:
 809                         m = vic_alternate_clock ? 0xb3 : 0xb4;
 810                         frac = vic_alternate_clock ? 0x1a3ee : 0;
 811                         break;
 812                 case 5940000:
 813                         m = 0xf7;
 814                         frac = vic_alternate_clock ? 0x8148 : 0x10000;
 815                         break;
 816                 }
 817
 818                 meson_hdmi_pll_set_params(priv, m, frac, od1, od2, od3);
 819         }
 820
 821         /* Setup vid_pll divider */
 822         meson_vid_pll_set(priv, vid_pll_div);
 823
 824         /* Set VCLK div */
 825         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 826                            VCLK_SEL_MASK, 0);
 827         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 828                            VCLK_DIV_MASK, vclk_div - 1);
 829
 830         /* Set HDMI-TX source */
 831         switch (hdmi_tx_div) {
 832         case 1:
 833                 /* enable vclk_div1 gate */
 834                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 835                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 836
 837                 /* select vclk_div1 for HDMI-TX */
 838                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 839                                    HDMI_TX_PIXEL_SEL_MASK, 0);
 840                 break;
 841         case 2:
 842                 /* enable vclk_div2 gate */
 843                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 844                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 845
 846                 /* select vclk_div2 for HDMI-TX */
 847                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 848                         HDMI_TX_PIXEL_SEL_MASK, 1 << HDMI_TX_PIXEL_SEL_SHIFT);
 849                 break;
 850         case 4:
 851                 /* enable vclk_div4 gate */
 852                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 853                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 854
 855                 /* select vclk_div4 for HDMI-TX */
 856                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 857                         HDMI_TX_PIXEL_SEL_MASK, 2 << HDMI_TX_PIXEL_SEL_SHIFT);
 858                 break;
 859         case 6:
 860                 /* enable vclk_div6 gate */
 861                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 862                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 863
 864                 /* select vclk_div6 for HDMI-TX */
 865                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 866                         HDMI_TX_PIXEL_SEL_MASK, 3 << HDMI_TX_PIXEL_SEL_SHIFT);
 867                 break;
 868         case 12:
 869                 /* enable vclk_div12 gate */
 870                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 871                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 872
 873                 /* select vclk_div12 for HDMI-TX */
 874                 regmap_update_bits(priv->hhi, HHI_HDMI_CLK_CNTL,
 875                         HDMI_TX_PIXEL_SEL_MASK, 4 << HDMI_TX_PIXEL_SEL_SHIFT);
 876                 break;
 877         }
 878         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 879                                    HDMI_TX_PIXEL_EN, HDMI_TX_PIXEL_EN);
 880
 881         /* Set ENCI/ENCP Source */
 882         switch (venc_div) {
 883         case 1:
 884                 /* enable vclk_div1 gate */
 885                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 886                                    VCLK_DIV1_EN, VCLK_DIV1_EN);
 887
 888                 if (hdmi_use_enci)
 889                         /* select vclk_div1 for enci */
 890                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 891                                            CTS_ENCI_SEL_MASK, 0);
 892                 else
 893                         /* select vclk_div1 for encp */
 894                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 895                                            CTS_ENCP_SEL_MASK, 0);
 896                 break;
 897         case 2:
 898                 /* enable vclk_div2 gate */
 899                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 900                                    VCLK_DIV2_EN, VCLK_DIV2_EN);
 901
 902                 if (hdmi_use_enci)
 903                         /* select vclk_div2 for enci */
 904                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 905                                 CTS_ENCI_SEL_MASK, 1 << CTS_ENCI_SEL_SHIFT);
 906                 else
 907                         /* select vclk_div2 for encp */
 908                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 909                                 CTS_ENCP_SEL_MASK, 1 << CTS_ENCP_SEL_SHIFT);
 910                 break;
 911         case 4:
 912                 /* enable vclk_div4 gate */
 913                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 914                                    VCLK_DIV4_EN, VCLK_DIV4_EN);
 915
 916                 if (hdmi_use_enci)
 917                         /* select vclk_div4 for enci */
 918                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 919                                 CTS_ENCI_SEL_MASK, 2 << CTS_ENCI_SEL_SHIFT);
 920                 else
 921                         /* select vclk_div4 for encp */
 922                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 923                                 CTS_ENCP_SEL_MASK, 2 << CTS_ENCP_SEL_SHIFT);
 924                 break;
 925         case 6:
 926                 /* enable vclk_div6 gate */
 927                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 928                                    VCLK_DIV6_EN, VCLK_DIV6_EN);
 929
 930                 if (hdmi_use_enci)
 931                         /* select vclk_div6 for enci */
 932                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 933                                 CTS_ENCI_SEL_MASK, 3 << CTS_ENCI_SEL_SHIFT);
 934                 else
 935                         /* select vclk_div6 for encp */
 936                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 937                                 CTS_ENCP_SEL_MASK, 3 << CTS_ENCP_SEL_SHIFT);
 938                 break;
 939         case 12:
 940                 /* enable vclk_div12 gate */
 941                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL,
 942                                    VCLK_DIV12_EN, VCLK_DIV12_EN);
 943
 944                 if (hdmi_use_enci)
 945                         /* select vclk_div12 for enci */
 946                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 947                                 CTS_ENCI_SEL_MASK, 4 << CTS_ENCI_SEL_SHIFT);
 948                 else
 949                         /* select vclk_div12 for encp */
 950                         regmap_update_bits(priv->hhi, HHI_VID_CLK_DIV,
 951                                 CTS_ENCP_SEL_MASK, 4 << CTS_ENCP_SEL_SHIFT);
 952                 break;
 953         }
 954
 955         if (hdmi_use_enci)
 956                 /* Enable ENCI clock gate */
 957                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 958                                    CTS_ENCI_EN, CTS_ENCI_EN);
 959         else
 960                 /* Enable ENCP clock gate */
 961                 regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
 962                                    CTS_ENCP_EN, CTS_ENCP_EN);
 963
 964         regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL, VCLK_EN, VCLK_EN);
 965 }
 966
 967 void meson_vclk_setup(struct meson_drm *priv, unsigned int target,
 968                       unsigned int vclk_freq, unsigned int venc_freq,
 969                       unsigned int dac_freq, bool hdmi_use_enci)
 970 {
 971         bool vic_alternate_clock = false;
 972         unsigned int freq;
 973         unsigned int hdmi_tx_div;
 974         unsigned int venc_div;
 975
 976         if (target == MESON_VCLK_TARGET_CVBS) {
 977                 meson_venci_cvbs_clock_config(priv);
 978                 return;
 979         } else if (target == MESON_VCLK_TARGET_DMT) {
 980                 /*
 981                  * The DMT clock path is fixed after the PLL:
 982                  * - automatic PLL freq + OD management
 983                  * - vid_pll_div = VID_PLL_DIV_5
 984                  * - vclk_div = 2
 985                  * - hdmi_tx_div = 1
 986                  * - venc_div = 1
 987                  * - encp encoder
 988                  */
 989                 meson_vclk_set(priv, vclk_freq * 10, 0, 0, 0,
 990                                VID_PLL_DIV_5, 2, 1, 1, false, false);
 991                 return;
 992         }
 993
 994         hdmi_tx_div = vclk_freq / dac_freq;
 995
 996         if (hdmi_tx_div == 0) {
 997                 pr_err("Fatal Error, invalid HDMI-TX freq %d\n",
 998                        dac_freq);
 999                 return;
1000         }
1001
1002         venc_div = vclk_freq / venc_freq;
1003
1004         if (venc_div == 0) {
1005                 pr_err("Fatal Error, invalid HDMI venc freq %d\n",
1006                        venc_freq);
1007                 return;
1008         }
1009
1010         for (freq = 0 ; params[freq].pixel_freq ; ++freq) {
1011                 if (vclk_freq == params[freq].pixel_freq ||
1012                     vclk_freq == FREQ_1000_1001(params[freq].pixel_freq)) {
1013                         if (vclk_freq != params[freq].pixel_freq)
1014                                 vic_alternate_clock = true;
1015                         else
1016                                 vic_alternate_clock = false;
1017
1018                         if (freq == MESON_VCLK_HDMI_ENCI_54000 &&
1019                             !hdmi_use_enci)
1020                                 continue;
1021
1022                         if (freq == MESON_VCLK_HDMI_DDR_54000 &&
1023                             hdmi_use_enci)
1024                                 continue;
1025
1026                         if (freq == MESON_VCLK_HDMI_DDR_148500 &&
1027                             dac_freq == vclk_freq)
1028                                 continue;
1029
1030                         if (freq == MESON_VCLK_HDMI_148500 &&
1031                             dac_freq != vclk_freq)
1032                                 continue;
1033                         break;
1034                 }
1035         }
1036
1037         if (!params[freq].pixel_freq) {
1038                 pr_err("Fatal Error, invalid HDMI vclk freq %d\n", vclk_freq);
1039                 return;
1040         }
1041
1042         meson_vclk_set(priv, params[freq].pll_base_freq,
1043                        params[freq].pll_od1, params[freq].pll_od2,
1044                        params[freq].pll_od3, params[freq].vid_pll_div,
1045                        params[freq].vclk_div, hdmi_tx_div, venc_div,
1046                        hdmi_use_enci, vic_alternate_clock);
1047 }
1048 EXPORT_SYMBOL_GPL(meson_vclk_setup);